SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/video/intelfb/intelfbhw.c

   1 /*
   2  * intelfb
   3  *
   4  * Linux framebuffer driver for Intel(R) 865G integrated graphics chips.
   5  *
   6  * Copyright © 2002, 2003 David Dawes <dawes@xfree86.org>
   7  *                   2004 Sylvain Meyer
   8  *
   9  * This driver consists of two parts.  The first part (intelfbdrv.c) provides
  10  * the basic fbdev interfaces, is derived in part from the radeonfb and
  11  * vesafb drivers, and is covered by the GPL.  The second part (intelfbhw.c)
  12  * provides the code to program the hardware.  Most of it is derived from
  13  * the i810/i830 XFree86 driver.  The HW-specific code is covered here
  14  * under a dual license (GPL and MIT/XFree86 license).
  15  *
  16  * Author: David Dawes
  17  *
  18  */
  19
  20 /* $DHD: intelfb/intelfbhw.c,v 1.9 2003/06/27 15:06:25 dawes Exp $ */
  21
  22 #include <linux/module.h>
  23 #include <linux/kernel.h>
  24 #include <linux/errno.h>
  25 #include <linux/string.h>
  26 #include <linux/mm.h>
  27 #include <linux/slab.h>
  28 #include <linux/delay.h>
  29 #include <linux/fb.h>
  30 #include <linux/ioport.h>
  31 #include <linux/init.h>
  32 #include <linux/pci.h>
  33 #include <linux/vmalloc.h>
  34 #include <linux/pagemap.h>
  35 #include <linux/interrupt.h>
  36
  37 #include <asm/io.h>
  38
  39 #include "intelfb.h"
  40 #include "intelfbhw.h"
  41
  42 struct pll_min_max {
  43         int min_m, max_m, min_m1, max_m1;
  44         int min_m2, max_m2, min_n, max_n;
  45         int min_p, max_p, min_p1, max_p1;
  46         int min_vco, max_vco, p_transition_clk, ref_clk;
  47         int p_inc_lo, p_inc_hi;
  48 };
  49
  50 #define PLLS_I8xx 0
  51 #define PLLS_I9xx 1
  52 #define PLLS_MAX 2
  53
  54 static struct pll_min_max plls[PLLS_MAX] = {
  55         { 108, 140, 18, 26,
  56           6, 16, 3, 16,
  57           4, 128, 0, 31,
  58           930000, 1400000, 165000, 48000,
  59           4, 2 },               /* I8xx */
  60
  61         { 75, 120, 10, 20,
  62           5, 9, 4, 7,
  63           5, 80, 1, 8,
  64           1400000, 2800000, 200000, 96000,
  65           10, 5 }               /* I9xx */
  66 };
  67
  68 int intelfbhw_get_chipset(struct pci_dev *pdev, struct intelfb_info *dinfo)
  69 {
  70         u32 tmp;
  71         if (!pdev || !dinfo)
  72                 return 1;
  73
  74         switch (pdev->device) {
  75         case PCI_DEVICE_ID_INTEL_830M:
  76                 dinfo->name = "Intel(R) 830M";
  77                 dinfo->chipset = INTEL_830M;
  78                 dinfo->mobile = 1;
  79                 dinfo->pll_index = PLLS_I8xx;
  80                 return 0;
  81         case PCI_DEVICE_ID_INTEL_845G:
  82                 dinfo->name = "Intel(R) 845G";
  83                 dinfo->chipset = INTEL_845G;
  84                 dinfo->mobile = 0;
  85                 dinfo->pll_index = PLLS_I8xx;
  86                 return 0;
  87         case PCI_DEVICE_ID_INTEL_854:
  88                 dinfo->mobile = 1;
  89                 dinfo->name = "Intel(R) 854";
  90                 dinfo->chipset = INTEL_854;
  91                 return 0;
  92         case PCI_DEVICE_ID_INTEL_85XGM:
  93                 tmp = 0;
  94                 dinfo->mobile = 1;
  95                 dinfo->pll_index = PLLS_I8xx;
  96                 pci_read_config_dword(pdev, INTEL_85X_CAPID, &tmp);
  97                 switch ((tmp >> INTEL_85X_VARIANT_SHIFT) &
  98                         INTEL_85X_VARIANT_MASK) {
  99                 case INTEL_VAR_855GME:
 100                         dinfo->name = "Intel(R) 855GME";
 101                         dinfo->chipset = INTEL_855GME;
 102                         return 0;
 103                 case INTEL_VAR_855GM:
 104                         dinfo->name = "Intel(R) 855GM";
 105                         dinfo->chipset = INTEL_855GM;
 106                         return 0;
 107                 case INTEL_VAR_852GME:
 108                         dinfo->name = "Intel(R) 852GME";
 109                         dinfo->chipset = INTEL_852GME;
 110                         return 0;
 111                 case INTEL_VAR_852GM:
 112                         dinfo->name = "Intel(R) 852GM";
 113                         dinfo->chipset = INTEL_852GM;
 114                         return 0;
 115                 default:
 116                         dinfo->name = "Intel(R) 852GM/855GM";
 117                         dinfo->chipset = INTEL_85XGM;
 118                         return 0;
 119                 }
 120                 break;
 121         case PCI_DEVICE_ID_INTEL_865G:
 122                 dinfo->name = "Intel(R) 865G";
 123                 dinfo->chipset = INTEL_865G;
 124                 dinfo->mobile = 0;
 125                 dinfo->pll_index = PLLS_I8xx;
 126                 return 0;
 127         case PCI_DEVICE_ID_INTEL_915G:
 128                 dinfo->name = "Intel(R) 915G";
 129                 dinfo->chipset = INTEL_915G;
 130                 dinfo->mobile = 0;
 131                 dinfo->pll_index = PLLS_I9xx;
 132                 return 0;
 133         case PCI_DEVICE_ID_INTEL_915GM:
 134                 dinfo->name = "Intel(R) 915GM";
 135                 dinfo->chipset = INTEL_915GM;
 136                 dinfo->mobile = 1;
 137                 dinfo->pll_index = PLLS_I9xx;
 138                 return 0;
 139         case PCI_DEVICE_ID_INTEL_945G:
 140                 dinfo->name = "Intel(R) 945G";
 141                 dinfo->chipset = INTEL_945G;
 142                 dinfo->mobile = 0;
 143                 dinfo->pll_index = PLLS_I9xx;
 144                 return 0;
 145         case PCI_DEVICE_ID_INTEL_945GM:
 146                 dinfo->name = "Intel(R) 945GM";
 147                 dinfo->chipset = INTEL_945GM;
 148                 dinfo->mobile = 1;
 149                 dinfo->pll_index = PLLS_I9xx;
 150                 return 0;
 151         case PCI_DEVICE_ID_INTEL_945GME:
 152                 dinfo->name = "Intel(R) 945GME";
 153                 dinfo->chipset = INTEL_945GME;
 154                 dinfo->mobile = 1;
 155                 dinfo->pll_index = PLLS_I9xx;
 156                 return 0;
 157         case PCI_DEVICE_ID_INTEL_965G:
 158                 dinfo->name = "Intel(R) 965G";
 159                 dinfo->chipset = INTEL_965G;
 160                 dinfo->mobile = 0;
 161                 dinfo->pll_index = PLLS_I9xx;
 162                 return 0;
 163         case PCI_DEVICE_ID_INTEL_965GM:
 164                 dinfo->name = "Intel(R) 965GM";
 165                 dinfo->chipset = INTEL_965GM;
 166                 dinfo->mobile = 1;
 167                 dinfo->pll_index = PLLS_I9xx;
 168                 return 0;
 169         default:
 170                 return 1;
 171         }
 172 }
 173
 174 int intelfbhw_get_memory(struct pci_dev *pdev, int *aperture_size,
 175                          int *stolen_size)
 176 {
 177         struct pci_dev *bridge_dev;
 178         u16 tmp;
 179         int stolen_overhead;
 180
 181         if (!pdev || !aperture_size || !stolen_size)
 182                 return 1;
 183
 184         /* Find the bridge device.  It is always 0:0.0 */
 185         if (!(bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0)))) {
 186                 ERR_MSG("cannot find bridge device\n");
 187                 return 1;
 188         }
 189
 190         /* Get the fb aperture size and "stolen" memory amount. */
 191         tmp = 0;
 192         pci_read_config_word(bridge_dev, INTEL_GMCH_CTRL, &tmp);
 193         pci_dev_put(bridge_dev);
 194
 195         switch (pdev->device) {
 196         case PCI_DEVICE_ID_INTEL_915G:
 197         case PCI_DEVICE_ID_INTEL_915GM:
 198         case PCI_DEVICE_ID_INTEL_945G:
 199         case PCI_DEVICE_ID_INTEL_945GM:
 200         case PCI_DEVICE_ID_INTEL_945GME:
 201         case PCI_DEVICE_ID_INTEL_965G:
 202         case PCI_DEVICE_ID_INTEL_965GM:
 203                 /* 915, 945 and 965 chipsets support a 256MB aperture.
 204                    Aperture size is determined by inspected the
 205                    base address of the aperture. */
 206                 if (pci_resource_start(pdev, 2) & 0x08000000)
 207                         *aperture_size = MB(128);
 208                 else
 209                         *aperture_size = MB(256);
 210                 break;
 211         default:
 212                 if ((tmp & INTEL_GMCH_MEM_MASK) == INTEL_GMCH_MEM_64M)
 213                         *aperture_size = MB(64);
 214                 else
 215                         *aperture_size = MB(128);
 216                 break;
 217         }
 218
 219         /* Stolen memory size is reduced by the GTT and the popup.
 220            GTT is 1K per MB of aperture size, and popup is 4K. */
 221         stolen_overhead = (*aperture_size / MB(1)) + 4;
 222         switch(pdev->device) {
 223         case PCI_DEVICE_ID_INTEL_830M:
 224         case PCI_DEVICE_ID_INTEL_845G:
 225                 switch (tmp & INTEL_830_GMCH_GMS_MASK) {
 226                 case INTEL_830_GMCH_GMS_STOLEN_512:
 227                         *stolen_size = KB(512) - KB(stolen_overhead);
 228                         return 0;
 229                 case INTEL_830_GMCH_GMS_STOLEN_1024:
 230                         *stolen_size = MB(1) - KB(stolen_overhead);
 231                         return 0;
 232                 case INTEL_830_GMCH_GMS_STOLEN_8192:
 233                         *stolen_size = MB(8) - KB(stolen_overhead);
 234                         return 0;
 235                 case INTEL_830_GMCH_GMS_LOCAL:
 236                         ERR_MSG("only local memory found\n");
 237                         return 1;
 238                 case INTEL_830_GMCH_GMS_DISABLED:
 239                         ERR_MSG("video memory is disabled\n");
 240                         return 1;
 241                 default:
 242                         ERR_MSG("unexpected GMCH_GMS value: 0x%02x\n",
 243                                 tmp & INTEL_830_GMCH_GMS_MASK);
 244                         return 1;
 245                 }
 246                 break;
 247         default:
 248                 switch (tmp & INTEL_855_GMCH_GMS_MASK) {
 249                 case INTEL_855_GMCH_GMS_STOLEN_1M:
 250                         *stolen_size = MB(1) - KB(stolen_overhead);
 251                         return 0;
 252                 case INTEL_855_GMCH_GMS_STOLEN_4M:
 253                         *stolen_size = MB(4) - KB(stolen_overhead);
 254                         return 0;
 255                 case INTEL_855_GMCH_GMS_STOLEN_8M:
 256                         *stolen_size = MB(8) - KB(stolen_overhead);
 257                         return 0;
 258                 case INTEL_855_GMCH_GMS_STOLEN_16M:
 259                         *stolen_size = MB(16) - KB(stolen_overhead);
 260                         return 0;
 261                 case INTEL_855_GMCH_GMS_STOLEN_32M:
 262                         *stolen_size = MB(32) - KB(stolen_overhead);
 263                         return 0;
 264                 case INTEL_915G_GMCH_GMS_STOLEN_48M:
 265                         *stolen_size = MB(48) - KB(stolen_overhead);
 266                         return 0;
 267                 case INTEL_915G_GMCH_GMS_STOLEN_64M:
 268                         *stolen_size = MB(64) - KB(stolen_overhead);
 269                         return 0;
 270                 case INTEL_855_GMCH_GMS_DISABLED:
 271                         ERR_MSG("video memory is disabled\n");
 272                         return 0;
 273                 default:
 274                         ERR_MSG("unexpected GMCH_GMS value: 0x%02x\n",
 275                                 tmp & INTEL_855_GMCH_GMS_MASK);
 276                         return 1;
 277                 }
 278         }
 279 }
 280
 281 int intelfbhw_check_non_crt(struct intelfb_info *dinfo)
 282 {
 283         int dvo = 0;
 284
 285         if (INREG(LVDS) & PORT_ENABLE)
 286                 dvo |= LVDS_PORT;
 287         if (INREG(DVOA) & PORT_ENABLE)
 288                 dvo |= DVOA_PORT;
 289         if (INREG(DVOB) & PORT_ENABLE)
 290                 dvo |= DVOB_PORT;
 291         if (INREG(DVOC) & PORT_ENABLE)
 292                 dvo |= DVOC_PORT;
 293
 294         return dvo;
 295 }
 296
 297 const char * intelfbhw_dvo_to_string(int dvo)
 298 {
 299         if (dvo & DVOA_PORT)
 300                 return "DVO port A";
 301         else if (dvo & DVOB_PORT)
 302                 return "DVO port B";
 303         else if (dvo & DVOC_PORT)
 304                 return "DVO port C";
 305         else if (dvo & LVDS_PORT)
 306                 return "LVDS port";
 307         else
 308                 return NULL;
 309 }
 310
 311
 312 int intelfbhw_validate_mode(struct intelfb_info *dinfo,
 313                             struct fb_var_screeninfo *var)
 314 {
 315         int bytes_per_pixel;
 316         int tmp;
 317
 318 #if VERBOSE > 0
 319         DBG_MSG("intelfbhw_validate_mode\n");
 320 #endif
 321
 322         bytes_per_pixel = var->bits_per_pixel / 8;
 323         if (bytes_per_pixel == 3)
 324                 bytes_per_pixel = 4;
 325
 326         /* Check if enough video memory. */
 327         tmp = var->yres_virtual * var->xres_virtual * bytes_per_pixel;
 328         if (tmp > dinfo->fb.size) {
 329                 WRN_MSG("Not enough video ram for mode "
 330                         "(%d KByte vs %d KByte).\n",
 331                         BtoKB(tmp), BtoKB(dinfo->fb.size));
 332                 return 1;
 333         }
 334
 335         /* Check if x/y limits are OK. */
 336         if (var->xres - 1 > HACTIVE_MASK) {
 337                 WRN_MSG("X resolution too large (%d vs %d).\n",
 338                         var->xres, HACTIVE_MASK + 1);
 339                 return 1;
 340         }
 341         if (var->yres - 1 > VACTIVE_MASK) {
 342                 WRN_MSG("Y resolution too large (%d vs %d).\n",
 343                         var->yres, VACTIVE_MASK + 1);
 344                 return 1;
 345         }
 346         if (var->xres < 4) {
 347                 WRN_MSG("X resolution too small (%d vs 4).\n", var->xres);
 348                 return 1;
 349         }
 350         if (var->yres < 4) {
 351                 WRN_MSG("Y resolution too small (%d vs 4).\n", var->yres);
 352                 return 1;
 353         }
 354
 355         /* Check for doublescan modes. */
 356         if (var->vmode & FB_VMODE_DOUBLE) {
 357                 WRN_MSG("Mode is double-scan.\n");
 358                 return 1;
 359         }
 360
 361         if ((var->vmode & FB_VMODE_INTERLACED) && (var->yres & 1)) {
 362                 WRN_MSG("Odd number of lines in interlaced mode\n");
 363                 return 1;
 364         }
 365
 366         /* Check if clock is OK. */
 367         tmp = 1000000000 / var->pixclock;
 368         if (tmp < MIN_CLOCK) {
 369                 WRN_MSG("Pixel clock is too low (%d MHz vs %d MHz).\n",
 370                         (tmp + 500) / 1000, MIN_CLOCK / 1000);
 371                 return 1;
 372         }
 373         if (tmp > MAX_CLOCK) {
 374                 WRN_MSG("Pixel clock is too high (%d MHz vs %d MHz).\n",
 375                         (tmp + 500) / 1000, MAX_CLOCK / 1000);
 376                 return 1;
 377         }
 378
 379         return 0;
 380 }
 381
 382 int intelfbhw_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
 383 {
 384         struct intelfb_info *dinfo = GET_DINFO(info);
 385         u32 offset, xoffset, yoffset;
 386
 387 #if VERBOSE > 0
 388         DBG_MSG("intelfbhw_pan_display\n");
 389 #endif
 390
 391         xoffset = ROUND_DOWN_TO(var->xoffset, 8);
 392         yoffset = var->yoffset;
 393
 394         if ((xoffset + var->xres > var->xres_virtual) ||
 395             (yoffset + var->yres > var->yres_virtual))
 396                 return -EINVAL;
 397
 398         offset = (yoffset * dinfo->pitch) +
 399                  (xoffset * var->bits_per_pixel) / 8;
 400
 401         offset += dinfo->fb.offset << 12;
 402
 403         dinfo->vsync.pan_offset = offset;
 404         if ((var->activate & FB_ACTIVATE_VBL) &&
 405             !intelfbhw_enable_irq(dinfo))
 406                 dinfo->vsync.pan_display = 1;
 407         else {
 408                 dinfo->vsync.pan_display = 0;
 409                 OUTREG(DSPABASE, offset);
 410         }
 411
 412         return 0;
 413 }
 414
 415 /* Blank the screen. */
 416 void intelfbhw_do_blank(int blank, struct fb_info *info)
 417 {
 418         struct intelfb_info *dinfo = GET_DINFO(info);
 419         u32 tmp;
 420
 421 #if VERBOSE > 0
 422         DBG_MSG("intelfbhw_do_blank: blank is %d\n", blank);
 423 #endif
 424
 425         /* Turn plane A on or off */
 426         tmp = INREG(DSPACNTR);
 427         if (blank)
 428                 tmp &= ~DISPPLANE_PLANE_ENABLE;
 429         else
 430                 tmp |= DISPPLANE_PLANE_ENABLE;
 431         OUTREG(DSPACNTR, tmp);
 432         /* Flush */
 433         tmp = INREG(DSPABASE);
 434         OUTREG(DSPABASE, tmp);
 435
 436         /* Turn off/on the HW cursor */
 437 #if VERBOSE > 0
 438         DBG_MSG("cursor_on is %d\n", dinfo->cursor_on);
 439 #endif
 440         if (dinfo->cursor_on) {
 441                 if (blank)
 442                         intelfbhw_cursor_hide(dinfo);
 443                 else
 444                         intelfbhw_cursor_show(dinfo);
 445                 dinfo->cursor_on = 1;
 446         }
 447         dinfo->cursor_blanked = blank;
 448
 449         /* Set DPMS level */
 450         tmp = INREG(ADPA) & ~ADPA_DPMS_CONTROL_MASK;
 451         switch (blank) {
 452         case FB_BLANK_UNBLANK:
 453         case FB_BLANK_NORMAL:
 454                 tmp |= ADPA_DPMS_D0;
 455                 break;
 456         case FB_BLANK_VSYNC_SUSPEND:
 457                 tmp |= ADPA_DPMS_D1;
 458                 break;
 459         case FB_BLANK_HSYNC_SUSPEND:
 460                 tmp |= ADPA_DPMS_D2;
 461                 break;
 462         case FB_BLANK_POWERDOWN:
 463                 tmp |= ADPA_DPMS_D3;
 464                 break;
 465         }
 466         OUTREG(ADPA, tmp);
 467
 468         return;
 469 }
 470
 471
 472 /* Check which pipe is connected to an active display plane. */
 473 int intelfbhw_active_pipe(const struct intelfb_hwstate *hw)
 474 {
 475         int pipe = -1;
 476
 477         /* keep old default behaviour - prefer PIPE_A */
 478         if (hw->disp_b_ctrl & DISPPLANE_PLANE_ENABLE) {
 479                 pipe = (hw->disp_b_ctrl >> DISPPLANE_SEL_PIPE_SHIFT);
 480                 pipe &= PIPE_MASK;
 481                 if (unlikely(pipe == PIPE_A))
 482                         return PIPE_A;
 483         }
 484         if (hw->disp_a_ctrl & DISPPLANE_PLANE_ENABLE) {
 485                 pipe = (hw->disp_a_ctrl >> DISPPLANE_SEL_PIPE_SHIFT);
 486                 pipe &= PIPE_MASK;
 487                 if (likely(pipe == PIPE_A))
 488                         return PIPE_A;
 489         }
 490         /* Impossible that no pipe is selected - return PIPE_A */
 491         WARN_ON(pipe == -1);
 492         if (unlikely(pipe == -1))
 493                 pipe = PIPE_A;
 494
 495         return pipe;
 496 }
 497
 498 void intelfbhw_setcolreg(struct intelfb_info *dinfo, unsigned regno,
 499                          unsigned red, unsigned green, unsigned blue,
 500                          unsigned transp)
 501 {
 502         u32 palette_reg = (dinfo->pipe == PIPE_A) ?
 503                           PALETTE_A : PALETTE_B;
 504
 505 #if VERBOSE > 0
 506         DBG_MSG("intelfbhw_setcolreg: %d: (%d, %d, %d)\n",
 507                 regno, red, green, blue);
 508 #endif
 509
 510         OUTREG(palette_reg + (regno << 2),
 511                (red << PALETTE_8_RED_SHIFT) |
 512                (green << PALETTE_8_GREEN_SHIFT) |
 513                (blue << PALETTE_8_BLUE_SHIFT));
 514 }
 515
 516
 517 int intelfbhw_read_hw_state(struct intelfb_info *dinfo,
 518                             struct intelfb_hwstate *hw, int flag)
 519 {
 520         int i;
 521
 522 #if VERBOSE > 0
 523         DBG_MSG("intelfbhw_read_hw_state\n");
 524 #endif
 525
 526         if (!hw || !dinfo)
 527                 return -1;
 528
 529         /* Read in as much of the HW state as possible. */
 530         hw->vga0_divisor = INREG(VGA0_DIVISOR);
 531         hw->vga1_divisor = INREG(VGA1_DIVISOR);
 532         hw->vga_pd = INREG(VGAPD);
 533         hw->dpll_a = INREG(DPLL_A);
 534         hw->dpll_b = INREG(DPLL_B);
 535         hw->fpa0 = INREG(FPA0);
 536         hw->fpa1 = INREG(FPA1);
 537         hw->fpb0 = INREG(FPB0);
 538         hw->fpb1 = INREG(FPB1);
 539
 540         if (flag == 1)
 541                 return flag;
 542
 543 #if 0
 544         /* This seems to be a problem with the 852GM/855GM */
 545         for (i = 0; i < PALETTE_8_ENTRIES; i++) {
 546                 hw->palette_a[i] = INREG(PALETTE_A + (i << 2));
 547                 hw->palette_b[i] = INREG(PALETTE_B + (i << 2));
 548         }
 549 #endif
 550
 551         if (flag == 2)
 552                 return flag;
 553
 554         hw->htotal_a = INREG(HTOTAL_A);
 555         hw->hblank_a = INREG(HBLANK_A);
 556         hw->hsync_a = INREG(HSYNC_A);
 557         hw->vtotal_a = INREG(VTOTAL_A);
 558         hw->vblank_a = INREG(VBLANK_A);
 559         hw->vsync_a = INREG(VSYNC_A);
 560         hw->src_size_a = INREG(SRC_SIZE_A);
 561         hw->bclrpat_a = INREG(BCLRPAT_A);
 562         hw->htotal_b = INREG(HTOTAL_B);
 563         hw->hblank_b = INREG(HBLANK_B);
 564         hw->hsync_b = INREG(HSYNC_B);
 565         hw->vtotal_b = INREG(VTOTAL_B);
 566         hw->vblank_b = INREG(VBLANK_B);
 567         hw->vsync_b = INREG(VSYNC_B);
 568         hw->src_size_b = INREG(SRC_SIZE_B);
 569         hw->bclrpat_b = INREG(BCLRPAT_B);
 570
 571         if (flag == 3)
 572                 return flag;
 573
 574         hw->adpa = INREG(ADPA);
 575         hw->dvoa = INREG(DVOA);
 576         hw->dvob = INREG(DVOB);
 577         hw->dvoc = INREG(DVOC);
 578         hw->dvoa_srcdim = INREG(DVOA_SRCDIM);
 579         hw->dvob_srcdim = INREG(DVOB_SRCDIM);
 580         hw->dvoc_srcdim = INREG(DVOC_SRCDIM);
 581         hw->lvds = INREG(LVDS);
 582
 583         if (flag == 4)
 584                 return flag;
 585
 586         hw->pipe_a_conf = INREG(PIPEACONF);
 587         hw->pipe_b_conf = INREG(PIPEBCONF);
 588         hw->disp_arb = INREG(DISPARB);
 589
 590         if (flag == 5)
 591                 return flag;
 592
 593         hw->cursor_a_control = INREG(CURSOR_A_CONTROL);
 594         hw->cursor_b_control = INREG(CURSOR_B_CONTROL);
 595         hw->cursor_a_base = INREG(CURSOR_A_BASEADDR);
 596         hw->cursor_b_base = INREG(CURSOR_B_BASEADDR);
 597
 598         if (flag == 6)
 599                 return flag;
 600
 601         for (i = 0; i < 4; i++) {
 602                 hw->cursor_a_palette[i] = INREG(CURSOR_A_PALETTE0 + (i << 2));
 603                 hw->cursor_b_palette[i] = INREG(CURSOR_B_PALETTE0 + (i << 2));
 604         }
 605
 606         if (flag == 7)
 607                 return flag;
 608
 609         hw->cursor_size = INREG(CURSOR_SIZE);
 610
 611         if (flag == 8)
 612                 return flag;
 613
 614         hw->disp_a_ctrl = INREG(DSPACNTR);
 615         hw->disp_b_ctrl = INREG(DSPBCNTR);
 616         hw->disp_a_base = INREG(DSPABASE);
 617         hw->disp_b_base = INREG(DSPBBASE);
 618         hw->disp_a_stride = INREG(DSPASTRIDE);
 619         hw->disp_b_stride = INREG(DSPBSTRIDE);
 620
 621         if (flag == 9)
 622                 return flag;
 623
 624         hw->vgacntrl = INREG(VGACNTRL);
 625
 626         if (flag == 10)
 627                 return flag;
 628
 629         hw->add_id = INREG(ADD_ID);
 630
 631         if (flag == 11)
 632                 return flag;
 633
 634         for (i = 0; i < 7; i++) {
 635                 hw->swf0x[i] = INREG(SWF00 + (i << 2));
 636                 hw->swf1x[i] = INREG(SWF10 + (i << 2));
 637                 if (i < 3)
 638                         hw->swf3x[i] = INREG(SWF30 + (i << 2));
 639         }
 640
 641         for (i = 0; i < 8; i++)
 642                 hw->fence[i] = INREG(FENCE + (i << 2));
 643
 644         hw->instpm = INREG(INSTPM);
 645         hw->mem_mode = INREG(MEM_MODE);
 646         hw->fw_blc_0 = INREG(FW_BLC_0);
 647         hw->fw_blc_1 = INREG(FW_BLC_1);
 648
 649         hw->hwstam = INREG16(HWSTAM);
 650         hw->ier = INREG16(IER);
 651         hw->iir = INREG16(IIR);
 652         hw->imr = INREG16(IMR);
 653
 654         return 0;
 655 }
 656
 657
 658 static int calc_vclock3(int index, int m, int n, int p)
 659 {
 660         if (p == 0 || n == 0)
 661                 return 0;
 662         return plls[index].ref_clk * m / n / p;
 663 }
 664
 665 static int calc_vclock(int index, int m1, int m2, int n, int p1, int p2,
 666                        int lvds)
 667 {
 668         struct pll_min_max *pll = &plls[index];
 669         u32 m, vco, p;
 670
 671         m = (5 * (m1 + 2)) + (m2 + 2);
 672         n += 2;
 673         vco = pll->ref_clk * m / n;
 674
 675         if (index == PLLS_I8xx)
 676                 p = ((p1 + 2) * (1 << (p2 + 1)));
 677         else
 678                 p = ((p1) * (p2 ? 5 : 10));
 679         return vco / p;
 680 }
 681
 682 #if REGDUMP
 683 static void intelfbhw_get_p1p2(struct intelfb_info *dinfo, int dpll,
 684                                int *o_p1, int *o_p2)
 685 {
 686         int p1, p2;
 687
 688         if (IS_I9XX(dinfo)) {
 689                 if (dpll & DPLL_P1_FORCE_DIV2)
 690                         p1 = 1;
 691                 else
 692                         p1 = (dpll >> DPLL_P1_SHIFT) & 0xff;
 693
 694                 p1 = ffs(p1);
 695
 696                 p2 = (dpll >> DPLL_I9XX_P2_SHIFT) & DPLL_P2_MASK;
 697         } else {
 698                 if (dpll & DPLL_P1_FORCE_DIV2)
 699                         p1 = 0;
 700                 else
 701                         p1 = (dpll >> DPLL_P1_SHIFT) & DPLL_P1_MASK;
 702                 p2 = (dpll >> DPLL_P2_SHIFT) & DPLL_P2_MASK;
 703         }
 704
 705         *o_p1 = p1;
 706         *o_p2 = p2;
 707 }
 708 #endif
 709
 710
 711 void intelfbhw_print_hw_state(struct intelfb_info *dinfo,
 712                               struct intelfb_hwstate *hw)
 713 {
 714 #if REGDUMP
 715         int i, m1, m2, n, p1, p2;
 716         int index = dinfo->pll_index;
 717         DBG_MSG("intelfbhw_print_hw_state\n");
 718
 719         if (!hw)
 720                 return;
 721         /* Read in as much of the HW state as possible. */
 722         printk("hw state dump start\n");
 723         printk("        VGA0_DIVISOR:           0x%08x\n", hw->vga0_divisor);
 724         printk("        VGA1_DIVISOR:           0x%08x\n", hw->vga1_divisor);
 725         printk("        VGAPD:                  0x%08x\n", hw->vga_pd);
 726         n = (hw->vga0_divisor >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 727         m1 = (hw->vga0_divisor >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 728         m2 = (hw->vga0_divisor >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 729
 730         intelfbhw_get_p1p2(dinfo, hw->vga_pd, &p1, &p2);
 731
 732         printk("        VGA0: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",
 733                m1, m2, n, p1, p2);
 734         printk("        VGA0: clock is %d\n",
 735                calc_vclock(index, m1, m2, n, p1, p2, 0));
 736
 737         n = (hw->vga1_divisor >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 738         m1 = (hw->vga1_divisor >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 739         m2 = (hw->vga1_divisor >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 740
 741         intelfbhw_get_p1p2(dinfo, hw->vga_pd, &p1, &p2);
 742         printk("        VGA1: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",
 743                m1, m2, n, p1, p2);
 744         printk("        VGA1: clock is %d\n",
 745                calc_vclock(index, m1, m2, n, p1, p2, 0));
 746
 747         printk("        DPLL_A:                 0x%08x\n", hw->dpll_a);
 748         printk("        DPLL_B:                 0x%08x\n", hw->dpll_b);
 749         printk("        FPA0:                   0x%08x\n", hw->fpa0);
 750         printk("        FPA1:                   0x%08x\n", hw->fpa1);
 751         printk("        FPB0:                   0x%08x\n", hw->fpb0);
 752         printk("        FPB1:                   0x%08x\n", hw->fpb1);
 753
 754         n = (hw->fpa0 >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 755         m1 = (hw->fpa0 >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 756         m2 = (hw->fpa0 >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 757
 758         intelfbhw_get_p1p2(dinfo, hw->dpll_a, &p1, &p2);
 759
 760         printk("        PLLA0: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",
 761                m1, m2, n, p1, p2);
 762         printk("        PLLA0: clock is %d\n",
 763                calc_vclock(index, m1, m2, n, p1, p2, 0));
 764
 765         n = (hw->fpa1 >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 766         m1 = (hw->fpa1 >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 767         m2 = (hw->fpa1 >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 768
 769         intelfbhw_get_p1p2(dinfo, hw->dpll_a, &p1, &p2);
 770
 771         printk("        PLLA1: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",
 772                m1, m2, n, p1, p2);
 773         printk("        PLLA1: clock is %d\n",
 774                calc_vclock(index, m1, m2, n, p1, p2, 0));
 775
 776 #if 0
 777         printk("        PALETTE_A:\n");
 778         for (i = 0; i < PALETTE_8_ENTRIES)
 779                 printk("        %3d:    0x%08x\n", i, hw->palette_a[i]);
 780         printk("        PALETTE_B:\n");
 781         for (i = 0; i < PALETTE_8_ENTRIES)
 782                 printk("        %3d:    0x%08x\n", i, hw->palette_b[i]);
 783 #endif
 784
 785         printk("        HTOTAL_A:               0x%08x\n", hw->htotal_a);
 786         printk("        HBLANK_A:               0x%08x\n", hw->hblank_a);
 787         printk("        HSYNC_A:                0x%08x\n", hw->hsync_a);
 788         printk("        VTOTAL_A:               0x%08x\n", hw->vtotal_a);
 789         printk("        VBLANK_A:               0x%08x\n", hw->vblank_a);
 790         printk("        VSYNC_A:                0x%08x\n", hw->vsync_a);
 791         printk("        SRC_SIZE_A:             0x%08x\n", hw->src_size_a);
 792         printk("        BCLRPAT_A:              0x%08x\n", hw->bclrpat_a);
 793         printk("        HTOTAL_B:               0x%08x\n", hw->htotal_b);
 794         printk("        HBLANK_B:               0x%08x\n", hw->hblank_b);
 795         printk("        HSYNC_B:                0x%08x\n", hw->hsync_b);
 796         printk("        VTOTAL_B:               0x%08x\n", hw->vtotal_b);
 797         printk("        VBLANK_B:               0x%08x\n", hw->vblank_b);
 798         printk("        VSYNC_B:                0x%08x\n", hw->vsync_b);
 799         printk("        SRC_SIZE_B:             0x%08x\n", hw->src_size_b);
 800         printk("        BCLRPAT_B:              0x%08x\n", hw->bclrpat_b);
 801
 802         printk("        ADPA:                   0x%08x\n", hw->adpa);
 803         printk("        DVOA:                   0x%08x\n", hw->dvoa);
 804         printk("        DVOB:                   0x%08x\n", hw->dvob);
 805         printk("        DVOC:                   0x%08x\n", hw->dvoc);
 806         printk("        DVOA_SRCDIM:            0x%08x\n", hw->dvoa_srcdim);
 807         printk("        DVOB_SRCDIM:            0x%08x\n", hw->dvob_srcdim);
 808         printk("        DVOC_SRCDIM:            0x%08x\n", hw->dvoc_srcdim);
 809         printk("        LVDS:                   0x%08x\n", hw->lvds);
 810
 811         printk("        PIPEACONF:              0x%08x\n", hw->pipe_a_conf);
 812         printk("        PIPEBCONF:              0x%08x\n", hw->pipe_b_conf);
 813         printk("        DISPARB:                0x%08x\n", hw->disp_arb);
 814
 815         printk("        CURSOR_A_CONTROL:       0x%08x\n", hw->cursor_a_control);
 816         printk("        CURSOR_B_CONTROL:       0x%08x\n", hw->cursor_b_control);
 817         printk("        CURSOR_A_BASEADDR:      0x%08x\n", hw->cursor_a_base);
 818         printk("        CURSOR_B_BASEADDR:      0x%08x\n", hw->cursor_b_base);
 819
 820         printk("        CURSOR_A_PALETTE:       ");
 821         for (i = 0; i < 4; i++) {
 822                 printk("0x%08x", hw->cursor_a_palette[i]);
 823                 if (i < 3)
 824                         printk(", ");
 825         }
 826         printk("\n");
 827         printk("        CURSOR_B_PALETTE:       ");
 828         for (i = 0; i < 4; i++) {
 829                 printk("0x%08x", hw->cursor_b_palette[i]);
 830                 if (i < 3)
 831                         printk(", ");
 832         }
 833         printk("\n");
 834
 835         printk("        CURSOR_SIZE:            0x%08x\n", hw->cursor_size);
 836
 837         printk("        DSPACNTR:               0x%08x\n", hw->disp_a_ctrl);
 838         printk("        DSPBCNTR:               0x%08x\n", hw->disp_b_ctrl);
 839         printk("        DSPABASE:               0x%08x\n", hw->disp_a_base);
 840         printk("        DSPBBASE:               0x%08x\n", hw->disp_b_base);
 841         printk("        DSPASTRIDE:             0x%08x\n", hw->disp_a_stride);
 842         printk("        DSPBSTRIDE:             0x%08x\n", hw->disp_b_stride);
 843
 844         printk("        VGACNTRL:               0x%08x\n", hw->vgacntrl);
 845         printk("        ADD_ID:                 0x%08x\n", hw->add_id);
 846
 847         for (i = 0; i < 7; i++) {
 848                 printk("        SWF0%d                  0x%08x\n", i,
 849                         hw->swf0x[i]);
 850         }
 851         for (i = 0; i < 7; i++) {
 852                 printk("        SWF1%d                  0x%08x\n", i,
 853                         hw->swf1x[i]);
 854         }
 855         for (i = 0; i < 3; i++) {
 856                 printk("        SWF3%d                  0x%08x\n", i,
 857                        hw->swf3x[i]);
 858         }
 859         for (i = 0; i < 8; i++)
 860                 printk("        FENCE%d                 0x%08x\n", i,
 861                        hw->fence[i]);
 862
 863         printk("        INSTPM                  0x%08x\n", hw->instpm);
 864         printk("        MEM_MODE                0x%08x\n", hw->mem_mode);
 865         printk("        FW_BLC_0                0x%08x\n", hw->fw_blc_0);
 866         printk("        FW_BLC_1                0x%08x\n", hw->fw_blc_1);
 867
 868         printk("        HWSTAM                  0x%04x\n", hw->hwstam);
 869         printk("        IER                     0x%04x\n", hw->ier);
 870         printk("        IIR                     0x%04x\n", hw->iir);
 871         printk("        IMR                     0x%04x\n", hw->imr);
 872         printk("hw state dump end\n");
 873 #endif
 874 }
 875
 876
 877
 878 /* Split the M parameter into M1 and M2. */
 879 static int splitm(int index, unsigned int m, unsigned int *retm1,
 880                   unsigned int *retm2)
 881 {
 882         int m1, m2;
 883         int testm;
 884         struct pll_min_max *pll = &plls[index];
 885
 886         /* no point optimising too much - brute force m */
 887         for (m1 = pll->min_m1; m1 < pll->max_m1 + 1; m1++) {
 888                 for (m2 = pll->min_m2; m2 < pll->max_m2 + 1; m2++) {
 889                         testm = (5 * (m1 + 2)) + (m2 + 2);
 890                         if (testm == m) {
 891                                 *retm1 = (unsigned int)m1;
 892                                 *retm2 = (unsigned int)m2;
 893                                 return 0;
 894                         }
 895                 }
 896         }
 897         return 1;
 898 }
 899
 900 /* Split the P parameter into P1 and P2. */
 901 static int splitp(int index, unsigned int p, unsigned int *retp1,
 902                   unsigned int *retp2)
 903 {
 904         int p1, p2;
 905         struct pll_min_max *pll = &plls[index];
 906
 907         if (index == PLLS_I9xx) {
 908                 p2 = (p % 10) ? 1 : 0;
 909
 910                 p1 = p / (p2 ? 5 : 10);
 911
 912                 *retp1 = (unsigned int)p1;
 913                 *retp2 = (unsigned int)p2;
 914                 return 0;
 915         }
 916
 917         if (p % 4 == 0)
 918                 p2 = 1;
 919         else
 920                 p2 = 0;
 921         p1 = (p / (1 << (p2 + 1))) - 2;
 922         if (p % 4 == 0 && p1 < pll->min_p1) {
 923                 p2 = 0;
 924                 p1 = (p / (1 << (p2 + 1))) - 2;
 925         }
 926         if (p1 < pll->min_p1 || p1 > pll->max_p1 ||
 927             (p1 + 2) * (1 << (p2 + 1)) != p) {
 928                 return 1;
 929         } else {
 930                 *retp1 = (unsigned int)p1;
 931                 *retp2 = (unsigned int)p2;
 932                 return 0;
 933         }
 934 }
 935
 936 static int calc_pll_params(int index, int clock, u32 *retm1, u32 *retm2,
 937                            u32 *retn, u32 *retp1, u32 *retp2, u32 *retclock)
 938 {
 939         u32 m1, m2, n, p1, p2, n1, testm;
 940         u32 f_vco, p, p_best = 0, m, f_out = 0;
 941         u32 err_max, err_target, err_best = 10000000;
 942         u32 n_best = 0, m_best = 0, f_best, f_err;
 943         u32 p_min, p_max, p_inc, div_max;
 944         struct pll_min_max *pll = &plls[index];
 945
 946         /* Accept 0.5% difference, but aim for 0.1% */
 947         err_max = 5 * clock / 1000;
 948         err_target = clock / 1000;
 949
 950         DBG_MSG("Clock is %d\n", clock);
 951
 952         div_max = pll->max_vco / clock;
 953
 954         p_inc = (clock <= pll->p_transition_clk) ? pll->p_inc_lo : pll->p_inc_hi;
 955         p_min = p_inc;
 956         p_max = ROUND_DOWN_TO(div_max, p_inc);
 957         if (p_min < pll->min_p)
 958                 p_min = pll->min_p;
 959         if (p_max > pll->max_p)
 960                 p_max = pll->max_p;
 961
 962         DBG_MSG("p range is %d-%d (%d)\n", p_min, p_max, p_inc);
 963
 964         p = p_min;
 965         do {
 966                 if (splitp(index, p, &p1, &p2)) {
 967                         WRN_MSG("cannot split p = %d\n", p);
 968                         p += p_inc;
 969                         continue;
 970                 }
 971                 n = pll->min_n;
 972                 f_vco = clock * p;
 973
 974                 do {
 975                         m = ROUND_UP_TO(f_vco * n, pll->ref_clk) / pll->ref_clk;
 976                         if (m < pll->min_m)
 977                                 m = pll->min_m + 1;
 978                         if (m > pll->max_m)
 979                                 m = pll->max_m - 1;
 980                         for (testm = m - 1; testm <= m; testm++) {
 981                                 f_out = calc_vclock3(index, testm, n, p);
 982                                 if (splitm(index, testm, &m1, &m2)) {
 983                                         WRN_MSG("cannot split m = %d\n",
 984                                                 testm);
 985                                         continue;
 986                                 }
 987                                 if (clock > f_out)
 988                                         f_err = clock - f_out;
 989                                 else/* slightly bias the error for bigger clocks */
 990                                         f_err = f_out - clock + 1;
 991
 992                                 if (f_err < err_best) {
 993                                         m_best = testm;
 994                                         n_best = n;
 995                                         p_best = p;
 996                                         f_best = f_out;
 997                                         err_best = f_err;
 998                                 }
 999                         }
1000                         n++;
1001                 } while ((n <= pll->max_n) && (f_out >= clock));
1002                 p += p_inc;
1003         } while ((p <= p_max));
1004
1005         if (!m_best) {
1006                 WRN_MSG("cannot find parameters for clock %d\n", clock);
1007                 return 1;
1008         }
1009         m = m_best;
1010         n = n_best;
1011         p = p_best;
1012         splitm(index, m, &m1, &m2);
1013         splitp(index, p, &p1, &p2);
1014         n1 = n - 2;
1015
1016         DBG_MSG("m, n, p: %d (%d,%d), %d (%d), %d (%d,%d), "
1017                 "f: %d (%d), VCO: %d\n",
1018                 m, m1, m2, n, n1, p, p1, p2,
1019                 calc_vclock3(index, m, n, p),
1020                 calc_vclock(index, m1, m2, n1, p1, p2, 0),
1021                 calc_vclock3(index, m, n, p) * p);
1022         *retm1 = m1;
1023         *retm2 = m2;
1024         *retn = n1;
1025         *retp1 = p1;
1026         *retp2 = p2;
1027         *retclock = calc_vclock(index, m1, m2, n1, p1, p2, 0);
1028
1029         return 0;
1030 }
1031
1032 static __inline__ int check_overflow(u32 value, u32 limit,
1033                                      const char *description)
1034 {
1035         if (value > limit) {
1036                 WRN_MSG("%s value %d exceeds limit %d\n",
1037                         description, value, limit);
1038                 return 1;
1039         }
1040         return 0;
1041 }
1042
1043 /* It is assumed that hw is filled in with the initial state information. */
1044 int intelfbhw_mode_to_hw(struct intelfb_info *dinfo,
1045                          struct intelfb_hwstate *hw,
1046                          struct fb_var_screeninfo *var)
1047 {
1048         int pipe = intelfbhw_active_pipe(hw);
1049         u32 *dpll, *fp0, *fp1;
1050         u32 m1, m2, n, p1, p2, clock_target, clock;
1051         u32 hsync_start, hsync_end, hblank_start, hblank_end, htotal, hactive;
1052         u32 vsync_start, vsync_end, vblank_start, vblank_end, vtotal, vactive;
1053         u32 vsync_pol, hsync_pol;
1054         u32 *vs, *vb, *vt, *hs, *hb, *ht, *ss, *pipe_conf;
1055         u32 stride_alignment;
1056
1057         DBG_MSG("intelfbhw_mode_to_hw\n");
1058
1059         /* Disable VGA */
1060         hw->vgacntrl |= VGA_DISABLE;
1061
1062         /* Set which pipe's registers will be set. */
1063         if (pipe == PIPE_B) {
1064                 dpll = &hw->dpll_b;
1065                 fp0 = &hw->fpb0;
1066                 fp1 = &hw->fpb1;
1067                 hs = &hw->hsync_b;
1068                 hb = &hw->hblank_b;
1069                 ht = &hw->htotal_b;
1070                 vs = &hw->vsync_b;
1071                 vb = &hw->vblank_b;
1072                 vt = &hw->vtotal_b;
1073                 ss = &hw->src_size_b;
1074                 pipe_conf = &hw->pipe_b_conf;
1075         } else {
1076                 dpll = &hw->dpll_a;
1077                 fp0 = &hw->fpa0;
1078                 fp1 = &hw->fpa1;
1079                 hs = &hw->hsync_a;
1080                 hb = &hw->hblank_a;
1081                 ht = &hw->htotal_a;
1082                 vs = &hw->vsync_a;
1083                 vb = &hw->vblank_a;
1084                 vt = &hw->vtotal_a;
1085                 ss = &hw->src_size_a;
1086                 pipe_conf = &hw->pipe_a_conf;
1087         }
1088
1089         /* Use ADPA register for sync control. */
1090         hw->adpa &= ~ADPA_USE_VGA_HVPOLARITY;
1091
1092         /* sync polarity */
1093         hsync_pol = (var->sync & FB_SYNC_HOR_HIGH_ACT) ?
1094                         ADPA_SYNC_ACTIVE_HIGH : ADPA_SYNC_ACTIVE_LOW;
1095         vsync_pol = (var->sync & FB_SYNC_VERT_HIGH_ACT) ?
1096                         ADPA_SYNC_ACTIVE_HIGH : ADPA_SYNC_ACTIVE_LOW;
1097         hw->adpa &= ~((ADPA_SYNC_ACTIVE_MASK << ADPA_VSYNC_ACTIVE_SHIFT) |
1098                       (ADPA_SYNC_ACTIVE_MASK << ADPA_HSYNC_ACTIVE_SHIFT));
1099         hw->adpa |= (hsync_pol << ADPA_HSYNC_ACTIVE_SHIFT) |
1100                     (vsync_pol << ADPA_VSYNC_ACTIVE_SHIFT);
1101
1102         /* Connect correct pipe to the analog port DAC */
1103         hw->adpa &= ~(PIPE_MASK << ADPA_PIPE_SELECT_SHIFT);
1104         hw->adpa |= (pipe << ADPA_PIPE_SELECT_SHIFT);
1105
1106         /* Set DPMS state to D0 (on) */
1107         hw->adpa &= ~ADPA_DPMS_CONTROL_MASK;
1108         hw->adpa |= ADPA_DPMS_D0;
1109
1110         hw->adpa |= ADPA_DAC_ENABLE;
1111
1112         *dpll |= (DPLL_VCO_ENABLE | DPLL_VGA_MODE_DISABLE);
1113         *dpll &= ~(DPLL_RATE_SELECT_MASK | DPLL_REFERENCE_SELECT_MASK);
1114         *dpll |= (DPLL_REFERENCE_DEFAULT | DPLL_RATE_SELECT_FP0);
1115
1116         /* Desired clock in kHz */
1117         clock_target = 1000000000 / var->pixclock;
1118
1119         if (calc_pll_params(dinfo->pll_index, clock_target, &m1, &m2,
1120                             &n, &p1, &p2, &clock)) {
1121                 WRN_MSG("calc_pll_params failed\n");
1122                 return 1;
1123         }
1124
1125         /* Check for overflow. */
1126         if (check_overflow(p1, DPLL_P1_MASK, "PLL P1 parameter"))
1127                 return 1;
1128         if (check_overflow(p2, DPLL_P2_MASK, "PLL P2 parameter"))
1129                 return 1;
1130         if (check_overflow(m1, FP_DIVISOR_MASK, "PLL M1 parameter"))
1131                 return 1;
1132         if (check_overflow(m2, FP_DIVISOR_MASK, "PLL M2 parameter"))
1133                 return 1;
1134         if (check_overflow(n, FP_DIVISOR_MASK, "PLL N parameter"))
1135                 return 1;
1136
1137         *dpll &= ~DPLL_P1_FORCE_DIV2;
1138         *dpll &= ~((DPLL_P2_MASK << DPLL_P2_SHIFT) |
1139                    (DPLL_P1_MASK << DPLL_P1_SHIFT));
1140
1141         if (IS_I9XX(dinfo)) {
1142                 *dpll |= (p2 << DPLL_I9XX_P2_SHIFT);
1143                 *dpll |= (1 << (p1 - 1)) << DPLL_P1_SHIFT;
1144         } else
1145                 *dpll |= (p2 << DPLL_P2_SHIFT) | (p1 << DPLL_P1_SHIFT);
1146
1147         *fp0 = (n << FP_N_DIVISOR_SHIFT) |
1148                (m1 << FP_M1_DIVISOR_SHIFT) |
1149                (m2 << FP_M2_DIVISOR_SHIFT);
1150         *fp1 = *fp0;
1151
1152         hw->dvob &= ~PORT_ENABLE;
1153         hw->dvoc &= ~PORT_ENABLE;
1154
1155         /* Use display plane A. */
1156         hw->disp_a_ctrl |= DISPPLANE_PLANE_ENABLE;
1157         hw->disp_a_ctrl &= ~DISPPLANE_GAMMA_ENABLE;
1158         hw->disp_a_ctrl &= ~DISPPLANE_PIXFORMAT_MASK;
1159         switch (intelfb_var_to_depth(var)) {
1160         case 8:
1161                 hw->disp_a_ctrl |= DISPPLANE_8BPP | DISPPLANE_GAMMA_ENABLE;
1162                 break;
1163         case 15:
1164                 hw->disp_a_ctrl |= DISPPLANE_15_16BPP;
1165                 break;
1166         case 16:
1167                 hw->disp_a_ctrl |= DISPPLANE_16BPP;
1168                 break;
1169         case 24:
1170                 hw->disp_a_ctrl |= DISPPLANE_32BPP_NO_ALPHA;
1171                 break;
1172         }
1173         hw->disp_a_ctrl &= ~(PIPE_MASK << DISPPLANE_SEL_PIPE_SHIFT);
1174         hw->disp_a_ctrl |= (pipe << DISPPLANE_SEL_PIPE_SHIFT);
1175
1176         /* Set CRTC registers. */
1177         hactive = var->xres;
1178         hsync_start = hactive + var->right_margin;
1179         hsync_end = hsync_start + var->hsync_len;
1180         htotal = hsync_end + var->left_margin;
1181         hblank_start = hactive;
1182         hblank_end = htotal;
1183
1184         DBG_MSG("H: act %d, ss %d, se %d, tot %d bs %d, be %d\n",
1185                 hactive, hsync_start, hsync_end, htotal, hblank_start,
1186                 hblank_end);
1187
1188         vactive = var->yres;
1189         if (var->vmode & FB_VMODE_INTERLACED)
1190                 vactive--; /* the chip adds 2 halflines automatically */
1191         vsync_start = vactive + var->lower_margin;
1192         vsync_end = vsync_start + var->vsync_len;
1193         vtotal = vsync_end + var->upper_margin;
1194         vblank_start = vactive;
1195         vblank_end = vtotal;
1196         vblank_end = vsync_end + 1;
1197
1198         DBG_MSG("V: act %d, ss %d, se %d, tot %d bs %d, be %d\n",
1199                 vactive, vsync_start, vsync_end, vtotal, vblank_start,
1200                 vblank_end);
1201
1202         /* Adjust for register values, and check for overflow. */
1203         hactive--;
1204         if (check_overflow(hactive, HACTIVE_MASK, "CRTC hactive"))
1205                 return 1;
1206         hsync_start--;
1207         if (check_overflow(hsync_start, HSYNCSTART_MASK, "CRTC hsync_start"))
1208                 return 1;
1209         hsync_end--;
1210         if (check_overflow(hsync_end, HSYNCEND_MASK, "CRTC hsync_end"))
1211                 return 1;
1212         htotal--;
1213         if (check_overflow(htotal, HTOTAL_MASK, "CRTC htotal"))
1214                 return 1;
1215         hblank_start--;
1216         if (check_overflow(hblank_start, HBLANKSTART_MASK, "CRTC hblank_start"))
1217                 return 1;
1218         hblank_end--;
1219         if (check_overflow(hblank_end, HBLANKEND_MASK, "CRTC hblank_end"))
1220                 return 1;
1221
1222         vactive--;
1223         if (check_overflow(vactive, VACTIVE_MASK, "CRTC vactive"))
1224                 return 1;
1225         vsync_start--;
1226         if (check_overflow(vsync_start, VSYNCSTART_MASK, "CRTC vsync_start"))
1227                 return 1;
1228         vsync_end--;
1229         if (check_overflow(vsync_end, VSYNCEND_MASK, "CRTC vsync_end"))
1230                 return 1;
1231         vtotal--;
1232         if (check_overflow(vtotal, VTOTAL_MASK, "CRTC vtotal"))
1233                 return 1;
1234         vblank_start--;
1235         if (check_overflow(vblank_start, VBLANKSTART_MASK, "CRTC vblank_start"))
1236                 return 1;
1237         vblank_end--;
1238         if (check_overflow(vblank_end, VBLANKEND_MASK, "CRTC vblank_end"))
1239                 return 1;
1240
1241         *ht = (htotal << HTOTAL_SHIFT) | (hactive << HACTIVE_SHIFT);
1242         *hb = (hblank_start << HBLANKSTART_SHIFT) |
1243               (hblank_end << HSYNCEND_SHIFT);
1244         *hs = (hsync_start << HSYNCSTART_SHIFT) | (hsync_end << HSYNCEND_SHIFT);
1245
1246         *vt = (vtotal << VTOTAL_SHIFT) | (vactive << VACTIVE_SHIFT);
1247         *vb = (vblank_start << VBLANKSTART_SHIFT) |
1248               (vblank_end << VSYNCEND_SHIFT);
1249         *vs = (vsync_start << VSYNCSTART_SHIFT) | (vsync_end << VSYNCEND_SHIFT);
1250         *ss = (hactive << SRC_SIZE_HORIZ_SHIFT) |
1251               (vactive << SRC_SIZE_VERT_SHIFT);
1252
1253         hw->disp_a_stride = dinfo->pitch;
1254         DBG_MSG("pitch is %d\n", hw->disp_a_stride);
1255
1256         hw->disp_a_base = hw->disp_a_stride * var->yoffset +
1257                           var->xoffset * var->bits_per_pixel / 8;
1258
1259         hw->disp_a_base += dinfo->fb.offset << 12;
1260
1261         /* Check stride alignment. */
1262         stride_alignment = IS_I9XX(dinfo) ? STRIDE_ALIGNMENT_I9XX :
1263                                             STRIDE_ALIGNMENT;
1264         if (hw->disp_a_stride % stride_alignment != 0) {
1265                 WRN_MSG("display stride %d has bad alignment %d\n",
1266                         hw->disp_a_stride, stride_alignment);
1267                 return 1;
1268         }
1269
1270         /* Set the palette to 8-bit mode. */
1271         *pipe_conf &= ~PIPECONF_GAMMA;
1272
1273         if (var->vmode & FB_VMODE_INTERLACED)
1274                 *pipe_conf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
1275         else
1276                 *pipe_conf &= ~PIPECONF_INTERLACE_MASK;
1277
1278         return 0;
1279 }
1280
1281 /* Program a (non-VGA) video mode. */
1282 int intelfbhw_program_mode(struct intelfb_info *dinfo,
1283                            const struct intelfb_hwstate *hw, int blank)
1284 {
1285         u32 tmp;
1286         const u32 *dpll, *fp0, *fp1, *pipe_conf;
1287         const u32 *hs, *ht, *hb, *vs, *vt, *vb, *ss;
1288         u32 dpll_reg, fp0_reg, fp1_reg, pipe_conf_reg, pipe_stat_reg;
1289         u32 hsync_reg, htotal_reg, hblank_reg;
1290         u32 vsync_reg, vtotal_reg, vblank_reg;
1291         u32 src_size_reg;
1292         u32 count, tmp_val[3];
1293
1294         /* Assume single pipe */
1295
1296 #if VERBOSE > 0
1297         DBG_MSG("intelfbhw_program_mode\n");
1298 #endif
1299
1300         /* Disable VGA */
1301         tmp = INREG(VGACNTRL);
1302         tmp |= VGA_DISABLE;
1303         OUTREG(VGACNTRL, tmp);
1304
1305         dinfo->pipe = intelfbhw_active_pipe(hw);
1306
1307         if (dinfo->pipe == PIPE_B) {
1308                 dpll = &hw->dpll_b;
1309                 fp0 = &hw->fpb0;
1310                 fp1 = &hw->fpb1;
1311                 pipe_conf = &hw->pipe_b_conf;
1312                 hs = &hw->hsync_b;
1313                 hb = &hw->hblank_b;
1314                 ht = &hw->htotal_b;
1315                 vs = &hw->vsync_b;
1316                 vb = &hw->vblank_b;
1317                 vt = &hw->vtotal_b;
1318                 ss = &hw->src_size_b;
1319                 dpll_reg = DPLL_B;
1320                 fp0_reg = FPB0;
1321                 fp1_reg = FPB1;
1322                 pipe_conf_reg = PIPEBCONF;
1323                 pipe_stat_reg = PIPEBSTAT;
1324                 hsync_reg = HSYNC_B;
1325                 htotal_reg = HTOTAL_B;
1326                 hblank_reg = HBLANK_B;
1327                 vsync_reg = VSYNC_B;
1328                 vtotal_reg = VTOTAL_B;
1329                 vblank_reg = VBLANK_B;
1330                 src_size_reg = SRC_SIZE_B;
1331         } else {
1332                 dpll = &hw->dpll_a;
1333                 fp0 = &hw->fpa0;
1334                 fp1 = &hw->fpa1;
1335                 pipe_conf = &hw->pipe_a_conf;
1336                 hs = &hw->hsync_a;
1337                 hb = &hw->hblank_a;
1338                 ht = &hw->htotal_a;
1339                 vs = &hw->vsync_a;
1340                 vb = &hw->vblank_a;
1341                 vt = &hw->vtotal_a;
1342                 ss = &hw->src_size_a;
1343                 dpll_reg = DPLL_A;
1344                 fp0_reg = FPA0;
1345                 fp1_reg = FPA1;
1346                 pipe_conf_reg = PIPEACONF;
1347                 pipe_stat_reg = PIPEASTAT;
1348                 hsync_reg = HSYNC_A;
1349                 htotal_reg = HTOTAL_A;
1350                 hblank_reg = HBLANK_A;
1351                 vsync_reg = VSYNC_A;
1352                 vtotal_reg = VTOTAL_A;
1353                 vblank_reg = VBLANK_A;
1354                 src_size_reg = SRC_SIZE_A;
1355         }
1356
1357         /* turn off pipe */
1358         tmp = INREG(pipe_conf_reg);
1359         tmp &= ~PIPECONF_ENABLE;
1360         OUTREG(pipe_conf_reg, tmp);
1361
1362         count = 0;
1363         do {
1364                 tmp_val[count % 3] = INREG(PIPEA_DSL);
1365                 if ((tmp_val[0] == tmp_val[1]) && (tmp_val[1] == tmp_val[2]))
1366                         break;
1367                 count++;
1368                 udelay(1);
1369                 if (count % 200 == 0) {
1370                         tmp = INREG(pipe_conf_reg);
1371                         tmp &= ~PIPECONF_ENABLE;
1372                         OUTREG(pipe_conf_reg, tmp);
1373                 }
1374         } while (count < 2000);
1375
1376         OUTREG(ADPA, INREG(ADPA) & ~ADPA_DAC_ENABLE);
1377
1378         /* Disable planes A and B. */
1379         tmp = INREG(DSPACNTR);
1380         tmp &= ~DISPPLANE_PLANE_ENABLE;
1381         OUTREG(DSPACNTR, tmp);
1382         tmp = INREG(DSPBCNTR);
1383         tmp &= ~DISPPLANE_PLANE_ENABLE;
1384         OUTREG(DSPBCNTR, tmp);
1385
1386         /* Wait for vblank. For now, just wait for a 50Hz cycle (20ms)) */
1387         mdelay(20);
1388
1389         OUTREG(DVOB, INREG(DVOB) & ~PORT_ENABLE);
1390         OUTREG(DVOC, INREG(DVOC) & ~PORT_ENABLE);
1391         OUTREG(ADPA, INREG(ADPA) & ~ADPA_DAC_ENABLE);
1392
1393         /* Disable Sync */
1394         tmp = INREG(ADPA);
1395         tmp &= ~ADPA_DPMS_CONTROL_MASK;
1396         tmp |= ADPA_DPMS_D3;
1397         OUTREG(ADPA, tmp);
1398
1399         /* do some funky magic - xyzzy */
1400         OUTREG(0x61204, 0xabcd0000);
1401
1402         /* turn off PLL */
1403         tmp = INREG(dpll_reg);
1404         tmp &= ~DPLL_VCO_ENABLE;
1405         OUTREG(dpll_reg, tmp);
1406
1407         /* Set PLL parameters */
1408         OUTREG(fp0_reg, *fp0);
1409         OUTREG(fp1_reg, *fp1);
1410
1411         /* Enable PLL */
1412         OUTREG(dpll_reg, *dpll);
1413
1414         /* Set DVOs B/C */
1415         OUTREG(DVOB, hw->dvob);
1416         OUTREG(DVOC, hw->dvoc);
1417
1418         /* undo funky magic */
1419         OUTREG(0x61204, 0x00000000);
1420
1421         /* Set ADPA */
1422         OUTREG(ADPA, INREG(ADPA) | ADPA_DAC_ENABLE);
1423         OUTREG(ADPA, (hw->adpa & ~(ADPA_DPMS_CONTROL_MASK)) | ADPA_DPMS_D3);
1424
1425         /* Set pipe parameters */
1426         OUTREG(hsync_reg, *hs);
1427         OUTREG(hblank_reg, *hb);
1428         OUTREG(htotal_reg, *ht);
1429         OUTREG(vsync_reg, *vs);
1430         OUTREG(vblank_reg, *vb);
1431         OUTREG(vtotal_reg, *vt);
1432         OUTREG(src_size_reg, *ss);
1433
1434         switch (dinfo->info->var.vmode & (FB_VMODE_INTERLACED |
1435                                           FB_VMODE_ODD_FLD_FIRST)) {
1436         case FB_VMODE_INTERLACED | FB_VMODE_ODD_FLD_FIRST:
1437                 OUTREG(pipe_stat_reg, 0xFFFF | PIPESTAT_FLD_EVT_ODD_EN);
1438                 break;
1439         case FB_VMODE_INTERLACED: /* even lines first */
1440                 OUTREG(pipe_stat_reg, 0xFFFF | PIPESTAT_FLD_EVT_EVEN_EN);
1441                 break;
1442         default:                /* non-interlaced */
1443                 OUTREG(pipe_stat_reg, 0xFFFF); /* clear all status bits only */
1444         }
1445         /* Enable pipe */
1446         OUTREG(pipe_conf_reg, *pipe_conf | PIPECONF_ENABLE);
1447
1448         /* Enable sync */
1449         tmp = INREG(ADPA);
1450         tmp &= ~ADPA_DPMS_CONTROL_MASK;
1451         tmp |= ADPA_DPMS_D0;
1452         OUTREG(ADPA, tmp);
1453
1454         /* setup display plane */
1455         if (dinfo->pdev->device == PCI_DEVICE_ID_INTEL_830M) {
1456                 /*
1457                  *      i830M errata: the display plane must be enabled
1458                  *      to allow writes to the other bits in the plane
1459                  *      control register.
1460                  */
1461                 tmp = INREG(DSPACNTR);
1462                 if ((tmp & DISPPLANE_PLANE_ENABLE) != DISPPLANE_PLANE_ENABLE) {
1463                         tmp |= DISPPLANE_PLANE_ENABLE;
1464                         OUTREG(DSPACNTR, tmp);
1465                         OUTREG(DSPACNTR,
1466                                hw->disp_a_ctrl|DISPPLANE_PLANE_ENABLE);
1467                         mdelay(1);
1468                 }
1469         }
1470
1471         OUTREG(DSPACNTR, hw->disp_a_ctrl & ~DISPPLANE_PLANE_ENABLE);
1472         OUTREG(DSPASTRIDE, hw->disp_a_stride);
1473         OUTREG(DSPABASE, hw->disp_a_base);
1474
1475         /* Enable plane */
1476         if (!blank) {
1477                 tmp = INREG(DSPACNTR);
1478                 tmp |= DISPPLANE_PLANE_ENABLE;
1479                 OUTREG(DSPACNTR, tmp);
1480                 OUTREG(DSPABASE, hw->disp_a_base);
1481         }
1482
1483         return 0;
1484 }
1485
1486 /* forward declarations */
1487 static void refresh_ring(struct intelfb_info *dinfo);
1488 static void reset_state(struct intelfb_info *dinfo);
1489 static void do_flush(struct intelfb_info *dinfo);
1490
1491 static  u32 get_ring_space(struct intelfb_info *dinfo)
1492 {
1493         u32 ring_space;
1494
1495         if (dinfo->ring_tail >= dinfo->ring_head)
1496                 ring_space = dinfo->ring.size -
1497                         (dinfo->ring_tail - dinfo->ring_head);
1498         else
1499                 ring_space = dinfo->ring_head - dinfo->ring_tail;
1500
1501         if (ring_space > RING_MIN_FREE)
1502                 ring_space -= RING_MIN_FREE;
1503         else
1504                 ring_space = 0;
1505
1506         return ring_space;
1507 }
1508
1509 static int wait_ring(struct intelfb_info *dinfo, int n)
1510 {
1511         int i = 0;
1512         unsigned long end;
1513         u32 last_head = INREG(PRI_RING_HEAD) & RING_HEAD_MASK;
1514
1515 #if VERBOSE > 0
1516         DBG_MSG("wait_ring: %d\n", n);
1517 #endif
1518
1519         end = jiffies + (HZ * 3);
1520         while (dinfo->ring_space < n) {
1521                 dinfo->ring_head = INREG(PRI_RING_HEAD) & RING_HEAD_MASK;
1522                 dinfo->ring_space = get_ring_space(dinfo);
1523
1524                 if (dinfo->ring_head != last_head) {
1525                         end = jiffies + (HZ * 3);
1526                         last_head = dinfo->ring_head;
1527                 }
1528                 i++;
1529                 if (time_before(end, jiffies)) {
1530                         if (!i) {
1531                                 /* Try again */
1532                                 reset_state(dinfo);
1533                                 refresh_ring(dinfo);
1534                                 do_flush(dinfo);
1535                                 end = jiffies + (HZ * 3);
1536                                 i = 1;
1537                         } else {
1538                                 WRN_MSG("ring buffer : space: %d wanted %d\n",
1539                                         dinfo->ring_space, n);
1540                                 WRN_MSG("lockup - turning off hardware "
1541                                         "acceleration\n");
1542                                 dinfo->ring_lockup = 1;
1543                                 break;
1544                         }
1545                 }
1546                 udelay(1);
1547         }
1548         return i;
1549 }
1550
1551 static void do_flush(struct intelfb_info *dinfo)
1552 {
1553         START_RING(2);
1554         OUT_RING(MI_FLUSH | MI_WRITE_DIRTY_STATE | MI_INVALIDATE_MAP_CACHE);
1555         OUT_RING(MI_NOOP);
1556         ADVANCE_RING();
1557 }
1558
1559 void intelfbhw_do_sync(struct intelfb_info *dinfo)
1560 {
1561 #if VERBOSE > 0
1562         DBG_MSG("intelfbhw_do_sync\n");
1563 #endif
1564
1565         if (!dinfo->accel)
1566                 return;
1567
1568         /*
1569          * Send a flush, then wait until the ring is empty.  This is what
1570          * the XFree86 driver does, and actually it doesn't seem a lot worse
1571          * than the recommended method (both have problems).
1572          */
1573         do_flush(dinfo);
1574         wait_ring(dinfo, dinfo->ring.size - RING_MIN_FREE);
1575         dinfo->ring_space = dinfo->ring.size - RING_MIN_FREE;
1576 }
1577
1578 static void refresh_ring(struct intelfb_info *dinfo)
1579 {
1580 #if VERBOSE > 0
1581         DBG_MSG("refresh_ring\n");
1582 #endif
1583
1584         dinfo->ring_head = INREG(PRI_RING_HEAD) & RING_HEAD_MASK;
1585         dinfo->ring_tail = INREG(PRI_RING_TAIL) & RING_TAIL_MASK;
1586         dinfo->ring_space = get_ring_space(dinfo);
1587 }
1588
1589 static void reset_state(struct intelfb_info *dinfo)
1590 {
1591         int i;
1592         u32 tmp;
1593
1594 #if VERBOSE > 0
1595         DBG_MSG("reset_state\n");
1596 #endif
1597
1598         for (i = 0; i < FENCE_NUM; i++)
1599                 OUTREG(FENCE + (i << 2), 0);
1600
1601         /* Flush the ring buffer if it's enabled. */
1602         tmp = INREG(PRI_RING_LENGTH);
1603         if (tmp & RING_ENABLE) {
1604 #if VERBOSE > 0
1605                 DBG_MSG("reset_state: ring was enabled\n");
1606 #endif
1607                 refresh_ring(dinfo);
1608                 intelfbhw_do_sync(dinfo);
1609                 DO_RING_IDLE();
1610         }
1611
1612         OUTREG(PRI_RING_LENGTH, 0);
1613         OUTREG(PRI_RING_HEAD, 0);
1614         OUTREG(PRI_RING_TAIL, 0);
1615         OUTREG(PRI_RING_START, 0);
1616 }
1617
1618 /* Stop the 2D engine, and turn off the ring buffer. */
1619 void intelfbhw_2d_stop(struct intelfb_info *dinfo)
1620 {
1621 #if VERBOSE > 0
1622         DBG_MSG("intelfbhw_2d_stop: accel: %d, ring_active: %d\n",
1623                 dinfo->accel, dinfo->ring_active);
1624 #endif
1625
1626         if (!dinfo->accel)
1627                 return;
1628
1629         dinfo->ring_active = 0;
1630         reset_state(dinfo);
1631 }
1632
1633 /*
1634  * Enable the ring buffer, and initialise the 2D engine.
1635  * It is assumed that the graphics engine has been stopped by previously
1636  * calling intelfb_2d_stop().
1637  */
1638 void intelfbhw_2d_start(struct intelfb_info *dinfo)
1639 {
1640 #if VERBOSE > 0
1641         DBG_MSG("intelfbhw_2d_start: accel: %d, ring_active: %d\n",
1642                 dinfo->accel, dinfo->ring_active);
1643 #endif
1644
1645         if (!dinfo->accel)
1646                 return;
1647
1648         /* Initialise the primary ring buffer. */
1649         OUTREG(PRI_RING_LENGTH, 0);
1650         OUTREG(PRI_RING_TAIL, 0);
1651         OUTREG(PRI_RING_HEAD, 0);
1652
1653         OUTREG(PRI_RING_START, dinfo->ring.physical & RING_START_MASK);
1654         OUTREG(PRI_RING_LENGTH,
1655                 ((dinfo->ring.size - GTT_PAGE_SIZE) & RING_LENGTH_MASK) |
1656                 RING_NO_REPORT | RING_ENABLE);
1657         refresh_ring(dinfo);
1658         dinfo->ring_active = 1;
1659 }
1660
1661 /* 2D fillrect (solid fill or invert) */
1662 void intelfbhw_do_fillrect(struct intelfb_info *dinfo, u32 x, u32 y, u32 w,
1663                            u32 h, u32 color, u32 pitch, u32 bpp, u32 rop)
1664 {
1665         u32 br00, br09, br13, br14, br16;
1666
1667 #if VERBOSE > 0
1668         DBG_MSG("intelfbhw_do_fillrect: (%d,%d) %dx%d, c 0x%06x, p %d bpp %d, "
1669                 "rop 0x%02x\n", x, y, w, h, color, pitch, bpp, rop);
1670 #endif
1671
1672         br00 = COLOR_BLT_CMD;
1673         br09 = dinfo->fb_start + (y * pitch + x * (bpp / 8));
1674         br13 = (rop << ROP_SHIFT) | pitch;
1675         br14 = (h << HEIGHT_SHIFT) | ((w * (bpp / 8)) << WIDTH_SHIFT);
1676         br16 = color;
1677
1678         switch (bpp) {
1679         case 8:
1680                 br13 |= COLOR_DEPTH_8;
1681                 break;
1682         case 16:
1683                 br13 |= COLOR_DEPTH_16;
1684                 break;
1685         case 32:
1686                 br13 |= COLOR_DEPTH_32;
1687                 br00 |= WRITE_ALPHA | WRITE_RGB;
1688                 break;
1689         }
1690
1691         START_RING(6);
1692         OUT_RING(br00);
1693         OUT_RING(br13);
1694         OUT_RING(br14);
1695         OUT_RING(br09);
1696         OUT_RING(br16);
1697         OUT_RING(MI_NOOP);
1698         ADVANCE_RING();
1699
1700 #if VERBOSE > 0
1701         DBG_MSG("ring = 0x%08x, 0x%08x (%d)\n", dinfo->ring_head,
1702                 dinfo->ring_tail, dinfo->ring_space);
1703 #endif
1704 }
1705
1706 void
1707 intelfbhw_do_bitblt(struct intelfb_info *dinfo, u32 curx, u32 cury,
1708                     u32 dstx, u32 dsty, u32 w, u32 h, u32 pitch, u32 bpp)
1709 {
1710         u32 br00, br09, br11, br12, br13, br22, br23, br26;
1711
1712 #if VERBOSE > 0
1713         DBG_MSG("intelfbhw_do_bitblt: (%d,%d)->(%d,%d) %dx%d, p %d bpp %d\n",
1714                 curx, cury, dstx, dsty, w, h, pitch, bpp);
1715 #endif
1716
1717         br00 = XY_SRC_COPY_BLT_CMD;
1718         br09 = dinfo->fb_start;
1719         br11 = (pitch << PITCH_SHIFT);
1720         br12 = dinfo->fb_start;
1721         br13 = (SRC_ROP_GXCOPY << ROP_SHIFT) | (pitch << PITCH_SHIFT);
1722         br22 = (dstx << WIDTH_SHIFT) | (dsty << HEIGHT_SHIFT);
1723         br23 = ((dstx + w) << WIDTH_SHIFT) |
1724                ((dsty + h) << HEIGHT_SHIFT);
1725         br26 = (curx << WIDTH_SHIFT) | (cury << HEIGHT_SHIFT);
1726
1727         switch (bpp) {
1728         case 8:
1729                 br13 |= COLOR_DEPTH_8;
1730                 break;
1731         case 16:
1732                 br13 |= COLOR_DEPTH_16;
1733                 break;
1734         case 32:
1735                 br13 |= COLOR_DEPTH_32;
1736                 br00 |= WRITE_ALPHA | WRITE_RGB;
1737                 break;
1738         }
1739
1740         START_RING(8);
1741         OUT_RING(br00);
1742         OUT_RING(br13);
1743         OUT_RING(br22);
1744         OUT_RING(br23);
1745         OUT_RING(br09);
1746         OUT_RING(br26);
1747         OUT_RING(br11);
1748         OUT_RING(br12);
1749         ADVANCE_RING();
1750 }
1751
1752 int intelfbhw_do_drawglyph(struct intelfb_info *dinfo, u32 fg, u32 bg, u32 w,
1753                            u32 h, const u8* cdat, u32 x, u32 y, u32 pitch,
1754                            u32 bpp)
1755 {
1756         int nbytes, ndwords, pad, tmp;
1757         u32 br00, br09, br13, br18, br19, br22, br23;
1758         int dat, ix, iy, iw;
1759         int i, j;
1760
1761 #if VERBOSE > 0
1762         DBG_MSG("intelfbhw_do_drawglyph: (%d,%d) %dx%d\n", x, y, w, h);
1763 #endif
1764
1765         /* size in bytes of a padded scanline */
1766         nbytes = ROUND_UP_TO(w, 16) / 8;
1767
1768         /* Total bytes of padded scanline data to write out. */
1769         nbytes = nbytes * h;
1770
1771         /*
1772          * Check if the glyph data exceeds the immediate mode limit.
1773          * It would take a large font (1K pixels) to hit this limit.
1774          */
1775         if (nbytes > MAX_MONO_IMM_SIZE)
1776                 return 0;
1777
1778         /* Src data is packaged a dword (32-bit) at a time. */
1779         ndwords = ROUND_UP_TO(nbytes, 4) / 4;
1780
1781         /*
1782          * Ring has to be padded to a quad word. But because the command starts
1783            with 7 bytes, pad only if there is an even number of ndwords
1784          */
1785         pad = !(ndwords % 2);
1786
1787         tmp = (XY_MONO_SRC_IMM_BLT_CMD & DW_LENGTH_MASK) + ndwords;
1788         br00 = (XY_MONO_SRC_IMM_BLT_CMD & ~DW_LENGTH_MASK) | tmp;
1789         br09 = dinfo->fb_start;
1790         br13 = (SRC_ROP_GXCOPY << ROP_SHIFT) | (pitch << PITCH_SHIFT);
1791         br18 = bg;
1792         br19 = fg;
1793         br22 = (x << WIDTH_SHIFT) | (y << HEIGHT_SHIFT);
1794         br23 = ((x + w) << WIDTH_SHIFT) | ((y + h) << HEIGHT_SHIFT);
1795
1796         switch (bpp) {
1797         case 8:
1798                 br13 |= COLOR_DEPTH_8;
1799                 break;
1800         case 16:
1801                 br13 |= COLOR_DEPTH_16;
1802                 break;
1803         case 32:
1804                 br13 |= COLOR_DEPTH_32;
1805                 br00 |= WRITE_ALPHA | WRITE_RGB;
1806                 break;
1807         }
1808
1809         START_RING(8 + ndwords);
1810         OUT_RING(br00);
1811         OUT_RING(br13);
1812         OUT_RING(br22);
1813         OUT_RING(br23);
1814         OUT_RING(br09);
1815         OUT_RING(br18);
1816         OUT_RING(br19);
1817         ix = iy = 0;
1818         iw = ROUND_UP_TO(w, 8) / 8;
1819         while (ndwords--) {
1820                 dat = 0;
1821                 for (j = 0; j < 2; ++j) {
1822                         for (i = 0; i < 2; ++i) {
1823                                 if (ix != iw || i == 0)
1824                                         dat |= cdat[iy*iw + ix++] << (i+j*2)*8;
1825                         }
1826                         if (ix == iw && iy != (h-1)) {
1827                                 ix = 0;
1828                                 ++iy;
1829                         }
1830                 }
1831                 OUT_RING(dat);
1832         }
1833         if (pad)
1834                 OUT_RING(MI_NOOP);
1835         ADVANCE_RING();
1836
1837         return 1;
1838 }
1839
1840 /* HW cursor functions. */
1841 void intelfbhw_cursor_init(struct intelfb_info *dinfo)
1842 {
1843         u32 tmp;
1844
1845 #if VERBOSE > 0
1846         DBG_MSG("intelfbhw_cursor_init\n");
1847 #endif
1848
1849         if (dinfo->mobile || IS_I9XX(dinfo)) {
1850                 if (!dinfo->cursor.physical)
1851                         return;
1852                 tmp = INREG(CURSOR_A_CONTROL);
1853                 tmp &= ~(CURSOR_MODE_MASK | CURSOR_MOBILE_GAMMA_ENABLE |
1854                          CURSOR_MEM_TYPE_LOCAL |
1855                          (1 << CURSOR_PIPE_SELECT_SHIFT));
1856                 tmp |= CURSOR_MODE_DISABLE;
1857                 OUTREG(CURSOR_A_CONTROL, tmp);
1858                 OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.physical);
1859         } else {
1860                 tmp = INREG(CURSOR_CONTROL);
1861                 tmp &= ~(CURSOR_FORMAT_MASK | CURSOR_GAMMA_ENABLE |
1862                          CURSOR_ENABLE | CURSOR_STRIDE_MASK);
1863                 tmp = CURSOR_FORMAT_3C;
1864                 OUTREG(CURSOR_CONTROL, tmp);
1865                 OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.offset << 12);
1866                 tmp = (64 << CURSOR_SIZE_H_SHIFT) |
1867                       (64 << CURSOR_SIZE_V_SHIFT);
1868                 OUTREG(CURSOR_SIZE, tmp);
1869         }
1870 }
1871
1872 void intelfbhw_cursor_hide(struct intelfb_info *dinfo)
1873 {
1874         u32 tmp;
1875
1876 #if VERBOSE > 0
1877         DBG_MSG("intelfbhw_cursor_hide\n");
1878 #endif
1879
1880         dinfo->cursor_on = 0;
1881         if (dinfo->mobile || IS_I9XX(dinfo)) {
1882                 if (!dinfo->cursor.physical)
1883                         return;
1884                 tmp = INREG(CURSOR_A_CONTROL);
1885                 tmp &= ~CURSOR_MODE_MASK;
1886                 tmp |= CURSOR_MODE_DISABLE;
1887                 OUTREG(CURSOR_A_CONTROL, tmp);
1888                 /* Flush changes */
1889                 OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.physical);
1890         } else {
1891                 tmp = INREG(CURSOR_CONTROL);
1892                 tmp &= ~CURSOR_ENABLE;
1893                 OUTREG(CURSOR_CONTROL, tmp);
1894         }
1895 }
1896
1897 void intelfbhw_cursor_show(struct intelfb_info *dinfo)
1898 {
1899         u32 tmp;
1900
1901 #if VERBOSE > 0
1902         DBG_MSG("intelfbhw_cursor_show\n");
1903 #endif
1904
1905         dinfo->cursor_on = 1;
1906
1907         if (dinfo->cursor_blanked)
1908                 return;
1909
1910         if (dinfo->mobile || IS_I9XX(dinfo)) {
1911                 if (!dinfo->cursor.physical)
1912                         return;
1913                 tmp = INREG(CURSOR_A_CONTROL);
1914                 tmp &= ~CURSOR_MODE_MASK;
1915                 tmp |= CURSOR_MODE_64_4C_AX;
1916                 OUTREG(CURSOR_A_CONTROL, tmp);
1917                 /* Flush changes */
1918                 OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.physical);
1919         } else {
1920                 tmp = INREG(CURSOR_CONTROL);
1921                 tmp |= CURSOR_ENABLE;
1922                 OUTREG(CURSOR_CONTROL, tmp);
1923         }
1924 }
1925
1926 void intelfbhw_cursor_setpos(struct intelfb_info *dinfo, int x, int y)
1927 {
1928         u32 tmp;
1929
1930 #if VERBOSE > 0
1931         DBG_MSG("intelfbhw_cursor_setpos: (%d, %d)\n", x, y);
1932 #endif
1933
1934         /*
1935          * Sets the position. The coordinates are assumed to already
1936          * have any offset adjusted. Assume that the cursor is never
1937          * completely off-screen, and that x, y are always >= 0.
1938          */
1939
1940         tmp = ((x & CURSOR_POS_MASK) << CURSOR_X_SHIFT) |
1941               ((y & CURSOR_POS_MASK) << CURSOR_Y_SHIFT);
1942         OUTREG(CURSOR_A_POSITION, tmp);
1943
1944         if (IS_I9XX(dinfo))
1945                 OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.physical);
1946 }
1947
1948 void intelfbhw_cursor_setcolor(struct intelfb_info *dinfo, u32 bg, u32 fg)
1949 {
1950 #if VERBOSE > 0
1951         DBG_MSG("intelfbhw_cursor_setcolor\n");
1952 #endif
1953
1954         OUTREG(CURSOR_A_PALETTE0, bg & CURSOR_PALETTE_MASK);
1955         OUTREG(CURSOR_A_PALETTE1, fg & CURSOR_PALETTE_MASK);
1956         OUTREG(CURSOR_A_PALETTE2, fg & CURSOR_PALETTE_MASK);
1957         OUTREG(CURSOR_A_PALETTE3, bg & CURSOR_PALETTE_MASK);
1958 }
1959
1960 void intelfbhw_cursor_load(struct intelfb_info *dinfo, int width, int height,
1961                            u8 *data)
1962 {
1963         u8 __iomem *addr = (u8 __iomem *)dinfo->cursor.virtual;
1964         int i, j, w = width / 8;
1965         int mod = width % 8, t_mask, d_mask;
1966
1967 #if VERBOSE > 0
1968         DBG_MSG("intelfbhw_cursor_load\n");
1969 #endif
1970
1971         if (!dinfo->cursor.virtual)
1972                 return;
1973
1974         t_mask = 0xff >> mod;
1975         d_mask = ~(0xff >> mod);
1976         for (i = height; i--; ) {
1977                 for (j = 0; j < w; j++) {
1978                         writeb(0x00, addr + j);
1979                         writeb(*(data++), addr + j+8);
1980                 }
1981                 if (mod) {
1982                         writeb(t_mask, addr + j);
1983                         writeb(*(data++) & d_mask, addr + j+8);
1984                 }
1985                 addr += 16;
1986         }
1987 }
1988
1989 void intelfbhw_cursor_reset(struct intelfb_info *dinfo)
1990 {
1991         u8 __iomem *addr = (u8 __iomem *)dinfo->cursor.virtual;
1992         int i, j;
1993
1994 #if VERBOSE > 0
1995         DBG_MSG("intelfbhw_cursor_reset\n");
1996 #endif
1997
1998         if (!dinfo->cursor.virtual)
1999                 return;
2000
2001         for (i = 64; i--; ) {
2002                 for (j = 0; j < 8; j++) {
2003                         writeb(0xff, addr + j+0);
2004                         writeb(0x00, addr + j+8);
2005                 }
2006                 addr += 16;
2007         }
2008 }
2009
2010 static irqreturn_t intelfbhw_irq(int irq, void *dev_id)
2011 {
2012         u16 tmp;
2013         struct intelfb_info *dinfo = dev_id;
2014
2015         spin_lock(&dinfo->int_lock);
2016
2017         tmp = INREG16(IIR);
2018         if (dinfo->info->var.vmode & FB_VMODE_INTERLACED)
2019                 tmp &= PIPE_A_EVENT_INTERRUPT;
2020         else
2021                 tmp &= VSYNC_PIPE_A_INTERRUPT; /* non-interlaced */
2022
2023         if (tmp == 0) {
2024                 spin_unlock(&dinfo->int_lock);
2025                 return IRQ_RETVAL(0); /* not us */
2026         }
2027
2028         /* clear status bits 0-15 ASAP and don't touch bits 16-31 */
2029         OUTREG(PIPEASTAT, INREG(PIPEASTAT));
2030
2031         OUTREG16(IIR, tmp);
2032         if (dinfo->vsync.pan_display) {
2033                 dinfo->vsync.pan_display = 0;
2034                 OUTREG(DSPABASE, dinfo->vsync.pan_offset);
2035         }
2036
2037         dinfo->vsync.count++;
2038         wake_up_interruptible(&dinfo->vsync.wait);
2039
2040         spin_unlock(&dinfo->int_lock);
2041
2042         return IRQ_RETVAL(1);
2043 }
2044
2045 int intelfbhw_enable_irq(struct intelfb_info *dinfo)
2046 {
2047         u16 tmp;
2048         if (!test_and_set_bit(0, &dinfo->irq_flags)) {
2049                 if (request_irq(dinfo->pdev->irq, intelfbhw_irq, IRQF_SHARED,
2050                                 "intelfb", dinfo)) {
2051                         clear_bit(0, &dinfo->irq_flags);
2052                         return -EINVAL;
2053                 }
2054
2055                 spin_lock_irq(&dinfo->int_lock);
2056                 OUTREG16(HWSTAM, 0xfffe); /* i830 DRM uses ffff */
2057                 OUTREG16(IMR, 0);
2058         } else
2059                 spin_lock_irq(&dinfo->int_lock);
2060
2061         if (dinfo->info->var.vmode & FB_VMODE_INTERLACED)
2062                 tmp = PIPE_A_EVENT_INTERRUPT;
2063         else
2064                 tmp = VSYNC_PIPE_A_INTERRUPT; /* non-interlaced */
2065         if (tmp != INREG16(IER)) {
2066                 DBG_MSG("changing IER to 0x%X\n", tmp);
2067                 OUTREG16(IER, tmp);
2068         }
2069
2070         spin_unlock_irq(&dinfo->int_lock);
2071         return 0;
2072 }
2073
2074 void intelfbhw_disable_irq(struct intelfb_info *dinfo)
2075 {
2076         if (test_and_clear_bit(0, &dinfo->irq_flags)) {
2077                 if (dinfo->vsync.pan_display) {
2078                         dinfo->vsync.pan_display = 0;
2079                         OUTREG(DSPABASE, dinfo->vsync.pan_offset);
2080                 }
2081                 spin_lock_irq(&dinfo->int_lock);
2082                 OUTREG16(HWSTAM, 0xffff);
2083                 OUTREG16(IMR, 0xffff);
2084                 OUTREG16(IER, 0x0);
2085
2086                 OUTREG16(IIR, INREG16(IIR)); /* clear IRQ requests */
2087                 spin_unlock_irq(&dinfo->int_lock);
2088
2089                 free_irq(dinfo->pdev->irq, dinfo);
2090         }
2091 }
2092
2093 int intelfbhw_wait_for_vsync(struct intelfb_info *dinfo, u32 pipe)
2094 {
2095         struct intelfb_vsync *vsync;
2096         unsigned int count;
2097         int ret;
2098
2099         switch (pipe) {
2100                 case 0:
2101                         vsync = &dinfo->vsync;
2102                         break;
2103                 default:
2104                         return -ENODEV;
2105         }
2106
2107         ret = intelfbhw_enable_irq(dinfo);
2108         if (ret)
2109                 return ret;
2110
2111         count = vsync->count;
2112         ret = wait_event_interruptible_timeout(vsync->wait,
2113                                                count != vsync->count, HZ / 10);
2114         if (ret < 0)
2115                 return ret;
2116         if (ret == 0) {
2117                 DBG_MSG("wait_for_vsync timed out!\n");
2118                 return -ETIMEDOUT;
2119         }
2120
2121         return 0;
2122 }