SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/video/intelfb/intelfbhw.c

   1 /*
   2  * intelfb
   3  *
   4  * Linux framebuffer driver for Intel(R) 865G integrated graphics chips.
   5  *
   6  * Copyright © 2002, 2003 David Dawes <dawes@xfree86.org>
   7  *                   2004 Sylvain Meyer
   8  *
   9  * This driver consists of two parts.  The first part (intelfbdrv.c) provides
  10  * the basic fbdev interfaces, is derived in part from the radeonfb and
  11  * vesafb drivers, and is covered by the GPL.  The second part (intelfbhw.c)
  12  * provides the code to program the hardware.  Most of it is derived from
  13  * the i810/i830 XFree86 driver.  The HW-specific code is covered here
  14  * under a dual license (GPL and MIT/XFree86 license).
  15  *
  16  * Author: David Dawes
  17  *
  18  */
  19
  20 /* $DHD: intelfb/intelfbhw.c,v 1.9 2003/06/27 15:06:25 dawes Exp $ */
  21
  22 #include <linux/module.h>
  23 #include <linux/kernel.h>
  24 #include <linux/errno.h>
  25 #include <linux/string.h>
  26 #include <linux/mm.h>
  27 #include <linux/slab.h>
  28 #include <linux/delay.h>
  29 #include <linux/fb.h>
  30 #include <linux/ioport.h>
  31 #include <linux/init.h>
  32 #include <linux/pci.h>
  33 #include <linux/vmalloc.h>
  34 #include <linux/pagemap.h>
  35 #include <linux/interrupt.h>
  36
  37 #include <asm/io.h>
  38
  39 #include "intelfb.h"
  40 #include "intelfbhw.h"
  41
  42 struct pll_min_max {
  43         int min_m, max_m, min_m1, max_m1;
  44         int min_m2, max_m2, min_n, max_n;
  45         int min_p, max_p, min_p1, max_p1;
  46         int min_vco, max_vco, p_transition_clk, ref_clk;
  47         int p_inc_lo, p_inc_hi;
  48 };
  49
  50 #define PLLS_I8xx 0
  51 #define PLLS_I9xx 1
  52 #define PLLS_MAX 2
  53
  54 static struct pll_min_max plls[PLLS_MAX] = {
  55         { 108, 140, 18, 26,
  56           6, 16, 3, 16,
  57           4, 128, 0, 31,
  58           930000, 1400000, 165000, 48000,
  59           4, 2 }, //I8xx
  60
  61         { 75, 120, 10, 20,
  62           5, 9, 4, 7,
  63           5, 80, 1, 8,
  64           1400000, 2800000, 200000, 96000,
  65           10, 5 }  //I9xx
  66 };
  67
  68 int
  69 intelfbhw_get_chipset(struct pci_dev *pdev, struct intelfb_info *dinfo)
  70 {
  71         u32 tmp;
  72         if (!pdev || !dinfo)
  73                 return 1;
  74
  75         switch (pdev->device) {
  76         case PCI_DEVICE_ID_INTEL_830M:
  77                 dinfo->name = "Intel(R) 830M";
  78                 dinfo->chipset = INTEL_830M;
  79                 dinfo->mobile = 1;
  80                 dinfo->pll_index = PLLS_I8xx;
  81                 return 0;
  82         case PCI_DEVICE_ID_INTEL_845G:
  83                 dinfo->name = "Intel(R) 845G";
  84                 dinfo->chipset = INTEL_845G;
  85                 dinfo->mobile = 0;
  86                 dinfo->pll_index = PLLS_I8xx;
  87                 return 0;
  88         case PCI_DEVICE_ID_INTEL_85XGM:
  89                 tmp = 0;
  90                 dinfo->mobile = 1;
  91                 dinfo->pll_index = PLLS_I8xx;
  92                 pci_read_config_dword(pdev, INTEL_85X_CAPID, &tmp);
  93                 switch ((tmp >> INTEL_85X_VARIANT_SHIFT) &
  94                         INTEL_85X_VARIANT_MASK) {
  95                 case INTEL_VAR_855GME:
  96                         dinfo->name = "Intel(R) 855GME";
  97                         dinfo->chipset = INTEL_855GME;
  98                         return 0;
  99                 case INTEL_VAR_855GM:
 100                         dinfo->name = "Intel(R) 855GM";
 101                         dinfo->chipset = INTEL_855GM;
 102                         return 0;
 103                 case INTEL_VAR_852GME:
 104                         dinfo->name = "Intel(R) 852GME";
 105                         dinfo->chipset = INTEL_852GME;
 106                         return 0;
 107                 case INTEL_VAR_852GM:
 108                         dinfo->name = "Intel(R) 852GM";
 109                         dinfo->chipset = INTEL_852GM;
 110                         return 0;
 111                 default:
 112                         dinfo->name = "Intel(R) 852GM/855GM";
 113                         dinfo->chipset = INTEL_85XGM;
 114                         return 0;
 115                 }
 116                 break;
 117         case PCI_DEVICE_ID_INTEL_865G:
 118                 dinfo->name = "Intel(R) 865G";
 119                 dinfo->chipset = INTEL_865G;
 120                 dinfo->mobile = 0;
 121                 dinfo->pll_index = PLLS_I8xx;
 122                 return 0;
 123         case PCI_DEVICE_ID_INTEL_915G:
 124                 dinfo->name = "Intel(R) 915G";
 125                 dinfo->chipset = INTEL_915G;
 126                 dinfo->mobile = 0;
 127                 dinfo->pll_index = PLLS_I9xx;
 128                 return 0;
 129         case PCI_DEVICE_ID_INTEL_915GM:
 130                 dinfo->name = "Intel(R) 915GM";
 131                 dinfo->chipset = INTEL_915GM;
 132                 dinfo->mobile = 1;
 133                 dinfo->pll_index = PLLS_I9xx;
 134                 return 0;
 135         case PCI_DEVICE_ID_INTEL_945G:
 136                 dinfo->name = "Intel(R) 945G";
 137                 dinfo->chipset = INTEL_945G;
 138                 dinfo->mobile = 0;
 139                 dinfo->pll_index = PLLS_I9xx;
 140                 return 0;
 141         case PCI_DEVICE_ID_INTEL_945GM:
 142                 dinfo->name = "Intel(R) 945GM";
 143                 dinfo->chipset = INTEL_945GM;
 144                 dinfo->mobile = 1;
 145                 dinfo->pll_index = PLLS_I9xx;
 146                 return 0;
 147         default:
 148                 return 1;
 149         }
 150 }
 151
 152 int
 153 intelfbhw_get_memory(struct pci_dev *pdev, int *aperture_size,
 154                      int *stolen_size)
 155 {
 156         struct pci_dev *bridge_dev;
 157         u16 tmp;
 158         int stolen_overhead;
 159
 160         if (!pdev || !aperture_size || !stolen_size)
 161                 return 1;
 162
 163         /* Find the bridge device.  It is always 0:0.0 */
 164         if (!(bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0)))) {
 165                 ERR_MSG("cannot find bridge device\n");
 166                 return 1;
 167         }
 168
 169         /* Get the fb aperture size and "stolen" memory amount. */
 170         tmp = 0;
 171         pci_read_config_word(bridge_dev, INTEL_GMCH_CTRL, &tmp);
 172         pci_dev_put(bridge_dev);
 173
 174         switch (pdev->device) {
 175         case PCI_DEVICE_ID_INTEL_915G:
 176         case PCI_DEVICE_ID_INTEL_915GM:
 177         case PCI_DEVICE_ID_INTEL_945G:
 178         case PCI_DEVICE_ID_INTEL_945GM:
 179                 /* 915 and 945 chipsets support a 256MB aperture.
 180                    Aperture size is determined by inspected the
 181                    base address of the aperture. */
 182                 if (pci_resource_start(pdev, 2) & 0x08000000)
 183                         *aperture_size = MB(128);
 184                 else
 185                         *aperture_size = MB(256);
 186                 break;
 187         default:
 188                 if ((tmp & INTEL_GMCH_MEM_MASK) == INTEL_GMCH_MEM_64M)
 189                         *aperture_size = MB(64);
 190                 else
 191                         *aperture_size = MB(128);
 192                 break;
 193         }
 194
 195         /* Stolen memory size is reduced by the GTT and the popup.
 196            GTT is 1K per MB of aperture size, and popup is 4K. */
 197         stolen_overhead = (*aperture_size / MB(1)) + 4;
 198         switch(pdev->device) {
 199         case PCI_DEVICE_ID_INTEL_830M:
 200         case PCI_DEVICE_ID_INTEL_845G:
 201                 switch (tmp & INTEL_830_GMCH_GMS_MASK) {
 202                 case INTEL_830_GMCH_GMS_STOLEN_512:
 203                         *stolen_size = KB(512) - KB(stolen_overhead);
 204                         return 0;
 205                 case INTEL_830_GMCH_GMS_STOLEN_1024:
 206                         *stolen_size = MB(1) - KB(stolen_overhead);
 207                         return 0;
 208                 case INTEL_830_GMCH_GMS_STOLEN_8192:
 209                         *stolen_size = MB(8) - KB(stolen_overhead);
 210                         return 0;
 211                 case INTEL_830_GMCH_GMS_LOCAL:
 212                         ERR_MSG("only local memory found\n");
 213                         return 1;
 214                 case INTEL_830_GMCH_GMS_DISABLED:
 215                         ERR_MSG("video memory is disabled\n");
 216                         return 1;
 217                 default:
 218                         ERR_MSG("unexpected GMCH_GMS value: 0x%02x\n",
 219                                 tmp & INTEL_830_GMCH_GMS_MASK);
 220                         return 1;
 221                 }
 222                 break;
 223         default:
 224                 switch (tmp & INTEL_855_GMCH_GMS_MASK) {
 225                 case INTEL_855_GMCH_GMS_STOLEN_1M:
 226                         *stolen_size = MB(1) - KB(stolen_overhead);
 227                         return 0;
 228                 case INTEL_855_GMCH_GMS_STOLEN_4M:
 229                         *stolen_size = MB(4) - KB(stolen_overhead);
 230                         return 0;
 231                 case INTEL_855_GMCH_GMS_STOLEN_8M:
 232                         *stolen_size = MB(8) - KB(stolen_overhead);
 233                         return 0;
 234                 case INTEL_855_GMCH_GMS_STOLEN_16M:
 235                         *stolen_size = MB(16) - KB(stolen_overhead);
 236                         return 0;
 237                 case INTEL_855_GMCH_GMS_STOLEN_32M:
 238                         *stolen_size = MB(32) - KB(stolen_overhead);
 239                         return 0;
 240                 case INTEL_915G_GMCH_GMS_STOLEN_48M:
 241                         *stolen_size = MB(48) - KB(stolen_overhead);
 242                         return 0;
 243                 case INTEL_915G_GMCH_GMS_STOLEN_64M:
 244                         *stolen_size = MB(64) - KB(stolen_overhead);
 245                         return 0;
 246                 case INTEL_855_GMCH_GMS_DISABLED:
 247                         ERR_MSG("video memory is disabled\n");
 248                         return 0;
 249                 default:
 250                         ERR_MSG("unexpected GMCH_GMS value: 0x%02x\n",
 251                                 tmp & INTEL_855_GMCH_GMS_MASK);
 252                         return 1;
 253                 }
 254         }
 255 }
 256
 257 int
 258 intelfbhw_check_non_crt(struct intelfb_info *dinfo)
 259 {
 260         int dvo = 0;
 261
 262         if (INREG(LVDS) & PORT_ENABLE)
 263                 dvo |= LVDS_PORT;
 264         if (INREG(DVOA) & PORT_ENABLE)
 265                 dvo |= DVOA_PORT;
 266         if (INREG(DVOB) & PORT_ENABLE)
 267                 dvo |= DVOB_PORT;
 268         if (INREG(DVOC) & PORT_ENABLE)
 269                 dvo |= DVOC_PORT;
 270
 271         return dvo;
 272 }
 273
 274 const char *
 275 intelfbhw_dvo_to_string(int dvo)
 276 {
 277         if (dvo & DVOA_PORT)
 278                 return "DVO port A";
 279         else if (dvo & DVOB_PORT)
 280                 return "DVO port B";
 281         else if (dvo & DVOC_PORT)
 282                 return "DVO port C";
 283         else if (dvo & LVDS_PORT)
 284                 return "LVDS port";
 285         else
 286                 return NULL;
 287 }
 288
 289
 290 int
 291 intelfbhw_validate_mode(struct intelfb_info *dinfo,
 292                         struct fb_var_screeninfo *var)
 293 {
 294         int bytes_per_pixel;
 295         int tmp;
 296
 297 #if VERBOSE > 0
 298         DBG_MSG("intelfbhw_validate_mode\n");
 299 #endif
 300
 301         bytes_per_pixel = var->bits_per_pixel / 8;
 302         if (bytes_per_pixel == 3)
 303                 bytes_per_pixel = 4;
 304
 305         /* Check if enough video memory. */
 306         tmp = var->yres_virtual * var->xres_virtual * bytes_per_pixel;
 307         if (tmp > dinfo->fb.size) {
 308                 WRN_MSG("Not enough video ram for mode "
 309                         "(%d KByte vs %d KByte).\n",
 310                         BtoKB(tmp), BtoKB(dinfo->fb.size));
 311                 return 1;
 312         }
 313
 314         /* Check if x/y limits are OK. */
 315         if (var->xres - 1 > HACTIVE_MASK) {
 316                 WRN_MSG("X resolution too large (%d vs %d).\n",
 317                         var->xres, HACTIVE_MASK + 1);
 318                 return 1;
 319         }
 320         if (var->yres - 1 > VACTIVE_MASK) {
 321                 WRN_MSG("Y resolution too large (%d vs %d).\n",
 322                         var->yres, VACTIVE_MASK + 1);
 323                 return 1;
 324         }
 325
 326         /* Check for interlaced/doublescan modes. */
 327         if (var->vmode & FB_VMODE_INTERLACED) {
 328                 WRN_MSG("Mode is interlaced.\n");
 329                 return 1;
 330         }
 331         if (var->vmode & FB_VMODE_DOUBLE) {
 332                 WRN_MSG("Mode is double-scan.\n");
 333                 return 1;
 334         }
 335
 336         /* Check if clock is OK. */
 337         tmp = 1000000000 / var->pixclock;
 338         if (tmp < MIN_CLOCK) {
 339                 WRN_MSG("Pixel clock is too low (%d MHz vs %d MHz).\n",
 340                         (tmp + 500) / 1000, MIN_CLOCK / 1000);
 341                 return 1;
 342         }
 343         if (tmp > MAX_CLOCK) {
 344                 WRN_MSG("Pixel clock is too high (%d MHz vs %d MHz).\n",
 345                         (tmp + 500) / 1000, MAX_CLOCK / 1000);
 346                 return 1;
 347         }
 348
 349         return 0;
 350 }
 351
 352 int
 353 intelfbhw_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
 354 {
 355         struct intelfb_info *dinfo = GET_DINFO(info);
 356         u32 offset, xoffset, yoffset;
 357
 358 #if VERBOSE > 0
 359         DBG_MSG("intelfbhw_pan_display\n");
 360 #endif
 361
 362         xoffset = ROUND_DOWN_TO(var->xoffset, 8);
 363         yoffset = var->yoffset;
 364
 365         if ((xoffset + var->xres > var->xres_virtual) ||
 366             (yoffset + var->yres > var->yres_virtual))
 367                 return -EINVAL;
 368
 369         offset = (yoffset * dinfo->pitch) +
 370                  (xoffset * var->bits_per_pixel) / 8;
 371
 372         offset += dinfo->fb.offset << 12;
 373
 374         dinfo->vsync.pan_offset = offset;
 375         if ((var->activate & FB_ACTIVATE_VBL) && !intelfbhw_enable_irq(dinfo, 0)) {
 376                 dinfo->vsync.pan_display = 1;
 377         } else {
 378                 dinfo->vsync.pan_display = 0;
 379                 OUTREG(DSPABASE, offset);
 380         }
 381
 382         return 0;
 383 }
 384
 385 /* Blank the screen. */
 386 void
 387 intelfbhw_do_blank(int blank, struct fb_info *info)
 388 {
 389         struct intelfb_info *dinfo = GET_DINFO(info);
 390         u32 tmp;
 391
 392 #if VERBOSE > 0
 393         DBG_MSG("intelfbhw_do_blank: blank is %d\n", blank);
 394 #endif
 395
 396         /* Turn plane A on or off */
 397         tmp = INREG(DSPACNTR);
 398         if (blank)
 399                 tmp &= ~DISPPLANE_PLANE_ENABLE;
 400         else
 401                 tmp |= DISPPLANE_PLANE_ENABLE;
 402         OUTREG(DSPACNTR, tmp);
 403         /* Flush */
 404         tmp = INREG(DSPABASE);
 405         OUTREG(DSPABASE, tmp);
 406
 407         /* Turn off/on the HW cursor */
 408 #if VERBOSE > 0
 409         DBG_MSG("cursor_on is %d\n", dinfo->cursor_on);
 410 #endif
 411         if (dinfo->cursor_on) {
 412                 if (blank) {
 413                         intelfbhw_cursor_hide(dinfo);
 414                 } else {
 415                         intelfbhw_cursor_show(dinfo);
 416                 }
 417                 dinfo->cursor_on = 1;
 418         }
 419         dinfo->cursor_blanked = blank;
 420
 421         /* Set DPMS level */
 422         tmp = INREG(ADPA) & ~ADPA_DPMS_CONTROL_MASK;
 423         switch (blank) {
 424         case FB_BLANK_UNBLANK:
 425         case FB_BLANK_NORMAL:
 426                 tmp |= ADPA_DPMS_D0;
 427                 break;
 428         case FB_BLANK_VSYNC_SUSPEND:
 429                 tmp |= ADPA_DPMS_D1;
 430                 break;
 431         case FB_BLANK_HSYNC_SUSPEND:
 432                 tmp |= ADPA_DPMS_D2;
 433                 break;
 434         case FB_BLANK_POWERDOWN:
 435                 tmp |= ADPA_DPMS_D3;
 436                 break;
 437         }
 438         OUTREG(ADPA, tmp);
 439
 440         return;
 441 }
 442
 443
 444 void
 445 intelfbhw_setcolreg(struct intelfb_info *dinfo, unsigned regno,
 446                     unsigned red, unsigned green, unsigned blue,
 447                     unsigned transp)
 448 {
 449 #if VERBOSE > 0
 450         DBG_MSG("intelfbhw_setcolreg: %d: (%d, %d, %d)\n",
 451                 regno, red, green, blue);
 452 #endif
 453
 454         u32 palette_reg = (dinfo->pipe == PIPE_A) ?
 455                           PALETTE_A : PALETTE_B;
 456
 457         OUTREG(palette_reg + (regno << 2),
 458                (red << PALETTE_8_RED_SHIFT) |
 459                (green << PALETTE_8_GREEN_SHIFT) |
 460                (blue << PALETTE_8_BLUE_SHIFT));
 461 }
 462
 463
 464 int
 465 intelfbhw_read_hw_state(struct intelfb_info *dinfo, struct intelfb_hwstate *hw,
 466                         int flag)
 467 {
 468         int i;
 469
 470 #if VERBOSE > 0
 471         DBG_MSG("intelfbhw_read_hw_state\n");
 472 #endif
 473
 474         if (!hw || !dinfo)
 475                 return -1;
 476
 477         /* Read in as much of the HW state as possible. */
 478         hw->vga0_divisor = INREG(VGA0_DIVISOR);
 479         hw->vga1_divisor = INREG(VGA1_DIVISOR);
 480         hw->vga_pd = INREG(VGAPD);
 481         hw->dpll_a = INREG(DPLL_A);
 482         hw->dpll_b = INREG(DPLL_B);
 483         hw->fpa0 = INREG(FPA0);
 484         hw->fpa1 = INREG(FPA1);
 485         hw->fpb0 = INREG(FPB0);
 486         hw->fpb1 = INREG(FPB1);
 487
 488         if (flag == 1)
 489                 return flag;
 490
 491 #if 0
 492         /* This seems to be a problem with the 852GM/855GM */
 493         for (i = 0; i < PALETTE_8_ENTRIES; i++) {
 494                 hw->palette_a[i] = INREG(PALETTE_A + (i << 2));
 495                 hw->palette_b[i] = INREG(PALETTE_B + (i << 2));
 496         }
 497 #endif
 498
 499         if (flag == 2)
 500                 return flag;
 501
 502         hw->htotal_a = INREG(HTOTAL_A);
 503         hw->hblank_a = INREG(HBLANK_A);
 504         hw->hsync_a = INREG(HSYNC_A);
 505         hw->vtotal_a = INREG(VTOTAL_A);
 506         hw->vblank_a = INREG(VBLANK_A);
 507         hw->vsync_a = INREG(VSYNC_A);
 508         hw->src_size_a = INREG(SRC_SIZE_A);
 509         hw->bclrpat_a = INREG(BCLRPAT_A);
 510         hw->htotal_b = INREG(HTOTAL_B);
 511         hw->hblank_b = INREG(HBLANK_B);
 512         hw->hsync_b = INREG(HSYNC_B);
 513         hw->vtotal_b = INREG(VTOTAL_B);
 514         hw->vblank_b = INREG(VBLANK_B);
 515         hw->vsync_b = INREG(VSYNC_B);
 516         hw->src_size_b = INREG(SRC_SIZE_B);
 517         hw->bclrpat_b = INREG(BCLRPAT_B);
 518
 519         if (flag == 3)
 520                 return flag;
 521
 522         hw->adpa = INREG(ADPA);
 523         hw->dvoa = INREG(DVOA);
 524         hw->dvob = INREG(DVOB);
 525         hw->dvoc = INREG(DVOC);
 526         hw->dvoa_srcdim = INREG(DVOA_SRCDIM);
 527         hw->dvob_srcdim = INREG(DVOB_SRCDIM);
 528         hw->dvoc_srcdim = INREG(DVOC_SRCDIM);
 529         hw->lvds = INREG(LVDS);
 530
 531         if (flag == 4)
 532                 return flag;
 533
 534         hw->pipe_a_conf = INREG(PIPEACONF);
 535         hw->pipe_b_conf = INREG(PIPEBCONF);
 536         hw->disp_arb = INREG(DISPARB);
 537
 538         if (flag == 5)
 539                 return flag;
 540
 541         hw->cursor_a_control = INREG(CURSOR_A_CONTROL);
 542         hw->cursor_b_control = INREG(CURSOR_B_CONTROL);
 543         hw->cursor_a_base = INREG(CURSOR_A_BASEADDR);
 544         hw->cursor_b_base = INREG(CURSOR_B_BASEADDR);
 545
 546         if (flag == 6)
 547                 return flag;
 548
 549         for (i = 0; i < 4; i++) {
 550                 hw->cursor_a_palette[i] = INREG(CURSOR_A_PALETTE0 + (i << 2));
 551                 hw->cursor_b_palette[i] = INREG(CURSOR_B_PALETTE0 + (i << 2));
 552         }
 553
 554         if (flag == 7)
 555                 return flag;
 556
 557         hw->cursor_size = INREG(CURSOR_SIZE);
 558
 559         if (flag == 8)
 560                 return flag;
 561
 562         hw->disp_a_ctrl = INREG(DSPACNTR);
 563         hw->disp_b_ctrl = INREG(DSPBCNTR);
 564         hw->disp_a_base = INREG(DSPABASE);
 565         hw->disp_b_base = INREG(DSPBBASE);
 566         hw->disp_a_stride = INREG(DSPASTRIDE);
 567         hw->disp_b_stride = INREG(DSPBSTRIDE);
 568
 569         if (flag == 9)
 570                 return flag;
 571
 572         hw->vgacntrl = INREG(VGACNTRL);
 573
 574         if (flag == 10)
 575                 return flag;
 576
 577         hw->add_id = INREG(ADD_ID);
 578
 579         if (flag == 11)
 580                 return flag;
 581
 582         for (i = 0; i < 7; i++) {
 583                 hw->swf0x[i] = INREG(SWF00 + (i << 2));
 584                 hw->swf1x[i] = INREG(SWF10 + (i << 2));
 585                 if (i < 3)
 586                         hw->swf3x[i] = INREG(SWF30 + (i << 2));
 587         }
 588
 589         for (i = 0; i < 8; i++)
 590                 hw->fence[i] = INREG(FENCE + (i << 2));
 591
 592         hw->instpm = INREG(INSTPM);
 593         hw->mem_mode = INREG(MEM_MODE);
 594         hw->fw_blc_0 = INREG(FW_BLC_0);
 595         hw->fw_blc_1 = INREG(FW_BLC_1);
 596
 597         hw->hwstam = INREG16(HWSTAM);
 598         hw->ier = INREG16(IER);
 599         hw->iir = INREG16(IIR);
 600         hw->imr = INREG16(IMR);
 601
 602         return 0;
 603 }
 604
 605
 606 static int calc_vclock3(int index, int m, int n, int p)
 607 {
 608         if (p == 0 || n == 0)
 609                 return 0;
 610         return plls[index].ref_clk * m / n / p;
 611 }
 612
 613 static int calc_vclock(int index, int m1, int m2, int n, int p1, int p2, int lvds)
 614 {
 615         struct pll_min_max *pll = &plls[index];
 616         u32 m, vco, p;
 617
 618         m = (5 * (m1 + 2)) + (m2 + 2);
 619         n += 2;
 620         vco = pll->ref_clk * m / n;
 621
 622         if (index == PLLS_I8xx) {
 623                 p = ((p1 + 2) * (1 << (p2 + 1)));
 624         } else {
 625                 p = ((p1) * (p2 ? 5 : 10));
 626         }
 627         return vco / p;
 628 }
 629
 630 #if REGDUMP
 631 static void
 632 intelfbhw_get_p1p2(struct intelfb_info *dinfo, int dpll, int *o_p1, int *o_p2)
 633 {
 634         int p1, p2;
 635
 636         if (IS_I9XX(dinfo)) {
 637                 if (dpll & DPLL_P1_FORCE_DIV2)
 638                         p1 = 1;
 639                 else
 640                         p1 = (dpll >> DPLL_P1_SHIFT) & 0xff;
 641
 642                 p1 = ffs(p1);
 643
 644                 p2 = (dpll >> DPLL_I9XX_P2_SHIFT) & DPLL_P2_MASK;
 645         } else {
 646                 if (dpll & DPLL_P1_FORCE_DIV2)
 647                         p1 = 0;
 648                 else
 649                         p1 = (dpll >> DPLL_P1_SHIFT) & DPLL_P1_MASK;
 650                 p2 = (dpll >> DPLL_P2_SHIFT) & DPLL_P2_MASK;
 651         }
 652
 653         *o_p1 = p1;
 654         *o_p2 = p2;
 655 }
 656 #endif
 657
 658
 659 void
 660 intelfbhw_print_hw_state(struct intelfb_info *dinfo, struct intelfb_hwstate *hw)
 661 {
 662 #if REGDUMP
 663         int i, m1, m2, n, p1, p2;
 664         int index = dinfo->pll_index;
 665         DBG_MSG("intelfbhw_print_hw_state\n");
 666
 667         if (!hw)
 668                 return;
 669         /* Read in as much of the HW state as possible. */
 670         printk("hw state dump start\n");
 671         printk("        VGA0_DIVISOR:           0x%08x\n", hw->vga0_divisor);
 672         printk("        VGA1_DIVISOR:           0x%08x\n", hw->vga1_divisor);
 673         printk("        VGAPD:                  0x%08x\n", hw->vga_pd);
 674         n = (hw->vga0_divisor >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 675         m1 = (hw->vga0_divisor >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 676         m2 = (hw->vga0_divisor >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 677
 678         intelfbhw_get_p1p2(dinfo, hw->vga_pd, &p1, &p2);
 679
 680         printk("        VGA0: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",
 681                m1, m2, n, p1, p2);
 682         printk("        VGA0: clock is %d\n",
 683                calc_vclock(index, m1, m2, n, p1, p2, 0));
 684
 685         n = (hw->vga1_divisor >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 686         m1 = (hw->vga1_divisor >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 687         m2 = (hw->vga1_divisor >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 688
 689         intelfbhw_get_p1p2(dinfo, hw->vga_pd, &p1, &p2);
 690         printk("        VGA1: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",
 691                m1, m2, n, p1, p2);
 692         printk("        VGA1: clock is %d\n", calc_vclock(index, m1, m2, n, p1, p2, 0));
 693
 694         printk("        DPLL_A:                 0x%08x\n", hw->dpll_a);
 695         printk("        DPLL_B:                 0x%08x\n", hw->dpll_b);
 696         printk("        FPA0:                   0x%08x\n", hw->fpa0);
 697         printk("        FPA1:                   0x%08x\n", hw->fpa1);
 698         printk("        FPB0:                   0x%08x\n", hw->fpb0);
 699         printk("        FPB1:                   0x%08x\n", hw->fpb1);
 700
 701         n = (hw->fpa0 >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 702         m1 = (hw->fpa0 >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 703         m2 = (hw->fpa0 >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 704
 705         intelfbhw_get_p1p2(dinfo, hw->dpll_a, &p1, &p2);
 706
 707         printk("        PLLA0: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",
 708                m1, m2, n, p1, p2);
 709         printk("        PLLA0: clock is %d\n", calc_vclock(index, m1, m2, n, p1, p2, 0));
 710
 711         n = (hw->fpa1 >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 712         m1 = (hw->fpa1 >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 713         m2 = (hw->fpa1 >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 714
 715         intelfbhw_get_p1p2(dinfo, hw->dpll_a, &p1, &p2);
 716
 717         printk("        PLLA1: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",
 718                m1, m2, n, p1, p2);
 719         printk("        PLLA1: clock is %d\n", calc_vclock(index, m1, m2, n, p1, p2, 0));
 720
 721 #if 0
 722         printk("        PALETTE_A:\n");
 723         for (i = 0; i < PALETTE_8_ENTRIES)
 724                 printk("        %3d:    0x%08x\n", i, hw->palette_a[i]);
 725         printk("        PALETTE_B:\n");
 726         for (i = 0; i < PALETTE_8_ENTRIES)
 727                 printk("        %3d:    0x%08x\n", i, hw->palette_b[i]);
 728 #endif
 729
 730         printk("        HTOTAL_A:               0x%08x\n", hw->htotal_a);
 731         printk("        HBLANK_A:               0x%08x\n", hw->hblank_a);
 732         printk("        HSYNC_A:                0x%08x\n", hw->hsync_a);
 733         printk("        VTOTAL_A:               0x%08x\n", hw->vtotal_a);
 734         printk("        VBLANK_A:               0x%08x\n", hw->vblank_a);
 735         printk("        VSYNC_A:                0x%08x\n", hw->vsync_a);
 736         printk("        SRC_SIZE_A:             0x%08x\n", hw->src_size_a);
 737         printk("        BCLRPAT_A:              0x%08x\n", hw->bclrpat_a);
 738         printk("        HTOTAL_B:               0x%08x\n", hw->htotal_b);
 739         printk("        HBLANK_B:               0x%08x\n", hw->hblank_b);
 740         printk("        HSYNC_B:                0x%08x\n", hw->hsync_b);
 741         printk("        VTOTAL_B:               0x%08x\n", hw->vtotal_b);
 742         printk("        VBLANK_B:               0x%08x\n", hw->vblank_b);
 743         printk("        VSYNC_B:                0x%08x\n", hw->vsync_b);
 744         printk("        SRC_SIZE_B:             0x%08x\n", hw->src_size_b);
 745         printk("        BCLRPAT_B:              0x%08x\n", hw->bclrpat_b);
 746
 747         printk("        ADPA:                   0x%08x\n", hw->adpa);
 748         printk("        DVOA:                   0x%08x\n", hw->dvoa);
 749         printk("        DVOB:                   0x%08x\n", hw->dvob);
 750         printk("        DVOC:                   0x%08x\n", hw->dvoc);
 751         printk("        DVOA_SRCDIM:            0x%08x\n", hw->dvoa_srcdim);
 752         printk("        DVOB_SRCDIM:            0x%08x\n", hw->dvob_srcdim);
 753         printk("        DVOC_SRCDIM:            0x%08x\n", hw->dvoc_srcdim);
 754         printk("        LVDS:                   0x%08x\n", hw->lvds);
 755
 756         printk("        PIPEACONF:              0x%08x\n", hw->pipe_a_conf);
 757         printk("        PIPEBCONF:              0x%08x\n", hw->pipe_b_conf);
 758         printk("        DISPARB:                0x%08x\n", hw->disp_arb);
 759
 760         printk("        CURSOR_A_CONTROL:       0x%08x\n", hw->cursor_a_control);
 761         printk("        CURSOR_B_CONTROL:       0x%08x\n", hw->cursor_b_control);
 762         printk("        CURSOR_A_BASEADDR:      0x%08x\n", hw->cursor_a_base);
 763         printk("        CURSOR_B_BASEADDR:      0x%08x\n", hw->cursor_b_base);
 764
 765         printk("        CURSOR_A_PALETTE:       ");
 766         for (i = 0; i < 4; i++) {
 767                 printk("0x%08x", hw->cursor_a_palette[i]);
 768                 if (i < 3)
 769                         printk(", ");
 770         }
 771         printk("\n");
 772         printk("        CURSOR_B_PALETTE:       ");
 773         for (i = 0; i < 4; i++) {
 774                 printk("0x%08x", hw->cursor_b_palette[i]);
 775                 if (i < 3)
 776                         printk(", ");
 777         }
 778         printk("\n");
 779
 780         printk("        CURSOR_SIZE:            0x%08x\n", hw->cursor_size);
 781
 782         printk("        DSPACNTR:               0x%08x\n", hw->disp_a_ctrl);
 783         printk("        DSPBCNTR:               0x%08x\n", hw->disp_b_ctrl);
 784         printk("        DSPABASE:               0x%08x\n", hw->disp_a_base);
 785         printk("        DSPBBASE:               0x%08x\n", hw->disp_b_base);
 786         printk("        DSPASTRIDE:             0x%08x\n", hw->disp_a_stride);
 787         printk("        DSPBSTRIDE:             0x%08x\n", hw->disp_b_stride);
 788
 789         printk("        VGACNTRL:               0x%08x\n", hw->vgacntrl);
 790         printk("        ADD_ID:                 0x%08x\n", hw->add_id);
 791
 792         for (i = 0; i < 7; i++) {
 793                 printk("        SWF0%d                  0x%08x\n", i,
 794                         hw->swf0x[i]);
 795         }
 796         for (i = 0; i < 7; i++) {
 797                 printk("        SWF1%d                  0x%08x\n", i,
 798                         hw->swf1x[i]);
 799         }
 800         for (i = 0; i < 3; i++) {
 801                 printk("        SWF3%d                  0x%08x\n", i,
 802                        hw->swf3x[i]);
 803         }
 804         for (i = 0; i < 8; i++)
 805                 printk("        FENCE%d                 0x%08x\n", i,
 806                        hw->fence[i]);
 807
 808         printk("        INSTPM                  0x%08x\n", hw->instpm);
 809         printk("        MEM_MODE                0x%08x\n", hw->mem_mode);
 810         printk("        FW_BLC_0                0x%08x\n", hw->fw_blc_0);
 811         printk("        FW_BLC_1                0x%08x\n", hw->fw_blc_1);
 812
 813         printk("        HWSTAM                  0x%04x\n", hw->hwstam);
 814         printk("        IER                     0x%04x\n", hw->ier);
 815         printk("        IIR                     0x%04x\n", hw->iir);
 816         printk("        IMR                     0x%04x\n", hw->imr);
 817         printk("hw state dump end\n");
 818 #endif
 819 }
 820
 821
 822
 823 /* Split the M parameter into M1 and M2. */
 824 static int
 825 splitm(int index, unsigned int m, unsigned int *retm1, unsigned int *retm2)
 826 {
 827         int m1, m2;
 828         int testm;
 829         struct pll_min_max *pll = &plls[index];
 830
 831         /* no point optimising too much - brute force m */
 832         for (m1 = pll->min_m1; m1 < pll->max_m1 + 1; m1++) {
 833                 for (m2 = pll->min_m2; m2 < pll->max_m2 + 1; m2++) {
 834                         testm = (5 * (m1 + 2)) + (m2 + 2);
 835                         if (testm == m) {
 836                                 *retm1 = (unsigned int)m1;
 837                                 *retm2 = (unsigned int)m2;
 838                                 return 0;
 839                         }
 840                 }
 841         }
 842         return 1;
 843 }
 844
 845 /* Split the P parameter into P1 and P2. */
 846 static int
 847 splitp(int index, unsigned int p, unsigned int *retp1, unsigned int *retp2)
 848 {
 849         int p1, p2;
 850         struct pll_min_max *pll = &plls[index];
 851
 852         if (index == PLLS_I9xx) {
 853                 p2 = (p % 10) ? 1 : 0;
 854
 855                 p1 = p / (p2 ? 5 : 10);
 856
 857                 *retp1 = (unsigned int)p1;
 858                 *retp2 = (unsigned int)p2;
 859                 return 0;
 860         }
 861
 862         if (p % 4 == 0)
 863                 p2 = 1;
 864         else
 865                 p2 = 0;
 866         p1 = (p / (1 << (p2 + 1))) - 2;
 867         if (p % 4 == 0 && p1 < pll->min_p1) {
 868                 p2 = 0;
 869                 p1 = (p / (1 << (p2 + 1))) - 2;
 870         }
 871         if (p1 < pll->min_p1 || p1 > pll->max_p1 ||
 872             (p1 + 2) * (1 << (p2 + 1)) != p) {
 873                 return 1;
 874         } else {
 875                 *retp1 = (unsigned int)p1;
 876                 *retp2 = (unsigned int)p2;
 877                 return 0;
 878         }
 879 }
 880
 881 static int
 882 calc_pll_params(int index, int clock, u32 *retm1, u32 *retm2, u32 *retn, u32 *retp1,
 883                 u32 *retp2, u32 *retclock)
 884 {
 885         u32 m1, m2, n, p1, p2, n1, testm;
 886         u32 f_vco, p, p_best = 0, m, f_out = 0;
 887         u32 err_max, err_target, err_best = 10000000;
 888         u32 n_best = 0, m_best = 0, f_best, f_err;
 889         u32 p_min, p_max, p_inc, div_max;
 890         struct pll_min_max *pll = &plls[index];
 891
 892         /* Accept 0.5% difference, but aim for 0.1% */
 893         err_max = 5 * clock / 1000;
 894         err_target = clock / 1000;
 895
 896         DBG_MSG("Clock is %d\n", clock);
 897
 898         div_max = pll->max_vco / clock;
 899
 900         p_inc = (clock <= pll->p_transition_clk) ? pll->p_inc_lo : pll->p_inc_hi;
 901         p_min = p_inc;
 902         p_max = ROUND_DOWN_TO(div_max, p_inc);
 903         if (p_min < pll->min_p)
 904                 p_min = pll->min_p;
 905         if (p_max > pll->max_p)
 906                 p_max = pll->max_p;
 907
 908         DBG_MSG("p range is %d-%d (%d)\n", p_min, p_max, p_inc);
 909
 910         p = p_min;
 911         do {
 912                 if (splitp(index, p, &p1, &p2)) {
 913                         WRN_MSG("cannot split p = %d\n", p);
 914                         p += p_inc;
 915                         continue;
 916                 }
 917                 n = pll->min_n;
 918                 f_vco = clock * p;
 919
 920                 do {
 921                         m = ROUND_UP_TO(f_vco * n, pll->ref_clk) / pll->ref_clk;
 922                         if (m < pll->min_m)
 923                                 m = pll->min_m + 1;
 924                         if (m > pll->max_m)
 925                                 m = pll->max_m - 1;
 926                         for (testm = m - 1; testm <= m; testm++) {
 927                                 f_out = calc_vclock3(index, m, n, p);
 928                                 if (splitm(index, testm, &m1, &m2)) {
 929                                         WRN_MSG("cannot split m = %d\n", m);
 930                                         n++;
 931                                         continue;
 932                                 }
 933                                 if (clock > f_out)
 934                                         f_err = clock - f_out;
 935                                 else/* slightly bias the error for bigger clocks */
 936                                         f_err = f_out - clock + 1;
 937
 938                                 if (f_err < err_best) {
 939                                         m_best = testm;
 940                                         n_best = n;
 941                                         p_best = p;
 942                                         f_best = f_out;
 943                                         err_best = f_err;
 944                                 }
 945                         }
 946                         n++;
 947                 } while ((n <= pll->max_n) && (f_out >= clock));
 948                 p += p_inc;
 949         } while ((p <= p_max));
 950
 951         if (!m_best) {
 952                 WRN_MSG("cannot find parameters for clock %d\n", clock);
 953                 return 1;
 954         }
 955         m = m_best;
 956         n = n_best;
 957         p = p_best;
 958         splitm(index, m, &m1, &m2);
 959         splitp(index, p, &p1, &p2);
 960         n1 = n - 2;
 961
 962         DBG_MSG("m, n, p: %d (%d,%d), %d (%d), %d (%d,%d), "
 963                 "f: %d (%d), VCO: %d\n",
 964                 m, m1, m2, n, n1, p, p1, p2,
 965                 calc_vclock3(index, m, n, p),
 966                 calc_vclock(index, m1, m2, n1, p1, p2, 0),
 967                 calc_vclock3(index, m, n, p) * p);
 968         *retm1 = m1;
 969         *retm2 = m2;
 970         *retn = n1;
 971         *retp1 = p1;
 972         *retp2 = p2;
 973         *retclock = calc_vclock(index, m1, m2, n1, p1, p2, 0);
 974
 975         return 0;
 976 }
 977
 978 static __inline__ int
 979 check_overflow(u32 value, u32 limit, const char *description)
 980 {
 981         if (value > limit) {
 982                 WRN_MSG("%s value %d exceeds limit %d\n",
 983                         description, value, limit);
 984                 return 1;
 985         }
 986         return 0;
 987 }
 988
 989 /* It is assumed that hw is filled in with the initial state information. */
 990 int
 991 intelfbhw_mode_to_hw(struct intelfb_info *dinfo, struct intelfb_hwstate *hw,
 992                      struct fb_var_screeninfo *var)
 993 {
 994         int pipe = PIPE_A;
 995         u32 *dpll, *fp0, *fp1;
 996         u32 m1, m2, n, p1, p2, clock_target, clock;
 997         u32 hsync_start, hsync_end, hblank_start, hblank_end, htotal, hactive;
 998         u32 vsync_start, vsync_end, vblank_start, vblank_end, vtotal, vactive;
 999         u32 vsync_pol, hsync_pol;
1000         u32 *vs, *vb, *vt, *hs, *hb, *ht, *ss, *pipe_conf;
1001         u32 stride_alignment;
1002
1003         DBG_MSG("intelfbhw_mode_to_hw\n");
1004
1005         /* Disable VGA */
1006         hw->vgacntrl |= VGA_DISABLE;
1007
1008         /* Check whether pipe A or pipe B is enabled. */
1009         if (hw->pipe_a_conf & PIPECONF_ENABLE)
1010                 pipe = PIPE_A;
1011         else if (hw->pipe_b_conf & PIPECONF_ENABLE)
1012                 pipe = PIPE_B;
1013
1014         /* Set which pipe's registers will be set. */
1015         if (pipe == PIPE_B) {
1016                 dpll = &hw->dpll_b;
1017                 fp0 = &hw->fpb0;
1018                 fp1 = &hw->fpb1;
1019                 hs = &hw->hsync_b;
1020                 hb = &hw->hblank_b;
1021                 ht = &hw->htotal_b;
1022                 vs = &hw->vsync_b;
1023                 vb = &hw->vblank_b;
1024                 vt = &hw->vtotal_b;
1025                 ss = &hw->src_size_b;
1026                 pipe_conf = &hw->pipe_b_conf;
1027         } else {
1028                 dpll = &hw->dpll_a;
1029                 fp0 = &hw->fpa0;
1030                 fp1 = &hw->fpa1;
1031                 hs = &hw->hsync_a;
1032                 hb = &hw->hblank_a;
1033                 ht = &hw->htotal_a;
1034                 vs = &hw->vsync_a;
1035                 vb = &hw->vblank_a;
1036                 vt = &hw->vtotal_a;
1037                 ss = &hw->src_size_a;
1038                 pipe_conf = &hw->pipe_a_conf;
1039         }
1040
1041         /* Use ADPA register for sync control. */
1042         hw->adpa &= ~ADPA_USE_VGA_HVPOLARITY;
1043
1044         /* sync polarity */
1045         hsync_pol = (var->sync & FB_SYNC_HOR_HIGH_ACT) ?
1046                         ADPA_SYNC_ACTIVE_HIGH : ADPA_SYNC_ACTIVE_LOW;
1047         vsync_pol = (var->sync & FB_SYNC_VERT_HIGH_ACT) ?
1048                         ADPA_SYNC_ACTIVE_HIGH : ADPA_SYNC_ACTIVE_LOW;
1049         hw->adpa &= ~((ADPA_SYNC_ACTIVE_MASK << ADPA_VSYNC_ACTIVE_SHIFT) |
1050                       (ADPA_SYNC_ACTIVE_MASK << ADPA_HSYNC_ACTIVE_SHIFT));
1051         hw->adpa |= (hsync_pol << ADPA_HSYNC_ACTIVE_SHIFT) |
1052                     (vsync_pol << ADPA_VSYNC_ACTIVE_SHIFT);
1053
1054         /* Connect correct pipe to the analog port DAC */
1055         hw->adpa &= ~(PIPE_MASK << ADPA_PIPE_SELECT_SHIFT);
1056         hw->adpa |= (pipe << ADPA_PIPE_SELECT_SHIFT);
1057
1058         /* Set DPMS state to D0 (on) */
1059         hw->adpa &= ~ADPA_DPMS_CONTROL_MASK;
1060         hw->adpa |= ADPA_DPMS_D0;
1061
1062         hw->adpa |= ADPA_DAC_ENABLE;
1063
1064         *dpll |= (DPLL_VCO_ENABLE | DPLL_VGA_MODE_DISABLE);
1065         *dpll &= ~(DPLL_RATE_SELECT_MASK | DPLL_REFERENCE_SELECT_MASK);
1066         *dpll |= (DPLL_REFERENCE_DEFAULT | DPLL_RATE_SELECT_FP0);
1067
1068         /* Desired clock in kHz */
1069         clock_target = 1000000000 / var->pixclock;
1070
1071         if (calc_pll_params(dinfo->pll_index, clock_target, &m1, &m2,
1072                             &n, &p1, &p2, &clock)) {
1073                 WRN_MSG("calc_pll_params failed\n");
1074                 return 1;
1075         }
1076
1077         /* Check for overflow. */
1078         if (check_overflow(p1, DPLL_P1_MASK, "PLL P1 parameter"))
1079                 return 1;
1080         if (check_overflow(p2, DPLL_P2_MASK, "PLL P2 parameter"))
1081                 return 1;
1082         if (check_overflow(m1, FP_DIVISOR_MASK, "PLL M1 parameter"))
1083                 return 1;
1084         if (check_overflow(m2, FP_DIVISOR_MASK, "PLL M2 parameter"))
1085                 return 1;
1086         if (check_overflow(n, FP_DIVISOR_MASK, "PLL N parameter"))
1087                 return 1;
1088
1089         *dpll &= ~DPLL_P1_FORCE_DIV2;
1090         *dpll &= ~((DPLL_P2_MASK << DPLL_P2_SHIFT) |
1091                    (DPLL_P1_MASK << DPLL_P1_SHIFT));
1092
1093         if (IS_I9XX(dinfo)) {
1094                 *dpll |= (p2 << DPLL_I9XX_P2_SHIFT);
1095                 *dpll |= (1 << (p1 - 1)) << DPLL_P1_SHIFT;
1096         } else {
1097                 *dpll |= (p2 << DPLL_P2_SHIFT) | (p1 << DPLL_P1_SHIFT);
1098         }
1099
1100         *fp0 = (n << FP_N_DIVISOR_SHIFT) |
1101                (m1 << FP_M1_DIVISOR_SHIFT) |
1102                (m2 << FP_M2_DIVISOR_SHIFT);
1103         *fp1 = *fp0;
1104
1105         hw->dvob &= ~PORT_ENABLE;
1106         hw->dvoc &= ~PORT_ENABLE;
1107
1108         /* Use display plane A. */
1109         hw->disp_a_ctrl |= DISPPLANE_PLANE_ENABLE;
1110         hw->disp_a_ctrl &= ~DISPPLANE_GAMMA_ENABLE;
1111         hw->disp_a_ctrl &= ~DISPPLANE_PIXFORMAT_MASK;
1112         switch (intelfb_var_to_depth(var)) {
1113         case 8:
1114                 hw->disp_a_ctrl |= DISPPLANE_8BPP | DISPPLANE_GAMMA_ENABLE;
1115                 break;
1116         case 15:
1117                 hw->disp_a_ctrl |= DISPPLANE_15_16BPP;
1118                 break;
1119         case 16:
1120                 hw->disp_a_ctrl |= DISPPLANE_16BPP;
1121                 break;
1122         case 24:
1123                 hw->disp_a_ctrl |= DISPPLANE_32BPP_NO_ALPHA;
1124                 break;
1125         }
1126         hw->disp_a_ctrl &= ~(PIPE_MASK << DISPPLANE_SEL_PIPE_SHIFT);
1127         hw->disp_a_ctrl |= (pipe << DISPPLANE_SEL_PIPE_SHIFT);
1128
1129         /* Set CRTC registers. */
1130         hactive = var->xres;
1131         hsync_start = hactive + var->right_margin;
1132         hsync_end = hsync_start + var->hsync_len;
1133         htotal = hsync_end + var->left_margin;
1134         hblank_start = hactive;
1135         hblank_end = htotal;
1136
1137         DBG_MSG("H: act %d, ss %d, se %d, tot %d bs %d, be %d\n",
1138                 hactive, hsync_start, hsync_end, htotal, hblank_start,
1139                 hblank_end);
1140
1141         vactive = var->yres;
1142         vsync_start = vactive + var->lower_margin;
1143         vsync_end = vsync_start + var->vsync_len;
1144         vtotal = vsync_end + var->upper_margin;
1145         vblank_start = vactive;
1146         vblank_end = vtotal;
1147         vblank_end = vsync_end + 1;
1148
1149         DBG_MSG("V: act %d, ss %d, se %d, tot %d bs %d, be %d\n",
1150                 vactive, vsync_start, vsync_end, vtotal, vblank_start,
1151                 vblank_end);
1152
1153         /* Adjust for register values, and check for overflow. */
1154         hactive--;
1155         if (check_overflow(hactive, HACTIVE_MASK, "CRTC hactive"))
1156                 return 1;
1157         hsync_start--;
1158         if (check_overflow(hsync_start, HSYNCSTART_MASK, "CRTC hsync_start"))
1159                 return 1;
1160         hsync_end--;
1161         if (check_overflow(hsync_end, HSYNCEND_MASK, "CRTC hsync_end"))
1162                 return 1;
1163         htotal--;
1164         if (check_overflow(htotal, HTOTAL_MASK, "CRTC htotal"))
1165                 return 1;
1166         hblank_start--;
1167         if (check_overflow(hblank_start, HBLANKSTART_MASK, "CRTC hblank_start"))
1168                 return 1;
1169         hblank_end--;
1170         if (check_overflow(hblank_end, HBLANKEND_MASK, "CRTC hblank_end"))
1171                 return 1;
1172
1173         vactive--;
1174         if (check_overflow(vactive, VACTIVE_MASK, "CRTC vactive"))
1175                 return 1;
1176         vsync_start--;
1177         if (check_overflow(vsync_start, VSYNCSTART_MASK, "CRTC vsync_start"))
1178                 return 1;
1179         vsync_end--;
1180         if (check_overflow(vsync_end, VSYNCEND_MASK, "CRTC vsync_end"))
1181                 return 1;
1182         vtotal--;
1183         if (check_overflow(vtotal, VTOTAL_MASK, "CRTC vtotal"))
1184                 return 1;
1185         vblank_start--;
1186         if (check_overflow(vblank_start, VBLANKSTART_MASK, "CRTC vblank_start"))
1187                 return 1;
1188         vblank_end--;
1189         if (check_overflow(vblank_end, VBLANKEND_MASK, "CRTC vblank_end"))
1190                 return 1;
1191
1192         *ht = (htotal << HTOTAL_SHIFT) | (hactive << HACTIVE_SHIFT);
1193         *hb = (hblank_start << HBLANKSTART_SHIFT) |
1194               (hblank_end << HSYNCEND_SHIFT);
1195         *hs = (hsync_start << HSYNCSTART_SHIFT) | (hsync_end << HSYNCEND_SHIFT);
1196
1197         *vt = (vtotal << VTOTAL_SHIFT) | (vactive << VACTIVE_SHIFT);
1198         *vb = (vblank_start << VBLANKSTART_SHIFT) |
1199               (vblank_end << VSYNCEND_SHIFT);
1200         *vs = (vsync_start << VSYNCSTART_SHIFT) | (vsync_end << VSYNCEND_SHIFT);
1201         *ss = (hactive << SRC_SIZE_HORIZ_SHIFT) |
1202               (vactive << SRC_SIZE_VERT_SHIFT);
1203
1204         hw->disp_a_stride = dinfo->pitch;
1205         DBG_MSG("pitch is %d\n", hw->disp_a_stride);
1206
1207         hw->disp_a_base = hw->disp_a_stride * var->yoffset +
1208                           var->xoffset * var->bits_per_pixel / 8;
1209
1210         hw->disp_a_base += dinfo->fb.offset << 12;
1211
1212         /* Check stride alignment. */
1213         stride_alignment = IS_I9XX(dinfo) ? STRIDE_ALIGNMENT_I9XX :
1214                                             STRIDE_ALIGNMENT;
1215         if (hw->disp_a_stride % stride_alignment != 0) {
1216                 WRN_MSG("display stride %d has bad alignment %d\n",
1217                         hw->disp_a_stride, stride_alignment);
1218                 return 1;
1219         }
1220
1221         /* Set the palette to 8-bit mode. */
1222         *pipe_conf &= ~PIPECONF_GAMMA;
1223         return 0;
1224 }
1225
1226 /* Program a (non-VGA) video mode. */
1227 int
1228 intelfbhw_program_mode(struct intelfb_info *dinfo,
1229                      const struct intelfb_hwstate *hw, int blank)
1230 {
1231         int pipe = PIPE_A;
1232         u32 tmp;
1233         const u32 *dpll, *fp0, *fp1, *pipe_conf;
1234         const u32 *hs, *ht, *hb, *vs, *vt, *vb, *ss;
1235         u32 dpll_reg, fp0_reg, fp1_reg, pipe_conf_reg;
1236         u32 hsync_reg, htotal_reg, hblank_reg;
1237         u32 vsync_reg, vtotal_reg, vblank_reg;
1238         u32 src_size_reg;
1239         u32 count, tmp_val[3];
1240
1241         /* Assume single pipe, display plane A, analog CRT. */
1242
1243 #if VERBOSE > 0
1244         DBG_MSG("intelfbhw_program_mode\n");
1245 #endif
1246
1247         /* Disable VGA */
1248         tmp = INREG(VGACNTRL);
1249         tmp |= VGA_DISABLE;
1250         OUTREG(VGACNTRL, tmp);
1251
1252         /* Check whether pipe A or pipe B is enabled. */
1253         if (hw->pipe_a_conf & PIPECONF_ENABLE)
1254                 pipe = PIPE_A;
1255         else if (hw->pipe_b_conf & PIPECONF_ENABLE)
1256                 pipe = PIPE_B;
1257
1258         dinfo->pipe = pipe;
1259
1260         if (pipe == PIPE_B) {
1261                 dpll = &hw->dpll_b;
1262                 fp0 = &hw->fpb0;
1263                 fp1 = &hw->fpb1;
1264                 pipe_conf = &hw->pipe_b_conf;
1265                 hs = &hw->hsync_b;
1266                 hb = &hw->hblank_b;
1267                 ht = &hw->htotal_b;
1268                 vs = &hw->vsync_b;
1269                 vb = &hw->vblank_b;
1270                 vt = &hw->vtotal_b;
1271                 ss = &hw->src_size_b;
1272                 dpll_reg = DPLL_B;
1273                 fp0_reg = FPB0;
1274                 fp1_reg = FPB1;
1275                 pipe_conf_reg = PIPEBCONF;
1276                 hsync_reg = HSYNC_B;
1277                 htotal_reg = HTOTAL_B;
1278                 hblank_reg = HBLANK_B;
1279                 vsync_reg = VSYNC_B;
1280                 vtotal_reg = VTOTAL_B;
1281                 vblank_reg = VBLANK_B;
1282                 src_size_reg = SRC_SIZE_B;
1283         } else {
1284                 dpll = &hw->dpll_a;
1285                 fp0 = &hw->fpa0;
1286                 fp1 = &hw->fpa1;
1287                 pipe_conf = &hw->pipe_a_conf;
1288                 hs = &hw->hsync_a;
1289                 hb = &hw->hblank_a;
1290                 ht = &hw->htotal_a;
1291                 vs = &hw->vsync_a;
1292                 vb = &hw->vblank_a;
1293                 vt = &hw->vtotal_a;
1294                 ss = &hw->src_size_a;
1295                 dpll_reg = DPLL_A;
1296                 fp0_reg = FPA0;
1297                 fp1_reg = FPA1;
1298                 pipe_conf_reg = PIPEACONF;
1299                 hsync_reg = HSYNC_A;
1300                 htotal_reg = HTOTAL_A;
1301                 hblank_reg = HBLANK_A;
1302                 vsync_reg = VSYNC_A;
1303                 vtotal_reg = VTOTAL_A;
1304                 vblank_reg = VBLANK_A;
1305                 src_size_reg = SRC_SIZE_A;
1306         }
1307
1308         /* turn off pipe */
1309         tmp = INREG(pipe_conf_reg);
1310         tmp &= ~PIPECONF_ENABLE;
1311         OUTREG(pipe_conf_reg, tmp);
1312
1313         count = 0;
1314         do {
1315                 tmp_val[count%3] = INREG(0x70000);
1316                 if ((tmp_val[0] == tmp_val[1]) && (tmp_val[1]==tmp_val[2]))
1317                         break;
1318                 count++;
1319                 udelay(1);
1320                 if (count % 200 == 0) {
1321                         tmp = INREG(pipe_conf_reg);
1322                         tmp &= ~PIPECONF_ENABLE;
1323                         OUTREG(pipe_conf_reg, tmp);
1324                 }
1325         } while(count < 2000);
1326
1327         OUTREG(ADPA, INREG(ADPA) & ~ADPA_DAC_ENABLE);
1328
1329         /* Disable planes A and B. */
1330         tmp = INREG(DSPACNTR);
1331         tmp &= ~DISPPLANE_PLANE_ENABLE;
1332         OUTREG(DSPACNTR, tmp);
1333         tmp = INREG(DSPBCNTR);
1334         tmp &= ~DISPPLANE_PLANE_ENABLE;
1335         OUTREG(DSPBCNTR, tmp);
1336
1337         /* Wait for vblank. For now, just wait for a 50Hz cycle (20ms)) */
1338         mdelay(20);
1339
1340         OUTREG(DVOB, INREG(DVOB) & ~PORT_ENABLE);
1341         OUTREG(DVOC, INREG(DVOC) & ~PORT_ENABLE);
1342         OUTREG(ADPA, INREG(ADPA) & ~ADPA_DAC_ENABLE);
1343
1344         /* Disable Sync */
1345         tmp = INREG(ADPA);
1346         tmp &= ~ADPA_DPMS_CONTROL_MASK;
1347         tmp |= ADPA_DPMS_D3;
1348         OUTREG(ADPA, tmp);
1349
1350         /* do some funky magic - xyzzy */
1351         OUTREG(0x61204, 0xabcd0000);
1352
1353         /* turn off PLL */
1354         tmp = INREG(dpll_reg);
1355         dpll_reg &= ~DPLL_VCO_ENABLE;
1356         OUTREG(dpll_reg, tmp);
1357
1358         /* Set PLL parameters */
1359         OUTREG(fp0_reg, *fp0);
1360         OUTREG(fp1_reg, *fp1);
1361
1362         /* Enable PLL */
1363         OUTREG(dpll_reg, *dpll);
1364
1365         /* Set DVOs B/C */
1366         OUTREG(DVOB, hw->dvob);
1367         OUTREG(DVOC, hw->dvoc);
1368
1369         /* undo funky magic */
1370         OUTREG(0x61204, 0x00000000);
1371
1372         /* Set ADPA */
1373         OUTREG(ADPA, INREG(ADPA) | ADPA_DAC_ENABLE);
1374         OUTREG(ADPA, (hw->adpa & ~(ADPA_DPMS_CONTROL_MASK)) | ADPA_DPMS_D3);
1375
1376         /* Set pipe parameters */
1377         OUTREG(hsync_reg, *hs);
1378         OUTREG(hblank_reg, *hb);
1379         OUTREG(htotal_reg, *ht);
1380         OUTREG(vsync_reg, *vs);
1381         OUTREG(vblank_reg, *vb);
1382         OUTREG(vtotal_reg, *vt);
1383         OUTREG(src_size_reg, *ss);
1384
1385         /* Enable pipe */
1386         OUTREG(pipe_conf_reg, *pipe_conf | PIPECONF_ENABLE);
1387
1388         /* Enable sync */
1389         tmp = INREG(ADPA);
1390         tmp &= ~ADPA_DPMS_CONTROL_MASK;
1391         tmp |= ADPA_DPMS_D0;
1392         OUTREG(ADPA, tmp);
1393
1394         /* setup display plane */
1395         if (dinfo->pdev->device == PCI_DEVICE_ID_INTEL_830M) {
1396                 /*
1397                  *      i830M errata: the display plane must be enabled
1398                  *      to allow writes to the other bits in the plane
1399                  *      control register.
1400                  */
1401                 tmp = INREG(DSPACNTR);
1402                 if ((tmp & DISPPLANE_PLANE_ENABLE) != DISPPLANE_PLANE_ENABLE) {
1403                         tmp |= DISPPLANE_PLANE_ENABLE;
1404                         OUTREG(DSPACNTR, tmp);
1405                         OUTREG(DSPACNTR,
1406                                hw->disp_a_ctrl|DISPPLANE_PLANE_ENABLE);
1407                         mdelay(1);
1408                 }
1409         }
1410
1411         OUTREG(DSPACNTR, hw->disp_a_ctrl & ~DISPPLANE_PLANE_ENABLE);
1412         OUTREG(DSPASTRIDE, hw->disp_a_stride);
1413         OUTREG(DSPABASE, hw->disp_a_base);
1414
1415         /* Enable plane */
1416         if (!blank) {
1417                 tmp = INREG(DSPACNTR);
1418                 tmp |= DISPPLANE_PLANE_ENABLE;
1419                 OUTREG(DSPACNTR, tmp);
1420                 OUTREG(DSPABASE, hw->disp_a_base);
1421         }
1422
1423         return 0;
1424 }
1425
1426 /* forward declarations */
1427 static void refresh_ring(struct intelfb_info *dinfo);
1428 static void reset_state(struct intelfb_info *dinfo);
1429 static void do_flush(struct intelfb_info *dinfo);
1430
1431 static  u32 get_ring_space(struct intelfb_info *dinfo)
1432 {
1433         u32 ring_space;
1434
1435         if (dinfo->ring_tail >= dinfo->ring_head)
1436                 ring_space = dinfo->ring.size -
1437                         (dinfo->ring_tail - dinfo->ring_head);
1438         else
1439                 ring_space = dinfo->ring_head - dinfo->ring_tail;
1440
1441         if (ring_space > RING_MIN_FREE)
1442                 ring_space -= RING_MIN_FREE;
1443         else
1444                 ring_space = 0;
1445
1446         return ring_space;
1447 }
1448
1449 static int
1450 wait_ring(struct intelfb_info *dinfo, int n)
1451 {
1452         int i = 0;
1453         unsigned long end;
1454         u32 last_head = INREG(PRI_RING_HEAD) & RING_HEAD_MASK;
1455
1456 #if VERBOSE > 0
1457         DBG_MSG("wait_ring: %d\n", n);
1458 #endif
1459
1460         end = jiffies + (HZ * 3);
1461         while (dinfo->ring_space < n) {
1462                 dinfo->ring_head = INREG(PRI_RING_HEAD) & RING_HEAD_MASK;
1463                 dinfo->ring_space = get_ring_space(dinfo);
1464
1465                 if (dinfo->ring_head != last_head) {
1466                         end = jiffies + (HZ * 3);
1467                         last_head = dinfo->ring_head;
1468                 }
1469                 i++;
1470                 if (time_before(end, jiffies)) {
1471                         if (!i) {
1472                                 /* Try again */
1473                                 reset_state(dinfo);
1474                                 refresh_ring(dinfo);
1475                                 do_flush(dinfo);
1476                                 end = jiffies + (HZ * 3);
1477                                 i = 1;
1478                         } else {
1479                                 WRN_MSG("ring buffer : space: %d wanted %d\n",
1480                                         dinfo->ring_space, n);
1481                                 WRN_MSG("lockup - turning off hardware "
1482                                         "acceleration\n");
1483                                 dinfo->ring_lockup = 1;
1484                                 break;
1485                         }
1486                 }
1487                 udelay(1);
1488         }
1489         return i;
1490 }
1491
1492 static void
1493 do_flush(struct intelfb_info *dinfo) {
1494         START_RING(2);
1495         OUT_RING(MI_FLUSH | MI_WRITE_DIRTY_STATE | MI_INVALIDATE_MAP_CACHE);
1496         OUT_RING(MI_NOOP);
1497         ADVANCE_RING();
1498 }
1499
1500 void
1501 intelfbhw_do_sync(struct intelfb_info *dinfo)
1502 {
1503 #if VERBOSE > 0
1504         DBG_MSG("intelfbhw_do_sync\n");
1505 #endif
1506
1507         if (!dinfo->accel)
1508                 return;
1509
1510         /*
1511          * Send a flush, then wait until the ring is empty.  This is what
1512          * the XFree86 driver does, and actually it doesn't seem a lot worse
1513          * than the recommended method (both have problems).
1514          */
1515         do_flush(dinfo);
1516         wait_ring(dinfo, dinfo->ring.size - RING_MIN_FREE);
1517         dinfo->ring_space = dinfo->ring.size - RING_MIN_FREE;
1518 }
1519
1520 static void
1521 refresh_ring(struct intelfb_info *dinfo)
1522 {
1523 #if VERBOSE > 0
1524         DBG_MSG("refresh_ring\n");
1525 #endif
1526
1527         dinfo->ring_head = INREG(PRI_RING_HEAD) & RING_HEAD_MASK;
1528         dinfo->ring_tail = INREG(PRI_RING_TAIL) & RING_TAIL_MASK;
1529         dinfo->ring_space = get_ring_space(dinfo);
1530 }
1531
1532 static void
1533 reset_state(struct intelfb_info *dinfo)
1534 {
1535         int i;
1536         u32 tmp;
1537
1538 #if VERBOSE > 0
1539         DBG_MSG("reset_state\n");
1540 #endif
1541
1542         for (i = 0; i < FENCE_NUM; i++)
1543                 OUTREG(FENCE + (i << 2), 0);
1544
1545         /* Flush the ring buffer if it's enabled. */
1546         tmp = INREG(PRI_RING_LENGTH);
1547         if (tmp & RING_ENABLE) {
1548 #if VERBOSE > 0
1549                 DBG_MSG("reset_state: ring was enabled\n");
1550 #endif
1551                 refresh_ring(dinfo);
1552                 intelfbhw_do_sync(dinfo);
1553                 DO_RING_IDLE();
1554         }
1555
1556         OUTREG(PRI_RING_LENGTH, 0);
1557         OUTREG(PRI_RING_HEAD, 0);
1558         OUTREG(PRI_RING_TAIL, 0);
1559         OUTREG(PRI_RING_START, 0);
1560 }
1561
1562 /* Stop the 2D engine, and turn off the ring buffer. */
1563 void
1564 intelfbhw_2d_stop(struct intelfb_info *dinfo)
1565 {
1566 #if VERBOSE > 0
1567         DBG_MSG("intelfbhw_2d_stop: accel: %d, ring_active: %d\n", dinfo->accel,
1568                 dinfo->ring_active);
1569 #endif
1570
1571         if (!dinfo->accel)
1572                 return;
1573
1574         dinfo->ring_active = 0;
1575         reset_state(dinfo);
1576 }
1577
1578 /*
1579  * Enable the ring buffer, and initialise the 2D engine.
1580  * It is assumed that the graphics engine has been stopped by previously
1581  * calling intelfb_2d_stop().
1582  */
1583 void
1584 intelfbhw_2d_start(struct intelfb_info *dinfo)
1585 {
1586 #if VERBOSE > 0
1587         DBG_MSG("intelfbhw_2d_start: accel: %d, ring_active: %d\n",
1588                 dinfo->accel, dinfo->ring_active);
1589 #endif
1590
1591         if (!dinfo->accel)
1592                 return;
1593
1594         /* Initialise the primary ring buffer. */
1595         OUTREG(PRI_RING_LENGTH, 0);
1596         OUTREG(PRI_RING_TAIL, 0);
1597         OUTREG(PRI_RING_HEAD, 0);
1598
1599         OUTREG(PRI_RING_START, dinfo->ring.physical & RING_START_MASK);
1600         OUTREG(PRI_RING_LENGTH,
1601                 ((dinfo->ring.size - GTT_PAGE_SIZE) & RING_LENGTH_MASK) |
1602                 RING_NO_REPORT | RING_ENABLE);
1603         refresh_ring(dinfo);
1604         dinfo->ring_active = 1;
1605 }
1606
1607 /* 2D fillrect (solid fill or invert) */
1608 void
1609 intelfbhw_do_fillrect(struct intelfb_info *dinfo, u32 x, u32 y, u32 w, u32 h,
1610                       u32 color, u32 pitch, u32 bpp, u32 rop)
1611 {
1612         u32 br00, br09, br13, br14, br16;
1613
1614 #if VERBOSE > 0
1615         DBG_MSG("intelfbhw_do_fillrect: (%d,%d) %dx%d, c 0x%06x, p %d bpp %d, "
1616                 "rop 0x%02x\n", x, y, w, h, color, pitch, bpp, rop);
1617 #endif
1618
1619         br00 = COLOR_BLT_CMD;
1620         br09 = dinfo->fb_start + (y * pitch + x * (bpp / 8));
1621         br13 = (rop << ROP_SHIFT) | pitch;
1622         br14 = (h << HEIGHT_SHIFT) | ((w * (bpp / 8)) << WIDTH_SHIFT);
1623         br16 = color;
1624
1625         switch (bpp) {
1626         case 8:
1627                 br13 |= COLOR_DEPTH_8;
1628                 break;
1629         case 16:
1630                 br13 |= COLOR_DEPTH_16;
1631                 break;
1632         case 32:
1633                 br13 |= COLOR_DEPTH_32;
1634                 br00 |= WRITE_ALPHA | WRITE_RGB;
1635                 break;
1636         }
1637
1638         START_RING(6);
1639         OUT_RING(br00);
1640         OUT_RING(br13);
1641         OUT_RING(br14);
1642         OUT_RING(br09);
1643         OUT_RING(br16);
1644         OUT_RING(MI_NOOP);
1645         ADVANCE_RING();
1646
1647 #if VERBOSE > 0
1648         DBG_MSG("ring = 0x%08x, 0x%08x (%d)\n", dinfo->ring_head,
1649                 dinfo->ring_tail, dinfo->ring_space);
1650 #endif
1651 }
1652
1653 void
1654 intelfbhw_do_bitblt(struct intelfb_info *dinfo, u32 curx, u32 cury,
1655                     u32 dstx, u32 dsty, u32 w, u32 h, u32 pitch, u32 bpp)
1656 {
1657         u32 br00, br09, br11, br12, br13, br22, br23, br26;
1658
1659 #if VERBOSE > 0
1660         DBG_MSG("intelfbhw_do_bitblt: (%d,%d)->(%d,%d) %dx%d, p %d bpp %d\n",
1661                 curx, cury, dstx, dsty, w, h, pitch, bpp);
1662 #endif
1663
1664         br00 = XY_SRC_COPY_BLT_CMD;
1665         br09 = dinfo->fb_start;
1666         br11 = (pitch << PITCH_SHIFT);
1667         br12 = dinfo->fb_start;
1668         br13 = (SRC_ROP_GXCOPY << ROP_SHIFT) | (pitch << PITCH_SHIFT);
1669         br22 = (dstx << WIDTH_SHIFT) | (dsty << HEIGHT_SHIFT);
1670         br23 = ((dstx + w) << WIDTH_SHIFT) |
1671                ((dsty + h) << HEIGHT_SHIFT);
1672         br26 = (curx << WIDTH_SHIFT) | (cury << HEIGHT_SHIFT);
1673
1674         switch (bpp) {
1675         case 8:
1676                 br13 |= COLOR_DEPTH_8;
1677                 break;
1678         case 16:
1679                 br13 |= COLOR_DEPTH_16;
1680                 break;
1681         case 32:
1682                 br13 |= COLOR_DEPTH_32;
1683                 br00 |= WRITE_ALPHA | WRITE_RGB;
1684                 break;
1685         }
1686
1687         START_RING(8);
1688         OUT_RING(br00);
1689         OUT_RING(br13);
1690         OUT_RING(br22);
1691         OUT_RING(br23);
1692         OUT_RING(br09);
1693         OUT_RING(br26);
1694         OUT_RING(br11);
1695         OUT_RING(br12);
1696         ADVANCE_RING();
1697 }
1698
1699 int
1700 intelfbhw_do_drawglyph(struct intelfb_info *dinfo, u32 fg, u32 bg, u32 w,
1701                        u32 h, const u8* cdat, u32 x, u32 y, u32 pitch, u32 bpp)
1702 {
1703         int nbytes, ndwords, pad, tmp;
1704         u32 br00, br09, br13, br18, br19, br22, br23;
1705         int dat, ix, iy, iw;
1706         int i, j;
1707
1708 #if VERBOSE > 0
1709         DBG_MSG("intelfbhw_do_drawglyph: (%d,%d) %dx%d\n", x, y, w, h);
1710 #endif
1711
1712         /* size in bytes of a padded scanline */
1713         nbytes = ROUND_UP_TO(w, 16) / 8;
1714
1715         /* Total bytes of padded scanline data to write out. */
1716         nbytes = nbytes * h;
1717
1718         /*
1719          * Check if the glyph data exceeds the immediate mode limit.
1720          * It would take a large font (1K pixels) to hit this limit.
1721          */
1722         if (nbytes > MAX_MONO_IMM_SIZE)
1723                 return 0;
1724
1725         /* Src data is packaged a dword (32-bit) at a time. */
1726         ndwords = ROUND_UP_TO(nbytes, 4) / 4;
1727
1728         /*
1729          * Ring has to be padded to a quad word. But because the command starts
1730            with 7 bytes, pad only if there is an even number of ndwords
1731          */
1732         pad = !(ndwords % 2);
1733
1734         tmp = (XY_MONO_SRC_IMM_BLT_CMD & DW_LENGTH_MASK) + ndwords;
1735         br00 = (XY_MONO_SRC_IMM_BLT_CMD & ~DW_LENGTH_MASK) | tmp;
1736         br09 = dinfo->fb_start;
1737         br13 = (SRC_ROP_GXCOPY << ROP_SHIFT) | (pitch << PITCH_SHIFT);
1738         br18 = bg;
1739         br19 = fg;
1740         br22 = (x << WIDTH_SHIFT) | (y << HEIGHT_SHIFT);
1741         br23 = ((x + w) << WIDTH_SHIFT) | ((y + h) << HEIGHT_SHIFT);
1742
1743         switch (bpp) {
1744         case 8:
1745                 br13 |= COLOR_DEPTH_8;
1746                 break;
1747         case 16:
1748                 br13 |= COLOR_DEPTH_16;
1749                 break;
1750         case 32:
1751                 br13 |= COLOR_DEPTH_32;
1752                 br00 |= WRITE_ALPHA | WRITE_RGB;
1753                 break;
1754         }
1755
1756         START_RING(8 + ndwords);
1757         OUT_RING(br00);
1758         OUT_RING(br13);
1759         OUT_RING(br22);
1760         OUT_RING(br23);
1761         OUT_RING(br09);
1762         OUT_RING(br18);
1763         OUT_RING(br19);
1764         ix = iy = 0;
1765         iw = ROUND_UP_TO(w, 8) / 8;
1766         while (ndwords--) {
1767                 dat = 0;
1768                 for (j = 0; j < 2; ++j) {
1769                         for (i = 0; i < 2; ++i) {
1770                                 if (ix != iw || i == 0)
1771                                         dat |= cdat[iy*iw + ix++] << (i+j*2)*8;
1772                         }
1773                         if (ix == iw && iy != (h-1)) {
1774                                 ix = 0;
1775                                 ++iy;
1776                         }
1777                 }
1778                 OUT_RING(dat);
1779         }
1780         if (pad)
1781                 OUT_RING(MI_NOOP);
1782         ADVANCE_RING();
1783
1784         return 1;
1785 }
1786
1787 /* HW cursor functions. */
1788 void
1789 intelfbhw_cursor_init(struct intelfb_info *dinfo)
1790 {
1791         u32 tmp;
1792
1793 #if VERBOSE > 0
1794         DBG_MSG("intelfbhw_cursor_init\n");
1795 #endif
1796
1797         if (dinfo->mobile || IS_I9XX(dinfo)) {
1798                 if (!dinfo->cursor.physical)
1799                         return;
1800                 tmp = INREG(CURSOR_A_CONTROL);
1801                 tmp &= ~(CURSOR_MODE_MASK | CURSOR_MOBILE_GAMMA_ENABLE |
1802                          CURSOR_MEM_TYPE_LOCAL |
1803                          (1 << CURSOR_PIPE_SELECT_SHIFT));
1804                 tmp |= CURSOR_MODE_DISABLE;
1805                 OUTREG(CURSOR_A_CONTROL, tmp);
1806                 OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.physical);
1807         } else {
1808                 tmp = INREG(CURSOR_CONTROL);
1809                 tmp &= ~(CURSOR_FORMAT_MASK | CURSOR_GAMMA_ENABLE |
1810                          CURSOR_ENABLE | CURSOR_STRIDE_MASK);
1811                 tmp = CURSOR_FORMAT_3C;
1812                 OUTREG(CURSOR_CONTROL, tmp);
1813                 OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.offset << 12);
1814                 tmp = (64 << CURSOR_SIZE_H_SHIFT) |
1815                       (64 << CURSOR_SIZE_V_SHIFT);
1816                 OUTREG(CURSOR_SIZE, tmp);
1817         }
1818 }
1819
1820 void
1821 intelfbhw_cursor_hide(struct intelfb_info *dinfo)
1822 {
1823         u32 tmp;
1824
1825 #if VERBOSE > 0
1826         DBG_MSG("intelfbhw_cursor_hide\n");
1827 #endif
1828
1829         dinfo->cursor_on = 0;
1830         if (dinfo->mobile || IS_I9XX(dinfo)) {
1831                 if (!dinfo->cursor.physical)
1832                         return;
1833                 tmp = INREG(CURSOR_A_CONTROL);
1834                 tmp &= ~CURSOR_MODE_MASK;
1835                 tmp |= CURSOR_MODE_DISABLE;
1836                 OUTREG(CURSOR_A_CONTROL, tmp);
1837                 /* Flush changes */
1838                 OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.physical);
1839         } else {
1840                 tmp = INREG(CURSOR_CONTROL);
1841                 tmp &= ~CURSOR_ENABLE;
1842                 OUTREG(CURSOR_CONTROL, tmp);
1843         }
1844 }
1845
1846 void
1847 intelfbhw_cursor_show(struct intelfb_info *dinfo)
1848 {
1849         u32 tmp;
1850
1851 #if VERBOSE > 0
1852         DBG_MSG("intelfbhw_cursor_show\n");
1853 #endif
1854
1855         dinfo->cursor_on = 1;
1856
1857         if (dinfo->cursor_blanked)
1858                 return;
1859
1860         if (dinfo->mobile || IS_I9XX(dinfo)) {
1861                 if (!dinfo->cursor.physical)
1862                         return;
1863                 tmp = INREG(CURSOR_A_CONTROL);
1864                 tmp &= ~CURSOR_MODE_MASK;
1865                 tmp |= CURSOR_MODE_64_4C_AX;
1866                 OUTREG(CURSOR_A_CONTROL, tmp);
1867                 /* Flush changes */
1868                 OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.physical);
1869         } else {
1870                 tmp = INREG(CURSOR_CONTROL);
1871                 tmp |= CURSOR_ENABLE;
1872                 OUTREG(CURSOR_CONTROL, tmp);
1873         }
1874 }
1875
1876 void
1877 intelfbhw_cursor_setpos(struct intelfb_info *dinfo, int x, int y)
1878 {
1879         u32 tmp;
1880
1881 #if VERBOSE > 0
1882         DBG_MSG("intelfbhw_cursor_setpos: (%d, %d)\n", x, y);
1883 #endif
1884
1885         /*
1886          * Sets the position. The coordinates are assumed to already
1887          * have any offset adjusted. Assume that the cursor is never
1888          * completely off-screen, and that x, y are always >= 0.
1889          */
1890
1891         tmp = ((x & CURSOR_POS_MASK) << CURSOR_X_SHIFT) |
1892               ((y & CURSOR_POS_MASK) << CURSOR_Y_SHIFT);
1893         OUTREG(CURSOR_A_POSITION, tmp);
1894
1895         if (IS_I9XX(dinfo)) {
1896                 OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.physical);
1897         }
1898 }
1899
1900 void
1901 intelfbhw_cursor_setcolor(struct intelfb_info *dinfo, u32 bg, u32 fg)
1902 {
1903 #if VERBOSE > 0
1904         DBG_MSG("intelfbhw_cursor_setcolor\n");
1905 #endif
1906
1907         OUTREG(CURSOR_A_PALETTE0, bg & CURSOR_PALETTE_MASK);
1908         OUTREG(CURSOR_A_PALETTE1, fg & CURSOR_PALETTE_MASK);
1909         OUTREG(CURSOR_A_PALETTE2, fg & CURSOR_PALETTE_MASK);
1910         OUTREG(CURSOR_A_PALETTE3, bg & CURSOR_PALETTE_MASK);
1911 }
1912
1913 void
1914 intelfbhw_cursor_load(struct intelfb_info *dinfo, int width, int height,
1915                       u8 *data)
1916 {
1917         u8 __iomem *addr = (u8 __iomem *)dinfo->cursor.virtual;
1918         int i, j, w = width / 8;
1919         int mod = width % 8, t_mask, d_mask;
1920
1921 #if VERBOSE > 0
1922         DBG_MSG("intelfbhw_cursor_load\n");
1923 #endif
1924
1925         if (!dinfo->cursor.virtual)
1926                 return;
1927
1928         t_mask = 0xff >> mod;
1929         d_mask = ~(0xff >> mod);
1930         for (i = height; i--; ) {
1931                 for (j = 0; j < w; j++) {
1932                         writeb(0x00, addr + j);
1933                         writeb(*(data++), addr + j+8);
1934                 }
1935                 if (mod) {
1936                         writeb(t_mask, addr + j);
1937                         writeb(*(data++) & d_mask, addr + j+8);
1938                 }
1939                 addr += 16;
1940         }
1941 }
1942
1943 void
1944 intelfbhw_cursor_reset(struct intelfb_info *dinfo) {
1945         u8 __iomem *addr = (u8 __iomem *)dinfo->cursor.virtual;
1946         int i, j;
1947
1948 #if VERBOSE > 0
1949         DBG_MSG("intelfbhw_cursor_reset\n");
1950 #endif
1951
1952         if (!dinfo->cursor.virtual)
1953                 return;
1954
1955         for (i = 64; i--; ) {
1956                 for (j = 0; j < 8; j++) {
1957                         writeb(0xff, addr + j+0);
1958                         writeb(0x00, addr + j+8);
1959                 }
1960                 addr += 16;
1961         }
1962 }
1963
1964 static irqreturn_t
1965 intelfbhw_irq(int irq, void *dev_id) {
1966         int handled = 0;
1967         u16 tmp;
1968         struct intelfb_info *dinfo = (struct intelfb_info *)dev_id;
1969
1970         spin_lock(&dinfo->int_lock);
1971
1972         tmp = INREG16(IIR);
1973         tmp &= VSYNC_PIPE_A_INTERRUPT;
1974
1975         if (tmp == 0) {
1976                 spin_unlock(&dinfo->int_lock);
1977                 return IRQ_RETVAL(handled);
1978         }
1979
1980         OUTREG16(IIR, tmp);
1981
1982         if (tmp & VSYNC_PIPE_A_INTERRUPT) {
1983                 dinfo->vsync.count++;
1984                 if (dinfo->vsync.pan_display) {
1985                         dinfo->vsync.pan_display = 0;
1986                         OUTREG(DSPABASE, dinfo->vsync.pan_offset);
1987                 }
1988                 wake_up_interruptible(&dinfo->vsync.wait);
1989                 handled = 1;
1990         }
1991
1992         spin_unlock(&dinfo->int_lock);
1993
1994         return IRQ_RETVAL(handled);
1995 }
1996
1997 int
1998 intelfbhw_enable_irq(struct intelfb_info *dinfo, int reenable) {
1999
2000         if (!test_and_set_bit(0, &dinfo->irq_flags)) {
2001                 if (request_irq(dinfo->pdev->irq, intelfbhw_irq, IRQF_SHARED,
2002                      "intelfb", dinfo)) {
2003                         clear_bit(0, &dinfo->irq_flags);
2004                         return -EINVAL;
2005                 }
2006
2007                 spin_lock_irq(&dinfo->int_lock);
2008                 OUTREG16(HWSTAM, 0xfffe);
2009                 OUTREG16(IMR, 0x0);
2010                 OUTREG16(IER, VSYNC_PIPE_A_INTERRUPT);
2011                 spin_unlock_irq(&dinfo->int_lock);
2012         } else if (reenable) {
2013                 u16 ier;
2014
2015                 spin_lock_irq(&dinfo->int_lock);
2016                 ier = INREG16(IER);
2017                 if ((ier & VSYNC_PIPE_A_INTERRUPT)) {
2018                         DBG_MSG("someone disabled the IRQ [%08X]\n", ier);
2019                         OUTREG(IER, VSYNC_PIPE_A_INTERRUPT);
2020                 }
2021                 spin_unlock_irq(&dinfo->int_lock);
2022         }
2023         return 0;
2024 }
2025
2026 void
2027 intelfbhw_disable_irq(struct intelfb_info *dinfo) {
2028         u16 tmp;
2029
2030         if (test_and_clear_bit(0, &dinfo->irq_flags)) {
2031                 if (dinfo->vsync.pan_display) {
2032                         dinfo->vsync.pan_display = 0;
2033                         OUTREG(DSPABASE, dinfo->vsync.pan_offset);
2034                 }
2035                 spin_lock_irq(&dinfo->int_lock);
2036                 OUTREG16(HWSTAM, 0xffff);
2037                 OUTREG16(IMR, 0xffff);
2038                 OUTREG16(IER, 0x0);
2039
2040                 tmp = INREG16(IIR);
2041                 OUTREG16(IIR, tmp);
2042                 spin_unlock_irq(&dinfo->int_lock);
2043
2044                 free_irq(dinfo->pdev->irq, dinfo);
2045         }
2046 }
2047
2048 int
2049 intelfbhw_wait_for_vsync(struct intelfb_info *dinfo, u32 pipe) {
2050         struct intelfb_vsync *vsync;
2051         unsigned int count;
2052         int ret;
2053
2054         switch (pipe) {
2055                 case 0:
2056                         vsync = &dinfo->vsync;
2057                         break;
2058                 default:
2059                         return -ENODEV;
2060         }
2061
2062         ret = intelfbhw_enable_irq(dinfo, 0);
2063         if (ret) {
2064                 return ret;
2065         }
2066
2067         count = vsync->count;
2068         ret = wait_event_interruptible_timeout(vsync->wait, count != vsync->count, HZ/10);
2069         if (ret < 0) {
2070                 return ret;
2071         }
2072         if (ret == 0) {
2073                 intelfbhw_enable_irq(dinfo, 1);
2074                 DBG_MSG("wait_for_vsync timed out!\n");
2075                 return -ETIMEDOUT;
2076         }
2077
2078         return 0;
2079 }