SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/video/intelfb/intelfbhw.c

   1 /*
   2  * intelfb
   3  *
   4  * Linux framebuffer driver for Intel(R) 865G integrated graphics chips.
   5  *
   6  * Copyright © 2002, 2003 David Dawes <dawes@xfree86.org>
   7  *                   2004 Sylvain Meyer
   8  *
   9  * This driver consists of two parts.  The first part (intelfbdrv.c) provides
  10  * the basic fbdev interfaces, is derived in part from the radeonfb and
  11  * vesafb drivers, and is covered by the GPL.  The second part (intelfbhw.c)
  12  * provides the code to program the hardware.  Most of it is derived from
  13  * the i810/i830 XFree86 driver.  The HW-specific code is covered here
  14  * under a dual license (GPL and MIT/XFree86 license).
  15  *
  16  * Author: David Dawes
  17  *
  18  */
  19
  20 /* $DHD: intelfb/intelfbhw.c,v 1.9 2003/06/27 15:06:25 dawes Exp $ */
  21
  22 #include <linux/config.h>
  23 #include <linux/module.h>
  24 #include <linux/kernel.h>
  25 #include <linux/errno.h>
  26 #include <linux/string.h>
  27 #include <linux/mm.h>
  28 #include <linux/tty.h>
  29 #include <linux/slab.h>
  30 #include <linux/delay.h>
  31 #include <linux/fb.h>
  32 #include <linux/ioport.h>
  33 #include <linux/init.h>
  34 #include <linux/pci.h>
  35 #include <linux/vmalloc.h>
  36 #include <linux/pagemap.h>
  37
  38 #include <asm/io.h>
  39
  40 #include "intelfb.h"
  41 #include "intelfbhw.h"
  42
  43 struct pll_min_max {
  44         int min_m, max_m, min_m1, max_m1;
  45         int min_m2, max_m2, min_n, max_n;
  46         int min_p, max_p, min_p1, max_p1;
  47         int min_vco, max_vco, p_transition_clk, ref_clk;
  48         int p_inc_lo, p_inc_hi;
  49 };
  50
  51 #define PLLS_I8xx 0
  52 #define PLLS_I9xx 1
  53 #define PLLS_MAX 2
  54
  55 static struct pll_min_max plls[PLLS_MAX] = {
  56         { 108, 140, 18, 26,
  57           6, 16, 3, 16,
  58           4, 128, 0, 31,
  59           930000, 1400000, 165000, 48000,
  60           4, 2 }, //I8xx
  61
  62         { 75, 120, 10, 20,
  63           5, 9, 4, 7,
  64           5, 80, 1, 8,
  65           1400000, 2800000, 200000, 96000,
  66           10, 5 }  //I9xx
  67 };
  68
  69 int
  70 intelfbhw_get_chipset(struct pci_dev *pdev, struct intelfb_info *dinfo)
  71 {
  72         u32 tmp;
  73         if (!pdev || !dinfo)
  74                 return 1;
  75
  76         switch (pdev->device) {
  77         case PCI_DEVICE_ID_INTEL_830M:
  78                 dinfo->name = "Intel(R) 830M";
  79                 dinfo->chipset = INTEL_830M;
  80                 dinfo->mobile = 1;
  81                 dinfo->pll_index = PLLS_I8xx;
  82                 return 0;
  83         case PCI_DEVICE_ID_INTEL_845G:
  84                 dinfo->name = "Intel(R) 845G";
  85                 dinfo->chipset = INTEL_845G;
  86                 dinfo->mobile = 0;
  87                 dinfo->pll_index = PLLS_I8xx;
  88                 return 0;
  89         case PCI_DEVICE_ID_INTEL_85XGM:
  90                 tmp = 0;
  91                 dinfo->mobile = 1;
  92                 dinfo->pll_index = PLLS_I8xx;
  93                 pci_read_config_dword(pdev, INTEL_85X_CAPID, &tmp);
  94                 switch ((tmp >> INTEL_85X_VARIANT_SHIFT) &
  95                         INTEL_85X_VARIANT_MASK) {
  96                 case INTEL_VAR_855GME:
  97                         dinfo->name = "Intel(R) 855GME";
  98                         dinfo->chipset = INTEL_855GME;
  99                         return 0;
 100                 case INTEL_VAR_855GM:
 101                         dinfo->name = "Intel(R) 855GM";
 102                         dinfo->chipset = INTEL_855GM;
 103                         return 0;
 104                 case INTEL_VAR_852GME:
 105                         dinfo->name = "Intel(R) 852GME";
 106                         dinfo->chipset = INTEL_852GME;
 107                         return 0;
 108                 case INTEL_VAR_852GM:
 109                         dinfo->name = "Intel(R) 852GM";
 110                         dinfo->chipset = INTEL_852GM;
 111                         return 0;
 112                 default:
 113                         dinfo->name = "Intel(R) 852GM/855GM";
 114                         dinfo->chipset = INTEL_85XGM;
 115                         return 0;
 116                 }
 117                 break;
 118         case PCI_DEVICE_ID_INTEL_865G:
 119                 dinfo->name = "Intel(R) 865G";
 120                 dinfo->chipset = INTEL_865G;
 121                 dinfo->mobile = 0;
 122                 dinfo->pll_index = PLLS_I8xx;
 123                 return 0;
 124         case PCI_DEVICE_ID_INTEL_915G:
 125                 dinfo->name = "Intel(R) 915G";
 126                 dinfo->chipset = INTEL_915G;
 127                 dinfo->mobile = 0;
 128                 dinfo->pll_index = PLLS_I9xx;
 129                 return 0;
 130         case PCI_DEVICE_ID_INTEL_915GM:
 131                 dinfo->name = "Intel(R) 915GM";
 132                 dinfo->chipset = INTEL_915GM;
 133                 dinfo->mobile = 1;
 134                 dinfo->pll_index = PLLS_I9xx;
 135                 return 0;
 136         case PCI_DEVICE_ID_INTEL_945G:
 137                 dinfo->name = "Intel(R) 945G";
 138                 dinfo->chipset = INTEL_945G;
 139                 dinfo->mobile = 0;
 140                 dinfo->pll_index = PLLS_I9xx;
 141                 return 0;
 142         case PCI_DEVICE_ID_INTEL_945GM:
 143                 dinfo->name = "Intel(R) 945GM";
 144                 dinfo->chipset = INTEL_945GM;
 145                 dinfo->mobile = 1;
 146                 dinfo->pll_index = PLLS_I9xx;
 147                 return 0;
 148         default:
 149                 return 1;
 150         }
 151 }
 152
 153 int
 154 intelfbhw_get_memory(struct pci_dev *pdev, int *aperture_size,
 155                      int *stolen_size)
 156 {
 157         struct pci_dev *bridge_dev;
 158         u16 tmp;
 159
 160         if (!pdev || !aperture_size || !stolen_size)
 161                 return 1;
 162
 163         /* Find the bridge device.  It is always 0:0.0 */
 164         if (!(bridge_dev = pci_find_slot(0, PCI_DEVFN(0, 0)))) {
 165                 ERR_MSG("cannot find bridge device\n");
 166                 return 1;
 167         }
 168
 169         /* Get the fb aperture size and "stolen" memory amount. */
 170         tmp = 0;
 171         pci_read_config_word(bridge_dev, INTEL_GMCH_CTRL, &tmp);
 172         switch (pdev->device) {
 173         case PCI_DEVICE_ID_INTEL_830M:
 174         case PCI_DEVICE_ID_INTEL_845G:
 175                 if ((tmp & INTEL_GMCH_MEM_MASK) == INTEL_GMCH_MEM_64M)
 176                         *aperture_size = MB(64);
 177                 else
 178                         *aperture_size = MB(128);
 179                 switch (tmp & INTEL_830_GMCH_GMS_MASK) {
 180                 case INTEL_830_GMCH_GMS_STOLEN_512:
 181                         *stolen_size = KB(512) - KB(132);
 182                         return 0;
 183                 case INTEL_830_GMCH_GMS_STOLEN_1024:
 184                         *stolen_size = MB(1) - KB(132);
 185                         return 0;
 186                 case INTEL_830_GMCH_GMS_STOLEN_8192:
 187                         *stolen_size = MB(8) - KB(132);
 188                         return 0;
 189                 case INTEL_830_GMCH_GMS_LOCAL:
 190                         ERR_MSG("only local memory found\n");
 191                         return 1;
 192                 case INTEL_830_GMCH_GMS_DISABLED:
 193                         ERR_MSG("video memory is disabled\n");
 194                         return 1;
 195                 default:
 196                         ERR_MSG("unexpected GMCH_GMS value: 0x%02x\n",
 197                                 tmp & INTEL_830_GMCH_GMS_MASK);
 198                         return 1;
 199                 }
 200                 break;
 201         default:
 202                 *aperture_size = MB(128);
 203                 switch (tmp & INTEL_855_GMCH_GMS_MASK) {
 204                 case INTEL_855_GMCH_GMS_STOLEN_1M:
 205                         *stolen_size = MB(1) - KB(132);
 206                         return 0;
 207                 case INTEL_855_GMCH_GMS_STOLEN_4M:
 208                         *stolen_size = MB(4) - KB(132);
 209                         return 0;
 210                 case INTEL_855_GMCH_GMS_STOLEN_8M:
 211                         *stolen_size = MB(8) - KB(132);
 212                         return 0;
 213                 case INTEL_855_GMCH_GMS_STOLEN_16M:
 214                         *stolen_size = MB(16) - KB(132);
 215                         return 0;
 216                 case INTEL_855_GMCH_GMS_STOLEN_32M:
 217                         *stolen_size = MB(32) - KB(132);
 218                         return 0;
 219                 case INTEL_915G_GMCH_GMS_STOLEN_48M:
 220                         *stolen_size = MB(48) - KB(132);
 221                         return 0;
 222                 case INTEL_915G_GMCH_GMS_STOLEN_64M:
 223                         *stolen_size = MB(64) - KB(132);
 224                         return 0;
 225                 case INTEL_855_GMCH_GMS_DISABLED:
 226                         ERR_MSG("video memory is disabled\n");
 227                         return 0;
 228                 default:
 229                         ERR_MSG("unexpected GMCH_GMS value: 0x%02x\n",
 230                                 tmp & INTEL_855_GMCH_GMS_MASK);
 231                         return 1;
 232                 }
 233         }
 234 }
 235
 236 int
 237 intelfbhw_check_non_crt(struct intelfb_info *dinfo)
 238 {
 239         int dvo = 0;
 240
 241         if (INREG(LVDS) & PORT_ENABLE)
 242                 dvo |= LVDS_PORT;
 243         if (INREG(DVOA) & PORT_ENABLE)
 244                 dvo |= DVOA_PORT;
 245         if (INREG(DVOB) & PORT_ENABLE)
 246                 dvo |= DVOB_PORT;
 247         if (INREG(DVOC) & PORT_ENABLE)
 248                 dvo |= DVOC_PORT;
 249
 250         return dvo;
 251 }
 252
 253 const char *
 254 intelfbhw_dvo_to_string(int dvo)
 255 {
 256         if (dvo & DVOA_PORT)
 257                 return "DVO port A";
 258         else if (dvo & DVOB_PORT)
 259                 return "DVO port B";
 260         else if (dvo & DVOC_PORT)
 261                 return "DVO port C";
 262         else if (dvo & LVDS_PORT)
 263                 return "LVDS port";
 264         else
 265                 return NULL;
 266 }
 267
 268
 269 int
 270 intelfbhw_validate_mode(struct intelfb_info *dinfo,
 271                         struct fb_var_screeninfo *var)
 272 {
 273         int bytes_per_pixel;
 274         int tmp;
 275
 276 #if VERBOSE > 0
 277         DBG_MSG("intelfbhw_validate_mode\n");
 278 #endif
 279
 280         bytes_per_pixel = var->bits_per_pixel / 8;
 281         if (bytes_per_pixel == 3)
 282                 bytes_per_pixel = 4;
 283
 284         /* Check if enough video memory. */
 285         tmp = var->yres_virtual * var->xres_virtual * bytes_per_pixel;
 286         if (tmp > dinfo->fb.size) {
 287                 WRN_MSG("Not enough video ram for mode "
 288                         "(%d KByte vs %d KByte).\n",
 289                         BtoKB(tmp), BtoKB(dinfo->fb.size));
 290                 return 1;
 291         }
 292
 293         /* Check if x/y limits are OK. */
 294         if (var->xres - 1 > HACTIVE_MASK) {
 295                 WRN_MSG("X resolution too large (%d vs %d).\n",
 296                         var->xres, HACTIVE_MASK + 1);
 297                 return 1;
 298         }
 299         if (var->yres - 1 > VACTIVE_MASK) {
 300                 WRN_MSG("Y resolution too large (%d vs %d).\n",
 301                         var->yres, VACTIVE_MASK + 1);
 302                 return 1;
 303         }
 304
 305         /* Check for interlaced/doublescan modes. */
 306         if (var->vmode & FB_VMODE_INTERLACED) {
 307                 WRN_MSG("Mode is interlaced.\n");
 308                 return 1;
 309         }
 310         if (var->vmode & FB_VMODE_DOUBLE) {
 311                 WRN_MSG("Mode is double-scan.\n");
 312                 return 1;
 313         }
 314
 315         /* Check if clock is OK. */
 316         tmp = 1000000000 / var->pixclock;
 317         if (tmp < MIN_CLOCK) {
 318                 WRN_MSG("Pixel clock is too low (%d MHz vs %d MHz).\n",
 319                         (tmp + 500) / 1000, MIN_CLOCK / 1000);
 320                 return 1;
 321         }
 322         if (tmp > MAX_CLOCK) {
 323                 WRN_MSG("Pixel clock is too high (%d MHz vs %d MHz).\n",
 324                         (tmp + 500) / 1000, MAX_CLOCK / 1000);
 325                 return 1;
 326         }
 327
 328         return 0;
 329 }
 330
 331 int
 332 intelfbhw_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
 333 {
 334         struct intelfb_info *dinfo = GET_DINFO(info);
 335         u32 offset, xoffset, yoffset;
 336
 337 #if VERBOSE > 0
 338         DBG_MSG("intelfbhw_pan_display\n");
 339 #endif
 340
 341         xoffset = ROUND_DOWN_TO(var->xoffset, 8);
 342         yoffset = var->yoffset;
 343
 344         if ((xoffset + var->xres > var->xres_virtual) ||
 345             (yoffset + var->yres > var->yres_virtual))
 346                 return -EINVAL;
 347
 348         offset = (yoffset * dinfo->pitch) +
 349                  (xoffset * var->bits_per_pixel) / 8;
 350
 351         offset += dinfo->fb.offset << 12;
 352
 353         OUTREG(DSPABASE, offset);
 354
 355         return 0;
 356 }
 357
 358 /* Blank the screen. */
 359 void
 360 intelfbhw_do_blank(int blank, struct fb_info *info)
 361 {
 362         struct intelfb_info *dinfo = GET_DINFO(info);
 363         u32 tmp;
 364
 365 #if VERBOSE > 0
 366         DBG_MSG("intelfbhw_do_blank: blank is %d\n", blank);
 367 #endif
 368
 369         /* Turn plane A on or off */
 370         tmp = INREG(DSPACNTR);
 371         if (blank)
 372                 tmp &= ~DISPPLANE_PLANE_ENABLE;
 373         else
 374                 tmp |= DISPPLANE_PLANE_ENABLE;
 375         OUTREG(DSPACNTR, tmp);
 376         /* Flush */
 377         tmp = INREG(DSPABASE);
 378         OUTREG(DSPABASE, tmp);
 379
 380         /* Turn off/on the HW cursor */
 381 #if VERBOSE > 0
 382         DBG_MSG("cursor_on is %d\n", dinfo->cursor_on);
 383 #endif
 384         if (dinfo->cursor_on) {
 385                 if (blank) {
 386                         intelfbhw_cursor_hide(dinfo);
 387                 } else {
 388                         intelfbhw_cursor_show(dinfo);
 389                 }
 390                 dinfo->cursor_on = 1;
 391         }
 392         dinfo->cursor_blanked = blank;
 393
 394         /* Set DPMS level */
 395         tmp = INREG(ADPA) & ~ADPA_DPMS_CONTROL_MASK;
 396         switch (blank) {
 397         case FB_BLANK_UNBLANK:
 398         case FB_BLANK_NORMAL:
 399                 tmp |= ADPA_DPMS_D0;
 400                 break;
 401         case FB_BLANK_VSYNC_SUSPEND:
 402                 tmp |= ADPA_DPMS_D1;
 403                 break;
 404         case FB_BLANK_HSYNC_SUSPEND:
 405                 tmp |= ADPA_DPMS_D2;
 406                 break;
 407         case FB_BLANK_POWERDOWN:
 408                 tmp |= ADPA_DPMS_D3;
 409                 break;
 410         }
 411         OUTREG(ADPA, tmp);
 412
 413         return;
 414 }
 415
 416
 417 void
 418 intelfbhw_setcolreg(struct intelfb_info *dinfo, unsigned regno,
 419                     unsigned red, unsigned green, unsigned blue,
 420                     unsigned transp)
 421 {
 422 #if VERBOSE > 0
 423         DBG_MSG("intelfbhw_setcolreg: %d: (%d, %d, %d)\n",
 424                 regno, red, green, blue);
 425 #endif
 426
 427         u32 palette_reg = (dinfo->pipe == PIPE_A) ?
 428                           PALETTE_A : PALETTE_B;
 429
 430         OUTREG(palette_reg + (regno << 2),
 431                (red << PALETTE_8_RED_SHIFT) |
 432                (green << PALETTE_8_GREEN_SHIFT) |
 433                (blue << PALETTE_8_BLUE_SHIFT));
 434 }
 435
 436
 437 int
 438 intelfbhw_read_hw_state(struct intelfb_info *dinfo, struct intelfb_hwstate *hw,
 439                         int flag)
 440 {
 441         int i;
 442
 443 #if VERBOSE > 0
 444         DBG_MSG("intelfbhw_read_hw_state\n");
 445 #endif
 446
 447         if (!hw || !dinfo)
 448                 return -1;
 449
 450         /* Read in as much of the HW state as possible. */
 451         hw->vga0_divisor = INREG(VGA0_DIVISOR);
 452         hw->vga1_divisor = INREG(VGA1_DIVISOR);
 453         hw->vga_pd = INREG(VGAPD);
 454         hw->dpll_a = INREG(DPLL_A);
 455         hw->dpll_b = INREG(DPLL_B);
 456         hw->fpa0 = INREG(FPA0);
 457         hw->fpa1 = INREG(FPA1);
 458         hw->fpb0 = INREG(FPB0);
 459         hw->fpb1 = INREG(FPB1);
 460
 461         if (flag == 1)
 462                 return flag;
 463
 464 #if 0
 465         /* This seems to be a problem with the 852GM/855GM */
 466         for (i = 0; i < PALETTE_8_ENTRIES; i++) {
 467                 hw->palette_a[i] = INREG(PALETTE_A + (i << 2));
 468                 hw->palette_b[i] = INREG(PALETTE_B + (i << 2));
 469         }
 470 #endif
 471
 472         if (flag == 2)
 473                 return flag;
 474
 475         hw->htotal_a = INREG(HTOTAL_A);
 476         hw->hblank_a = INREG(HBLANK_A);
 477         hw->hsync_a = INREG(HSYNC_A);
 478         hw->vtotal_a = INREG(VTOTAL_A);
 479         hw->vblank_a = INREG(VBLANK_A);
 480         hw->vsync_a = INREG(VSYNC_A);
 481         hw->src_size_a = INREG(SRC_SIZE_A);
 482         hw->bclrpat_a = INREG(BCLRPAT_A);
 483         hw->htotal_b = INREG(HTOTAL_B);
 484         hw->hblank_b = INREG(HBLANK_B);
 485         hw->hsync_b = INREG(HSYNC_B);
 486         hw->vtotal_b = INREG(VTOTAL_B);
 487         hw->vblank_b = INREG(VBLANK_B);
 488         hw->vsync_b = INREG(VSYNC_B);
 489         hw->src_size_b = INREG(SRC_SIZE_B);
 490         hw->bclrpat_b = INREG(BCLRPAT_B);
 491
 492         if (flag == 3)
 493                 return flag;
 494
 495         hw->adpa = INREG(ADPA);
 496         hw->dvoa = INREG(DVOA);
 497         hw->dvob = INREG(DVOB);
 498         hw->dvoc = INREG(DVOC);
 499         hw->dvoa_srcdim = INREG(DVOA_SRCDIM);
 500         hw->dvob_srcdim = INREG(DVOB_SRCDIM);
 501         hw->dvoc_srcdim = INREG(DVOC_SRCDIM);
 502         hw->lvds = INREG(LVDS);
 503
 504         if (flag == 4)
 505                 return flag;
 506
 507         hw->pipe_a_conf = INREG(PIPEACONF);
 508         hw->pipe_b_conf = INREG(PIPEBCONF);
 509         hw->disp_arb = INREG(DISPARB);
 510
 511         if (flag == 5)
 512                 return flag;
 513
 514         hw->cursor_a_control = INREG(CURSOR_A_CONTROL);
 515         hw->cursor_b_control = INREG(CURSOR_B_CONTROL);
 516         hw->cursor_a_base = INREG(CURSOR_A_BASEADDR);
 517         hw->cursor_b_base = INREG(CURSOR_B_BASEADDR);
 518
 519         if (flag == 6)
 520                 return flag;
 521
 522         for (i = 0; i < 4; i++) {
 523                 hw->cursor_a_palette[i] = INREG(CURSOR_A_PALETTE0 + (i << 2));
 524                 hw->cursor_b_palette[i] = INREG(CURSOR_B_PALETTE0 + (i << 2));
 525         }
 526
 527         if (flag == 7)
 528                 return flag;
 529
 530         hw->cursor_size = INREG(CURSOR_SIZE);
 531
 532         if (flag == 8)
 533                 return flag;
 534
 535         hw->disp_a_ctrl = INREG(DSPACNTR);
 536         hw->disp_b_ctrl = INREG(DSPBCNTR);
 537         hw->disp_a_base = INREG(DSPABASE);
 538         hw->disp_b_base = INREG(DSPBBASE);
 539         hw->disp_a_stride = INREG(DSPASTRIDE);
 540         hw->disp_b_stride = INREG(DSPBSTRIDE);
 541
 542         if (flag == 9)
 543                 return flag;
 544
 545         hw->vgacntrl = INREG(VGACNTRL);
 546
 547         if (flag == 10)
 548                 return flag;
 549
 550         hw->add_id = INREG(ADD_ID);
 551
 552         if (flag == 11)
 553                 return flag;
 554
 555         for (i = 0; i < 7; i++) {
 556                 hw->swf0x[i] = INREG(SWF00 + (i << 2));
 557                 hw->swf1x[i] = INREG(SWF10 + (i << 2));
 558                 if (i < 3)
 559                         hw->swf3x[i] = INREG(SWF30 + (i << 2));
 560         }
 561
 562         for (i = 0; i < 8; i++)
 563                 hw->fence[i] = INREG(FENCE + (i << 2));
 564
 565         hw->instpm = INREG(INSTPM);
 566         hw->mem_mode = INREG(MEM_MODE);
 567         hw->fw_blc_0 = INREG(FW_BLC_0);
 568         hw->fw_blc_1 = INREG(FW_BLC_1);
 569
 570         return 0;
 571 }
 572
 573
 574 static int calc_vclock3(int index, int m, int n, int p)
 575 {
 576         if (p == 0 || n == 0)
 577                 return 0;
 578         return plls[index].ref_clk * m / n / p;
 579 }
 580
 581 static int calc_vclock(int index, int m1, int m2, int n, int p1, int p2, int lvds)
 582 {
 583         int p2_val;
 584         switch(index)
 585         {
 586         case PLLS_I9xx:
 587                 if (p1 == 0)
 588                         return 0;
 589                 if (lvds)
 590                         p2_val = p2 ? 7 : 14;
 591                 else
 592                         p2_val = p2 ? 5 : 10;
 593                 return ((plls[index].ref_clk * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) /
 594                          ((p1)) * (p2_val)));
 595         case PLLS_I8xx:
 596         default:
 597                 return ((plls[index].ref_clk * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) /
 598                          ((p1+2) * (1 << (p2 + 1)))));
 599         }
 600 }
 601
 602 void
 603 intelfbhw_print_hw_state(struct intelfb_info *dinfo, struct intelfb_hwstate *hw)
 604 {
 605 #if REGDUMP
 606         int i, m1, m2, n, p1, p2;
 607         int index = dinfo->pll_index;
 608         DBG_MSG("intelfbhw_print_hw_state\n");
 609
 610         if (!hw || !dinfo)
 611                 return;
 612         /* Read in as much of the HW state as possible. */
 613         printk("hw state dump start\n");
 614         printk("        VGA0_DIVISOR:           0x%08x\n", hw->vga0_divisor);
 615         printk("        VGA1_DIVISOR:           0x%08x\n", hw->vga1_divisor);
 616         printk("        VGAPD:                  0x%08x\n", hw->vga_pd);
 617         n = (hw->vga0_divisor >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 618         m1 = (hw->vga0_divisor >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 619         m2 = (hw->vga0_divisor >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 620         if (hw->vga_pd & VGAPD_0_P1_FORCE_DIV2)
 621                 p1 = 0;
 622         else
 623                 p1 = (hw->vga_pd >> VGAPD_0_P1_SHIFT) & DPLL_P1_MASK;
 624
 625         p2 = (hw->vga_pd >> VGAPD_0_P2_SHIFT) & DPLL_P2_MASK;
 626
 627         printk("        VGA0: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",
 628                m1, m2, n, p1, p2);
 629         printk("        VGA0: clock is %d\n",
 630                calc_vclock(index, m1, m2, n, p1, p2, 0));
 631
 632         n = (hw->vga1_divisor >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 633         m1 = (hw->vga1_divisor >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 634         m2 = (hw->vga1_divisor >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 635         if (hw->vga_pd & VGAPD_1_P1_FORCE_DIV2)
 636                 p1 = 0;
 637         else
 638                 p1 = (hw->vga_pd >> VGAPD_1_P1_SHIFT) & DPLL_P1_MASK;
 639         p2 = (hw->vga_pd >> VGAPD_1_P2_SHIFT) & DPLL_P2_MASK;
 640         printk("        VGA1: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",
 641                m1, m2, n, p1, p2);
 642         printk("        VGA1: clock is %d\n", calc_vclock(index, m1, m2, n, p1, p2, 0));
 643
 644         printk("        DPLL_A:                 0x%08x\n", hw->dpll_a);
 645         printk("        DPLL_B:                 0x%08x\n", hw->dpll_b);
 646         printk("        FPA0:                   0x%08x\n", hw->fpa0);
 647         printk("        FPA1:                   0x%08x\n", hw->fpa1);
 648         printk("        FPB0:                   0x%08x\n", hw->fpb0);
 649         printk("        FPB1:                   0x%08x\n", hw->fpb1);
 650
 651         n = (hw->fpa0 >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 652         m1 = (hw->fpa0 >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 653         m2 = (hw->fpa0 >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 654
 655         if (IS_I9XX(dinfo)) {
 656                 int tmpp1;
 657
 658                 if (hw->dpll_a & DPLL_P1_FORCE_DIV2)
 659                         p1 = 0;
 660                 else
 661                         p1 = (hw->dpll_a >> DPLL_P1_SHIFT) & 0xff;
 662
 663                 tmpp1 = p1;
 664
 665                 switch (tmpp1)
 666                 {
 667                 case 0x1: p1 = 1; break;
 668                 case 0x2: p1 = 2; break;
 669                 case 0x4: p1 = 3; break;
 670                 case 0x8: p1 = 4; break;
 671                 case 0x10: p1 = 5; break;
 672                 case 0x20: p1 = 6; break;
 673                 case 0x40: p1 = 7; break;
 674                 case 0x80: p1 = 8; break;
 675                 default: break;
 676                 }
 677
 678                 p2 = (hw->dpll_a >> DPLL_I9XX_P2_SHIFT) & DPLL_P2_MASK;
 679
 680         } else {
 681                 if (hw->dpll_a & DPLL_P1_FORCE_DIV2)
 682                         p1 = 0;
 683                 else
 684                         p1 = (hw->dpll_a >> DPLL_P1_SHIFT) & DPLL_P1_MASK;
 685                 p2 = (hw->dpll_a >> DPLL_P2_SHIFT) & DPLL_P2_MASK;
 686         }
 687
 688         printk("        PLLA0: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",
 689                m1, m2, n, p1, p2);
 690         printk("        PLLA0: clock is %d\n", calc_vclock(index, m1, m2, n, p1, p2, 0));
 691
 692         n = (hw->fpa1 >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 693         m1 = (hw->fpa1 >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 694         m2 = (hw->fpa1 >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 695
 696         if (IS_I9XX(dinfo)) {
 697                 int tmpp1;
 698
 699                 if (hw->dpll_a & DPLL_P1_FORCE_DIV2)
 700                         p1 = 0;
 701                 else
 702                         p1 = (hw->dpll_a >> DPLL_P1_SHIFT) & 0xff;
 703
 704                 tmpp1 = p1;
 705
 706                 switch (tmpp1) {
 707                 case 0x1: p1 = 1; break;
 708                 case 0x2: p1 = 2; break;
 709                 case 0x4: p1 = 3; break;
 710                 case 0x8: p1 = 4; break;
 711                 case 0x10: p1 = 5; break;
 712                 case 0x20: p1 = 6; break;
 713                 case 0x40: p1 = 7; break;
 714                 case 0x80: p1 = 8; break;
 715                 default: break;
 716                 }
 717
 718                 p2 = (hw->dpll_a >> DPLL_I9XX_P2_SHIFT) & DPLL_P2_MASK;
 719
 720         } else {
 721                 if (hw->dpll_a & DPLL_P1_FORCE_DIV2)
 722                         p1 = 0;
 723                 else
 724                         p1 = (hw->dpll_a >> DPLL_P1_SHIFT) & DPLL_P1_MASK;
 725                 p2 = (hw->dpll_a >> DPLL_P2_SHIFT) & DPLL_P2_MASK;
 726         }
 727         printk("        PLLA1: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",
 728                m1, m2, n, p1, p2);
 729         printk("        PLLA1: clock is %d\n", calc_vclock(index, m1, m2, n, p1, p2, 0));
 730
 731 #if 0
 732         printk("        PALETTE_A:\n");
 733         for (i = 0; i < PALETTE_8_ENTRIES)
 734                 printk("        %3d:    0x%08x\n", i, hw->palette_a[i]);
 735         printk("        PALETTE_B:\n");
 736         for (i = 0; i < PALETTE_8_ENTRIES)
 737                 printk("        %3d:    0x%08x\n", i, hw->palette_b[i]);
 738 #endif
 739
 740         printk("        HTOTAL_A:               0x%08x\n", hw->htotal_a);
 741         printk("        HBLANK_A:               0x%08x\n", hw->hblank_a);
 742         printk("        HSYNC_A:                0x%08x\n", hw->hsync_a);
 743         printk("        VTOTAL_A:               0x%08x\n", hw->vtotal_a);
 744         printk("        VBLANK_A:               0x%08x\n", hw->vblank_a);
 745         printk("        VSYNC_A:                0x%08x\n", hw->vsync_a);
 746         printk("        SRC_SIZE_A:             0x%08x\n", hw->src_size_a);
 747         printk("        BCLRPAT_A:              0x%08x\n", hw->bclrpat_a);
 748         printk("        HTOTAL_B:               0x%08x\n", hw->htotal_b);
 749         printk("        HBLANK_B:               0x%08x\n", hw->hblank_b);
 750         printk("        HSYNC_B:                0x%08x\n", hw->hsync_b);
 751         printk("        VTOTAL_B:               0x%08x\n", hw->vtotal_b);
 752         printk("        VBLANK_B:               0x%08x\n", hw->vblank_b);
 753         printk("        VSYNC_B:                0x%08x\n", hw->vsync_b);
 754         printk("        SRC_SIZE_B:             0x%08x\n", hw->src_size_b);
 755         printk("        BCLRPAT_B:              0x%08x\n", hw->bclrpat_b);
 756
 757         printk("        ADPA:                   0x%08x\n", hw->adpa);
 758         printk("        DVOA:                   0x%08x\n", hw->dvoa);
 759         printk("        DVOB:                   0x%08x\n", hw->dvob);
 760         printk("        DVOC:                   0x%08x\n", hw->dvoc);
 761         printk("        DVOA_SRCDIM:            0x%08x\n", hw->dvoa_srcdim);
 762         printk("        DVOB_SRCDIM:            0x%08x\n", hw->dvob_srcdim);
 763         printk("        DVOC_SRCDIM:            0x%08x\n", hw->dvoc_srcdim);
 764         printk("        LVDS:                   0x%08x\n", hw->lvds);
 765
 766         printk("        PIPEACONF:              0x%08x\n", hw->pipe_a_conf);
 767         printk("        PIPEBCONF:              0x%08x\n", hw->pipe_b_conf);
 768         printk("        DISPARB:                0x%08x\n", hw->disp_arb);
 769
 770         printk("        CURSOR_A_CONTROL:       0x%08x\n", hw->cursor_a_control);
 771         printk("        CURSOR_B_CONTROL:       0x%08x\n", hw->cursor_b_control);
 772         printk("        CURSOR_A_BASEADDR:      0x%08x\n", hw->cursor_a_base);
 773         printk("        CURSOR_B_BASEADDR:      0x%08x\n", hw->cursor_b_base);
 774
 775         printk("        CURSOR_A_PALETTE:       ");
 776         for (i = 0; i < 4; i++) {
 777                 printk("0x%08x", hw->cursor_a_palette[i]);
 778                 if (i < 3)
 779                         printk(", ");
 780         }
 781         printk("\n");
 782         printk("        CURSOR_B_PALETTE:       ");
 783         for (i = 0; i < 4; i++) {
 784                 printk("0x%08x", hw->cursor_b_palette[i]);
 785                 if (i < 3)
 786                         printk(", ");
 787         }
 788         printk("\n");
 789
 790         printk("        CURSOR_SIZE:            0x%08x\n", hw->cursor_size);
 791
 792         printk("        DSPACNTR:               0x%08x\n", hw->disp_a_ctrl);
 793         printk("        DSPBCNTR:               0x%08x\n", hw->disp_b_ctrl);
 794         printk("        DSPABASE:               0x%08x\n", hw->disp_a_base);
 795         printk("        DSPBBASE:               0x%08x\n", hw->disp_b_base);
 796         printk("        DSPASTRIDE:             0x%08x\n", hw->disp_a_stride);
 797         printk("        DSPBSTRIDE:             0x%08x\n", hw->disp_b_stride);
 798
 799         printk("        VGACNTRL:               0x%08x\n", hw->vgacntrl);
 800         printk("        ADD_ID:                 0x%08x\n", hw->add_id);
 801
 802         for (i = 0; i < 7; i++) {
 803                 printk("        SWF0%d                  0x%08x\n", i,
 804                         hw->swf0x[i]);
 805         }
 806         for (i = 0; i < 7; i++) {
 807                 printk("        SWF1%d                  0x%08x\n", i,
 808                         hw->swf1x[i]);
 809         }
 810         for (i = 0; i < 3; i++) {
 811                 printk("        SWF3%d                  0x%08x\n", i,
 812                        hw->swf3x[i]);
 813         }
 814         for (i = 0; i < 8; i++)
 815                 printk("        FENCE%d                 0x%08x\n", i,
 816                        hw->fence[i]);
 817
 818         printk("        INSTPM                  0x%08x\n", hw->instpm);
 819         printk("        MEM_MODE                0x%08x\n", hw->mem_mode);
 820         printk("        FW_BLC_0                0x%08x\n", hw->fw_blc_0);
 821         printk("        FW_BLC_1                0x%08x\n", hw->fw_blc_1);
 822
 823         printk("hw state dump end\n");
 824 #endif
 825 }
 826
 827
 828
 829 /* Split the M parameter into M1 and M2. */
 830 static int
 831 splitm(int index, unsigned int m, unsigned int *retm1, unsigned int *retm2)
 832 {
 833         int m1, m2;
 834         int testm;
 835         /* no point optimising too much - brute force m */
 836         for (m1 = plls[index].min_m1; m1 < plls[index].max_m1+1; m1++) {
 837                 for (m2 = plls[index].min_m2; m2 < plls[index].max_m2+1; m2++) {
 838                         testm = (5 * (m1 + 2)) + (m2 + 2);
 839                         if (testm == m) {
 840                                 *retm1 = (unsigned int)m1;
 841                                 *retm2 = (unsigned int)m2;
 842                                 return 0;
 843                         }
 844                 }
 845         }
 846         return 1;
 847 }
 848
 849 /* Split the P parameter into P1 and P2. */
 850 static int
 851 splitp(int index, unsigned int p, unsigned int *retp1, unsigned int *retp2)
 852 {
 853         int p1, p2;
 854
 855         if (index == PLLS_I9xx) {
 856                 p2 = (p % 10) ? 1 : 0;
 857
 858                 p1 = p / (p2 ? 5 : 10);
 859
 860                 *retp1 = (unsigned int)p1;
 861                 *retp2 = (unsigned int)p2;
 862                 return 0;
 863         }
 864
 865         if (index == PLLS_I8xx) {
 866                 if (p % 4 == 0)
 867                         p2 = 1;
 868                 else
 869                         p2 = 0;
 870                 p1 = (p / (1 << (p2 + 1))) - 2;
 871                 if (p % 4 == 0 && p1 < plls[index].min_p1) {
 872                         p2 = 0;
 873                         p1 = (p / (1 << (p2 + 1))) - 2;
 874                 }
 875                 if (p1 < plls[index].min_p1 ||
 876                     p1 > plls[index].max_p1 ||
 877                     (p1 + 2) * (1 << (p2 + 1)) != p) {
 878                         return 1;
 879                 } else {
 880                         *retp1 = (unsigned int)p1;
 881                         *retp2 = (unsigned int)p2;
 882                         return 0;
 883                 }
 884         }
 885         return 1;
 886 }
 887
 888 static int
 889 calc_pll_params(int index, int clock, u32 *retm1, u32 *retm2, u32 *retn, u32 *retp1,
 890                 u32 *retp2, u32 *retclock)
 891 {
 892         u32 m1, m2, n, p1, p2, n1, testm;
 893         u32 f_vco, p, p_best = 0, m, f_out = 0;
 894         u32 err_max, err_target, err_best = 10000000;
 895         u32 n_best = 0, m_best = 0, f_best, f_err;
 896         u32 p_min, p_max, p_inc, div_max;
 897         struct pll_min_max *pll = &plls[index];
 898
 899         /* Accept 0.5% difference, but aim for 0.1% */
 900         err_max = 5 * clock / 1000;
 901         err_target = clock / 1000;
 902
 903         DBG_MSG("Clock is %d\n", clock);
 904
 905         div_max = pll->max_vco / clock;
 906
 907         p_inc = (clock <= pll->p_transition_clk) ? pll->p_inc_lo : pll->p_inc_hi;
 908         p_min = p_inc;
 909         p_max = ROUND_DOWN_TO(div_max, p_inc);
 910         if (p_min < pll->min_p)
 911                 p_min = pll->min_p;
 912         if (p_max > pll->max_p)
 913                 p_max = pll->max_p;
 914
 915         DBG_MSG("p range is %d-%d (%d)\n", p_min, p_max, p_inc);
 916
 917         p = p_min;
 918         do {
 919                 if (splitp(index, p, &p1, &p2)) {
 920                         WRN_MSG("cannot split p = %d\n", p);
 921                         p += p_inc;
 922                         continue;
 923                 }
 924                 n = pll->min_n;
 925                 f_vco = clock * p;
 926
 927                 do {
 928                         m = ROUND_UP_TO(f_vco * n, pll->ref_clk) / pll->ref_clk;
 929                         if (m < pll->min_m)
 930                                 m = pll->min_m + 1;
 931                         if (m > pll->max_m)
 932                                 m = pll->max_m - 1;
 933                         for (testm = m - 1; testm <= m; testm++) {
 934                                 f_out = calc_vclock3(index, m, n, p);
 935                                 if (splitm(index, m, &m1, &m2)) {
 936                                         WRN_MSG("cannot split m = %d\n", m);
 937                                         n++;
 938                                         continue;
 939                                 }
 940                                 if (clock > f_out)
 941                                         f_err = clock - f_out;
 942                                 else/* slightly bias the error for bigger clocks */
 943                                         f_err = f_out - clock + 1;
 944
 945                                 if (f_err < err_best) {
 946                                         m_best = m;
 947                                         n_best = n;
 948                                         p_best = p;
 949                                         f_best = f_out;
 950                                         err_best = f_err;
 951                                 }
 952                         }
 953                         n++;
 954                 } while ((n <= pll->max_n) && (f_out >= clock));
 955                 p += p_inc;
 956         } while ((p <= p_max));
 957
 958         if (!m_best) {
 959                 WRN_MSG("cannot find parameters for clock %d\n", clock);
 960                 return 1;
 961         }
 962         m = m_best;
 963         n = n_best;
 964         p = p_best;
 965         splitm(index, m, &m1, &m2);
 966         splitp(index, p, &p1, &p2);
 967         n1 = n - 2;
 968
 969         DBG_MSG("m, n, p: %d (%d,%d), %d (%d), %d (%d,%d), "
 970                 "f: %d (%d), VCO: %d\n",
 971                 m, m1, m2, n, n1, p, p1, p2,
 972                 calc_vclock3(index, m, n, p),
 973                 calc_vclock(index, m1, m2, n1, p1, p2, 0),
 974                 calc_vclock3(index, m, n, p) * p);
 975         *retm1 = m1;
 976         *retm2 = m2;
 977         *retn = n1;
 978         *retp1 = p1;
 979         *retp2 = p2;
 980         *retclock = calc_vclock(index, m1, m2, n1, p1, p2, 0);
 981
 982         return 0;
 983 }
 984
 985 static __inline__ int
 986 check_overflow(u32 value, u32 limit, const char *description)
 987 {
 988         if (value > limit) {
 989                 WRN_MSG("%s value %d exceeds limit %d\n",
 990                         description, value, limit);
 991                 return 1;
 992         }
 993         return 0;
 994 }
 995
 996 /* It is assumed that hw is filled in with the initial state information. */
 997 int
 998 intelfbhw_mode_to_hw(struct intelfb_info *dinfo, struct intelfb_hwstate *hw,
 999                      struct fb_var_screeninfo *var)
1000 {
1001         int pipe = PIPE_A;
1002         u32 *dpll, *fp0, *fp1;
1003         u32 m1, m2, n, p1, p2, clock_target, clock;
1004         u32 hsync_start, hsync_end, hblank_start, hblank_end, htotal, hactive;
1005         u32 vsync_start, vsync_end, vblank_start, vblank_end, vtotal, vactive;
1006         u32 vsync_pol, hsync_pol;
1007         u32 *vs, *vb, *vt, *hs, *hb, *ht, *ss, *pipe_conf;
1008
1009         DBG_MSG("intelfbhw_mode_to_hw\n");
1010
1011         /* Disable VGA */
1012         hw->vgacntrl |= VGA_DISABLE;
1013
1014         /* Check whether pipe A or pipe B is enabled. */
1015         if (hw->pipe_a_conf & PIPECONF_ENABLE)
1016                 pipe = PIPE_A;
1017         else if (hw->pipe_b_conf & PIPECONF_ENABLE)
1018                 pipe = PIPE_B;
1019
1020         /* Set which pipe's registers will be set. */
1021         if (pipe == PIPE_B) {
1022                 dpll = &hw->dpll_b;
1023                 fp0 = &hw->fpb0;
1024                 fp1 = &hw->fpb1;
1025                 hs = &hw->hsync_b;
1026                 hb = &hw->hblank_b;
1027                 ht = &hw->htotal_b;
1028                 vs = &hw->vsync_b;
1029                 vb = &hw->vblank_b;
1030                 vt = &hw->vtotal_b;
1031                 ss = &hw->src_size_b;
1032                 pipe_conf = &hw->pipe_b_conf;
1033         } else {
1034                 dpll = &hw->dpll_a;
1035                 fp0 = &hw->fpa0;
1036                 fp1 = &hw->fpa1;
1037                 hs = &hw->hsync_a;
1038                 hb = &hw->hblank_a;
1039                 ht = &hw->htotal_a;
1040                 vs = &hw->vsync_a;
1041                 vb = &hw->vblank_a;
1042                 vt = &hw->vtotal_a;
1043                 ss = &hw->src_size_a;
1044                 pipe_conf = &hw->pipe_a_conf;
1045         }
1046
1047         /* Use ADPA register for sync control. */
1048         hw->adpa &= ~ADPA_USE_VGA_HVPOLARITY;
1049
1050         /* sync polarity */
1051         hsync_pol = (var->sync & FB_SYNC_HOR_HIGH_ACT) ?
1052                         ADPA_SYNC_ACTIVE_HIGH : ADPA_SYNC_ACTIVE_LOW;
1053         vsync_pol = (var->sync & FB_SYNC_VERT_HIGH_ACT) ?
1054                         ADPA_SYNC_ACTIVE_HIGH : ADPA_SYNC_ACTIVE_LOW;
1055         hw->adpa &= ~((ADPA_SYNC_ACTIVE_MASK << ADPA_VSYNC_ACTIVE_SHIFT) |
1056                       (ADPA_SYNC_ACTIVE_MASK << ADPA_HSYNC_ACTIVE_SHIFT));
1057         hw->adpa |= (hsync_pol << ADPA_HSYNC_ACTIVE_SHIFT) |
1058                     (vsync_pol << ADPA_VSYNC_ACTIVE_SHIFT);
1059
1060         /* Connect correct pipe to the analog port DAC */
1061         hw->adpa &= ~(PIPE_MASK << ADPA_PIPE_SELECT_SHIFT);
1062         hw->adpa |= (pipe << ADPA_PIPE_SELECT_SHIFT);
1063
1064         /* Set DPMS state to D0 (on) */
1065         hw->adpa &= ~ADPA_DPMS_CONTROL_MASK;
1066         hw->adpa |= ADPA_DPMS_D0;
1067
1068         hw->adpa |= ADPA_DAC_ENABLE;
1069
1070         *dpll |= (DPLL_VCO_ENABLE | DPLL_VGA_MODE_DISABLE);
1071         *dpll &= ~(DPLL_RATE_SELECT_MASK | DPLL_REFERENCE_SELECT_MASK);
1072         *dpll |= (DPLL_REFERENCE_DEFAULT | DPLL_RATE_SELECT_FP0);
1073
1074         /* Desired clock in kHz */
1075         clock_target = 1000000000 / var->pixclock;
1076
1077         if (calc_pll_params(dinfo->pll_index, clock_target, &m1, &m2,
1078                             &n, &p1, &p2, &clock)) {
1079                 WRN_MSG("calc_pll_params failed\n");
1080                 return 1;
1081         }
1082
1083         /* Check for overflow. */
1084         if (check_overflow(p1, DPLL_P1_MASK, "PLL P1 parameter"))
1085                 return 1;
1086         if (check_overflow(p2, DPLL_P2_MASK, "PLL P2 parameter"))
1087                 return 1;
1088         if (check_overflow(m1, FP_DIVISOR_MASK, "PLL M1 parameter"))
1089                 return 1;
1090         if (check_overflow(m2, FP_DIVISOR_MASK, "PLL M2 parameter"))
1091                 return 1;
1092         if (check_overflow(n, FP_DIVISOR_MASK, "PLL N parameter"))
1093                 return 1;
1094
1095         *dpll &= ~DPLL_P1_FORCE_DIV2;
1096         *dpll &= ~((DPLL_P2_MASK << DPLL_P2_SHIFT) |
1097                    (DPLL_P1_MASK << DPLL_P1_SHIFT));
1098
1099         if (IS_I9XX(dinfo)) {
1100                 *dpll |= (p2 << DPLL_I9XX_P2_SHIFT);
1101                 *dpll |= (1 << (p1 - 1)) << DPLL_P1_SHIFT;
1102         } else {
1103                 *dpll |= (p2 << DPLL_P2_SHIFT) | (p1 << DPLL_P1_SHIFT);
1104         }
1105
1106         *fp0 = (n << FP_N_DIVISOR_SHIFT) |
1107                (m1 << FP_M1_DIVISOR_SHIFT) |
1108                (m2 << FP_M2_DIVISOR_SHIFT);
1109         *fp1 = *fp0;
1110
1111         hw->dvob &= ~PORT_ENABLE;
1112         hw->dvoc &= ~PORT_ENABLE;
1113
1114         /* Use display plane A. */
1115         hw->disp_a_ctrl |= DISPPLANE_PLANE_ENABLE;
1116         hw->disp_a_ctrl &= ~DISPPLANE_GAMMA_ENABLE;
1117         hw->disp_a_ctrl &= ~DISPPLANE_PIXFORMAT_MASK;
1118         switch (intelfb_var_to_depth(var)) {
1119         case 8:
1120                 hw->disp_a_ctrl |= DISPPLANE_8BPP | DISPPLANE_GAMMA_ENABLE;
1121                 break;
1122         case 15:
1123                 hw->disp_a_ctrl |= DISPPLANE_15_16BPP;
1124                 break;
1125         case 16:
1126                 hw->disp_a_ctrl |= DISPPLANE_16BPP;
1127                 break;
1128         case 24:
1129                 hw->disp_a_ctrl |= DISPPLANE_32BPP_NO_ALPHA;
1130                 break;
1131         }
1132         hw->disp_a_ctrl &= ~(PIPE_MASK << DISPPLANE_SEL_PIPE_SHIFT);
1133         hw->disp_a_ctrl |= (pipe << DISPPLANE_SEL_PIPE_SHIFT);
1134
1135         /* Set CRTC registers. */
1136         hactive = var->xres;
1137         hsync_start = hactive + var->right_margin;
1138         hsync_end = hsync_start + var->hsync_len;
1139         htotal = hsync_end + var->left_margin;
1140         hblank_start = hactive;
1141         hblank_end = htotal;
1142
1143         DBG_MSG("H: act %d, ss %d, se %d, tot %d bs %d, be %d\n",
1144                 hactive, hsync_start, hsync_end, htotal, hblank_start,
1145                 hblank_end);
1146
1147         vactive = var->yres;
1148         vsync_start = vactive + var->lower_margin;
1149         vsync_end = vsync_start + var->vsync_len;
1150         vtotal = vsync_end + var->upper_margin;
1151         vblank_start = vactive;
1152         vblank_end = vtotal;
1153         vblank_end = vsync_end + 1;
1154
1155         DBG_MSG("V: act %d, ss %d, se %d, tot %d bs %d, be %d\n",
1156                 vactive, vsync_start, vsync_end, vtotal, vblank_start,
1157                 vblank_end);
1158
1159         /* Adjust for register values, and check for overflow. */
1160         hactive--;
1161         if (check_overflow(hactive, HACTIVE_MASK, "CRTC hactive"))
1162                 return 1;
1163         hsync_start--;
1164         if (check_overflow(hsync_start, HSYNCSTART_MASK, "CRTC hsync_start"))
1165                 return 1;
1166         hsync_end--;
1167         if (check_overflow(hsync_end, HSYNCEND_MASK, "CRTC hsync_end"))
1168                 return 1;
1169         htotal--;
1170         if (check_overflow(htotal, HTOTAL_MASK, "CRTC htotal"))
1171                 return 1;
1172         hblank_start--;
1173         if (check_overflow(hblank_start, HBLANKSTART_MASK, "CRTC hblank_start"))
1174                 return 1;
1175         hblank_end--;
1176         if (check_overflow(hblank_end, HBLANKEND_MASK, "CRTC hblank_end"))
1177                 return 1;
1178
1179         vactive--;
1180         if (check_overflow(vactive, VACTIVE_MASK, "CRTC vactive"))
1181                 return 1;
1182         vsync_start--;
1183         if (check_overflow(vsync_start, VSYNCSTART_MASK, "CRTC vsync_start"))
1184                 return 1;
1185         vsync_end--;
1186         if (check_overflow(vsync_end, VSYNCEND_MASK, "CRTC vsync_end"))
1187                 return 1;
1188         vtotal--;
1189         if (check_overflow(vtotal, VTOTAL_MASK, "CRTC vtotal"))
1190                 return 1;
1191         vblank_start--;
1192         if (check_overflow(vblank_start, VBLANKSTART_MASK, "CRTC vblank_start"))
1193                 return 1;
1194         vblank_end--;
1195         if (check_overflow(vblank_end, VBLANKEND_MASK, "CRTC vblank_end"))
1196                 return 1;
1197
1198         *ht = (htotal << HTOTAL_SHIFT) | (hactive << HACTIVE_SHIFT);
1199         *hb = (hblank_start << HBLANKSTART_SHIFT) |
1200               (hblank_end << HSYNCEND_SHIFT);
1201         *hs = (hsync_start << HSYNCSTART_SHIFT) | (hsync_end << HSYNCEND_SHIFT);
1202
1203         *vt = (vtotal << VTOTAL_SHIFT) | (vactive << VACTIVE_SHIFT);
1204         *vb = (vblank_start << VBLANKSTART_SHIFT) |
1205               (vblank_end << VSYNCEND_SHIFT);
1206         *vs = (vsync_start << VSYNCSTART_SHIFT) | (vsync_end << VSYNCEND_SHIFT);
1207         *ss = (hactive << SRC_SIZE_HORIZ_SHIFT) |
1208               (vactive << SRC_SIZE_VERT_SHIFT);
1209
1210         hw->disp_a_stride = dinfo->pitch;
1211         DBG_MSG("pitch is %d\n", hw->disp_a_stride);
1212
1213         hw->disp_a_base = hw->disp_a_stride * var->yoffset +
1214                           var->xoffset * var->bits_per_pixel / 8;
1215
1216         hw->disp_a_base += dinfo->fb.offset << 12;
1217
1218         /* Check stride alignment. */
1219         if (hw->disp_a_stride % STRIDE_ALIGNMENT != 0) {
1220                 WRN_MSG("display stride %d has bad alignment %d\n",
1221                         hw->disp_a_stride, STRIDE_ALIGNMENT);
1222                 return 1;
1223         }
1224
1225         /* Set the palette to 8-bit mode. */
1226         *pipe_conf &= ~PIPECONF_GAMMA;
1227         return 0;
1228 }
1229
1230 /* Program a (non-VGA) video mode. */
1231 int
1232 intelfbhw_program_mode(struct intelfb_info *dinfo,
1233                      const struct intelfb_hwstate *hw, int blank)
1234 {
1235         int pipe = PIPE_A;
1236         u32 tmp;
1237         const u32 *dpll, *fp0, *fp1, *pipe_conf;
1238         const u32 *hs, *ht, *hb, *vs, *vt, *vb, *ss;
1239         u32 dpll_reg, fp0_reg, fp1_reg, pipe_conf_reg;
1240         u32 hsync_reg, htotal_reg, hblank_reg;
1241         u32 vsync_reg, vtotal_reg, vblank_reg;
1242         u32 src_size_reg;
1243         u32 count, tmp_val[3];
1244
1245         /* Assume single pipe, display plane A, analog CRT. */
1246
1247 #if VERBOSE > 0
1248         DBG_MSG("intelfbhw_program_mode\n");
1249 #endif
1250
1251         /* Disable VGA */
1252         tmp = INREG(VGACNTRL);
1253         tmp |= VGA_DISABLE;
1254         OUTREG(VGACNTRL, tmp);
1255
1256         /* Check whether pipe A or pipe B is enabled. */
1257         if (hw->pipe_a_conf & PIPECONF_ENABLE)
1258                 pipe = PIPE_A;
1259         else if (hw->pipe_b_conf & PIPECONF_ENABLE)
1260                 pipe = PIPE_B;
1261
1262         dinfo->pipe = pipe;
1263
1264         if (pipe == PIPE_B) {
1265                 dpll = &hw->dpll_b;
1266                 fp0 = &hw->fpb0;
1267                 fp1 = &hw->fpb1;
1268                 pipe_conf = &hw->pipe_b_conf;
1269                 hs = &hw->hsync_b;
1270                 hb = &hw->hblank_b;
1271                 ht = &hw->htotal_b;
1272                 vs = &hw->vsync_b;
1273                 vb = &hw->vblank_b;
1274                 vt = &hw->vtotal_b;
1275                 ss = &hw->src_size_b;
1276                 dpll_reg = DPLL_B;
1277                 fp0_reg = FPB0;
1278                 fp1_reg = FPB1;
1279                 pipe_conf_reg = PIPEBCONF;
1280                 hsync_reg = HSYNC_B;
1281                 htotal_reg = HTOTAL_B;
1282                 hblank_reg = HBLANK_B;
1283                 vsync_reg = VSYNC_B;
1284                 vtotal_reg = VTOTAL_B;
1285                 vblank_reg = VBLANK_B;
1286                 src_size_reg = SRC_SIZE_B;
1287         } else {
1288                 dpll = &hw->dpll_a;
1289                 fp0 = &hw->fpa0;
1290                 fp1 = &hw->fpa1;
1291                 pipe_conf = &hw->pipe_a_conf;
1292                 hs = &hw->hsync_a;
1293                 hb = &hw->hblank_a;
1294                 ht = &hw->htotal_a;
1295                 vs = &hw->vsync_a;
1296                 vb = &hw->vblank_a;
1297                 vt = &hw->vtotal_a;
1298                 ss = &hw->src_size_a;
1299                 dpll_reg = DPLL_A;
1300                 fp0_reg = FPA0;
1301                 fp1_reg = FPA1;
1302                 pipe_conf_reg = PIPEACONF;
1303                 hsync_reg = HSYNC_A;
1304                 htotal_reg = HTOTAL_A;
1305                 hblank_reg = HBLANK_A;
1306                 vsync_reg = VSYNC_A;
1307                 vtotal_reg = VTOTAL_A;
1308                 vblank_reg = VBLANK_A;
1309                 src_size_reg = SRC_SIZE_A;
1310         }
1311
1312         /* turn off pipe */
1313         tmp = INREG(pipe_conf_reg);
1314         tmp &= ~PIPECONF_ENABLE;
1315         OUTREG(pipe_conf_reg, tmp);
1316
1317         count = 0;
1318         do {
1319                 tmp_val[count%3] = INREG(0x70000);
1320                 if ((tmp_val[0] == tmp_val[1]) && (tmp_val[1]==tmp_val[2]))
1321                         break;
1322                 count++;
1323                 udelay(1);
1324                 if (count % 200 == 0) {
1325                         tmp = INREG(pipe_conf_reg);
1326                         tmp &= ~PIPECONF_ENABLE;
1327                         OUTREG(pipe_conf_reg, tmp);
1328                 }
1329         } while(count < 2000);
1330
1331         OUTREG(ADPA, INREG(ADPA) & ~ADPA_DAC_ENABLE);
1332
1333         /* Disable planes A and B. */
1334         tmp = INREG(DSPACNTR);
1335         tmp &= ~DISPPLANE_PLANE_ENABLE;
1336         OUTREG(DSPACNTR, tmp);
1337         tmp = INREG(DSPBCNTR);
1338         tmp &= ~DISPPLANE_PLANE_ENABLE;
1339         OUTREG(DSPBCNTR, tmp);
1340
1341         /* Wait for vblank. For now, just wait for a 50Hz cycle (20ms)) */
1342         mdelay(20);
1343
1344         /* Disable Sync */
1345         tmp = INREG(ADPA);
1346         tmp &= ~ADPA_DPMS_CONTROL_MASK;
1347         tmp |= ADPA_DPMS_D3;
1348         OUTREG(ADPA, tmp);
1349
1350         /* do some funky magic - xyzzy */
1351         OUTREG(0x61204, 0xabcd0000);
1352
1353         /* turn off PLL */
1354         tmp = INREG(dpll_reg);
1355         dpll_reg &= ~DPLL_VCO_ENABLE;
1356         OUTREG(dpll_reg, tmp);
1357
1358         /* Set PLL parameters */
1359         OUTREG(dpll_reg, *dpll & ~DPLL_VCO_ENABLE);
1360         OUTREG(fp0_reg, *fp0);
1361         OUTREG(fp1_reg, *fp1);
1362
1363         /* Enable PLL */
1364         tmp = INREG(dpll_reg);
1365         tmp |= DPLL_VCO_ENABLE;
1366         OUTREG(dpll_reg, tmp);
1367
1368         /* Set DVOs B/C */
1369         OUTREG(DVOB, hw->dvob);
1370         OUTREG(DVOC, hw->dvoc);
1371
1372         /* undo funky magic */
1373         OUTREG(0x61204, 0x00000000);
1374
1375         /* Set ADPA */
1376         OUTREG(ADPA, INREG(ADPA) | ADPA_DAC_ENABLE);
1377         OUTREG(ADPA, (hw->adpa & ~(ADPA_DPMS_CONTROL_MASK)) | ADPA_DPMS_D3);
1378
1379         /* Set pipe parameters */
1380         OUTREG(hsync_reg, *hs);
1381         OUTREG(hblank_reg, *hb);
1382         OUTREG(htotal_reg, *ht);
1383         OUTREG(vsync_reg, *vs);
1384         OUTREG(vblank_reg, *vb);
1385         OUTREG(vtotal_reg, *vt);
1386         OUTREG(src_size_reg, *ss);
1387
1388         /* Enable pipe */
1389         OUTREG(pipe_conf_reg, *pipe_conf | PIPECONF_ENABLE);
1390
1391         /* Enable sync */
1392         tmp = INREG(ADPA);
1393         tmp &= ~ADPA_DPMS_CONTROL_MASK;
1394         tmp |= ADPA_DPMS_D0;
1395         OUTREG(ADPA, tmp);
1396
1397         /* setup display plane */
1398         if (dinfo->pdev->device == PCI_DEVICE_ID_INTEL_830M) {
1399                 /*
1400                  *      i830M errata: the display plane must be enabled
1401                  *      to allow writes to the other bits in the plane
1402                  *      control register.
1403                  */
1404                 tmp = INREG(DSPACNTR);
1405                 if ((tmp & DISPPLANE_PLANE_ENABLE) != DISPPLANE_PLANE_ENABLE) {
1406                         tmp |= DISPPLANE_PLANE_ENABLE;
1407                         OUTREG(DSPACNTR, tmp);
1408                         OUTREG(DSPACNTR,
1409                                hw->disp_a_ctrl|DISPPLANE_PLANE_ENABLE);
1410                         mdelay(1);
1411                 }
1412         }
1413
1414         OUTREG(DSPACNTR, hw->disp_a_ctrl & ~DISPPLANE_PLANE_ENABLE);
1415         OUTREG(DSPASTRIDE, hw->disp_a_stride);
1416         OUTREG(DSPABASE, hw->disp_a_base);
1417
1418         /* Enable plane */
1419         if (!blank) {
1420                 tmp = INREG(DSPACNTR);
1421                 tmp |= DISPPLANE_PLANE_ENABLE;
1422                 OUTREG(DSPACNTR, tmp);
1423                 OUTREG(DSPABASE, hw->disp_a_base);
1424         }
1425
1426         return 0;
1427 }
1428
1429 /* forward declarations */
1430 static void refresh_ring(struct intelfb_info *dinfo);
1431 static void reset_state(struct intelfb_info *dinfo);
1432 static void do_flush(struct intelfb_info *dinfo);
1433
1434 static int
1435 wait_ring(struct intelfb_info *dinfo, int n)
1436 {
1437         int i = 0;
1438         unsigned long end;
1439         u32 last_head = INREG(PRI_RING_HEAD) & RING_HEAD_MASK;
1440
1441 #if VERBOSE > 0
1442         DBG_MSG("wait_ring: %d\n", n);
1443 #endif
1444
1445         end = jiffies + (HZ * 3);
1446         while (dinfo->ring_space < n) {
1447                 dinfo->ring_head = (u8 __iomem *)(INREG(PRI_RING_HEAD) &
1448                                                    RING_HEAD_MASK);
1449                 if (dinfo->ring_tail + RING_MIN_FREE <
1450                     (u32 __iomem) dinfo->ring_head)
1451                         dinfo->ring_space = (u32 __iomem) dinfo->ring_head
1452                                 - (dinfo->ring_tail + RING_MIN_FREE);
1453                 else
1454                         dinfo->ring_space = (dinfo->ring.size +
1455                                              (u32 __iomem) dinfo->ring_head)
1456                                 - (dinfo->ring_tail + RING_MIN_FREE);
1457                 if ((u32 __iomem) dinfo->ring_head != last_head) {
1458                         end = jiffies + (HZ * 3);
1459                         last_head = (u32 __iomem) dinfo->ring_head;
1460                 }
1461                 i++;
1462                 if (time_before(end, jiffies)) {
1463                         if (!i) {
1464                                 /* Try again */
1465                                 reset_state(dinfo);
1466                                 refresh_ring(dinfo);
1467                                 do_flush(dinfo);
1468                                 end = jiffies + (HZ * 3);
1469                                 i = 1;
1470                         } else {
1471                                 WRN_MSG("ring buffer : space: %d wanted %d\n",
1472                                         dinfo->ring_space, n);
1473                                 WRN_MSG("lockup - turning off hardware "
1474                                         "acceleration\n");
1475                                 dinfo->ring_lockup = 1;
1476                                 break;
1477                         }
1478                 }
1479                 udelay(1);
1480         }
1481         return i;
1482 }
1483
1484 static void
1485 do_flush(struct intelfb_info *dinfo) {
1486         START_RING(2);
1487         OUT_RING(MI_FLUSH | MI_WRITE_DIRTY_STATE | MI_INVALIDATE_MAP_CACHE);
1488         OUT_RING(MI_NOOP);
1489         ADVANCE_RING();
1490 }
1491
1492 void
1493 intelfbhw_do_sync(struct intelfb_info *dinfo)
1494 {
1495 #if VERBOSE > 0
1496         DBG_MSG("intelfbhw_do_sync\n");
1497 #endif
1498
1499         if (!dinfo->accel)
1500                 return;
1501
1502         /*
1503          * Send a flush, then wait until the ring is empty.  This is what
1504          * the XFree86 driver does, and actually it doesn't seem a lot worse
1505          * than the recommended method (both have problems).
1506          */
1507         do_flush(dinfo);
1508         wait_ring(dinfo, dinfo->ring.size - RING_MIN_FREE);
1509         dinfo->ring_space = dinfo->ring.size - RING_MIN_FREE;
1510 }
1511
1512 static void
1513 refresh_ring(struct intelfb_info *dinfo)
1514 {
1515 #if VERBOSE > 0
1516         DBG_MSG("refresh_ring\n");
1517 #endif
1518
1519         dinfo->ring_head = (u8 __iomem *) (INREG(PRI_RING_HEAD) &
1520                                            RING_HEAD_MASK);
1521         dinfo->ring_tail = INREG(PRI_RING_TAIL) & RING_TAIL_MASK;
1522         if (dinfo->ring_tail + RING_MIN_FREE < (u32 __iomem)dinfo->ring_head)
1523                 dinfo->ring_space = (u32 __iomem) dinfo->ring_head
1524                         - (dinfo->ring_tail + RING_MIN_FREE);
1525         else
1526                 dinfo->ring_space = (dinfo->ring.size +
1527                                      (u32 __iomem) dinfo->ring_head)
1528                         - (dinfo->ring_tail + RING_MIN_FREE);
1529 }
1530
1531 static void
1532 reset_state(struct intelfb_info *dinfo)
1533 {
1534         int i;
1535         u32 tmp;
1536
1537 #if VERBOSE > 0
1538         DBG_MSG("reset_state\n");
1539 #endif
1540
1541         for (i = 0; i < FENCE_NUM; i++)
1542                 OUTREG(FENCE + (i << 2), 0);
1543
1544         /* Flush the ring buffer if it's enabled. */
1545         tmp = INREG(PRI_RING_LENGTH);
1546         if (tmp & RING_ENABLE) {
1547 #if VERBOSE > 0
1548                 DBG_MSG("reset_state: ring was enabled\n");
1549 #endif
1550                 refresh_ring(dinfo);
1551                 intelfbhw_do_sync(dinfo);
1552                 DO_RING_IDLE();
1553         }
1554
1555         OUTREG(PRI_RING_LENGTH, 0);
1556         OUTREG(PRI_RING_HEAD, 0);
1557         OUTREG(PRI_RING_TAIL, 0);
1558         OUTREG(PRI_RING_START, 0);
1559 }
1560
1561 /* Stop the 2D engine, and turn off the ring buffer. */
1562 void
1563 intelfbhw_2d_stop(struct intelfb_info *dinfo)
1564 {
1565 #if VERBOSE > 0
1566         DBG_MSG("intelfbhw_2d_stop: accel: %d, ring_active: %d\n", dinfo->accel,
1567                 dinfo->ring_active);
1568 #endif
1569
1570         if (!dinfo->accel)
1571                 return;
1572
1573         dinfo->ring_active = 0;
1574         reset_state(dinfo);
1575 }
1576
1577 /*
1578  * Enable the ring buffer, and initialise the 2D engine.
1579  * It is assumed that the graphics engine has been stopped by previously
1580  * calling intelfb_2d_stop().
1581  */
1582 void
1583 intelfbhw_2d_start(struct intelfb_info *dinfo)
1584 {
1585 #if VERBOSE > 0
1586         DBG_MSG("intelfbhw_2d_start: accel: %d, ring_active: %d\n",
1587                 dinfo->accel, dinfo->ring_active);
1588 #endif
1589
1590         if (!dinfo->accel)
1591                 return;
1592
1593         /* Initialise the primary ring buffer. */
1594         OUTREG(PRI_RING_LENGTH, 0);
1595         OUTREG(PRI_RING_TAIL, 0);
1596         OUTREG(PRI_RING_HEAD, 0);
1597
1598         OUTREG(PRI_RING_START, dinfo->ring.physical & RING_START_MASK);
1599         OUTREG(PRI_RING_LENGTH,
1600                 ((dinfo->ring.size - GTT_PAGE_SIZE) & RING_LENGTH_MASK) |
1601                 RING_NO_REPORT | RING_ENABLE);
1602         refresh_ring(dinfo);
1603         dinfo->ring_active = 1;
1604 }
1605
1606 /* 2D fillrect (solid fill or invert) */
1607 void
1608 intelfbhw_do_fillrect(struct intelfb_info *dinfo, u32 x, u32 y, u32 w, u32 h,
1609                       u32 color, u32 pitch, u32 bpp, u32 rop)
1610 {
1611         u32 br00, br09, br13, br14, br16;
1612
1613 #if VERBOSE > 0
1614         DBG_MSG("intelfbhw_do_fillrect: (%d,%d) %dx%d, c 0x%06x, p %d bpp %d, "
1615                 "rop 0x%02x\n", x, y, w, h, color, pitch, bpp, rop);
1616 #endif
1617
1618         br00 = COLOR_BLT_CMD;
1619         br09 = dinfo->fb_start + (y * pitch + x * (bpp / 8));
1620         br13 = (rop << ROP_SHIFT) | pitch;
1621         br14 = (h << HEIGHT_SHIFT) | ((w * (bpp / 8)) << WIDTH_SHIFT);
1622         br16 = color;
1623
1624         switch (bpp) {
1625         case 8:
1626                 br13 |= COLOR_DEPTH_8;
1627                 break;
1628         case 16:
1629                 br13 |= COLOR_DEPTH_16;
1630                 break;
1631         case 32:
1632                 br13 |= COLOR_DEPTH_32;
1633                 br00 |= WRITE_ALPHA | WRITE_RGB;
1634                 break;
1635         }
1636
1637         START_RING(6);
1638         OUT_RING(br00);
1639         OUT_RING(br13);
1640         OUT_RING(br14);
1641         OUT_RING(br09);
1642         OUT_RING(br16);
1643         OUT_RING(MI_NOOP);
1644         ADVANCE_RING();
1645
1646 #if VERBOSE > 0
1647         DBG_MSG("ring = 0x%08x, 0x%08x (%d)\n", dinfo->ring_head,
1648                 dinfo->ring_tail, dinfo->ring_space);
1649 #endif
1650 }
1651
1652 void
1653 intelfbhw_do_bitblt(struct intelfb_info *dinfo, u32 curx, u32 cury,
1654                     u32 dstx, u32 dsty, u32 w, u32 h, u32 pitch, u32 bpp)
1655 {
1656         u32 br00, br09, br11, br12, br13, br22, br23, br26;
1657
1658 #if VERBOSE > 0
1659         DBG_MSG("intelfbhw_do_bitblt: (%d,%d)->(%d,%d) %dx%d, p %d bpp %d\n",
1660                 curx, cury, dstx, dsty, w, h, pitch, bpp);
1661 #endif
1662
1663         br00 = XY_SRC_COPY_BLT_CMD;
1664         br09 = dinfo->fb_start;
1665         br11 = (pitch << PITCH_SHIFT);
1666         br12 = dinfo->fb_start;
1667         br13 = (SRC_ROP_GXCOPY << ROP_SHIFT) | (pitch << PITCH_SHIFT);
1668         br22 = (dstx << WIDTH_SHIFT) | (dsty << HEIGHT_SHIFT);
1669         br23 = ((dstx + w) << WIDTH_SHIFT) |
1670                ((dsty + h) << HEIGHT_SHIFT);
1671         br26 = (curx << WIDTH_SHIFT) | (cury << HEIGHT_SHIFT);
1672
1673         switch (bpp) {
1674         case 8:
1675                 br13 |= COLOR_DEPTH_8;
1676                 break;
1677         case 16:
1678                 br13 |= COLOR_DEPTH_16;
1679                 break;
1680         case 32:
1681                 br13 |= COLOR_DEPTH_32;
1682                 br00 |= WRITE_ALPHA | WRITE_RGB;
1683                 break;
1684         }
1685
1686         START_RING(8);
1687         OUT_RING(br00);
1688         OUT_RING(br13);
1689         OUT_RING(br22);
1690         OUT_RING(br23);
1691         OUT_RING(br09);
1692         OUT_RING(br26);
1693         OUT_RING(br11);
1694         OUT_RING(br12);
1695         ADVANCE_RING();
1696 }
1697
1698 int
1699 intelfbhw_do_drawglyph(struct intelfb_info *dinfo, u32 fg, u32 bg, u32 w,
1700                        u32 h, const u8* cdat, u32 x, u32 y, u32 pitch, u32 bpp)
1701 {
1702         int nbytes, ndwords, pad, tmp;
1703         u32 br00, br09, br13, br18, br19, br22, br23;
1704         int dat, ix, iy, iw;
1705         int i, j;
1706
1707 #if VERBOSE > 0
1708         DBG_MSG("intelfbhw_do_drawglyph: (%d,%d) %dx%d\n", x, y, w, h);
1709 #endif
1710
1711         /* size in bytes of a padded scanline */
1712         nbytes = ROUND_UP_TO(w, 16) / 8;
1713
1714         /* Total bytes of padded scanline data to write out. */
1715         nbytes = nbytes * h;
1716
1717         /*
1718          * Check if the glyph data exceeds the immediate mode limit.
1719          * It would take a large font (1K pixels) to hit this limit.
1720          */
1721         if (nbytes > MAX_MONO_IMM_SIZE)
1722                 return 0;
1723
1724         /* Src data is packaged a dword (32-bit) at a time. */
1725         ndwords = ROUND_UP_TO(nbytes, 4) / 4;
1726
1727         /*
1728          * Ring has to be padded to a quad word. But because the command starts
1729            with 7 bytes, pad only if there is an even number of ndwords
1730          */
1731         pad = !(ndwords % 2);
1732
1733         tmp = (XY_MONO_SRC_IMM_BLT_CMD & DW_LENGTH_MASK) + ndwords;
1734         br00 = (XY_MONO_SRC_IMM_BLT_CMD & ~DW_LENGTH_MASK) | tmp;
1735         br09 = dinfo->fb_start;
1736         br13 = (SRC_ROP_GXCOPY << ROP_SHIFT) | (pitch << PITCH_SHIFT);
1737         br18 = bg;
1738         br19 = fg;
1739         br22 = (x << WIDTH_SHIFT) | (y << HEIGHT_SHIFT);
1740         br23 = ((x + w) << WIDTH_SHIFT) | ((y + h) << HEIGHT_SHIFT);
1741
1742         switch (bpp) {
1743         case 8:
1744                 br13 |= COLOR_DEPTH_8;
1745                 break;
1746         case 16:
1747                 br13 |= COLOR_DEPTH_16;
1748                 break;
1749         case 32:
1750                 br13 |= COLOR_DEPTH_32;
1751                 br00 |= WRITE_ALPHA | WRITE_RGB;
1752                 break;
1753         }
1754
1755         START_RING(8 + ndwords);
1756         OUT_RING(br00);
1757         OUT_RING(br13);
1758         OUT_RING(br22);
1759         OUT_RING(br23);
1760         OUT_RING(br09);
1761         OUT_RING(br18);
1762         OUT_RING(br19);
1763         ix = iy = 0;
1764         iw = ROUND_UP_TO(w, 8) / 8;
1765         while (ndwords--) {
1766                 dat = 0;
1767                 for (j = 0; j < 2; ++j) {
1768                         for (i = 0; i < 2; ++i) {
1769                                 if (ix != iw || i == 0)
1770                                         dat |= cdat[iy*iw + ix++] << (i+j*2)*8;
1771                         }
1772                         if (ix == iw && iy != (h-1)) {
1773                                 ix = 0;
1774                                 ++iy;
1775                         }
1776                 }
1777                 OUT_RING(dat);
1778         }
1779         if (pad)
1780                 OUT_RING(MI_NOOP);
1781         ADVANCE_RING();
1782
1783         return 1;
1784 }
1785
1786 /* HW cursor functions. */
1787 void
1788 intelfbhw_cursor_init(struct intelfb_info *dinfo)
1789 {
1790         u32 tmp;
1791
1792 #if VERBOSE > 0
1793         DBG_MSG("intelfbhw_cursor_init\n");
1794 #endif
1795
1796         if (dinfo->mobile || IS_I9XX(dinfo)) {
1797                 if (!dinfo->cursor.physical)
1798                         return;
1799                 tmp = INREG(CURSOR_A_CONTROL);
1800                 tmp &= ~(CURSOR_MODE_MASK | CURSOR_MOBILE_GAMMA_ENABLE |
1801                          CURSOR_MEM_TYPE_LOCAL |
1802                          (1 << CURSOR_PIPE_SELECT_SHIFT));
1803                 tmp |= CURSOR_MODE_DISABLE;
1804                 OUTREG(CURSOR_A_CONTROL, tmp);
1805                 OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.physical);
1806         } else {
1807                 tmp = INREG(CURSOR_CONTROL);
1808                 tmp &= ~(CURSOR_FORMAT_MASK | CURSOR_GAMMA_ENABLE |
1809                          CURSOR_ENABLE | CURSOR_STRIDE_MASK);
1810                 tmp = CURSOR_FORMAT_3C;
1811                 OUTREG(CURSOR_CONTROL, tmp);
1812                 OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.offset << 12);
1813                 tmp = (64 << CURSOR_SIZE_H_SHIFT) |
1814                       (64 << CURSOR_SIZE_V_SHIFT);
1815                 OUTREG(CURSOR_SIZE, tmp);
1816         }
1817 }
1818
1819 void
1820 intelfbhw_cursor_hide(struct intelfb_info *dinfo)
1821 {
1822         u32 tmp;
1823
1824 #if VERBOSE > 0
1825         DBG_MSG("intelfbhw_cursor_hide\n");
1826 #endif
1827
1828         dinfo->cursor_on = 0;
1829         if (dinfo->mobile || IS_I9XX(dinfo)) {
1830                 if (!dinfo->cursor.physical)
1831                         return;
1832                 tmp = INREG(CURSOR_A_CONTROL);
1833                 tmp &= ~CURSOR_MODE_MASK;
1834                 tmp |= CURSOR_MODE_DISABLE;
1835                 OUTREG(CURSOR_A_CONTROL, tmp);
1836                 /* Flush changes */
1837                 OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.physical);
1838         } else {
1839                 tmp = INREG(CURSOR_CONTROL);
1840                 tmp &= ~CURSOR_ENABLE;
1841                 OUTREG(CURSOR_CONTROL, tmp);
1842         }
1843 }
1844
1845 void
1846 intelfbhw_cursor_show(struct intelfb_info *dinfo)
1847 {
1848         u32 tmp;
1849
1850 #if VERBOSE > 0
1851         DBG_MSG("intelfbhw_cursor_show\n");
1852 #endif
1853
1854         dinfo->cursor_on = 1;
1855
1856         if (dinfo->cursor_blanked)
1857                 return;
1858
1859         if (dinfo->mobile || IS_I9XX(dinfo)) {
1860                 if (!dinfo->cursor.physical)
1861                         return;
1862                 tmp = INREG(CURSOR_A_CONTROL);
1863                 tmp &= ~CURSOR_MODE_MASK;
1864                 tmp |= CURSOR_MODE_64_4C_AX;
1865                 OUTREG(CURSOR_A_CONTROL, tmp);
1866                 /* Flush changes */
1867                 OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.physical);
1868         } else {
1869                 tmp = INREG(CURSOR_CONTROL);
1870                 tmp |= CURSOR_ENABLE;
1871                 OUTREG(CURSOR_CONTROL, tmp);
1872         }
1873 }
1874
1875 void
1876 intelfbhw_cursor_setpos(struct intelfb_info *dinfo, int x, int y)
1877 {
1878         u32 tmp;
1879
1880 #if VERBOSE > 0
1881         DBG_MSG("intelfbhw_cursor_setpos: (%d, %d)\n", x, y);
1882 #endif
1883
1884         /*
1885          * Sets the position. The coordinates are assumed to already
1886          * have any offset adjusted. Assume that the cursor is never
1887          * completely off-screen, and that x, y are always >= 0.
1888          */
1889
1890         tmp = ((x & CURSOR_POS_MASK) << CURSOR_X_SHIFT) |
1891               ((y & CURSOR_POS_MASK) << CURSOR_Y_SHIFT);
1892         OUTREG(CURSOR_A_POSITION, tmp);
1893
1894         if (IS_I9XX(dinfo)) {
1895                 OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.physical);
1896         }
1897 }
1898
1899 void
1900 intelfbhw_cursor_setcolor(struct intelfb_info *dinfo, u32 bg, u32 fg)
1901 {
1902 #if VERBOSE > 0
1903         DBG_MSG("intelfbhw_cursor_setcolor\n");
1904 #endif
1905
1906         OUTREG(CURSOR_A_PALETTE0, bg & CURSOR_PALETTE_MASK);
1907         OUTREG(CURSOR_A_PALETTE1, fg & CURSOR_PALETTE_MASK);
1908         OUTREG(CURSOR_A_PALETTE2, fg & CURSOR_PALETTE_MASK);
1909         OUTREG(CURSOR_A_PALETTE3, bg & CURSOR_PALETTE_MASK);
1910 }
1911
1912 void
1913 intelfbhw_cursor_load(struct intelfb_info *dinfo, int width, int height,
1914                       u8 *data)
1915 {
1916         u8 __iomem *addr = (u8 __iomem *)dinfo->cursor.virtual;
1917         int i, j, w = width / 8;
1918         int mod = width % 8, t_mask, d_mask;
1919
1920 #if VERBOSE > 0
1921         DBG_MSG("intelfbhw_cursor_load\n");
1922 #endif
1923
1924         if (!dinfo->cursor.virtual)
1925                 return;
1926
1927         t_mask = 0xff >> mod;
1928         d_mask = ~(0xff >> mod);
1929         for (i = height; i--; ) {
1930                 for (j = 0; j < w; j++) {
1931                         writeb(0x00, addr + j);
1932                         writeb(*(data++), addr + j+8);
1933                 }
1934                 if (mod) {
1935                         writeb(t_mask, addr + j);
1936                         writeb(*(data++) & d_mask, addr + j+8);
1937                 }
1938                 addr += 16;
1939         }
1940 }
1941
1942 void
1943 intelfbhw_cursor_reset(struct intelfb_info *dinfo) {
1944         u8 __iomem *addr = (u8 __iomem *)dinfo->cursor.virtual;
1945         int i, j;
1946
1947 #if VERBOSE > 0
1948         DBG_MSG("intelfbhw_cursor_reset\n");
1949 #endif
1950
1951         if (!dinfo->cursor.virtual)
1952                 return;
1953
1954         for (i = 64; i--; ) {
1955                 for (j = 0; j < 8; j++) {
1956                         writeb(0xff, addr + j+0);
1957                         writeb(0x00, addr + j+8);
1958                 }
1959                 addr += 16;
1960         }
1961 }