SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/video/intelfb/intelfbhw.c

   1 /*
   2  * intelfb
   3  *
   4  * Linux framebuffer driver for Intel(R) 865G integrated graphics chips.
   5  *
   6  * Copyright © 2002, 2003 David Dawes <dawes@xfree86.org>
   7  *                   2004 Sylvain Meyer
   8  *
   9  * This driver consists of two parts.  The first part (intelfbdrv.c) provides
  10  * the basic fbdev interfaces, is derived in part from the radeonfb and
  11  * vesafb drivers, and is covered by the GPL.  The second part (intelfbhw.c)
  12  * provides the code to program the hardware.  Most of it is derived from
  13  * the i810/i830 XFree86 driver.  The HW-specific code is covered here
  14  * under a dual license (GPL and MIT/XFree86 license).
  15  *
  16  * Author: David Dawes
  17  *
  18  */
  19
  20 /* $DHD: intelfb/intelfbhw.c,v 1.9 2003/06/27 15:06:25 dawes Exp $ */
  21
  22 #include <linux/config.h>
  23 #include <linux/module.h>
  24 #include <linux/kernel.h>
  25 #include <linux/errno.h>
  26 #include <linux/string.h>
  27 #include <linux/mm.h>
  28 #include <linux/tty.h>
  29 #include <linux/slab.h>
  30 #include <linux/delay.h>
  31 #include <linux/fb.h>
  32 #include <linux/ioport.h>
  33 #include <linux/init.h>
  34 #include <linux/pci.h>
  35 #include <linux/vmalloc.h>
  36 #include <linux/pagemap.h>
  37
  38 #include <asm/io.h>
  39
  40 #include "intelfb.h"
  41 #include "intelfbhw.h"
  42
  43 struct pll_min_max {
  44         int min_m, max_m, min_m1, max_m1;
  45         int min_m2, max_m2, min_n, max_n;
  46         int min_p, max_p, min_p1, max_p1;
  47         int min_vco, max_vco, p_transition_clk, ref_clk;
  48         int p_inc_lo, p_inc_hi;
  49 };
  50
  51 #define PLLS_I8xx 0
  52 #define PLLS_I9xx 1
  53 #define PLLS_MAX 2
  54
  55 static struct pll_min_max plls[PLLS_MAX] = {
  56         { 108, 140, 18, 26,
  57           6, 16, 3, 16,
  58           4, 128, 0, 31,
  59           930000, 1400000, 165000, 48000,
  60           4, 2 }, //I8xx
  61
  62         { 75, 120, 10, 20,
  63           5, 9, 4, 7,
  64           5, 80, 1, 8,
  65           1400000, 2800000, 200000, 96000,
  66           10, 5 }  //I9xx
  67 };
  68
  69 int
  70 intelfbhw_get_chipset(struct pci_dev *pdev, struct intelfb_info *dinfo)
  71 {
  72         u32 tmp;
  73         if (!pdev || !dinfo)
  74                 return 1;
  75
  76         switch (pdev->device) {
  77         case PCI_DEVICE_ID_INTEL_830M:
  78                 dinfo->name = "Intel(R) 830M";
  79                 dinfo->chipset = INTEL_830M;
  80                 dinfo->mobile = 1;
  81                 dinfo->pll_index = PLLS_I8xx;
  82                 return 0;
  83         case PCI_DEVICE_ID_INTEL_845G:
  84                 dinfo->name = "Intel(R) 845G";
  85                 dinfo->chipset = INTEL_845G;
  86                 dinfo->mobile = 0;
  87                 dinfo->pll_index = PLLS_I8xx;
  88                 return 0;
  89         case PCI_DEVICE_ID_INTEL_85XGM:
  90                 tmp = 0;
  91                 dinfo->mobile = 1;
  92                 dinfo->pll_index = PLLS_I8xx;
  93                 pci_read_config_dword(pdev, INTEL_85X_CAPID, &tmp);
  94                 switch ((tmp >> INTEL_85X_VARIANT_SHIFT) &
  95                         INTEL_85X_VARIANT_MASK) {
  96                 case INTEL_VAR_855GME:
  97                         dinfo->name = "Intel(R) 855GME";
  98                         dinfo->chipset = INTEL_855GME;
  99                         return 0;
 100                 case INTEL_VAR_855GM:
 101                         dinfo->name = "Intel(R) 855GM";
 102                         dinfo->chipset = INTEL_855GM;
 103                         return 0;
 104                 case INTEL_VAR_852GME:
 105                         dinfo->name = "Intel(R) 852GME";
 106                         dinfo->chipset = INTEL_852GME;
 107                         return 0;
 108                 case INTEL_VAR_852GM:
 109                         dinfo->name = "Intel(R) 852GM";
 110                         dinfo->chipset = INTEL_852GM;
 111                         return 0;
 112                 default:
 113                         dinfo->name = "Intel(R) 852GM/855GM";
 114                         dinfo->chipset = INTEL_85XGM;
 115                         return 0;
 116                 }
 117                 break;
 118         case PCI_DEVICE_ID_INTEL_865G:
 119                 dinfo->name = "Intel(R) 865G";
 120                 dinfo->chipset = INTEL_865G;
 121                 dinfo->mobile = 0;
 122                 dinfo->pll_index = PLLS_I8xx;
 123                 return 0;
 124         case PCI_DEVICE_ID_INTEL_915G:
 125                 dinfo->name = "Intel(R) 915G";
 126                 dinfo->chipset = INTEL_915G;
 127                 dinfo->mobile = 0;
 128                 dinfo->pll_index = PLLS_I9xx;
 129                 return 0;
 130         case PCI_DEVICE_ID_INTEL_915GM:
 131                 dinfo->name = "Intel(R) 915GM";
 132                 dinfo->chipset = INTEL_915GM;
 133                 dinfo->mobile = 1;
 134                 dinfo->pll_index = PLLS_I9xx;
 135                 return 0;
 136         case PCI_DEVICE_ID_INTEL_945G:
 137                 dinfo->name = "Intel(R) 945G";
 138                 dinfo->chipset = INTEL_945G;
 139                 dinfo->mobile = 0;
 140                 dinfo->pll_index = PLLS_I9xx;
 141                 return 0;
 142         case PCI_DEVICE_ID_INTEL_945GM:
 143                 dinfo->name = "Intel(R) 945GM";
 144                 dinfo->chipset = INTEL_945GM;
 145                 dinfo->mobile = 1;
 146                 dinfo->pll_index = PLLS_I9xx;
 147                 return 0;
 148         default:
 149                 return 1;
 150         }
 151 }
 152
 153 int
 154 intelfbhw_get_memory(struct pci_dev *pdev, int *aperture_size,
 155                      int *stolen_size)
 156 {
 157         struct pci_dev *bridge_dev;
 158         u16 tmp;
 159         int stolen_overhead;
 160
 161         if (!pdev || !aperture_size || !stolen_size)
 162                 return 1;
 163
 164         /* Find the bridge device.  It is always 0:0.0 */
 165         if (!(bridge_dev = pci_find_slot(0, PCI_DEVFN(0, 0)))) {
 166                 ERR_MSG("cannot find bridge device\n");
 167                 return 1;
 168         }
 169
 170         /* Get the fb aperture size and "stolen" memory amount. */
 171         tmp = 0;
 172         pci_read_config_word(bridge_dev, INTEL_GMCH_CTRL, &tmp);
 173         switch (pdev->device) {
 174         case PCI_DEVICE_ID_INTEL_915G:
 175         case PCI_DEVICE_ID_INTEL_915GM:
 176         case PCI_DEVICE_ID_INTEL_945G:
 177         case PCI_DEVICE_ID_INTEL_945GM:
 178                 /* 915 and 945 chipsets support a 256MB aperture.
 179                    Aperture size is determined by inspected the
 180                    base address of the aperture. */
 181                 if (pci_resource_start(pdev, 2) & 0x08000000)
 182                         *aperture_size = MB(128);
 183                 else
 184                         *aperture_size = MB(256);
 185                 break;
 186         default:
 187                 if ((tmp & INTEL_GMCH_MEM_MASK) == INTEL_GMCH_MEM_64M)
 188                         *aperture_size = MB(64);
 189                 else
 190                         *aperture_size = MB(128);
 191                 break;
 192         }
 193
 194         /* Stolen memory size is reduced by the GTT and the popup.
 195            GTT is 1K per MB of aperture size, and popup is 4K. */
 196         stolen_overhead = (*aperture_size / MB(1)) + 4;
 197         switch(pdev->device) {
 198         case PCI_DEVICE_ID_INTEL_830M:
 199         case PCI_DEVICE_ID_INTEL_845G:
 200                 switch (tmp & INTEL_830_GMCH_GMS_MASK) {
 201                 case INTEL_830_GMCH_GMS_STOLEN_512:
 202                         *stolen_size = KB(512) - KB(stolen_overhead);
 203                         return 0;
 204                 case INTEL_830_GMCH_GMS_STOLEN_1024:
 205                         *stolen_size = MB(1) - KB(stolen_overhead);
 206                         return 0;
 207                 case INTEL_830_GMCH_GMS_STOLEN_8192:
 208                         *stolen_size = MB(8) - KB(stolen_overhead);
 209                         return 0;
 210                 case INTEL_830_GMCH_GMS_LOCAL:
 211                         ERR_MSG("only local memory found\n");
 212                         return 1;
 213                 case INTEL_830_GMCH_GMS_DISABLED:
 214                         ERR_MSG("video memory is disabled\n");
 215                         return 1;
 216                 default:
 217                         ERR_MSG("unexpected GMCH_GMS value: 0x%02x\n",
 218                                 tmp & INTEL_830_GMCH_GMS_MASK);
 219                         return 1;
 220                 }
 221                 break;
 222         default:
 223                 switch (tmp & INTEL_855_GMCH_GMS_MASK) {
 224                 case INTEL_855_GMCH_GMS_STOLEN_1M:
 225                         *stolen_size = MB(1) - KB(stolen_overhead);
 226                         return 0;
 227                 case INTEL_855_GMCH_GMS_STOLEN_4M:
 228                         *stolen_size = MB(4) - KB(stolen_overhead);
 229                         return 0;
 230                 case INTEL_855_GMCH_GMS_STOLEN_8M:
 231                         *stolen_size = MB(8) - KB(stolen_overhead);
 232                         return 0;
 233                 case INTEL_855_GMCH_GMS_STOLEN_16M:
 234                         *stolen_size = MB(16) - KB(stolen_overhead);
 235                         return 0;
 236                 case INTEL_855_GMCH_GMS_STOLEN_32M:
 237                         *stolen_size = MB(32) - KB(stolen_overhead);
 238                         return 0;
 239                 case INTEL_915G_GMCH_GMS_STOLEN_48M:
 240                         *stolen_size = MB(48) - KB(stolen_overhead);
 241                         return 0;
 242                 case INTEL_915G_GMCH_GMS_STOLEN_64M:
 243                         *stolen_size = MB(64) - KB(stolen_overhead);
 244                         return 0;
 245                 case INTEL_855_GMCH_GMS_DISABLED:
 246                         ERR_MSG("video memory is disabled\n");
 247                         return 0;
 248                 default:
 249                         ERR_MSG("unexpected GMCH_GMS value: 0x%02x\n",
 250                                 tmp & INTEL_855_GMCH_GMS_MASK);
 251                         return 1;
 252                 }
 253         }
 254 }
 255
 256 int
 257 intelfbhw_check_non_crt(struct intelfb_info *dinfo)
 258 {
 259         int dvo = 0;
 260
 261         if (INREG(LVDS) & PORT_ENABLE)
 262                 dvo |= LVDS_PORT;
 263         if (INREG(DVOA) & PORT_ENABLE)
 264                 dvo |= DVOA_PORT;
 265         if (INREG(DVOB) & PORT_ENABLE)
 266                 dvo |= DVOB_PORT;
 267         if (INREG(DVOC) & PORT_ENABLE)
 268                 dvo |= DVOC_PORT;
 269
 270         return dvo;
 271 }
 272
 273 const char *
 274 intelfbhw_dvo_to_string(int dvo)
 275 {
 276         if (dvo & DVOA_PORT)
 277                 return "DVO port A";
 278         else if (dvo & DVOB_PORT)
 279                 return "DVO port B";
 280         else if (dvo & DVOC_PORT)
 281                 return "DVO port C";
 282         else if (dvo & LVDS_PORT)
 283                 return "LVDS port";
 284         else
 285                 return NULL;
 286 }
 287
 288
 289 int
 290 intelfbhw_validate_mode(struct intelfb_info *dinfo,
 291                         struct fb_var_screeninfo *var)
 292 {
 293         int bytes_per_pixel;
 294         int tmp;
 295
 296 #if VERBOSE > 0
 297         DBG_MSG("intelfbhw_validate_mode\n");
 298 #endif
 299
 300         bytes_per_pixel = var->bits_per_pixel / 8;
 301         if (bytes_per_pixel == 3)
 302                 bytes_per_pixel = 4;
 303
 304         /* Check if enough video memory. */
 305         tmp = var->yres_virtual * var->xres_virtual * bytes_per_pixel;
 306         if (tmp > dinfo->fb.size) {
 307                 WRN_MSG("Not enough video ram for mode "
 308                         "(%d KByte vs %d KByte).\n",
 309                         BtoKB(tmp), BtoKB(dinfo->fb.size));
 310                 return 1;
 311         }
 312
 313         /* Check if x/y limits are OK. */
 314         if (var->xres - 1 > HACTIVE_MASK) {
 315                 WRN_MSG("X resolution too large (%d vs %d).\n",
 316                         var->xres, HACTIVE_MASK + 1);
 317                 return 1;
 318         }
 319         if (var->yres - 1 > VACTIVE_MASK) {
 320                 WRN_MSG("Y resolution too large (%d vs %d).\n",
 321                         var->yres, VACTIVE_MASK + 1);
 322                 return 1;
 323         }
 324
 325         /* Check for interlaced/doublescan modes. */
 326         if (var->vmode & FB_VMODE_INTERLACED) {
 327                 WRN_MSG("Mode is interlaced.\n");
 328                 return 1;
 329         }
 330         if (var->vmode & FB_VMODE_DOUBLE) {
 331                 WRN_MSG("Mode is double-scan.\n");
 332                 return 1;
 333         }
 334
 335         /* Check if clock is OK. */
 336         tmp = 1000000000 / var->pixclock;
 337         if (tmp < MIN_CLOCK) {
 338                 WRN_MSG("Pixel clock is too low (%d MHz vs %d MHz).\n",
 339                         (tmp + 500) / 1000, MIN_CLOCK / 1000);
 340                 return 1;
 341         }
 342         if (tmp > MAX_CLOCK) {
 343                 WRN_MSG("Pixel clock is too high (%d MHz vs %d MHz).\n",
 344                         (tmp + 500) / 1000, MAX_CLOCK / 1000);
 345                 return 1;
 346         }
 347
 348         return 0;
 349 }
 350
 351 int
 352 intelfbhw_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
 353 {
 354         struct intelfb_info *dinfo = GET_DINFO(info);
 355         u32 offset, xoffset, yoffset;
 356
 357 #if VERBOSE > 0
 358         DBG_MSG("intelfbhw_pan_display\n");
 359 #endif
 360
 361         xoffset = ROUND_DOWN_TO(var->xoffset, 8);
 362         yoffset = var->yoffset;
 363
 364         if ((xoffset + var->xres > var->xres_virtual) ||
 365             (yoffset + var->yres > var->yres_virtual))
 366                 return -EINVAL;
 367
 368         offset = (yoffset * dinfo->pitch) +
 369                  (xoffset * var->bits_per_pixel) / 8;
 370
 371         offset += dinfo->fb.offset << 12;
 372
 373         OUTREG(DSPABASE, offset);
 374
 375         return 0;
 376 }
 377
 378 /* Blank the screen. */
 379 void
 380 intelfbhw_do_blank(int blank, struct fb_info *info)
 381 {
 382         struct intelfb_info *dinfo = GET_DINFO(info);
 383         u32 tmp;
 384
 385 #if VERBOSE > 0
 386         DBG_MSG("intelfbhw_do_blank: blank is %d\n", blank);
 387 #endif
 388
 389         /* Turn plane A on or off */
 390         tmp = INREG(DSPACNTR);
 391         if (blank)
 392                 tmp &= ~DISPPLANE_PLANE_ENABLE;
 393         else
 394                 tmp |= DISPPLANE_PLANE_ENABLE;
 395         OUTREG(DSPACNTR, tmp);
 396         /* Flush */
 397         tmp = INREG(DSPABASE);
 398         OUTREG(DSPABASE, tmp);
 399
 400         /* Turn off/on the HW cursor */
 401 #if VERBOSE > 0
 402         DBG_MSG("cursor_on is %d\n", dinfo->cursor_on);
 403 #endif
 404         if (dinfo->cursor_on) {
 405                 if (blank) {
 406                         intelfbhw_cursor_hide(dinfo);
 407                 } else {
 408                         intelfbhw_cursor_show(dinfo);
 409                 }
 410                 dinfo->cursor_on = 1;
 411         }
 412         dinfo->cursor_blanked = blank;
 413
 414         /* Set DPMS level */
 415         tmp = INREG(ADPA) & ~ADPA_DPMS_CONTROL_MASK;
 416         switch (blank) {
 417         case FB_BLANK_UNBLANK:
 418         case FB_BLANK_NORMAL:
 419                 tmp |= ADPA_DPMS_D0;
 420                 break;
 421         case FB_BLANK_VSYNC_SUSPEND:
 422                 tmp |= ADPA_DPMS_D1;
 423                 break;
 424         case FB_BLANK_HSYNC_SUSPEND:
 425                 tmp |= ADPA_DPMS_D2;
 426                 break;
 427         case FB_BLANK_POWERDOWN:
 428                 tmp |= ADPA_DPMS_D3;
 429                 break;
 430         }
 431         OUTREG(ADPA, tmp);
 432
 433         return;
 434 }
 435
 436
 437 void
 438 intelfbhw_setcolreg(struct intelfb_info *dinfo, unsigned regno,
 439                     unsigned red, unsigned green, unsigned blue,
 440                     unsigned transp)
 441 {
 442 #if VERBOSE > 0
 443         DBG_MSG("intelfbhw_setcolreg: %d: (%d, %d, %d)\n",
 444                 regno, red, green, blue);
 445 #endif
 446
 447         u32 palette_reg = (dinfo->pipe == PIPE_A) ?
 448                           PALETTE_A : PALETTE_B;
 449
 450         OUTREG(palette_reg + (regno << 2),
 451                (red << PALETTE_8_RED_SHIFT) |
 452                (green << PALETTE_8_GREEN_SHIFT) |
 453                (blue << PALETTE_8_BLUE_SHIFT));
 454 }
 455
 456
 457 int
 458 intelfbhw_read_hw_state(struct intelfb_info *dinfo, struct intelfb_hwstate *hw,
 459                         int flag)
 460 {
 461         int i;
 462
 463 #if VERBOSE > 0
 464         DBG_MSG("intelfbhw_read_hw_state\n");
 465 #endif
 466
 467         if (!hw || !dinfo)
 468                 return -1;
 469
 470         /* Read in as much of the HW state as possible. */
 471         hw->vga0_divisor = INREG(VGA0_DIVISOR);
 472         hw->vga1_divisor = INREG(VGA1_DIVISOR);
 473         hw->vga_pd = INREG(VGAPD);
 474         hw->dpll_a = INREG(DPLL_A);
 475         hw->dpll_b = INREG(DPLL_B);
 476         hw->fpa0 = INREG(FPA0);
 477         hw->fpa1 = INREG(FPA1);
 478         hw->fpb0 = INREG(FPB0);
 479         hw->fpb1 = INREG(FPB1);
 480
 481         if (flag == 1)
 482                 return flag;
 483
 484 #if 0
 485         /* This seems to be a problem with the 852GM/855GM */
 486         for (i = 0; i < PALETTE_8_ENTRIES; i++) {
 487                 hw->palette_a[i] = INREG(PALETTE_A + (i << 2));
 488                 hw->palette_b[i] = INREG(PALETTE_B + (i << 2));
 489         }
 490 #endif
 491
 492         if (flag == 2)
 493                 return flag;
 494
 495         hw->htotal_a = INREG(HTOTAL_A);
 496         hw->hblank_a = INREG(HBLANK_A);
 497         hw->hsync_a = INREG(HSYNC_A);
 498         hw->vtotal_a = INREG(VTOTAL_A);
 499         hw->vblank_a = INREG(VBLANK_A);
 500         hw->vsync_a = INREG(VSYNC_A);
 501         hw->src_size_a = INREG(SRC_SIZE_A);
 502         hw->bclrpat_a = INREG(BCLRPAT_A);
 503         hw->htotal_b = INREG(HTOTAL_B);
 504         hw->hblank_b = INREG(HBLANK_B);
 505         hw->hsync_b = INREG(HSYNC_B);
 506         hw->vtotal_b = INREG(VTOTAL_B);
 507         hw->vblank_b = INREG(VBLANK_B);
 508         hw->vsync_b = INREG(VSYNC_B);
 509         hw->src_size_b = INREG(SRC_SIZE_B);
 510         hw->bclrpat_b = INREG(BCLRPAT_B);
 511
 512         if (flag == 3)
 513                 return flag;
 514
 515         hw->adpa = INREG(ADPA);
 516         hw->dvoa = INREG(DVOA);
 517         hw->dvob = INREG(DVOB);
 518         hw->dvoc = INREG(DVOC);
 519         hw->dvoa_srcdim = INREG(DVOA_SRCDIM);
 520         hw->dvob_srcdim = INREG(DVOB_SRCDIM);
 521         hw->dvoc_srcdim = INREG(DVOC_SRCDIM);
 522         hw->lvds = INREG(LVDS);
 523
 524         if (flag == 4)
 525                 return flag;
 526
 527         hw->pipe_a_conf = INREG(PIPEACONF);
 528         hw->pipe_b_conf = INREG(PIPEBCONF);
 529         hw->disp_arb = INREG(DISPARB);
 530
 531         if (flag == 5)
 532                 return flag;
 533
 534         hw->cursor_a_control = INREG(CURSOR_A_CONTROL);
 535         hw->cursor_b_control = INREG(CURSOR_B_CONTROL);
 536         hw->cursor_a_base = INREG(CURSOR_A_BASEADDR);
 537         hw->cursor_b_base = INREG(CURSOR_B_BASEADDR);
 538
 539         if (flag == 6)
 540                 return flag;
 541
 542         for (i = 0; i < 4; i++) {
 543                 hw->cursor_a_palette[i] = INREG(CURSOR_A_PALETTE0 + (i << 2));
 544                 hw->cursor_b_palette[i] = INREG(CURSOR_B_PALETTE0 + (i << 2));
 545         }
 546
 547         if (flag == 7)
 548                 return flag;
 549
 550         hw->cursor_size = INREG(CURSOR_SIZE);
 551
 552         if (flag == 8)
 553                 return flag;
 554
 555         hw->disp_a_ctrl = INREG(DSPACNTR);
 556         hw->disp_b_ctrl = INREG(DSPBCNTR);
 557         hw->disp_a_base = INREG(DSPABASE);
 558         hw->disp_b_base = INREG(DSPBBASE);
 559         hw->disp_a_stride = INREG(DSPASTRIDE);
 560         hw->disp_b_stride = INREG(DSPBSTRIDE);
 561
 562         if (flag == 9)
 563                 return flag;
 564
 565         hw->vgacntrl = INREG(VGACNTRL);
 566
 567         if (flag == 10)
 568                 return flag;
 569
 570         hw->add_id = INREG(ADD_ID);
 571
 572         if (flag == 11)
 573                 return flag;
 574
 575         for (i = 0; i < 7; i++) {
 576                 hw->swf0x[i] = INREG(SWF00 + (i << 2));
 577                 hw->swf1x[i] = INREG(SWF10 + (i << 2));
 578                 if (i < 3)
 579                         hw->swf3x[i] = INREG(SWF30 + (i << 2));
 580         }
 581
 582         for (i = 0; i < 8; i++)
 583                 hw->fence[i] = INREG(FENCE + (i << 2));
 584
 585         hw->instpm = INREG(INSTPM);
 586         hw->mem_mode = INREG(MEM_MODE);
 587         hw->fw_blc_0 = INREG(FW_BLC_0);
 588         hw->fw_blc_1 = INREG(FW_BLC_1);
 589
 590         return 0;
 591 }
 592
 593
 594 static int calc_vclock3(int index, int m, int n, int p)
 595 {
 596         if (p == 0 || n == 0)
 597                 return 0;
 598         return plls[index].ref_clk * m / n / p;
 599 }
 600
 601 static int calc_vclock(int index, int m1, int m2, int n, int p1, int p2, int lvds)
 602 {
 603         int p2_val;
 604         switch(index)
 605         {
 606         case PLLS_I9xx:
 607                 if (p1 == 0)
 608                         return 0;
 609                 if (lvds)
 610                         p2_val = p2 ? 7 : 14;
 611                 else
 612                         p2_val = p2 ? 5 : 10;
 613                 return ((plls[index].ref_clk * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) /
 614                          ((p1)) * (p2_val)));
 615         case PLLS_I8xx:
 616         default:
 617                 return ((plls[index].ref_clk * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) /
 618                          ((p1+2) * (1 << (p2 + 1)))));
 619         }
 620 }
 621
 622 void
 623 intelfbhw_print_hw_state(struct intelfb_info *dinfo, struct intelfb_hwstate *hw)
 624 {
 625 #if REGDUMP
 626         int i, m1, m2, n, p1, p2;
 627         int index = dinfo->pll_index;
 628         DBG_MSG("intelfbhw_print_hw_state\n");
 629
 630         if (!hw || !dinfo)
 631                 return;
 632         /* Read in as much of the HW state as possible. */
 633         printk("hw state dump start\n");
 634         printk("        VGA0_DIVISOR:           0x%08x\n", hw->vga0_divisor);
 635         printk("        VGA1_DIVISOR:           0x%08x\n", hw->vga1_divisor);
 636         printk("        VGAPD:                  0x%08x\n", hw->vga_pd);
 637         n = (hw->vga0_divisor >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 638         m1 = (hw->vga0_divisor >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 639         m2 = (hw->vga0_divisor >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 640         if (hw->vga_pd & VGAPD_0_P1_FORCE_DIV2)
 641                 p1 = 0;
 642         else
 643                 p1 = (hw->vga_pd >> VGAPD_0_P1_SHIFT) & DPLL_P1_MASK;
 644
 645         p2 = (hw->vga_pd >> VGAPD_0_P2_SHIFT) & DPLL_P2_MASK;
 646
 647         printk("        VGA0: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",
 648                m1, m2, n, p1, p2);
 649         printk("        VGA0: clock is %d\n",
 650                calc_vclock(index, m1, m2, n, p1, p2, 0));
 651
 652         n = (hw->vga1_divisor >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 653         m1 = (hw->vga1_divisor >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 654         m2 = (hw->vga1_divisor >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 655         if (hw->vga_pd & VGAPD_1_P1_FORCE_DIV2)
 656                 p1 = 0;
 657         else
 658                 p1 = (hw->vga_pd >> VGAPD_1_P1_SHIFT) & DPLL_P1_MASK;
 659         p2 = (hw->vga_pd >> VGAPD_1_P2_SHIFT) & DPLL_P2_MASK;
 660         printk("        VGA1: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",
 661                m1, m2, n, p1, p2);
 662         printk("        VGA1: clock is %d\n", calc_vclock(index, m1, m2, n, p1, p2, 0));
 663
 664         printk("        DPLL_A:                 0x%08x\n", hw->dpll_a);
 665         printk("        DPLL_B:                 0x%08x\n", hw->dpll_b);
 666         printk("        FPA0:                   0x%08x\n", hw->fpa0);
 667         printk("        FPA1:                   0x%08x\n", hw->fpa1);
 668         printk("        FPB0:                   0x%08x\n", hw->fpb0);
 669         printk("        FPB1:                   0x%08x\n", hw->fpb1);
 670
 671         n = (hw->fpa0 >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 672         m1 = (hw->fpa0 >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 673         m2 = (hw->fpa0 >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 674
 675         if (IS_I9XX(dinfo)) {
 676                 int tmpp1;
 677
 678                 if (hw->dpll_a & DPLL_P1_FORCE_DIV2)
 679                         p1 = 0;
 680                 else
 681                         p1 = (hw->dpll_a >> DPLL_P1_SHIFT) & 0xff;
 682
 683                 tmpp1 = p1;
 684
 685                 switch (tmpp1)
 686                 {
 687                 case 0x1: p1 = 1; break;
 688                 case 0x2: p1 = 2; break;
 689                 case 0x4: p1 = 3; break;
 690                 case 0x8: p1 = 4; break;
 691                 case 0x10: p1 = 5; break;
 692                 case 0x20: p1 = 6; break;
 693                 case 0x40: p1 = 7; break;
 694                 case 0x80: p1 = 8; break;
 695                 default: break;
 696                 }
 697
 698                 p2 = (hw->dpll_a >> DPLL_I9XX_P2_SHIFT) & DPLL_P2_MASK;
 699
 700         } else {
 701                 if (hw->dpll_a & DPLL_P1_FORCE_DIV2)
 702                         p1 = 0;
 703                 else
 704                         p1 = (hw->dpll_a >> DPLL_P1_SHIFT) & DPLL_P1_MASK;
 705                 p2 = (hw->dpll_a >> DPLL_P2_SHIFT) & DPLL_P2_MASK;
 706         }
 707
 708         printk("        PLLA0: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",
 709                m1, m2, n, p1, p2);
 710         printk("        PLLA0: clock is %d\n", calc_vclock(index, m1, m2, n, p1, p2, 0));
 711
 712         n = (hw->fpa1 >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 713         m1 = (hw->fpa1 >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 714         m2 = (hw->fpa1 >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 715
 716         if (IS_I9XX(dinfo)) {
 717                 int tmpp1;
 718
 719                 if (hw->dpll_a & DPLL_P1_FORCE_DIV2)
 720                         p1 = 0;
 721                 else
 722                         p1 = (hw->dpll_a >> DPLL_P1_SHIFT) & 0xff;
 723
 724                 tmpp1 = p1;
 725
 726                 switch (tmpp1) {
 727                 case 0x1: p1 = 1; break;
 728                 case 0x2: p1 = 2; break;
 729                 case 0x4: p1 = 3; break;
 730                 case 0x8: p1 = 4; break;
 731                 case 0x10: p1 = 5; break;
 732                 case 0x20: p1 = 6; break;
 733                 case 0x40: p1 = 7; break;
 734                 case 0x80: p1 = 8; break;
 735                 default: break;
 736                 }
 737
 738                 p2 = (hw->dpll_a >> DPLL_I9XX_P2_SHIFT) & DPLL_P2_MASK;
 739
 740         } else {
 741                 if (hw->dpll_a & DPLL_P1_FORCE_DIV2)
 742                         p1 = 0;
 743                 else
 744                         p1 = (hw->dpll_a >> DPLL_P1_SHIFT) & DPLL_P1_MASK;
 745                 p2 = (hw->dpll_a >> DPLL_P2_SHIFT) & DPLL_P2_MASK;
 746         }
 747         printk("        PLLA1: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",
 748                m1, m2, n, p1, p2);
 749         printk("        PLLA1: clock is %d\n", calc_vclock(index, m1, m2, n, p1, p2, 0));
 750
 751 #if 0
 752         printk("        PALETTE_A:\n");
 753         for (i = 0; i < PALETTE_8_ENTRIES)
 754                 printk("        %3d:    0x%08x\n", i, hw->palette_a[i]);
 755         printk("        PALETTE_B:\n");
 756         for (i = 0; i < PALETTE_8_ENTRIES)
 757                 printk("        %3d:    0x%08x\n", i, hw->palette_b[i]);
 758 #endif
 759
 760         printk("        HTOTAL_A:               0x%08x\n", hw->htotal_a);
 761         printk("        HBLANK_A:               0x%08x\n", hw->hblank_a);
 762         printk("        HSYNC_A:                0x%08x\n", hw->hsync_a);
 763         printk("        VTOTAL_A:               0x%08x\n", hw->vtotal_a);
 764         printk("        VBLANK_A:               0x%08x\n", hw->vblank_a);
 765         printk("        VSYNC_A:                0x%08x\n", hw->vsync_a);
 766         printk("        SRC_SIZE_A:             0x%08x\n", hw->src_size_a);
 767         printk("        BCLRPAT_A:              0x%08x\n", hw->bclrpat_a);
 768         printk("        HTOTAL_B:               0x%08x\n", hw->htotal_b);
 769         printk("        HBLANK_B:               0x%08x\n", hw->hblank_b);
 770         printk("        HSYNC_B:                0x%08x\n", hw->hsync_b);
 771         printk("        VTOTAL_B:               0x%08x\n", hw->vtotal_b);
 772         printk("        VBLANK_B:               0x%08x\n", hw->vblank_b);
 773         printk("        VSYNC_B:                0x%08x\n", hw->vsync_b);
 774         printk("        SRC_SIZE_B:             0x%08x\n", hw->src_size_b);
 775         printk("        BCLRPAT_B:              0x%08x\n", hw->bclrpat_b);
 776
 777         printk("        ADPA:                   0x%08x\n", hw->adpa);
 778         printk("        DVOA:                   0x%08x\n", hw->dvoa);
 779         printk("        DVOB:                   0x%08x\n", hw->dvob);
 780         printk("        DVOC:                   0x%08x\n", hw->dvoc);
 781         printk("        DVOA_SRCDIM:            0x%08x\n", hw->dvoa_srcdim);
 782         printk("        DVOB_SRCDIM:            0x%08x\n", hw->dvob_srcdim);
 783         printk("        DVOC_SRCDIM:            0x%08x\n", hw->dvoc_srcdim);
 784         printk("        LVDS:                   0x%08x\n", hw->lvds);
 785
 786         printk("        PIPEACONF:              0x%08x\n", hw->pipe_a_conf);
 787         printk("        PIPEBCONF:              0x%08x\n", hw->pipe_b_conf);
 788         printk("        DISPARB:                0x%08x\n", hw->disp_arb);
 789
 790         printk("        CURSOR_A_CONTROL:       0x%08x\n", hw->cursor_a_control);
 791         printk("        CURSOR_B_CONTROL:       0x%08x\n", hw->cursor_b_control);
 792         printk("        CURSOR_A_BASEADDR:      0x%08x\n", hw->cursor_a_base);
 793         printk("        CURSOR_B_BASEADDR:      0x%08x\n", hw->cursor_b_base);
 794
 795         printk("        CURSOR_A_PALETTE:       ");
 796         for (i = 0; i < 4; i++) {
 797                 printk("0x%08x", hw->cursor_a_palette[i]);
 798                 if (i < 3)
 799                         printk(", ");
 800         }
 801         printk("\n");
 802         printk("        CURSOR_B_PALETTE:       ");
 803         for (i = 0; i < 4; i++) {
 804                 printk("0x%08x", hw->cursor_b_palette[i]);
 805                 if (i < 3)
 806                         printk(", ");
 807         }
 808         printk("\n");
 809
 810         printk("        CURSOR_SIZE:            0x%08x\n", hw->cursor_size);
 811
 812         printk("        DSPACNTR:               0x%08x\n", hw->disp_a_ctrl);
 813         printk("        DSPBCNTR:               0x%08x\n", hw->disp_b_ctrl);
 814         printk("        DSPABASE:               0x%08x\n", hw->disp_a_base);
 815         printk("        DSPBBASE:               0x%08x\n", hw->disp_b_base);
 816         printk("        DSPASTRIDE:             0x%08x\n", hw->disp_a_stride);
 817         printk("        DSPBSTRIDE:             0x%08x\n", hw->disp_b_stride);
 818
 819         printk("        VGACNTRL:               0x%08x\n", hw->vgacntrl);
 820         printk("        ADD_ID:                 0x%08x\n", hw->add_id);
 821
 822         for (i = 0; i < 7; i++) {
 823                 printk("        SWF0%d                  0x%08x\n", i,
 824                         hw->swf0x[i]);
 825         }
 826         for (i = 0; i < 7; i++) {
 827                 printk("        SWF1%d                  0x%08x\n", i,
 828                         hw->swf1x[i]);
 829         }
 830         for (i = 0; i < 3; i++) {
 831                 printk("        SWF3%d                  0x%08x\n", i,
 832                        hw->swf3x[i]);
 833         }
 834         for (i = 0; i < 8; i++)
 835                 printk("        FENCE%d                 0x%08x\n", i,
 836                        hw->fence[i]);
 837
 838         printk("        INSTPM                  0x%08x\n", hw->instpm);
 839         printk("        MEM_MODE                0x%08x\n", hw->mem_mode);
 840         printk("        FW_BLC_0                0x%08x\n", hw->fw_blc_0);
 841         printk("        FW_BLC_1                0x%08x\n", hw->fw_blc_1);
 842
 843         printk("hw state dump end\n");
 844 #endif
 845 }
 846
 847
 848
 849 /* Split the M parameter into M1 and M2. */
 850 static int
 851 splitm(int index, unsigned int m, unsigned int *retm1, unsigned int *retm2)
 852 {
 853         int m1, m2;
 854         int testm;
 855         /* no point optimising too much - brute force m */
 856         for (m1 = plls[index].min_m1; m1 < plls[index].max_m1+1; m1++) {
 857                 for (m2 = plls[index].min_m2; m2 < plls[index].max_m2+1; m2++) {
 858                         testm = (5 * (m1 + 2)) + (m2 + 2);
 859                         if (testm == m) {
 860                                 *retm1 = (unsigned int)m1;
 861                                 *retm2 = (unsigned int)m2;
 862                                 return 0;
 863                         }
 864                 }
 865         }
 866         return 1;
 867 }
 868
 869 /* Split the P parameter into P1 and P2. */
 870 static int
 871 splitp(int index, unsigned int p, unsigned int *retp1, unsigned int *retp2)
 872 {
 873         int p1, p2;
 874
 875         if (index == PLLS_I9xx) {
 876                 p2 = (p % 10) ? 1 : 0;
 877
 878                 p1 = p / (p2 ? 5 : 10);
 879
 880                 *retp1 = (unsigned int)p1;
 881                 *retp2 = (unsigned int)p2;
 882                 return 0;
 883         }
 884
 885         if (index == PLLS_I8xx) {
 886                 if (p % 4 == 0)
 887                         p2 = 1;
 888                 else
 889                         p2 = 0;
 890                 p1 = (p / (1 << (p2 + 1))) - 2;
 891                 if (p % 4 == 0 && p1 < plls[index].min_p1) {
 892                         p2 = 0;
 893                         p1 = (p / (1 << (p2 + 1))) - 2;
 894                 }
 895                 if (p1 < plls[index].min_p1 ||
 896                     p1 > plls[index].max_p1 ||
 897                     (p1 + 2) * (1 << (p2 + 1)) != p) {
 898                         return 1;
 899                 } else {
 900                         *retp1 = (unsigned int)p1;
 901                         *retp2 = (unsigned int)p2;
 902                         return 0;
 903                 }
 904         }
 905         return 1;
 906 }
 907
 908 static int
 909 calc_pll_params(int index, int clock, u32 *retm1, u32 *retm2, u32 *retn, u32 *retp1,
 910                 u32 *retp2, u32 *retclock)
 911 {
 912         u32 m1, m2, n, p1, p2, n1, testm;
 913         u32 f_vco, p, p_best = 0, m, f_out = 0;
 914         u32 err_max, err_target, err_best = 10000000;
 915         u32 n_best = 0, m_best = 0, f_best, f_err;
 916         u32 p_min, p_max, p_inc, div_max;
 917         struct pll_min_max *pll = &plls[index];
 918
 919         /* Accept 0.5% difference, but aim for 0.1% */
 920         err_max = 5 * clock / 1000;
 921         err_target = clock / 1000;
 922
 923         DBG_MSG("Clock is %d\n", clock);
 924
 925         div_max = pll->max_vco / clock;
 926
 927         p_inc = (clock <= pll->p_transition_clk) ? pll->p_inc_lo : pll->p_inc_hi;
 928         p_min = p_inc;
 929         p_max = ROUND_DOWN_TO(div_max, p_inc);
 930         if (p_min < pll->min_p)
 931                 p_min = pll->min_p;
 932         if (p_max > pll->max_p)
 933                 p_max = pll->max_p;
 934
 935         DBG_MSG("p range is %d-%d (%d)\n", p_min, p_max, p_inc);
 936
 937         p = p_min;
 938         do {
 939                 if (splitp(index, p, &p1, &p2)) {
 940                         WRN_MSG("cannot split p = %d\n", p);
 941                         p += p_inc;
 942                         continue;
 943                 }
 944                 n = pll->min_n;
 945                 f_vco = clock * p;
 946
 947                 do {
 948                         m = ROUND_UP_TO(f_vco * n, pll->ref_clk) / pll->ref_clk;
 949                         if (m < pll->min_m)
 950                                 m = pll->min_m + 1;
 951                         if (m > pll->max_m)
 952                                 m = pll->max_m - 1;
 953                         for (testm = m - 1; testm <= m; testm++) {
 954                                 f_out = calc_vclock3(index, m, n, p);
 955                                 if (splitm(index, m, &m1, &m2)) {
 956                                         WRN_MSG("cannot split m = %d\n", m);
 957                                         n++;
 958                                         continue;
 959                                 }
 960                                 if (clock > f_out)
 961                                         f_err = clock - f_out;
 962                                 else/* slightly bias the error for bigger clocks */
 963                                         f_err = f_out - clock + 1;
 964
 965                                 if (f_err < err_best) {
 966                                         m_best = m;
 967                                         n_best = n;
 968                                         p_best = p;
 969                                         f_best = f_out;
 970                                         err_best = f_err;
 971                                 }
 972                         }
 973                         n++;
 974                 } while ((n <= pll->max_n) && (f_out >= clock));
 975                 p += p_inc;
 976         } while ((p <= p_max));
 977
 978         if (!m_best) {
 979                 WRN_MSG("cannot find parameters for clock %d\n", clock);
 980                 return 1;
 981         }
 982         m = m_best;
 983         n = n_best;
 984         p = p_best;
 985         splitm(index, m, &m1, &m2);
 986         splitp(index, p, &p1, &p2);
 987         n1 = n - 2;
 988
 989         DBG_MSG("m, n, p: %d (%d,%d), %d (%d), %d (%d,%d), "
 990                 "f: %d (%d), VCO: %d\n",
 991                 m, m1, m2, n, n1, p, p1, p2,
 992                 calc_vclock3(index, m, n, p),
 993                 calc_vclock(index, m1, m2, n1, p1, p2, 0),
 994                 calc_vclock3(index, m, n, p) * p);
 995         *retm1 = m1;
 996         *retm2 = m2;
 997         *retn = n1;
 998         *retp1 = p1;
 999         *retp2 = p2;
1000         *retclock = calc_vclock(index, m1, m2, n1, p1, p2, 0);
1001
1002         return 0;
1003 }
1004
1005 static __inline__ int
1006 check_overflow(u32 value, u32 limit, const char *description)
1007 {
1008         if (value > limit) {
1009                 WRN_MSG("%s value %d exceeds limit %d\n",
1010                         description, value, limit);
1011                 return 1;
1012         }
1013         return 0;
1014 }
1015
1016 /* It is assumed that hw is filled in with the initial state information. */
1017 int
1018 intelfbhw_mode_to_hw(struct intelfb_info *dinfo, struct intelfb_hwstate *hw,
1019                      struct fb_var_screeninfo *var)
1020 {
1021         int pipe = PIPE_A;
1022         u32 *dpll, *fp0, *fp1;
1023         u32 m1, m2, n, p1, p2, clock_target, clock;
1024         u32 hsync_start, hsync_end, hblank_start, hblank_end, htotal, hactive;
1025         u32 vsync_start, vsync_end, vblank_start, vblank_end, vtotal, vactive;
1026         u32 vsync_pol, hsync_pol;
1027         u32 *vs, *vb, *vt, *hs, *hb, *ht, *ss, *pipe_conf;
1028         u32 stride_alignment;
1029
1030         DBG_MSG("intelfbhw_mode_to_hw\n");
1031
1032         /* Disable VGA */
1033         hw->vgacntrl |= VGA_DISABLE;
1034
1035         /* Check whether pipe A or pipe B is enabled. */
1036         if (hw->pipe_a_conf & PIPECONF_ENABLE)
1037                 pipe = PIPE_A;
1038         else if (hw->pipe_b_conf & PIPECONF_ENABLE)
1039                 pipe = PIPE_B;
1040
1041         /* Set which pipe's registers will be set. */
1042         if (pipe == PIPE_B) {
1043                 dpll = &hw->dpll_b;
1044                 fp0 = &hw->fpb0;
1045                 fp1 = &hw->fpb1;
1046                 hs = &hw->hsync_b;
1047                 hb = &hw->hblank_b;
1048                 ht = &hw->htotal_b;
1049                 vs = &hw->vsync_b;
1050                 vb = &hw->vblank_b;
1051                 vt = &hw->vtotal_b;
1052                 ss = &hw->src_size_b;
1053                 pipe_conf = &hw->pipe_b_conf;
1054         } else {
1055                 dpll = &hw->dpll_a;
1056                 fp0 = &hw->fpa0;
1057                 fp1 = &hw->fpa1;
1058                 hs = &hw->hsync_a;
1059                 hb = &hw->hblank_a;
1060                 ht = &hw->htotal_a;
1061                 vs = &hw->vsync_a;
1062                 vb = &hw->vblank_a;
1063                 vt = &hw->vtotal_a;
1064                 ss = &hw->src_size_a;
1065                 pipe_conf = &hw->pipe_a_conf;
1066         }
1067
1068         /* Use ADPA register for sync control. */
1069         hw->adpa &= ~ADPA_USE_VGA_HVPOLARITY;
1070
1071         /* sync polarity */
1072         hsync_pol = (var->sync & FB_SYNC_HOR_HIGH_ACT) ?
1073                         ADPA_SYNC_ACTIVE_HIGH : ADPA_SYNC_ACTIVE_LOW;
1074         vsync_pol = (var->sync & FB_SYNC_VERT_HIGH_ACT) ?
1075                         ADPA_SYNC_ACTIVE_HIGH : ADPA_SYNC_ACTIVE_LOW;
1076         hw->adpa &= ~((ADPA_SYNC_ACTIVE_MASK << ADPA_VSYNC_ACTIVE_SHIFT) |
1077                       (ADPA_SYNC_ACTIVE_MASK << ADPA_HSYNC_ACTIVE_SHIFT));
1078         hw->adpa |= (hsync_pol << ADPA_HSYNC_ACTIVE_SHIFT) |
1079                     (vsync_pol << ADPA_VSYNC_ACTIVE_SHIFT);
1080
1081         /* Connect correct pipe to the analog port DAC */
1082         hw->adpa &= ~(PIPE_MASK << ADPA_PIPE_SELECT_SHIFT);
1083         hw->adpa |= (pipe << ADPA_PIPE_SELECT_SHIFT);
1084
1085         /* Set DPMS state to D0 (on) */
1086         hw->adpa &= ~ADPA_DPMS_CONTROL_MASK;
1087         hw->adpa |= ADPA_DPMS_D0;
1088
1089         hw->adpa |= ADPA_DAC_ENABLE;
1090
1091         *dpll |= (DPLL_VCO_ENABLE | DPLL_VGA_MODE_DISABLE);
1092         *dpll &= ~(DPLL_RATE_SELECT_MASK | DPLL_REFERENCE_SELECT_MASK);
1093         *dpll |= (DPLL_REFERENCE_DEFAULT | DPLL_RATE_SELECT_FP0);
1094
1095         /* Desired clock in kHz */
1096         clock_target = 1000000000 / var->pixclock;
1097
1098         if (calc_pll_params(dinfo->pll_index, clock_target, &m1, &m2,
1099                             &n, &p1, &p2, &clock)) {
1100                 WRN_MSG("calc_pll_params failed\n");
1101                 return 1;
1102         }
1103
1104         /* Check for overflow. */
1105         if (check_overflow(p1, DPLL_P1_MASK, "PLL P1 parameter"))
1106                 return 1;
1107         if (check_overflow(p2, DPLL_P2_MASK, "PLL P2 parameter"))
1108                 return 1;
1109         if (check_overflow(m1, FP_DIVISOR_MASK, "PLL M1 parameter"))
1110                 return 1;
1111         if (check_overflow(m2, FP_DIVISOR_MASK, "PLL M2 parameter"))
1112                 return 1;
1113         if (check_overflow(n, FP_DIVISOR_MASK, "PLL N parameter"))
1114                 return 1;
1115
1116         *dpll &= ~DPLL_P1_FORCE_DIV2;
1117         *dpll &= ~((DPLL_P2_MASK << DPLL_P2_SHIFT) |
1118                    (DPLL_P1_MASK << DPLL_P1_SHIFT));
1119
1120         if (IS_I9XX(dinfo)) {
1121                 *dpll |= (p2 << DPLL_I9XX_P2_SHIFT);
1122                 *dpll |= (1 << (p1 - 1)) << DPLL_P1_SHIFT;
1123         } else {
1124                 *dpll |= (p2 << DPLL_P2_SHIFT) | (p1 << DPLL_P1_SHIFT);
1125         }
1126
1127         *fp0 = (n << FP_N_DIVISOR_SHIFT) |
1128                (m1 << FP_M1_DIVISOR_SHIFT) |
1129                (m2 << FP_M2_DIVISOR_SHIFT);
1130         *fp1 = *fp0;
1131
1132         hw->dvob &= ~PORT_ENABLE;
1133         hw->dvoc &= ~PORT_ENABLE;
1134
1135         /* Use display plane A. */
1136         hw->disp_a_ctrl |= DISPPLANE_PLANE_ENABLE;
1137         hw->disp_a_ctrl &= ~DISPPLANE_GAMMA_ENABLE;
1138         hw->disp_a_ctrl &= ~DISPPLANE_PIXFORMAT_MASK;
1139         switch (intelfb_var_to_depth(var)) {
1140         case 8:
1141                 hw->disp_a_ctrl |= DISPPLANE_8BPP | DISPPLANE_GAMMA_ENABLE;
1142                 break;
1143         case 15:
1144                 hw->disp_a_ctrl |= DISPPLANE_15_16BPP;
1145                 break;
1146         case 16:
1147                 hw->disp_a_ctrl |= DISPPLANE_16BPP;
1148                 break;
1149         case 24:
1150                 hw->disp_a_ctrl |= DISPPLANE_32BPP_NO_ALPHA;
1151                 break;
1152         }
1153         hw->disp_a_ctrl &= ~(PIPE_MASK << DISPPLANE_SEL_PIPE_SHIFT);
1154         hw->disp_a_ctrl |= (pipe << DISPPLANE_SEL_PIPE_SHIFT);
1155
1156         /* Set CRTC registers. */
1157         hactive = var->xres;
1158         hsync_start = hactive + var->right_margin;
1159         hsync_end = hsync_start + var->hsync_len;
1160         htotal = hsync_end + var->left_margin;
1161         hblank_start = hactive;
1162         hblank_end = htotal;
1163
1164         DBG_MSG("H: act %d, ss %d, se %d, tot %d bs %d, be %d\n",
1165                 hactive, hsync_start, hsync_end, htotal, hblank_start,
1166                 hblank_end);
1167
1168         vactive = var->yres;
1169         vsync_start = vactive + var->lower_margin;
1170         vsync_end = vsync_start + var->vsync_len;
1171         vtotal = vsync_end + var->upper_margin;
1172         vblank_start = vactive;
1173         vblank_end = vtotal;
1174         vblank_end = vsync_end + 1;
1175
1176         DBG_MSG("V: act %d, ss %d, se %d, tot %d bs %d, be %d\n",
1177                 vactive, vsync_start, vsync_end, vtotal, vblank_start,
1178                 vblank_end);
1179
1180         /* Adjust for register values, and check for overflow. */
1181         hactive--;
1182         if (check_overflow(hactive, HACTIVE_MASK, "CRTC hactive"))
1183                 return 1;
1184         hsync_start--;
1185         if (check_overflow(hsync_start, HSYNCSTART_MASK, "CRTC hsync_start"))
1186                 return 1;
1187         hsync_end--;
1188         if (check_overflow(hsync_end, HSYNCEND_MASK, "CRTC hsync_end"))
1189                 return 1;
1190         htotal--;
1191         if (check_overflow(htotal, HTOTAL_MASK, "CRTC htotal"))
1192                 return 1;
1193         hblank_start--;
1194         if (check_overflow(hblank_start, HBLANKSTART_MASK, "CRTC hblank_start"))
1195                 return 1;
1196         hblank_end--;
1197         if (check_overflow(hblank_end, HBLANKEND_MASK, "CRTC hblank_end"))
1198                 return 1;
1199
1200         vactive--;
1201         if (check_overflow(vactive, VACTIVE_MASK, "CRTC vactive"))
1202                 return 1;
1203         vsync_start--;
1204         if (check_overflow(vsync_start, VSYNCSTART_MASK, "CRTC vsync_start"))
1205                 return 1;
1206         vsync_end--;
1207         if (check_overflow(vsync_end, VSYNCEND_MASK, "CRTC vsync_end"))
1208                 return 1;
1209         vtotal--;
1210         if (check_overflow(vtotal, VTOTAL_MASK, "CRTC vtotal"))
1211                 return 1;
1212         vblank_start--;
1213         if (check_overflow(vblank_start, VBLANKSTART_MASK, "CRTC vblank_start"))
1214                 return 1;
1215         vblank_end--;
1216         if (check_overflow(vblank_end, VBLANKEND_MASK, "CRTC vblank_end"))
1217                 return 1;
1218
1219         *ht = (htotal << HTOTAL_SHIFT) | (hactive << HACTIVE_SHIFT);
1220         *hb = (hblank_start << HBLANKSTART_SHIFT) |
1221               (hblank_end << HSYNCEND_SHIFT);
1222         *hs = (hsync_start << HSYNCSTART_SHIFT) | (hsync_end << HSYNCEND_SHIFT);
1223
1224         *vt = (vtotal << VTOTAL_SHIFT) | (vactive << VACTIVE_SHIFT);
1225         *vb = (vblank_start << VBLANKSTART_SHIFT) |
1226               (vblank_end << VSYNCEND_SHIFT);
1227         *vs = (vsync_start << VSYNCSTART_SHIFT) | (vsync_end << VSYNCEND_SHIFT);
1228         *ss = (hactive << SRC_SIZE_HORIZ_SHIFT) |
1229               (vactive << SRC_SIZE_VERT_SHIFT);
1230
1231         hw->disp_a_stride = dinfo->pitch;
1232         DBG_MSG("pitch is %d\n", hw->disp_a_stride);
1233
1234         hw->disp_a_base = hw->disp_a_stride * var->yoffset +
1235                           var->xoffset * var->bits_per_pixel / 8;
1236
1237         hw->disp_a_base += dinfo->fb.offset << 12;
1238
1239         /* Check stride alignment. */
1240         stride_alignment = IS_I9XX(dinfo) ? STRIDE_ALIGNMENT_I9XX :
1241                                             STRIDE_ALIGNMENT;
1242         if (hw->disp_a_stride % stride_alignment != 0) {
1243                 WRN_MSG("display stride %d has bad alignment %d\n",
1244                         hw->disp_a_stride, stride_alignment);
1245                 return 1;
1246         }
1247
1248         /* Set the palette to 8-bit mode. */
1249         *pipe_conf &= ~PIPECONF_GAMMA;
1250         return 0;
1251 }
1252
1253 /* Program a (non-VGA) video mode. */
1254 int
1255 intelfbhw_program_mode(struct intelfb_info *dinfo,
1256                      const struct intelfb_hwstate *hw, int blank)
1257 {
1258         int pipe = PIPE_A;
1259         u32 tmp;
1260         const u32 *dpll, *fp0, *fp1, *pipe_conf;
1261         const u32 *hs, *ht, *hb, *vs, *vt, *vb, *ss;
1262         u32 dpll_reg, fp0_reg, fp1_reg, pipe_conf_reg;
1263         u32 hsync_reg, htotal_reg, hblank_reg;
1264         u32 vsync_reg, vtotal_reg, vblank_reg;
1265         u32 src_size_reg;
1266         u32 count, tmp_val[3];
1267
1268         /* Assume single pipe, display plane A, analog CRT. */
1269
1270 #if VERBOSE > 0
1271         DBG_MSG("intelfbhw_program_mode\n");
1272 #endif
1273
1274         /* Disable VGA */
1275         tmp = INREG(VGACNTRL);
1276         tmp |= VGA_DISABLE;
1277         OUTREG(VGACNTRL, tmp);
1278
1279         /* Check whether pipe A or pipe B is enabled. */
1280         if (hw->pipe_a_conf & PIPECONF_ENABLE)
1281                 pipe = PIPE_A;
1282         else if (hw->pipe_b_conf & PIPECONF_ENABLE)
1283                 pipe = PIPE_B;
1284
1285         dinfo->pipe = pipe;
1286
1287         if (pipe == PIPE_B) {
1288                 dpll = &hw->dpll_b;
1289                 fp0 = &hw->fpb0;
1290                 fp1 = &hw->fpb1;
1291                 pipe_conf = &hw->pipe_b_conf;
1292                 hs = &hw->hsync_b;
1293                 hb = &hw->hblank_b;
1294                 ht = &hw->htotal_b;
1295                 vs = &hw->vsync_b;
1296                 vb = &hw->vblank_b;
1297                 vt = &hw->vtotal_b;
1298                 ss = &hw->src_size_b;
1299                 dpll_reg = DPLL_B;
1300                 fp0_reg = FPB0;
1301                 fp1_reg = FPB1;
1302                 pipe_conf_reg = PIPEBCONF;
1303                 hsync_reg = HSYNC_B;
1304                 htotal_reg = HTOTAL_B;
1305                 hblank_reg = HBLANK_B;
1306                 vsync_reg = VSYNC_B;
1307                 vtotal_reg = VTOTAL_B;
1308                 vblank_reg = VBLANK_B;
1309                 src_size_reg = SRC_SIZE_B;
1310         } else {
1311                 dpll = &hw->dpll_a;
1312                 fp0 = &hw->fpa0;
1313                 fp1 = &hw->fpa1;
1314                 pipe_conf = &hw->pipe_a_conf;
1315                 hs = &hw->hsync_a;
1316                 hb = &hw->hblank_a;
1317                 ht = &hw->htotal_a;
1318                 vs = &hw->vsync_a;
1319                 vb = &hw->vblank_a;
1320                 vt = &hw->vtotal_a;
1321                 ss = &hw->src_size_a;
1322                 dpll_reg = DPLL_A;
1323                 fp0_reg = FPA0;
1324                 fp1_reg = FPA1;
1325                 pipe_conf_reg = PIPEACONF;
1326                 hsync_reg = HSYNC_A;
1327                 htotal_reg = HTOTAL_A;
1328                 hblank_reg = HBLANK_A;
1329                 vsync_reg = VSYNC_A;
1330                 vtotal_reg = VTOTAL_A;
1331                 vblank_reg = VBLANK_A;
1332                 src_size_reg = SRC_SIZE_A;
1333         }
1334
1335         /* turn off pipe */
1336         tmp = INREG(pipe_conf_reg);
1337         tmp &= ~PIPECONF_ENABLE;
1338         OUTREG(pipe_conf_reg, tmp);
1339
1340         count = 0;
1341         do {
1342                 tmp_val[count%3] = INREG(0x70000);
1343                 if ((tmp_val[0] == tmp_val[1]) && (tmp_val[1]==tmp_val[2]))
1344                         break;
1345                 count++;
1346                 udelay(1);
1347                 if (count % 200 == 0) {
1348                         tmp = INREG(pipe_conf_reg);
1349                         tmp &= ~PIPECONF_ENABLE;
1350                         OUTREG(pipe_conf_reg, tmp);
1351                 }
1352         } while(count < 2000);
1353
1354         OUTREG(ADPA, INREG(ADPA) & ~ADPA_DAC_ENABLE);
1355
1356         /* Disable planes A and B. */
1357         tmp = INREG(DSPACNTR);
1358         tmp &= ~DISPPLANE_PLANE_ENABLE;
1359         OUTREG(DSPACNTR, tmp);
1360         tmp = INREG(DSPBCNTR);
1361         tmp &= ~DISPPLANE_PLANE_ENABLE;
1362         OUTREG(DSPBCNTR, tmp);
1363
1364         /* Wait for vblank. For now, just wait for a 50Hz cycle (20ms)) */
1365         mdelay(20);
1366
1367         /* Disable Sync */
1368         tmp = INREG(ADPA);
1369         tmp &= ~ADPA_DPMS_CONTROL_MASK;
1370         tmp |= ADPA_DPMS_D3;
1371         OUTREG(ADPA, tmp);
1372
1373         /* do some funky magic - xyzzy */
1374         OUTREG(0x61204, 0xabcd0000);
1375
1376         /* turn off PLL */
1377         tmp = INREG(dpll_reg);
1378         dpll_reg &= ~DPLL_VCO_ENABLE;
1379         OUTREG(dpll_reg, tmp);
1380
1381         /* Set PLL parameters */
1382         OUTREG(dpll_reg, *dpll & ~DPLL_VCO_ENABLE);
1383         OUTREG(fp0_reg, *fp0);
1384         OUTREG(fp1_reg, *fp1);
1385
1386         /* Enable PLL */
1387         tmp = INREG(dpll_reg);
1388         tmp |= DPLL_VCO_ENABLE;
1389         OUTREG(dpll_reg, tmp);
1390
1391         /* Set DVOs B/C */
1392         OUTREG(DVOB, hw->dvob);
1393         OUTREG(DVOC, hw->dvoc);
1394
1395         /* undo funky magic */
1396         OUTREG(0x61204, 0x00000000);
1397
1398         /* Set ADPA */
1399         OUTREG(ADPA, INREG(ADPA) | ADPA_DAC_ENABLE);
1400         OUTREG(ADPA, (hw->adpa & ~(ADPA_DPMS_CONTROL_MASK)) | ADPA_DPMS_D3);
1401
1402         /* Set pipe parameters */
1403         OUTREG(hsync_reg, *hs);
1404         OUTREG(hblank_reg, *hb);
1405         OUTREG(htotal_reg, *ht);
1406         OUTREG(vsync_reg, *vs);
1407         OUTREG(vblank_reg, *vb);
1408         OUTREG(vtotal_reg, *vt);
1409         OUTREG(src_size_reg, *ss);
1410
1411         /* Enable pipe */
1412         OUTREG(pipe_conf_reg, *pipe_conf | PIPECONF_ENABLE);
1413
1414         /* Enable sync */
1415         tmp = INREG(ADPA);
1416         tmp &= ~ADPA_DPMS_CONTROL_MASK;
1417         tmp |= ADPA_DPMS_D0;
1418         OUTREG(ADPA, tmp);
1419
1420         /* setup display plane */
1421         if (dinfo->pdev->device == PCI_DEVICE_ID_INTEL_830M) {
1422                 /*
1423                  *      i830M errata: the display plane must be enabled
1424                  *      to allow writes to the other bits in the plane
1425                  *      control register.
1426                  */
1427                 tmp = INREG(DSPACNTR);
1428                 if ((tmp & DISPPLANE_PLANE_ENABLE) != DISPPLANE_PLANE_ENABLE) {
1429                         tmp |= DISPPLANE_PLANE_ENABLE;
1430                         OUTREG(DSPACNTR, tmp);
1431                         OUTREG(DSPACNTR,
1432                                hw->disp_a_ctrl|DISPPLANE_PLANE_ENABLE);
1433                         mdelay(1);
1434                 }
1435         }
1436
1437         OUTREG(DSPACNTR, hw->disp_a_ctrl & ~DISPPLANE_PLANE_ENABLE);
1438         OUTREG(DSPASTRIDE, hw->disp_a_stride);
1439         OUTREG(DSPABASE, hw->disp_a_base);
1440
1441         /* Enable plane */
1442         if (!blank) {
1443                 tmp = INREG(DSPACNTR);
1444                 tmp |= DISPPLANE_PLANE_ENABLE;
1445                 OUTREG(DSPACNTR, tmp);
1446                 OUTREG(DSPABASE, hw->disp_a_base);
1447         }
1448
1449         return 0;
1450 }
1451
1452 /* forward declarations */
1453 static void refresh_ring(struct intelfb_info *dinfo);
1454 static void reset_state(struct intelfb_info *dinfo);
1455 static void do_flush(struct intelfb_info *dinfo);
1456
1457 static int
1458 wait_ring(struct intelfb_info *dinfo, int n)
1459 {
1460         int i = 0;
1461         unsigned long end;
1462         u32 last_head = INREG(PRI_RING_HEAD) & RING_HEAD_MASK;
1463
1464 #if VERBOSE > 0
1465         DBG_MSG("wait_ring: %d\n", n);
1466 #endif
1467
1468         end = jiffies + (HZ * 3);
1469         while (dinfo->ring_space < n) {
1470                 dinfo->ring_head = (u8 __iomem *)(INREG(PRI_RING_HEAD) &
1471                                                    RING_HEAD_MASK);
1472                 if (dinfo->ring_tail + RING_MIN_FREE <
1473                     (u32 __iomem) dinfo->ring_head)
1474                         dinfo->ring_space = (u32 __iomem) dinfo->ring_head
1475                                 - (dinfo->ring_tail + RING_MIN_FREE);
1476                 else
1477                         dinfo->ring_space = (dinfo->ring.size +
1478                                              (u32 __iomem) dinfo->ring_head)
1479                                 - (dinfo->ring_tail + RING_MIN_FREE);
1480                 if ((u32 __iomem) dinfo->ring_head != last_head) {
1481                         end = jiffies + (HZ * 3);
1482                         last_head = (u32 __iomem) dinfo->ring_head;
1483                 }
1484                 i++;
1485                 if (time_before(end, jiffies)) {
1486                         if (!i) {
1487                                 /* Try again */
1488                                 reset_state(dinfo);
1489                                 refresh_ring(dinfo);
1490                                 do_flush(dinfo);
1491                                 end = jiffies + (HZ * 3);
1492                                 i = 1;
1493                         } else {
1494                                 WRN_MSG("ring buffer : space: %d wanted %d\n",
1495                                         dinfo->ring_space, n);
1496                                 WRN_MSG("lockup - turning off hardware "
1497                                         "acceleration\n");
1498                                 dinfo->ring_lockup = 1;
1499                                 break;
1500                         }
1501                 }
1502                 udelay(1);
1503         }
1504         return i;
1505 }
1506
1507 static void
1508 do_flush(struct intelfb_info *dinfo) {
1509         START_RING(2);
1510         OUT_RING(MI_FLUSH | MI_WRITE_DIRTY_STATE | MI_INVALIDATE_MAP_CACHE);
1511         OUT_RING(MI_NOOP);
1512         ADVANCE_RING();
1513 }
1514
1515 void
1516 intelfbhw_do_sync(struct intelfb_info *dinfo)
1517 {
1518 #if VERBOSE > 0
1519         DBG_MSG("intelfbhw_do_sync\n");
1520 #endif
1521
1522         if (!dinfo->accel)
1523                 return;
1524
1525         /*
1526          * Send a flush, then wait until the ring is empty.  This is what
1527          * the XFree86 driver does, and actually it doesn't seem a lot worse
1528          * than the recommended method (both have problems).
1529          */
1530         do_flush(dinfo);
1531         wait_ring(dinfo, dinfo->ring.size - RING_MIN_FREE);
1532         dinfo->ring_space = dinfo->ring.size - RING_MIN_FREE;
1533 }
1534
1535 static void
1536 refresh_ring(struct intelfb_info *dinfo)
1537 {
1538 #if VERBOSE > 0
1539         DBG_MSG("refresh_ring\n");
1540 #endif
1541
1542         dinfo->ring_head = (u8 __iomem *) (INREG(PRI_RING_HEAD) &
1543                                            RING_HEAD_MASK);
1544         dinfo->ring_tail = INREG(PRI_RING_TAIL) & RING_TAIL_MASK;
1545         if (dinfo->ring_tail + RING_MIN_FREE < (u32 __iomem)dinfo->ring_head)
1546                 dinfo->ring_space = (u32 __iomem) dinfo->ring_head
1547                         - (dinfo->ring_tail + RING_MIN_FREE);
1548         else
1549                 dinfo->ring_space = (dinfo->ring.size +
1550                                      (u32 __iomem) dinfo->ring_head)
1551                         - (dinfo->ring_tail + RING_MIN_FREE);
1552 }
1553
1554 static void
1555 reset_state(struct intelfb_info *dinfo)
1556 {
1557         int i;
1558         u32 tmp;
1559
1560 #if VERBOSE > 0
1561         DBG_MSG("reset_state\n");
1562 #endif
1563
1564         for (i = 0; i < FENCE_NUM; i++)
1565                 OUTREG(FENCE + (i << 2), 0);
1566
1567         /* Flush the ring buffer if it's enabled. */
1568         tmp = INREG(PRI_RING_LENGTH);
1569         if (tmp & RING_ENABLE) {
1570 #if VERBOSE > 0
1571                 DBG_MSG("reset_state: ring was enabled\n");
1572 #endif
1573                 refresh_ring(dinfo);
1574                 intelfbhw_do_sync(dinfo);
1575                 DO_RING_IDLE();
1576         }
1577
1578         OUTREG(PRI_RING_LENGTH, 0);
1579         OUTREG(PRI_RING_HEAD, 0);
1580         OUTREG(PRI_RING_TAIL, 0);
1581         OUTREG(PRI_RING_START, 0);
1582 }
1583
1584 /* Stop the 2D engine, and turn off the ring buffer. */
1585 void
1586 intelfbhw_2d_stop(struct intelfb_info *dinfo)
1587 {
1588 #if VERBOSE > 0
1589         DBG_MSG("intelfbhw_2d_stop: accel: %d, ring_active: %d\n", dinfo->accel,
1590                 dinfo->ring_active);
1591 #endif
1592
1593         if (!dinfo->accel)
1594                 return;
1595
1596         dinfo->ring_active = 0;
1597         reset_state(dinfo);
1598 }
1599
1600 /*
1601  * Enable the ring buffer, and initialise the 2D engine.
1602  * It is assumed that the graphics engine has been stopped by previously
1603  * calling intelfb_2d_stop().
1604  */
1605 void
1606 intelfbhw_2d_start(struct intelfb_info *dinfo)
1607 {
1608 #if VERBOSE > 0
1609         DBG_MSG("intelfbhw_2d_start: accel: %d, ring_active: %d\n",
1610                 dinfo->accel, dinfo->ring_active);
1611 #endif
1612
1613         if (!dinfo->accel)
1614                 return;
1615
1616         /* Initialise the primary ring buffer. */
1617         OUTREG(PRI_RING_LENGTH, 0);
1618         OUTREG(PRI_RING_TAIL, 0);
1619         OUTREG(PRI_RING_HEAD, 0);
1620
1621         OUTREG(PRI_RING_START, dinfo->ring.physical & RING_START_MASK);
1622         OUTREG(PRI_RING_LENGTH,
1623                 ((dinfo->ring.size - GTT_PAGE_SIZE) & RING_LENGTH_MASK) |
1624                 RING_NO_REPORT | RING_ENABLE);
1625         refresh_ring(dinfo);
1626         dinfo->ring_active = 1;
1627 }
1628
1629 /* 2D fillrect (solid fill or invert) */
1630 void
1631 intelfbhw_do_fillrect(struct intelfb_info *dinfo, u32 x, u32 y, u32 w, u32 h,
1632                       u32 color, u32 pitch, u32 bpp, u32 rop)
1633 {
1634         u32 br00, br09, br13, br14, br16;
1635
1636 #if VERBOSE > 0
1637         DBG_MSG("intelfbhw_do_fillrect: (%d,%d) %dx%d, c 0x%06x, p %d bpp %d, "
1638                 "rop 0x%02x\n", x, y, w, h, color, pitch, bpp, rop);
1639 #endif
1640
1641         br00 = COLOR_BLT_CMD;
1642         br09 = dinfo->fb_start + (y * pitch + x * (bpp / 8));
1643         br13 = (rop << ROP_SHIFT) | pitch;
1644         br14 = (h << HEIGHT_SHIFT) | ((w * (bpp / 8)) << WIDTH_SHIFT);
1645         br16 = color;
1646
1647         switch (bpp) {
1648         case 8:
1649                 br13 |= COLOR_DEPTH_8;
1650                 break;
1651         case 16:
1652                 br13 |= COLOR_DEPTH_16;
1653                 break;
1654         case 32:
1655                 br13 |= COLOR_DEPTH_32;
1656                 br00 |= WRITE_ALPHA | WRITE_RGB;
1657                 break;
1658         }
1659
1660         START_RING(6);
1661         OUT_RING(br00);
1662         OUT_RING(br13);
1663         OUT_RING(br14);
1664         OUT_RING(br09);
1665         OUT_RING(br16);
1666         OUT_RING(MI_NOOP);
1667         ADVANCE_RING();
1668
1669 #if VERBOSE > 0
1670         DBG_MSG("ring = 0x%08x, 0x%08x (%d)\n", dinfo->ring_head,
1671                 dinfo->ring_tail, dinfo->ring_space);
1672 #endif
1673 }
1674
1675 void
1676 intelfbhw_do_bitblt(struct intelfb_info *dinfo, u32 curx, u32 cury,
1677                     u32 dstx, u32 dsty, u32 w, u32 h, u32 pitch, u32 bpp)
1678 {
1679         u32 br00, br09, br11, br12, br13, br22, br23, br26;
1680
1681 #if VERBOSE > 0
1682         DBG_MSG("intelfbhw_do_bitblt: (%d,%d)->(%d,%d) %dx%d, p %d bpp %d\n",
1683                 curx, cury, dstx, dsty, w, h, pitch, bpp);
1684 #endif
1685
1686         br00 = XY_SRC_COPY_BLT_CMD;
1687         br09 = dinfo->fb_start;
1688         br11 = (pitch << PITCH_SHIFT);
1689         br12 = dinfo->fb_start;
1690         br13 = (SRC_ROP_GXCOPY << ROP_SHIFT) | (pitch << PITCH_SHIFT);
1691         br22 = (dstx << WIDTH_SHIFT) | (dsty << HEIGHT_SHIFT);
1692         br23 = ((dstx + w) << WIDTH_SHIFT) |
1693                ((dsty + h) << HEIGHT_SHIFT);
1694         br26 = (curx << WIDTH_SHIFT) | (cury << HEIGHT_SHIFT);
1695
1696         switch (bpp) {
1697         case 8:
1698                 br13 |= COLOR_DEPTH_8;
1699                 break;
1700         case 16:
1701                 br13 |= COLOR_DEPTH_16;
1702                 break;
1703         case 32:
1704                 br13 |= COLOR_DEPTH_32;
1705                 br00 |= WRITE_ALPHA | WRITE_RGB;
1706                 break;
1707         }
1708
1709         START_RING(8);
1710         OUT_RING(br00);
1711         OUT_RING(br13);
1712         OUT_RING(br22);
1713         OUT_RING(br23);
1714         OUT_RING(br09);
1715         OUT_RING(br26);
1716         OUT_RING(br11);
1717         OUT_RING(br12);
1718         ADVANCE_RING();
1719 }
1720
1721 int
1722 intelfbhw_do_drawglyph(struct intelfb_info *dinfo, u32 fg, u32 bg, u32 w,
1723                        u32 h, const u8* cdat, u32 x, u32 y, u32 pitch, u32 bpp)
1724 {
1725         int nbytes, ndwords, pad, tmp;
1726         u32 br00, br09, br13, br18, br19, br22, br23;
1727         int dat, ix, iy, iw;
1728         int i, j;
1729
1730 #if VERBOSE > 0
1731         DBG_MSG("intelfbhw_do_drawglyph: (%d,%d) %dx%d\n", x, y, w, h);
1732 #endif
1733
1734         /* size in bytes of a padded scanline */
1735         nbytes = ROUND_UP_TO(w, 16) / 8;
1736
1737         /* Total bytes of padded scanline data to write out. */
1738         nbytes = nbytes * h;
1739
1740         /*
1741          * Check if the glyph data exceeds the immediate mode limit.
1742          * It would take a large font (1K pixels) to hit this limit.
1743          */
1744         if (nbytes > MAX_MONO_IMM_SIZE)
1745                 return 0;
1746
1747         /* Src data is packaged a dword (32-bit) at a time. */
1748         ndwords = ROUND_UP_TO(nbytes, 4) / 4;
1749
1750         /*
1751          * Ring has to be padded to a quad word. But because the command starts
1752            with 7 bytes, pad only if there is an even number of ndwords
1753          */
1754         pad = !(ndwords % 2);
1755
1756         tmp = (XY_MONO_SRC_IMM_BLT_CMD & DW_LENGTH_MASK) + ndwords;
1757         br00 = (XY_MONO_SRC_IMM_BLT_CMD & ~DW_LENGTH_MASK) | tmp;
1758         br09 = dinfo->fb_start;
1759         br13 = (SRC_ROP_GXCOPY << ROP_SHIFT) | (pitch << PITCH_SHIFT);
1760         br18 = bg;
1761         br19 = fg;
1762         br22 = (x << WIDTH_SHIFT) | (y << HEIGHT_SHIFT);
1763         br23 = ((x + w) << WIDTH_SHIFT) | ((y + h) << HEIGHT_SHIFT);
1764
1765         switch (bpp) {
1766         case 8:
1767                 br13 |= COLOR_DEPTH_8;
1768                 break;
1769         case 16:
1770                 br13 |= COLOR_DEPTH_16;
1771                 break;
1772         case 32:
1773                 br13 |= COLOR_DEPTH_32;
1774                 br00 |= WRITE_ALPHA | WRITE_RGB;
1775                 break;
1776         }
1777
1778         START_RING(8 + ndwords);
1779         OUT_RING(br00);
1780         OUT_RING(br13);
1781         OUT_RING(br22);
1782         OUT_RING(br23);
1783         OUT_RING(br09);
1784         OUT_RING(br18);
1785         OUT_RING(br19);
1786         ix = iy = 0;
1787         iw = ROUND_UP_TO(w, 8) / 8;
1788         while (ndwords--) {
1789                 dat = 0;
1790                 for (j = 0; j < 2; ++j) {
1791                         for (i = 0; i < 2; ++i) {
1792                                 if (ix != iw || i == 0)
1793                                         dat |= cdat[iy*iw + ix++] << (i+j*2)*8;
1794                         }
1795                         if (ix == iw && iy != (h-1)) {
1796                                 ix = 0;
1797                                 ++iy;
1798                         }
1799                 }
1800                 OUT_RING(dat);
1801         }
1802         if (pad)
1803                 OUT_RING(MI_NOOP);
1804         ADVANCE_RING();
1805
1806         return 1;
1807 }
1808
1809 /* HW cursor functions. */
1810 void
1811 intelfbhw_cursor_init(struct intelfb_info *dinfo)
1812 {
1813         u32 tmp;
1814
1815 #if VERBOSE > 0
1816         DBG_MSG("intelfbhw_cursor_init\n");
1817 #endif
1818
1819         if (dinfo->mobile || IS_I9XX(dinfo)) {
1820                 if (!dinfo->cursor.physical)
1821                         return;
1822                 tmp = INREG(CURSOR_A_CONTROL);
1823                 tmp &= ~(CURSOR_MODE_MASK | CURSOR_MOBILE_GAMMA_ENABLE |
1824                          CURSOR_MEM_TYPE_LOCAL |
1825                          (1 << CURSOR_PIPE_SELECT_SHIFT));
1826                 tmp |= CURSOR_MODE_DISABLE;
1827                 OUTREG(CURSOR_A_CONTROL, tmp);
1828                 OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.physical);
1829         } else {
1830                 tmp = INREG(CURSOR_CONTROL);
1831                 tmp &= ~(CURSOR_FORMAT_MASK | CURSOR_GAMMA_ENABLE |
1832                          CURSOR_ENABLE | CURSOR_STRIDE_MASK);
1833                 tmp = CURSOR_FORMAT_3C;
1834                 OUTREG(CURSOR_CONTROL, tmp);
1835                 OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.offset << 12);
1836                 tmp = (64 << CURSOR_SIZE_H_SHIFT) |
1837                       (64 << CURSOR_SIZE_V_SHIFT);
1838                 OUTREG(CURSOR_SIZE, tmp);
1839         }
1840 }
1841
1842 void
1843 intelfbhw_cursor_hide(struct intelfb_info *dinfo)
1844 {
1845         u32 tmp;
1846
1847 #if VERBOSE > 0
1848         DBG_MSG("intelfbhw_cursor_hide\n");
1849 #endif
1850
1851         dinfo->cursor_on = 0;
1852         if (dinfo->mobile || IS_I9XX(dinfo)) {
1853                 if (!dinfo->cursor.physical)
1854                         return;
1855                 tmp = INREG(CURSOR_A_CONTROL);
1856                 tmp &= ~CURSOR_MODE_MASK;
1857                 tmp |= CURSOR_MODE_DISABLE;
1858                 OUTREG(CURSOR_A_CONTROL, tmp);
1859                 /* Flush changes */
1860                 OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.physical);
1861         } else {
1862                 tmp = INREG(CURSOR_CONTROL);
1863                 tmp &= ~CURSOR_ENABLE;
1864                 OUTREG(CURSOR_CONTROL, tmp);
1865         }
1866 }
1867
1868 void
1869 intelfbhw_cursor_show(struct intelfb_info *dinfo)
1870 {
1871         u32 tmp;
1872
1873 #if VERBOSE > 0
1874         DBG_MSG("intelfbhw_cursor_show\n");
1875 #endif
1876
1877         dinfo->cursor_on = 1;
1878
1879         if (dinfo->cursor_blanked)
1880                 return;
1881
1882         if (dinfo->mobile || IS_I9XX(dinfo)) {
1883                 if (!dinfo->cursor.physical)
1884                         return;
1885                 tmp = INREG(CURSOR_A_CONTROL);
1886                 tmp &= ~CURSOR_MODE_MASK;
1887                 tmp |= CURSOR_MODE_64_4C_AX;
1888                 OUTREG(CURSOR_A_CONTROL, tmp);
1889                 /* Flush changes */
1890                 OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.physical);
1891         } else {
1892                 tmp = INREG(CURSOR_CONTROL);
1893                 tmp |= CURSOR_ENABLE;
1894                 OUTREG(CURSOR_CONTROL, tmp);
1895         }
1896 }
1897
1898 void
1899 intelfbhw_cursor_setpos(struct intelfb_info *dinfo, int x, int y)
1900 {
1901         u32 tmp;
1902
1903 #if VERBOSE > 0
1904         DBG_MSG("intelfbhw_cursor_setpos: (%d, %d)\n", x, y);
1905 #endif
1906
1907         /*
1908          * Sets the position. The coordinates are assumed to already
1909          * have any offset adjusted. Assume that the cursor is never
1910          * completely off-screen, and that x, y are always >= 0.
1911          */
1912
1913         tmp = ((x & CURSOR_POS_MASK) << CURSOR_X_SHIFT) |
1914               ((y & CURSOR_POS_MASK) << CURSOR_Y_SHIFT);
1915         OUTREG(CURSOR_A_POSITION, tmp);
1916
1917         if (IS_I9XX(dinfo)) {
1918                 OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.physical);
1919         }
1920 }
1921
1922 void
1923 intelfbhw_cursor_setcolor(struct intelfb_info *dinfo, u32 bg, u32 fg)
1924 {
1925 #if VERBOSE > 0
1926         DBG_MSG("intelfbhw_cursor_setcolor\n");
1927 #endif
1928
1929         OUTREG(CURSOR_A_PALETTE0, bg & CURSOR_PALETTE_MASK);
1930         OUTREG(CURSOR_A_PALETTE1, fg & CURSOR_PALETTE_MASK);
1931         OUTREG(CURSOR_A_PALETTE2, fg & CURSOR_PALETTE_MASK);
1932         OUTREG(CURSOR_A_PALETTE3, bg & CURSOR_PALETTE_MASK);
1933 }
1934
1935 void
1936 intelfbhw_cursor_load(struct intelfb_info *dinfo, int width, int height,
1937                       u8 *data)
1938 {
1939         u8 __iomem *addr = (u8 __iomem *)dinfo->cursor.virtual;
1940         int i, j, w = width / 8;
1941         int mod = width % 8, t_mask, d_mask;
1942
1943 #if VERBOSE > 0
1944         DBG_MSG("intelfbhw_cursor_load\n");
1945 #endif
1946
1947         if (!dinfo->cursor.virtual)
1948                 return;
1949
1950         t_mask = 0xff >> mod;
1951         d_mask = ~(0xff >> mod);
1952         for (i = height; i--; ) {
1953                 for (j = 0; j < w; j++) {
1954                         writeb(0x00, addr + j);
1955                         writeb(*(data++), addr + j+8);
1956                 }
1957                 if (mod) {
1958                         writeb(t_mask, addr + j);
1959                         writeb(*(data++) & d_mask, addr + j+8);
1960                 }
1961                 addr += 16;
1962         }
1963 }
1964
1965 void
1966 intelfbhw_cursor_reset(struct intelfb_info *dinfo) {
1967         u8 __iomem *addr = (u8 __iomem *)dinfo->cursor.virtual;
1968         int i, j;
1969
1970 #if VERBOSE > 0
1971         DBG_MSG("intelfbhw_cursor_reset\n");
1972 #endif
1973
1974         if (!dinfo->cursor.virtual)
1975                 return;
1976
1977         for (i = 64; i--; ) {
1978                 for (j = 0; j < 8; j++) {
1979                         writeb(0xff, addr + j+0);
1980                         writeb(0x00, addr + j+8);
1981                 }
1982                 addr += 16;
1983         }
1984 }