SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/staging/rtl8187se/r8185b_init.c

   1 /*++
   2 Copyright (c) Realtek Semiconductor Corp. All rights reserved.
   3
   4 Module Name:
   5         r8185b_init.c
   6
   7 Abstract:
   8         Hardware Initialization and Hardware IO for RTL8185B
   9
  10 Major Change History:
  11         When        Who      What
  12         ----------    ---------------   -------------------------------
  13         2006-11-15    Xiong             Created
  14
  15 Notes:
  16         This file is ported from RTL8185B Windows driver.
  17
  18
  19 --*/
  20
  21 /*--------------------------Include File------------------------------------*/
  22 #include <linux/spinlock.h>
  23 #include "r8180_hw.h"
  24 #include "r8180.h"
  25 #include "r8180_sa2400.h"  /* PHILIPS Radio frontend */
  26 #include "r8180_max2820.h" /* MAXIM Radio frontend */
  27 #include "r8180_gct.h"     /* GCT Radio frontend */
  28 #include "r8180_rtl8225.h" /* RTL8225 Radio frontend */
  29 #include "r8180_rtl8255.h" /* RTL8255 Radio frontend */
  30 #include "r8180_93cx6.h"   /* Card EEPROM */
  31 #include "r8180_wx.h"
  32
  33 #include "r8180_pm.h"
  34
  35 #include "ieee80211/dot11d.h"
  36
  37
  38 //#define CONFIG_RTL8180_IO_MAP
  39
  40 #define TC_3W_POLL_MAX_TRY_CNT 5
  41 static u8 MAC_REG_TABLE[][2]={
  42                         //PAGA 0:
  43                         // 0x34(BRSR), 0xBE(RATE_FALLBACK_CTL), 0x1E0(ARFR) would set in HwConfigureRTL8185()
  44                         // 0x272(RFSW_CTRL), 0x1CE(AESMSK_QC) set in InitializeAdapter8185().
  45                         // 0x1F0~0x1F8  set in MacConfig_85BASIC()
  46                         {0x08, 0xae}, {0x0a, 0x72}, {0x5b, 0x42},
  47                         {0x84, 0x88}, {0x85, 0x24}, {0x88, 0x54}, {0x8b, 0xb8}, {0x8c, 0x03},
  48                         {0x8d, 0x40}, {0x8e, 0x00}, {0x8f, 0x00}, {0x5b, 0x18}, {0x91, 0x03},
  49                         {0x94, 0x0F}, {0x95, 0x32},
  50                         {0x96, 0x00}, {0x97, 0x07}, {0xb4, 0x22}, {0xdb, 0x00},
  51                         {0xf0, 0x32}, {0xf1, 0x32}, {0xf2, 0x00}, {0xf3, 0x00}, {0xf4, 0x32},
  52                         {0xf5, 0x43}, {0xf6, 0x00}, {0xf7, 0x00}, {0xf8, 0x46}, {0xf9, 0xa4},
  53                         {0xfa, 0x00}, {0xfb, 0x00}, {0xfc, 0x96}, {0xfd, 0xa4}, {0xfe, 0x00},
  54                         {0xff, 0x00},
  55
  56                         //PAGE 1:
  57                         // For Flextronics system Logo PCIHCT failure:
  58                         // 0x1C4~0x1CD set no-zero value to avoid PCI configuration space 0x45[7]=1
  59                         {0x5e, 0x01},
  60                         {0x58, 0x00}, {0x59, 0x00}, {0x5a, 0x04}, {0x5b, 0x00}, {0x60, 0x24},
  61                         {0x61, 0x97}, {0x62, 0xF0}, {0x63, 0x09}, {0x80, 0x0F}, {0x81, 0xFF},
  62                         {0x82, 0xFF}, {0x83, 0x03},
  63                         {0xC4, 0x22}, {0xC5, 0x22}, {0xC6, 0x22}, {0xC7, 0x22}, {0xC8, 0x22}, //lzm add 080826
  64                         {0xC9, 0x22}, {0xCA, 0x22}, {0xCB, 0x22}, {0xCC, 0x22}, {0xCD, 0x22},//lzm add 080826
  65                         {0xe2, 0x00},
  66
  67
  68                         //PAGE 2:
  69                         {0x5e, 0x02},
  70                         {0x0c, 0x04}, {0x4c, 0x30}, {0x4d, 0x08}, {0x50, 0x05}, {0x51, 0xf5},
  71                         {0x52, 0x04}, {0x53, 0xa0}, {0x54, 0xff}, {0x55, 0xff}, {0x56, 0xff},
  72                         {0x57, 0xff}, {0x58, 0x08}, {0x59, 0x08}, {0x5a, 0x08}, {0x5b, 0x08},
  73                         {0x60, 0x08}, {0x61, 0x08}, {0x62, 0x08}, {0x63, 0x08}, {0x64, 0x2f},
  74                         {0x8c, 0x3f}, {0x8d, 0x3f}, {0x8e, 0x3f},
  75                         {0x8f, 0x3f}, {0xc4, 0xff}, {0xc5, 0xff}, {0xc6, 0xff}, {0xc7, 0xff},
  76                         {0xc8, 0x00}, {0xc9, 0x00}, {0xca, 0x80}, {0xcb, 0x00},
  77
  78                         //PAGA 0:
  79                         {0x5e, 0x00},{0x9f, 0x03}
  80                 };
  81
  82
  83 static u8  ZEBRA_AGC[]={
  84                         0,
  85                         0x7E,0x7E,0x7E,0x7E,0x7D,0x7C,0x7B,0x7A,0x79,0x78,0x77,0x76,0x75,0x74,0x73,0x72,
  86                         0x71,0x70,0x6F,0x6E,0x6D,0x6C,0x6B,0x6A,0x69,0x68,0x67,0x66,0x65,0x64,0x63,0x62,
  87                         0x48,0x47,0x46,0x45,0x44,0x29,0x28,0x27,0x26,0x25,0x24,0x23,0x22,0x21,0x08,0x07,
  88                         0x06,0x05,0x04,0x03,0x02,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
  89                         0x0f,0x0f,0x0f,0x0f,0x0f,0x0f,0x0f,0x0f,0x0f,0x0f,0x10,0x11,0x12,0x13,0x15,0x16,
  90                         0x17,0x17,0x18,0x18,0x19,0x1a,0x1a,0x1b,0x1b,0x1c,0x1c,0x1d,0x1d,0x1d,0x1e,0x1e,
  91                         0x1f,0x1f,0x1f,0x20,0x20,0x20,0x20,0x21,0x21,0x21,0x22,0x22,0x22,0x23,0x23,0x24,
  92                         0x24,0x25,0x25,0x25,0x26,0x26,0x27,0x27,0x2F,0x2F,0x2F,0x2F,0x2F,0x2F,0x2F,0x2F
  93                         };
  94
  95 static u32 ZEBRA_RF_RX_GAIN_TABLE[]={
  96                         0x0096,0x0076,0x0056,0x0036,0x0016,0x01f6,0x01d6,0x01b6,
  97                         0x0196,0x0176,0x00F7,0x00D7,0x00B7,0x0097,0x0077,0x0057,
  98                         0x0037,0x00FB,0x00DB,0x00BB,0x00FF,0x00E3,0x00C3,0x00A3,
  99                         0x0083,0x0063,0x0043,0x0023,0x0003,0x01E3,0x01C3,0x01A3,
 100                         0x0183,0x0163,0x0143,0x0123,0x0103
 101         };
 102
 103 static u8 OFDM_CONFIG[]={
 104                         // OFDM reg0x06[7:0]=0xFF: Enable power saving mode in RX
 105                         // OFDM reg0x3C[4]=1'b1: Enable RX power saving mode
 106                         // ofdm 0x3a = 0x7b ,(original : 0xfb) For ECS shielding room TP test
 107
 108                         // 0x00
 109                         0x10, 0x0F, 0x0A, 0x0C, 0x14, 0xFA, 0xFF, 0x50,
 110                         0x00, 0x50, 0x00, 0x00, 0x00, 0x5C, 0x00, 0x00,
 111                         // 0x10
 112                         0x40, 0x00, 0x40, 0x00, 0x00, 0x00, 0xA8, 0x26,
 113                         0x32, 0x33, 0x06, 0xA5, 0x6F, 0x55, 0xC8, 0xBB,
 114                         // 0x20
 115                         0x0A, 0xE1, 0x2C, 0x4A, 0x86, 0x83, 0x34, 0x00,
 116                         0x4F, 0x24, 0x6F, 0xC2, 0x03, 0x40, 0x80, 0x00,
 117                         // 0x30
 118                         0xC0, 0xC1, 0x58, 0xF1, 0x00, 0xC4, 0x90, 0x3e,
 119                         0xD8, 0x3C, 0x7B, 0x10, 0x10
 120                 };
 121
 122 /*---------------------------------------------------------------
 123   * Hardware IO
 124   * the code is ported from Windows source code
 125   ----------------------------------------------------------------*/
 126
 127 void
 128 PlatformIOWrite1Byte(
 129         struct net_device *dev,
 130         u32             offset,
 131         u8              data
 132         )
 133 {
 134         write_nic_byte(dev, offset, data);
 135         read_nic_byte(dev, offset); // To make sure write operation is completed, 2005.11.09, by rcnjko.
 136
 137 }
 138
 139 void
 140 PlatformIOWrite2Byte(
 141         struct net_device *dev,
 142         u32             offset,
 143         u16             data
 144         )
 145 {
 146         write_nic_word(dev, offset, data);
 147         read_nic_word(dev, offset); // To make sure write operation is completed, 2005.11.09, by rcnjko.
 148
 149
 150 }
 151 u8 PlatformIORead1Byte(struct net_device *dev, u32 offset);
 152
 153 void
 154 PlatformIOWrite4Byte(
 155         struct net_device *dev,
 156         u32             offset,
 157         u32             data
 158         )
 159 {
 160 //{by amy 080312
 161 if (offset == PhyAddr)
 162         {//For Base Band configuration.
 163                 unsigned char   cmdByte;
 164                 unsigned long   dataBytes;
 165                 unsigned char   idx;
 166                 u8      u1bTmp;
 167
 168                 cmdByte = (u8)(data & 0x000000ff);
 169                 dataBytes = data>>8;
 170
 171                 //
 172                 // 071010, rcnjko:
 173                 // The critical section is only BB read/write race condition.
 174                 // Assumption:
 175                 // 1. We assume NO one will access BB at DIRQL, otherwise, system will crash for
 176                 // acquiring the spinlock in such context.
 177                 // 2. PlatformIOWrite4Byte() MUST NOT be recursive.
 178                 //
 179 //              NdisAcquireSpinLock( &(pDevice->IoSpinLock) );
 180
 181                 for(idx = 0; idx < 30; idx++)
 182                 { // Make sure command bit is clear before access it.
 183                         u1bTmp = PlatformIORead1Byte(dev, PhyAddr);
 184                         if((u1bTmp & BIT7) == 0)
 185                                 break;
 186                         else
 187                                 mdelay(10);
 188                 }
 189
 190                 for(idx=0; idx < 3; idx++)
 191                 {
 192                         PlatformIOWrite1Byte(dev,offset+1+idx,((u8*)&dataBytes)[idx] );
 193                 }
 194                 write_nic_byte(dev, offset, cmdByte);
 195
 196 //              NdisReleaseSpinLock( &(pDevice->IoSpinLock) );
 197         }
 198 //by amy 080312}
 199         else{
 200                 write_nic_dword(dev, offset, data);
 201                 read_nic_dword(dev, offset); // To make sure write operation is completed, 2005.11.09, by rcnjko.
 202         }
 203 }
 204
 205 u8
 206 PlatformIORead1Byte(
 207         struct net_device *dev,
 208         u32             offset
 209         )
 210 {
 211         u8      data = 0;
 212
 213         data = read_nic_byte(dev, offset);
 214
 215
 216         return data;
 217 }
 218
 219 u16
 220 PlatformIORead2Byte(
 221         struct net_device *dev,
 222         u32             offset
 223         )
 224 {
 225         u16     data = 0;
 226
 227         data = read_nic_word(dev, offset);
 228
 229
 230         return data;
 231 }
 232
 233 u32
 234 PlatformIORead4Byte(
 235         struct net_device *dev,
 236         u32             offset
 237         )
 238 {
 239         u32     data = 0;
 240
 241         data = read_nic_dword(dev, offset);
 242
 243
 244         return data;
 245 }
 246
 247 void
 248 SetOutputEnableOfRfPins(
 249         struct net_device *dev
 250         )
 251 {
 252         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
 253
 254         switch(priv->rf_chip)
 255         {
 256         case RFCHIPID_RTL8225:
 257         case RF_ZEBRA2:
 258         case RF_ZEBRA4:
 259                 write_nic_word(dev, RFPinsEnable, 0x1bff);
 260                 //write_nic_word(dev, RFPinsEnable, 0x1fff);
 261                 break;
 262         }
 263 }
 264
 265 void
 266 ZEBRA_RFSerialWrite(
 267         struct net_device *dev,
 268         u32                     data2Write,
 269         u8                      totalLength,
 270         u8                      low2high
 271         )
 272 {
 273         ThreeWireReg            twreg;
 274         int                             i;
 275         u16                             oval,oval2,oval3;
 276         u32                             mask;
 277         u16                             UshortBuffer;
 278
 279         u8                      u1bTmp;
 280         // RTL8187S HSSI Read/Write Function
 281         u1bTmp = read_nic_byte(dev, RF_SW_CONFIG);
 282         u1bTmp |=   RF_SW_CFG_SI;   //reg08[1]=1 Serial Interface(SI)
 283         write_nic_byte(dev, RF_SW_CONFIG, u1bTmp);
 284         UshortBuffer = read_nic_word(dev, RFPinsOutput);
 285         oval = UshortBuffer & 0xfff8; // We shall clear bit0, 1, 2 first, 2005.10.28, by rcnjko.
 286
 287         oval2 = read_nic_word(dev, RFPinsEnable);
 288         oval3 = read_nic_word(dev, RFPinsSelect);
 289
 290         // <RJ_NOTE> 3-wire should be controled by HW when we finish SW 3-wire programming. 2005.08.10, by rcnjko.
 291         oval3 &= 0xfff8;
 292
 293         write_nic_word(dev, RFPinsEnable, (oval2|0x0007)); // Set To Output Enable
 294         write_nic_word(dev, RFPinsSelect, (oval3|0x0007)); // Set To SW Switch
 295         udelay(10);
 296
 297         // Add this to avoid hardware and software 3-wire conflict.
 298         // 2005.03.01, by rcnjko.
 299         twreg.longData = 0;
 300         twreg.struc.enableB = 1;
 301         write_nic_word(dev, RFPinsOutput, (twreg.longData|oval)); // Set SI_EN (RFLE)
 302         udelay(2);
 303         twreg.struc.enableB = 0;
 304         write_nic_word(dev, RFPinsOutput, (twreg.longData|oval)); // Clear SI_EN (RFLE)
 305         udelay(10);
 306
 307         mask = (low2high)?0x01:((u32)0x01<<(totalLength-1));
 308
 309         for(i=0; i<totalLength/2; i++)
 310         {
 311                 twreg.struc.data = ((data2Write&mask)!=0) ? 1 : 0;
 312                 write_nic_word(dev, RFPinsOutput, (twreg.longData|oval));
 313                 twreg.struc.clk = 1;
 314                 write_nic_word(dev, RFPinsOutput, (twreg.longData|oval));
 315                 write_nic_word(dev, RFPinsOutput, (twreg.longData|oval));
 316
 317                 mask = (low2high)?(mask<<1):(mask>>1);
 318                 twreg.struc.data = ((data2Write&mask)!=0) ? 1 : 0;
 319                 write_nic_word(dev, RFPinsOutput, (twreg.longData|oval));
 320                 write_nic_word(dev, RFPinsOutput, (twreg.longData|oval));
 321                 twreg.struc.clk = 0;
 322                 write_nic_word(dev, RFPinsOutput, (twreg.longData|oval));
 323                 mask = (low2high)?(mask<<1):(mask>>1);
 324         }
 325
 326         twreg.struc.enableB = 1;
 327         twreg.struc.clk = 0;
 328         twreg.struc.data = 0;
 329         write_nic_word(dev, RFPinsOutput, twreg.longData|oval);
 330         udelay(10);
 331
 332         write_nic_word(dev, RFPinsOutput, oval|0x0004);
 333         write_nic_word(dev, RFPinsSelect, oval3|0x0000);
 334
 335         SetOutputEnableOfRfPins(dev);
 336 }
 337 //by amy
 338
 339
 340 int
 341 HwHSSIThreeWire(
 342         struct net_device *dev,
 343         u8                      *pDataBuf,
 344         u8                      nDataBufBitCnt,
 345         int                     bSI,
 346         int                     bWrite
 347         )
 348 {
 349         int     bResult = 1;
 350         u8      TryCnt;
 351         u8      u1bTmp;
 352
 353         do
 354         {
 355                 // Check if WE and RE are cleared.
 356                 for(TryCnt = 0; TryCnt < TC_3W_POLL_MAX_TRY_CNT; TryCnt++)
 357                 {
 358                         u1bTmp = read_nic_byte(dev, SW_3W_CMD1);
 359                         if( (u1bTmp & (SW_3W_CMD1_RE|SW_3W_CMD1_WE)) == 0 )
 360                         {
 361                                 break;
 362                         }
 363                         udelay(10);
 364                 }
 365                 if (TryCnt == TC_3W_POLL_MAX_TRY_CNT)
 366                         panic("HwThreeWire(): CmdReg: %#X RE|WE bits are not clear!!\n", u1bTmp);
 367
 368                 // RTL8187S HSSI Read/Write Function
 369                 u1bTmp = read_nic_byte(dev, RF_SW_CONFIG);
 370
 371                 if(bSI)
 372                 {
 373                         u1bTmp |=   RF_SW_CFG_SI;   //reg08[1]=1 Serial Interface(SI)
 374                 }else
 375                 {
 376                         u1bTmp &= ~RF_SW_CFG_SI;  //reg08[1]=0 Parallel Interface(PI)
 377                 }
 378
 379                 write_nic_byte(dev, RF_SW_CONFIG, u1bTmp);
 380
 381                 if(bSI)
 382                 {
 383                         // jong: HW SI read must set reg84[3]=0.
 384                         u1bTmp = read_nic_byte(dev, RFPinsSelect);
 385                         u1bTmp &= ~BIT3;
 386                         write_nic_byte(dev, RFPinsSelect, u1bTmp );
 387                 }
 388                 // Fill up data buffer for write operation.
 389
 390                 if(bWrite)
 391                 {
 392                         if(nDataBufBitCnt == 16)
 393                         {
 394                                 write_nic_word(dev, SW_3W_DB0, *((u16*)pDataBuf));
 395                         }
 396                         else if(nDataBufBitCnt == 64)  // RTL8187S shouldn't enter this case
 397                         {
 398                                 write_nic_dword(dev, SW_3W_DB0, *((u32*)pDataBuf));
 399                                 write_nic_dword(dev, SW_3W_DB1, *((u32*)(pDataBuf + 4)));
 400                         }
 401                         else
 402                         {
 403                                 int idx;
 404                                 int ByteCnt = nDataBufBitCnt / 8;
 405                                 //printk("%d\n",nDataBufBitCnt);
 406                                 if ((nDataBufBitCnt % 8) != 0)
 407                                 panic("HwThreeWire(): nDataBufBitCnt(%d) should be multiple of 8!!!\n",
 408                                 nDataBufBitCnt);
 409
 410                                if (nDataBufBitCnt > 64)
 411                                 panic("HwThreeWire(): nDataBufBitCnt(%d) should <= 64!!!\n",
 412                                 nDataBufBitCnt);
 413
 414                                 for(idx = 0; idx < ByteCnt; idx++)
 415                                 {
 416                                         write_nic_byte(dev, (SW_3W_DB0+idx), *(pDataBuf+idx));
 417                                 }
 418                         }
 419                 }
 420                 else            //read
 421                 {
 422                         if(bSI)
 423                         {
 424                                 // SI - reg274[3:0] : RF register's Address
 425                                 write_nic_word(dev, SW_3W_DB0, *((u16*)pDataBuf) );
 426                         }
 427                         else
 428                         {
 429                                 // PI - reg274[15:12] : RF register's Address
 430                                 write_nic_word(dev, SW_3W_DB0, (*((u16*)pDataBuf)) << 12);
 431                         }
 432                 }
 433
 434                 // Set up command: WE or RE.
 435                 if(bWrite)
 436                 {
 437                         write_nic_byte(dev, SW_3W_CMD1, SW_3W_CMD1_WE);
 438                 }
 439                 else
 440                 {
 441                         write_nic_byte(dev, SW_3W_CMD1, SW_3W_CMD1_RE);
 442                 }
 443
 444                 // Check if DONE is set.
 445                 for(TryCnt = 0; TryCnt < TC_3W_POLL_MAX_TRY_CNT; TryCnt++)
 446                 {
 447                         u1bTmp = read_nic_byte(dev, SW_3W_CMD1);
 448                         if(  (u1bTmp & SW_3W_CMD1_DONE) != 0 )
 449                         {
 450                                 break;
 451                         }
 452                         udelay(10);
 453                 }
 454
 455                 write_nic_byte(dev, SW_3W_CMD1, 0);
 456
 457                 // Read back data for read operation.
 458                 if(bWrite == 0)
 459                 {
 460                         if(bSI)
 461                         {
 462                                 //Serial Interface : reg363_362[11:0]
 463                                 *((u16*)pDataBuf) = read_nic_word(dev, SI_DATA_READ) ;
 464                         }
 465                         else
 466                         {
 467                                 //Parallel Interface : reg361_360[11:0]
 468                                 *((u16*)pDataBuf) = read_nic_word(dev, PI_DATA_READ);
 469                         }
 470
 471                         *((u16*)pDataBuf) &= 0x0FFF;
 472                 }
 473
 474         }while(0);
 475
 476         return bResult;
 477 }
 478 //by amy
 479
 480 int
 481 HwThreeWire(
 482         struct net_device *dev,
 483         u8                      *pDataBuf,
 484         u8                      nDataBufBitCnt,
 485         int                     bHold,
 486         int                     bWrite
 487         )
 488 {
 489         int     bResult = 1;
 490         u8      TryCnt;
 491         u8      u1bTmp;
 492
 493         do
 494         {
 495                 // Check if WE and RE are cleared.
 496                 for(TryCnt = 0; TryCnt < TC_3W_POLL_MAX_TRY_CNT; TryCnt++)
 497                 {
 498                         u1bTmp = read_nic_byte(dev, SW_3W_CMD1);
 499                         if( (u1bTmp & (SW_3W_CMD1_RE|SW_3W_CMD1_WE)) == 0 )
 500                         {
 501                                 break;
 502                         }
 503                         udelay(10);
 504                 }
 505                 if (TryCnt == TC_3W_POLL_MAX_TRY_CNT)
 506                         panic("HwThreeWire(): CmdReg: %#X RE|WE bits are not clear!!\n", u1bTmp);
 507
 508                 // Fill up data buffer for write operation.
 509                 if(nDataBufBitCnt == 16)
 510                 {
 511                         write_nic_word(dev, SW_3W_DB0, *((u16 *)pDataBuf));
 512                 }
 513                 else if(nDataBufBitCnt == 64)
 514                 {
 515                         write_nic_dword(dev, SW_3W_DB0, *((u32 *)pDataBuf));
 516                         write_nic_dword(dev, SW_3W_DB1, *((u32 *)(pDataBuf + 4)));
 517                 }
 518                 else
 519                 {
 520                         int idx;
 521                         int ByteCnt = nDataBufBitCnt / 8;
 522
 523                         if ((nDataBufBitCnt % 8) != 0)
 524                                 panic("HwThreeWire(): nDataBufBitCnt(%d) should be multiple of 8!!!\n",
 525                                 nDataBufBitCnt);
 526
 527                         if (nDataBufBitCnt > 64)
 528                                 panic("HwThreeWire(): nDataBufBitCnt(%d) should <= 64!!!\n",
 529                                 nDataBufBitCnt);
 530
 531                         for(idx = 0; idx < ByteCnt; idx++)
 532                         {
 533                                 write_nic_byte(dev, (SW_3W_DB0+idx), *(pDataBuf+idx));
 534                         }
 535                 }
 536
 537                 // Fill up length field.
 538                 u1bTmp = (u8)(nDataBufBitCnt - 1); // Number of bits - 1.
 539                 if(bHold)
 540                         u1bTmp |= SW_3W_CMD0_HOLD;
 541                 write_nic_byte(dev, SW_3W_CMD0, u1bTmp);
 542
 543                 // Set up command: WE or RE.
 544                 if(bWrite)
 545                 {
 546                         write_nic_byte(dev, SW_3W_CMD1, SW_3W_CMD1_WE);
 547                 }
 548                 else
 549                 {
 550                         write_nic_byte(dev, SW_3W_CMD1, SW_3W_CMD1_RE);
 551                 }
 552
 553                 // Check if WE and RE are cleared and DONE is set.
 554                 for(TryCnt = 0; TryCnt < TC_3W_POLL_MAX_TRY_CNT; TryCnt++)
 555                 {
 556                         u1bTmp = read_nic_byte(dev, SW_3W_CMD1);
 557                         if( (u1bTmp & (SW_3W_CMD1_RE|SW_3W_CMD1_WE)) == 0 &&
 558                                 (u1bTmp & SW_3W_CMD1_DONE) != 0 )
 559                         {
 560                                 break;
 561                         }
 562                         udelay(10);
 563                 }
 564                 if(TryCnt == TC_3W_POLL_MAX_TRY_CNT)
 565                 {
 566                         //RT_ASSERT(TryCnt != TC_3W_POLL_MAX_TRY_CNT,
 567                         //      ("HwThreeWire(): CmdReg: %#X RE|WE bits are not clear or DONE is not set!!\n", u1bTmp));
 568                         // Workaround suggested by wcchu: clear WE here. 2006.07.07, by rcnjko.
 569                         write_nic_byte(dev, SW_3W_CMD1, 0);
 570                 }
 571
 572                 // Read back data for read operation.
 573                 // <RJ_TODO> I am not sure if this is correct output format of a read operation.
 574                 if(bWrite == 0)
 575                 {
 576                         if(nDataBufBitCnt == 16)
 577                         {
 578                                 *((u16 *)pDataBuf) = read_nic_word(dev, SW_3W_DB0);
 579                         }
 580                         else if(nDataBufBitCnt == 64)
 581                         {
 582                                 *((u32 *)pDataBuf) = read_nic_dword(dev, SW_3W_DB0);
 583                                 *((u32 *)(pDataBuf + 4)) = read_nic_dword(dev, SW_3W_DB1);
 584                         }
 585                         else
 586                         {
 587                                 int idx;
 588                                 int ByteCnt = nDataBufBitCnt / 8;
 589
 590                                 if ((nDataBufBitCnt % 8) != 0)
 591                                         panic("HwThreeWire(): nDataBufBitCnt(%d) should be multiple of 8!!!\n",
 592                                         nDataBufBitCnt);
 593
 594                                 if (nDataBufBitCnt > 64)
 595                                         panic("HwThreeWire(): nDataBufBitCnt(%d) should <= 64!!!\n",
 596                                         nDataBufBitCnt);
 597
 598                                 for(idx = 0; idx < ByteCnt; idx++)
 599                                 {
 600                                         *(pDataBuf+idx) = read_nic_byte(dev, (SW_3W_DB0+idx));
 601                                 }
 602                         }
 603                 }
 604
 605         }while(0);
 606
 607         return bResult;
 608 }
 609
 610
 611 void
 612 RF_WriteReg(
 613         struct net_device *dev,
 614         u8              offset,
 615         u32             data
 616         )
 617 {
 618         //RFReg                 reg;
 619         u32                     data2Write;
 620         u8                      len;
 621         u8                      low2high;
 622         //u32                   RF_Read = 0;
 623         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
 624
 625
 626         switch(priv->rf_chip)
 627         {
 628         case RFCHIPID_RTL8225:
 629         case RF_ZEBRA2:         // Annie 2006-05-12.
 630         case RF_ZEBRA4:        //by amy
 631                 switch(priv->RegThreeWireMode)
 632                 {
 633                 case SW_THREE_WIRE:
 634                         { // Perform SW 3-wire programming by driver.
 635                                 data2Write = (data << 4) | (u32)(offset & 0x0f);
 636                                 len = 16;
 637                                 low2high = 0;
 638                                 ZEBRA_RFSerialWrite(dev, data2Write, len, low2high);
 639                         }
 640                         break;
 641
 642                 case HW_THREE_WIRE:
 643                         { // Pure HW 3-wire.
 644                                 data2Write = (data << 4) | (u32)(offset & 0x0f);
 645                                 len = 16;
 646                                 HwThreeWire(
 647                                         dev,
 648                                         (u8 *)(&data2Write),    // pDataBuf,
 649                                         len,                            // nDataBufBitCnt,
 650                                         0,                                      // bHold,
 651                                         1);                                     // bWrite
 652                         }
 653                         break;
 654                         case HW_THREE_WIRE_PI: //Parallel Interface
 655                         { // Pure HW 3-wire.
 656                                 data2Write = (data << 4) | (u32)(offset & 0x0f);
 657                                 len = 16;
 658                                         HwHSSIThreeWire(
 659                                                 dev,
 660                                                 (u8*)(&data2Write),     // pDataBuf,
 661                                                 len,                                            // nDataBufBitCnt,
 662                                                 0,                                      // bSI
 663                                                 1);                                     // bWrite
 664
 665                                 //printk("33333\n");
 666                         }
 667                         break;
 668
 669                         case HW_THREE_WIRE_SI: //Serial Interface
 670                         { // Pure HW 3-wire.
 671                                 data2Write = (data << 4) | (u32)(offset & 0x0f);
 672                                 len = 16;
 673 //                                printk(" enter  ZEBRA_RFSerialWrite\n ");
 674 //                                low2high = 0;
 675 //                                ZEBRA_RFSerialWrite(dev, data2Write, len, low2high);
 676
 677                                 HwHSSIThreeWire(
 678                                         dev,
 679                                         (u8*)(&data2Write),     // pDataBuf,
 680                                         len,                                            // nDataBufBitCnt,
 681                                         1,                                      // bSI
 682                                         1);                                     // bWrite
 683
 684 //                                 printk(" exit ZEBRA_RFSerialWrite\n ");
 685                         }
 686                         break;
 687
 688
 689                 default:
 690                         DMESGE("RF_WriteReg(): invalid RegThreeWireMode(%d) !!!", priv->RegThreeWireMode);
 691                         break;
 692                 }
 693                 break;
 694
 695         default:
 696                 DMESGE("RF_WriteReg(): unknown RFChipID: %#X", priv->rf_chip);
 697                 break;
 698         }
 699 }
 700
 701
 702 void
 703 ZEBRA_RFSerialRead(
 704         struct net_device *dev,
 705         u32             data2Write,
 706         u8              wLength,
 707         u32             *data2Read,
 708         u8              rLength,
 709         u8              low2high
 710         )
 711 {
 712         ThreeWireReg    twreg;
 713         int                             i;
 714         u16                     oval,oval2,oval3,tmp, wReg80;
 715         u32                     mask;
 716         u8                      u1bTmp;
 717         ThreeWireReg    tdata;
 718         //PHAL_DATA_8187        pHalData = GetHalData8187(pAdapter);
 719         { // RTL8187S HSSI Read/Write Function
 720                 u1bTmp = read_nic_byte(dev, RF_SW_CONFIG);
 721                 u1bTmp |=   RF_SW_CFG_SI;   //reg08[1]=1 Serial Interface(SI)
 722                 write_nic_byte(dev, RF_SW_CONFIG, u1bTmp);
 723         }
 724
 725         wReg80 = oval = read_nic_word(dev, RFPinsOutput);
 726         oval2 = read_nic_word(dev, RFPinsEnable);
 727         oval3 = read_nic_word(dev, RFPinsSelect);
 728
 729         write_nic_word(dev, RFPinsEnable, oval2|0xf);
 730         write_nic_word(dev, RFPinsSelect, oval3|0xf);
 731
 732         *data2Read = 0;
 733
 734         // We must clear BIT0-3 here, otherwise,
 735         // SW_Enalbe will be true when we first call ZEBRA_RFSerialRead() after 8187MPVC open,
 736         // which will cause the value read become 0. 2005.04.11, by rcnjko.
 737         oval &= ~0xf;
 738
 739         // Avoid collision with hardware three-wire.
 740         twreg.longData = 0;
 741         twreg.struc.enableB = 1;
 742         write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(4);
 743
 744         twreg.longData = 0;
 745         twreg.struc.enableB = 0;
 746         twreg.struc.clk = 0;
 747         twreg.struc.read_write = 0;
 748         write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(5);
 749
 750         mask = (low2high) ? 0x01 : ((u32)0x01<<(32-1));
 751         for(i = 0; i < wLength/2; i++)
 752         {
 753                 twreg.struc.data = ((data2Write&mask) != 0) ? 1 : 0;
 754                 write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(1);
 755                 twreg.struc.clk = 1;
 756                 write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(2);
 757                 write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(2);
 758
 759                 mask = (low2high) ? (mask<<1): (mask>>1);
 760
 761                 if(i == 2)
 762                 {
 763                         // Commented out by Jackie, 2004.08.26. <RJ_NOTE> We must comment out the following two lines for we cannot pull down VCOPDN during RF Serail Read.
 764                         //PlatformEFIOWrite2Byte(pAdapter, RFPinsEnable, 0xe);     // turn off data enable
 765                         //PlatformEFIOWrite2Byte(pAdapter, RFPinsSelect, 0xe);
 766
 767                         twreg.struc.read_write=1;
 768                         write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(2);
 769                         twreg.struc.clk = 0;
 770                         write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(2);
 771                         break;
 772                 }
 773                 twreg.struc.data = ((data2Write&mask) != 0) ? 1: 0;
 774                 write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(2);
 775                 write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(2);
 776
 777                 twreg.struc.clk = 0;
 778                 write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(1);
 779
 780                 mask = (low2high) ? (mask<<1) : (mask>>1);
 781         }
 782
 783         twreg.struc.clk = 0;
 784         twreg.struc.data = 0;
 785         write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(2);
 786         mask = (low2high) ? 0x01 : ((u32)0x01 << (12-1));
 787
 788         //
 789         // 061016, by rcnjko:
 790         // We must set data pin to HW controled, otherwise RF can't driver it and
 791         // value RF register won't be able to read back properly.
 792         //
 793         write_nic_word(dev, RFPinsEnable, ( ((oval2|0x0E) & (~0x01))) );
 794
 795         for(i = 0; i < rLength; i++)
 796         {
 797                 write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(1);
 798                 twreg.struc.clk = 1;
 799                 write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(2);
 800                 write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(2);
 801                 write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(2);
 802                 tmp = read_nic_word(dev, RFPinsInput);
 803                 tdata.longData = tmp;
 804                 *data2Read |= tdata.struc.clk ? mask : 0;
 805
 806                 twreg.struc.clk = 0;
 807                 write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(2);
 808
 809                 mask = (low2high) ? (mask<<1) : (mask>>1);
 810         }
 811         twreg.struc.enableB = 1;
 812         twreg.struc.clk = 0;
 813         twreg.struc.data = 0;
 814         twreg.struc.read_write = 1;
 815         write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(2);
 816
 817         //PlatformEFIOWrite2Byte(pAdapter, RFPinsEnable, oval2|0x8);   // Set To Output Enable
 818         write_nic_word(dev, RFPinsEnable, oval2);   // Set To Output Enable, <RJ_NOTE> We cannot enable BIT3 here, otherwise, we will failed to switch channel. 2005.04.12.
 819         //PlatformEFIOWrite2Byte(pAdapter, RFPinsEnable, 0x1bff);
 820         write_nic_word(dev, RFPinsSelect, oval3);   // Set To SW Switch
 821         //PlatformEFIOWrite2Byte(pAdapter, RFPinsSelect, 0x0488);
 822         write_nic_word(dev, RFPinsOutput, 0x3a0);
 823         //PlatformEFIOWrite2Byte(pAdapter, RFPinsOutput, 0x0480);
 824 }
 825
 826
 827 u32
 828 RF_ReadReg(
 829         struct net_device *dev,
 830         u8              offset
 831         )
 832 {
 833         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
 834         u32                     data2Write;
 835         u8                      wlen;
 836         u8                      rlen;
 837         u8                      low2high;
 838         u32                     dataRead;
 839
 840         switch(priv->rf_chip)
 841         {
 842         case RFCHIPID_RTL8225:
 843         case RF_ZEBRA2:
 844         case RF_ZEBRA4:
 845                 switch(priv->RegThreeWireMode)
 846                 {
 847                         case HW_THREE_WIRE_PI: // For 87S  Parallel Interface.
 848                         {
 849                                 data2Write = ((u32)(offset&0x0f));
 850                                 wlen=16;
 851                                 HwHSSIThreeWire(
 852                                         dev,
 853                                         (u8*)(&data2Write),     // pDataBuf,
 854                                         wlen,                                   // nDataBufBitCnt,
 855                                         0,                                      // bSI
 856                                         0);                                     // bWrite
 857                                 dataRead= data2Write;
 858                         }
 859                         break;
 860
 861                         case HW_THREE_WIRE_SI: // For 87S Serial Interface.
 862                         {
 863                                 data2Write = ((u32)(offset&0x0f)) ;
 864                                 wlen=16;
 865                                 HwHSSIThreeWire(
 866                                         dev,
 867                                         (u8*)(&data2Write),     // pDataBuf,
 868                                         wlen,                                   // nDataBufBitCnt,
 869                                         1,                                      // bSI
 870                                         0                                       // bWrite
 871                                         );
 872                                 dataRead= data2Write;
 873                         }
 874                         break;
 875
 876                         // Perform SW 3-wire programming by driver.
 877                         default:
 878                         {
 879                                 data2Write = ((u32)(offset&0x1f)) << 27; // For Zebra E-cut. 2005.04.11, by rcnjko.
 880                                 wlen = 6;
 881                                 rlen = 12;
 882                                 low2high = 0;
 883                                 ZEBRA_RFSerialRead(dev, data2Write, wlen,&dataRead,rlen, low2high);
 884                         }
 885                         break;
 886                 }
 887                 break;
 888         default:
 889                 dataRead = 0;
 890                 break;
 891         }
 892
 893         return dataRead;
 894 }
 895
 896
 897 // by Owen on 04/07/14 for writing BB register successfully
 898 void
 899 WriteBBPortUchar(
 900         struct net_device *dev,
 901         u32             Data
 902         )
 903 {
 904         //u8    TimeoutCounter;
 905         u8      RegisterContent;
 906         u8      UCharData;
 907
 908         UCharData = (u8)((Data & 0x0000ff00) >> 8);
 909         PlatformIOWrite4Byte(dev, PhyAddr, Data);
 910         //for(TimeoutCounter = 10; TimeoutCounter > 0; TimeoutCounter--)
 911         {
 912                 PlatformIOWrite4Byte(dev, PhyAddr, Data & 0xffffff7f);
 913                 RegisterContent = PlatformIORead1Byte(dev, PhyDataR);
 914                 //if(UCharData == RegisterContent)
 915                 //      break;
 916         }
 917 }
 918
 919 u8
 920 ReadBBPortUchar(
 921         struct net_device *dev,
 922         u32             addr
 923         )
 924 {
 925         //u8    TimeoutCounter;
 926         u8      RegisterContent;
 927
 928         PlatformIOWrite4Byte(dev, PhyAddr, addr & 0xffffff7f);
 929         RegisterContent = PlatformIORead1Byte(dev, PhyDataR);
 930
 931         return RegisterContent;
 932 }
 933 //{by amy 080312
 934 //
 935 //      Description:
 936 //              Perform Antenna settings with antenna diversity on 87SE.
 937 //    Created by Roger, 2008.01.25.
 938 //
 939 bool
 940 SetAntennaConfig87SE(
 941         struct net_device *dev,
 942         u8                      DefaultAnt,             // 0: Main, 1: Aux.
 943         bool            bAntDiversity   // 1:Enable, 0: Disable.
 944 )
 945 {
 946         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
 947         bool   bAntennaSwitched = true;
 948
 949         //printk("SetAntennaConfig87SE(): DefaultAnt(%d), bAntDiversity(%d)\n", DefaultAnt, bAntDiversity);
 950
 951         // Threshold for antenna diversity.
 952         write_phy_cck(dev, 0x0c, 0x09); // Reg0c : 09
 953
 954         if( bAntDiversity )  //  Enable Antenna Diversity.
 955         {
 956                 if( DefaultAnt == 1 )  // aux antenna
 957                 {
 958                         // Mac register, aux antenna
 959                         write_nic_byte(dev, ANTSEL, 0x00);
 960
 961                         // Config CCK RX antenna.
 962                         write_phy_cck(dev, 0x11, 0xbb); // Reg11 : bb
 963                         write_phy_cck(dev, 0x01, 0xc7); // Reg01 : c7
 964
 965                         // Config OFDM RX antenna.
 966                         write_phy_ofdm(dev, 0x0D, 0x54);   // Reg0d : 54
 967                         write_phy_ofdm(dev, 0x18, 0xb2);  // Reg18 : b2
 968                 }
 969                 else //  use main antenna
 970                 {
 971                         // Mac register, main antenna
 972                         write_nic_byte(dev, ANTSEL, 0x03);
 973                         //base band
 974                         // Config CCK RX antenna.
 975                         write_phy_cck(dev, 0x11, 0x9b); // Reg11 : 9b
 976                         write_phy_cck(dev, 0x01, 0xc7); // Reg01 : c7
 977
 978                         // Config OFDM RX antenna.
 979                         write_phy_ofdm(dev, 0x0d, 0x5c);   // Reg0d : 5c
 980                         write_phy_ofdm(dev, 0x18, 0xb2);  // Reg18 : b2
 981                 }
 982         }
 983         else   // Disable Antenna Diversity.
 984         {
 985                 if( DefaultAnt == 1 ) // aux Antenna
 986                 {
 987                         // Mac register, aux antenna
 988                         write_nic_byte(dev, ANTSEL, 0x00);
 989
 990                         // Config CCK RX antenna.
 991                         write_phy_cck(dev, 0x11, 0xbb); // Reg11 : bb
 992                         write_phy_cck(dev, 0x01, 0x47); // Reg01 : 47
 993
 994                         // Config OFDM RX antenna.
 995                         write_phy_ofdm(dev, 0x0D, 0x54);   // Reg0d : 54
 996                         write_phy_ofdm(dev, 0x18, 0x32);  // Reg18 : 32
 997                 }
 998                 else // main Antenna
 999                 {
1000                         // Mac register, main antenna
1001                         write_nic_byte(dev, ANTSEL, 0x03);
1002
1003                         // Config CCK RX antenna.
1004                         write_phy_cck(dev, 0x11, 0x9b); // Reg11 : 9b
1005                         write_phy_cck(dev, 0x01, 0x47); // Reg01 : 47
1006
1007                         // Config OFDM RX antenna.
1008                         write_phy_ofdm(dev, 0x0D, 0x5c);   // Reg0d : 5c
1009                         write_phy_ofdm(dev, 0x18, 0x32);  // Reg18 : 32
1010                 }
1011         }
1012         priv->CurrAntennaIndex = DefaultAnt; // Update default settings.
1013         return  bAntennaSwitched;
1014 }
1015 //by amy 080312
1016 /*---------------------------------------------------------------
1017   * Hardware Initialization.
1018   * the code is ported from Windows source code
1019   ----------------------------------------------------------------*/
1020
1021 void
1022 ZEBRA_Config_85BASIC_HardCode(
1023         struct net_device *dev
1024         )
1025 {
1026
1027         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1028         u32                     i;
1029         u32     addr,data;
1030         u32     u4bRegOffset, u4bRegValue, u4bRF23, u4bRF24;
1031        u8                       u1b24E;
1032
1033
1034         //=============================================================================
1035         // 87S_PCIE :: RADIOCFG.TXT
1036         //=============================================================================
1037
1038
1039         // Page1 : reg16-reg30
1040         RF_WriteReg(dev, 0x00, 0x013f);                 mdelay(1); // switch to page1
1041         u4bRF23= RF_ReadReg(dev, 0x08);                 mdelay(1);
1042         u4bRF24= RF_ReadReg(dev, 0x09);                 mdelay(1);
1043
1044         if (u4bRF23==0x818 && u4bRF24==0x70C && priv->card_8185 == VERSION_8187S_C)
1045                 priv->card_8185 = VERSION_8187S_D;
1046
1047         // Page0 : reg0-reg15
1048
1049 //      RF_WriteReg(dev, 0x00, 0x003f);                 mdelay(1);//1
1050         RF_WriteReg(dev, 0x00, 0x009f);         mdelay(1);// 1
1051
1052         RF_WriteReg(dev, 0x01, 0x06e0);                 mdelay(1);
1053
1054 //      RF_WriteReg(dev, 0x02, 0x004c);                 mdelay(1);//2
1055         RF_WriteReg(dev, 0x02, 0x004d);                 mdelay(1);// 2
1056
1057 //      RF_WriteReg(dev, 0x03, 0x0000);                 mdelay(1);//3
1058         RF_WriteReg(dev, 0x03, 0x07f1);                 mdelay(1);// 3
1059
1060         RF_WriteReg(dev, 0x04, 0x0975);                 mdelay(1);
1061         RF_WriteReg(dev, 0x05, 0x0c72);                 mdelay(1);
1062         RF_WriteReg(dev, 0x06, 0x0ae6);                 mdelay(1);
1063         RF_WriteReg(dev, 0x07, 0x00ca);                 mdelay(1);
1064         RF_WriteReg(dev, 0x08, 0x0e1c);                 mdelay(1);
1065         RF_WriteReg(dev, 0x09, 0x02f0);                 mdelay(1);
1066         RF_WriteReg(dev, 0x0a, 0x09d0);                 mdelay(1);
1067         RF_WriteReg(dev, 0x0b, 0x01ba);                 mdelay(1);
1068         RF_WriteReg(dev, 0x0c, 0x0640);                 mdelay(1);
1069         RF_WriteReg(dev, 0x0d, 0x08df);                 mdelay(1);
1070         RF_WriteReg(dev, 0x0e, 0x0020);                 mdelay(1);
1071         RF_WriteReg(dev, 0x0f, 0x0990);                 mdelay(1);
1072
1073
1074         // Page1 : reg16-reg30
1075         RF_WriteReg(dev, 0x00, 0x013f);                 mdelay(1);
1076
1077         RF_WriteReg(dev, 0x03, 0x0806);                 mdelay(1);
1078
1079         if(priv->card_8185 < VERSION_8187S_C)
1080         {
1081                 RF_WriteReg(dev, 0x04, 0x03f7);                 mdelay(1);
1082                 RF_WriteReg(dev, 0x05, 0x05ab);                 mdelay(1);
1083                 RF_WriteReg(dev, 0x06, 0x00c1);                 mdelay(1);
1084         }
1085         else
1086         {
1087                 RF_WriteReg(dev, 0x04, 0x03a7);                 mdelay(1);
1088                 RF_WriteReg(dev, 0x05, 0x059b);                 mdelay(1);
1089                 RF_WriteReg(dev, 0x06, 0x0081);                 mdelay(1);
1090         }
1091
1092
1093         RF_WriteReg(dev, 0x07, 0x01A0);                 mdelay(1);
1094 // Don't write RF23/RF24 to make a difference between 87S C cut and D cut. asked by SD3 stevenl.
1095 //      RF_WriteReg(dev, 0x08, 0x0597);                 mdelay(1);
1096 //      RF_WriteReg(dev, 0x09, 0x050a);                 mdelay(1);
1097         RF_WriteReg(dev, 0x0a, 0x0001);                 mdelay(1);
1098         RF_WriteReg(dev, 0x0b, 0x0418);                 mdelay(1);
1099
1100         if(priv->card_8185 == VERSION_8187S_D)
1101         {
1102                 RF_WriteReg(dev, 0x0c, 0x0fbe);                 mdelay(1);
1103                 RF_WriteReg(dev, 0x0d, 0x0008);                 mdelay(1);
1104                 RF_WriteReg(dev, 0x0e, 0x0807);                 mdelay(1); // RX LO buffer
1105         }
1106         else
1107         {
1108                 RF_WriteReg(dev, 0x0c, 0x0fbe);                 mdelay(1);
1109                 RF_WriteReg(dev, 0x0d, 0x0008);                 mdelay(1);
1110                 RF_WriteReg(dev, 0x0e, 0x0806);                 mdelay(1); // RX LO buffer
1111         }
1112
1113         RF_WriteReg(dev, 0x0f, 0x0acc);                 mdelay(1);
1114
1115 //      RF_WriteReg(dev, 0x00, 0x017f);                 mdelay(1);//6
1116         RF_WriteReg(dev, 0x00, 0x01d7);                 mdelay(1);// 6
1117
1118         RF_WriteReg(dev, 0x03, 0x0e00);                 mdelay(1);
1119         RF_WriteReg(dev, 0x04, 0x0e50);                 mdelay(1);
1120         for(i=0;i<=36;i++)
1121         {
1122                 RF_WriteReg(dev, 0x01, i);                     mdelay(1);
1123                 RF_WriteReg(dev, 0x02, ZEBRA_RF_RX_GAIN_TABLE[i]); mdelay(1);
1124                 //DbgPrint("RF - 0x%x = 0x%x", i, ZEBRA_RF_RX_GAIN_TABLE[i]);
1125         }
1126
1127         RF_WriteReg(dev, 0x05, 0x0203);                 mdelay(1);      /// 203, 343
1128         //RF_WriteReg(dev, 0x06, 0x0300);                       mdelay(1);      // 400
1129         RF_WriteReg(dev, 0x06, 0x0200);                 mdelay(1);      // 400
1130
1131         RF_WriteReg(dev, 0x00, 0x0137);                 mdelay(1);      // switch to reg16-reg30, and HSSI disable 137
1132         mdelay(10);     // Deay 10 ms. //0xfd
1133
1134 //      RF_WriteReg(dev, 0x0c, 0x09be);                 mdelay(1);      // 7
1135         //RF_WriteReg(dev, 0x0c, 0x07be);                       mdelay(1);
1136         //mdelay(10);   // Deay 10 ms. //0xfd
1137
1138         RF_WriteReg(dev, 0x0d, 0x0008);                 mdelay(1);      // Z4 synthesizer loop filter setting, 392
1139         mdelay(10);     // Deay 10 ms. //0xfd
1140
1141         RF_WriteReg(dev, 0x00, 0x0037);                 mdelay(1);      // switch to reg0-reg15, and HSSI disable
1142         mdelay(10);     // Deay 10 ms. //0xfd
1143
1144         RF_WriteReg(dev, 0x04, 0x0160);                 mdelay(1);      // CBC on, Tx Rx disable, High gain
1145         mdelay(10);     // Deay 10 ms. //0xfd
1146
1147         RF_WriteReg(dev, 0x07, 0x0080);                 mdelay(1);      // Z4 setted channel 1
1148         mdelay(10);     // Deay 10 ms. //0xfd
1149
1150         RF_WriteReg(dev, 0x02, 0x088D);                 mdelay(1);      // LC calibration
1151         mdelay(200);    // Deay 200 ms. //0xfd
1152         mdelay(10);     // Deay 10 ms. //0xfd
1153         mdelay(10);     // Deay 10 ms. //0xfd
1154
1155         RF_WriteReg(dev, 0x00, 0x0137);                 mdelay(1);      // switch to reg16-reg30 137, and HSSI disable 137
1156         mdelay(10);     // Deay 10 ms. //0xfd
1157
1158         RF_WriteReg(dev, 0x07, 0x0000);                 mdelay(1);
1159         RF_WriteReg(dev, 0x07, 0x0180);                 mdelay(1);
1160         RF_WriteReg(dev, 0x07, 0x0220);                 mdelay(1);
1161         RF_WriteReg(dev, 0x07, 0x03E0);                 mdelay(1);
1162
1163         // DAC calibration off 20070702
1164         RF_WriteReg(dev, 0x06, 0x00c1);                 mdelay(1);
1165         RF_WriteReg(dev, 0x0a, 0x0001);                 mdelay(1);
1166 //{by amy 080312
1167         // For crystal calibration, added by Roger, 2007.12.11.
1168         if( priv->bXtalCalibration ) // reg 30.
1169         { // enable crystal calibration.
1170                 // RF Reg[30], (1)Xin:[12:9], Xout:[8:5],  addr[4:0].
1171                 // (2)PA Pwr delay timer[15:14], default: 2.4us, set BIT15=0
1172                 // (3)RF signal on/off when calibration[13], default: on, set BIT13=0.
1173                 // So we should minus 4 BITs offset.
1174                 RF_WriteReg(dev, 0x0f, (priv->XtalCal_Xin<<5)|(priv->XtalCal_Xout<<1)|BIT11|BIT9);                      mdelay(1);
1175                 printk("ZEBRA_Config_85BASIC_HardCode(): (%02x)\n",
1176                                 (priv->XtalCal_Xin<<5) | (priv->XtalCal_Xout<<1) | BIT11| BIT9);
1177         }
1178         else
1179         { // using default value. Xin=6, Xout=6.
1180                 RF_WriteReg(dev, 0x0f, 0x0acc);                 mdelay(1);
1181         }
1182 //by amy 080312
1183 //      RF_WriteReg(dev, 0x0f, 0x0acc);                 mdelay(1);  //-by amy 080312
1184
1185         RF_WriteReg(dev, 0x00, 0x00bf);                 mdelay(1); // switch to reg0-reg15, and HSSI enable
1186 //      RF_WriteReg(dev, 0x0d, 0x009f);                 mdelay(1); // Rx BB start calibration, 00c//-edward
1187         RF_WriteReg(dev, 0x0d, 0x08df);                 mdelay(1); // Rx BB start calibration, 00c//+edward
1188         RF_WriteReg(dev, 0x02, 0x004d);                 mdelay(1); // temperature meter off
1189         RF_WriteReg(dev, 0x04, 0x0975);                 mdelay(1); // Rx mode
1190         mdelay(10);     // Deay 10 ms. //0xfe
1191         mdelay(10);     // Deay 10 ms. //0xfe
1192         mdelay(10);     // Deay 10 ms. //0xfe
1193         RF_WriteReg(dev, 0x00, 0x0197);                 mdelay(1); // Rx mode//+edward
1194         RF_WriteReg(dev, 0x05, 0x05ab);                 mdelay(1); // Rx mode//+edward
1195         RF_WriteReg(dev, 0x00, 0x009f);                 mdelay(1); // Rx mode//+edward
1196
1197         RF_WriteReg(dev, 0x01, 0x0000);                 mdelay(1); // Rx mode//+edward
1198         RF_WriteReg(dev, 0x02, 0x0000);                 mdelay(1); // Rx mode//+edward
1199         //power save parameters.
1200         u1b24E = read_nic_byte(dev, 0x24E);
1201         write_nic_byte(dev, 0x24E, (u1b24E & (~(BIT5|BIT6))));
1202
1203         //=============================================================================
1204
1205         //=============================================================================
1206         // CCKCONF.TXT
1207         //=============================================================================
1208
1209         /*      [POWER SAVE] Power Saving Parameters by jong. 2007-11-27
1210                 CCK reg0x00[7]=1'b1 :power saving for TX (default)
1211                 CCK reg0x00[6]=1'b1: power saving for RX (default)
1212                 CCK reg0x06[4]=1'b1: turn off channel estimation related circuits if not doing channel estimation.
1213                 CCK reg0x06[3]=1'b1: turn off unused circuits before cca = 1
1214                 CCK reg0x06[2]=1'b1: turn off cck's circuit if macrst =0
1215         */
1216
1217         write_phy_cck(dev,0x00,0xc8);
1218         write_phy_cck(dev,0x06,0x1c);
1219         write_phy_cck(dev,0x10,0x78);
1220         write_phy_cck(dev,0x2e,0xd0);
1221         write_phy_cck(dev,0x2f,0x06);
1222         write_phy_cck(dev,0x01,0x46);
1223
1224         // power control
1225         write_nic_byte(dev, CCK_TXAGC, 0x10);
1226         write_nic_byte(dev, OFDM_TXAGC, 0x1B);
1227         write_nic_byte(dev, ANTSEL, 0x03);
1228
1229
1230
1231         //=============================================================================
1232         // AGC.txt
1233         //=============================================================================
1234
1235 //      PlatformIOWrite4Byte( dev, PhyAddr, 0x00001280);        // Annie, 2006-05-05
1236         write_phy_ofdm(dev, 0x00, 0x12);
1237         //WriteBBPortUchar(dev, 0x00001280);
1238
1239         for (i=0; i<128; i++)
1240         {
1241                 //DbgPrint("AGC - [%x+1] = 0x%x\n", i, ZEBRA_AGC[i+1]);
1242
1243                 data = ZEBRA_AGC[i+1];
1244                 data = data << 8;
1245                 data = data | 0x0000008F;
1246
1247                 addr = i + 0x80; //enable writing AGC table
1248                 addr = addr << 8;
1249                 addr = addr | 0x0000008E;
1250
1251                 WriteBBPortUchar(dev, data);
1252                 WriteBBPortUchar(dev, addr);
1253                 WriteBBPortUchar(dev, 0x0000008E);
1254         }
1255
1256         PlatformIOWrite4Byte( dev, PhyAddr, 0x00001080);        // Annie, 2006-05-05
1257         //WriteBBPortUchar(dev, 0x00001080);
1258
1259         //=============================================================================
1260
1261         //=============================================================================
1262         // OFDMCONF.TXT
1263         //=============================================================================
1264
1265         for(i=0; i<60; i++)
1266         {
1267                 u4bRegOffset=i;
1268                 u4bRegValue=OFDM_CONFIG[i];
1269
1270                 //DbgPrint("OFDM - 0x%x = 0x%x\n", u4bRegOffset, u4bRegValue);
1271
1272                 WriteBBPortUchar(dev,
1273                                                 (0x00000080 |
1274                                                 (u4bRegOffset & 0x7f) |
1275                                                 ((u4bRegValue & 0xff) << 8)));
1276         }
1277
1278         //=============================================================================
1279 //by amy for antenna
1280         //=============================================================================
1281 //{by amy 080312
1282         // Config Sw/Hw  Combinational Antenna Diversity. Added by Roger, 2008.02.26.
1283         SetAntennaConfig87SE(dev, priv->bDefaultAntenna1, priv->bSwAntennaDiverity);
1284 //by amy 080312}
1285 //by amy for antenna
1286 }
1287
1288
1289 void
1290 UpdateInitialGain(
1291         struct net_device *dev
1292         )
1293 {
1294         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1295         //unsigned char* IGTable;
1296         //u8                    DIG_CurrentInitialGain = 4;
1297         //unsigned char u1Tmp;
1298
1299         //lzm add 080826
1300         if(priv->eRFPowerState != eRfOn)
1301         {
1302                 //Don't access BB/RF under disable PLL situation.
1303                 //RT_TRACE(COMP_DIG, DBG_LOUD, ("UpdateInitialGain - pHalData->eRFPowerState!=eRfOn\n"));
1304                 // Back to the original state
1305                 priv->InitialGain= priv->InitialGainBackUp;
1306                 return;
1307         }
1308
1309         switch(priv->rf_chip)
1310         {
1311         case RF_ZEBRA4:
1312                 // Dynamic set initial gain, follow 87B
1313                 switch(priv->InitialGain)
1314                 {
1315                         case 1: //m861dBm
1316                                 //DMESG("RTL8187 + 8225 Initial Gain State 1: -82 dBm \n");
1317                                 write_phy_ofdm(dev, 0x17, 0x26);        mdelay(1);
1318                                 write_phy_ofdm(dev, 0x24, 0x86);        mdelay(1);
1319                                 write_phy_ofdm(dev, 0x05, 0xfa);        mdelay(1);
1320                                 break;
1321
1322                         case 2: //m862dBm
1323                                 //DMESG("RTL8187 + 8225 Initial Gain State 2: -82 dBm \n");
1324                                 write_phy_ofdm(dev, 0x17, 0x36);        mdelay(1);
1325                                 write_phy_ofdm(dev, 0x24, 0x86);        mdelay(1);
1326                                 write_phy_ofdm(dev, 0x05, 0xfa);        mdelay(1);
1327                                 break;
1328
1329                         case 3: //m863dBm
1330                                 //DMESG("RTL8187 + 8225 Initial Gain State 3: -82 dBm \n");
1331                                 write_phy_ofdm(dev, 0x17, 0x36);        mdelay(1);
1332                                 write_phy_ofdm(dev, 0x24, 0x86);        mdelay(1);
1333                                 write_phy_ofdm(dev, 0x05, 0xfb);        mdelay(1);
1334                                 break;
1335
1336                         case 4: //m864dBm
1337                                 //DMESG("RTL8187 + 8225 Initial Gain State 4: -78 dBm \n");
1338                                 write_phy_ofdm(dev, 0x17, 0x46);        mdelay(1);
1339                                 write_phy_ofdm(dev, 0x24, 0x86);        mdelay(1);
1340                                 write_phy_ofdm(dev, 0x05, 0xfb);        mdelay(1);
1341                                 break;
1342
1343                         case 5: //m82dBm
1344                                 //DMESG("RTL8187 + 8225 Initial Gain State 5: -74 dBm \n");
1345                                 write_phy_ofdm(dev, 0x17, 0x46);        mdelay(1);
1346                                 write_phy_ofdm(dev, 0x24, 0x96);        mdelay(1);
1347                                 write_phy_ofdm(dev, 0x05, 0xfb);        mdelay(1);
1348                                 break;
1349
1350                         case 6: //m78dBm
1351                                 //DMESG ("RTL8187 + 8225 Initial Gain State 6: -70 dBm \n");
1352                                 write_phy_ofdm(dev, 0x17, 0x56);        mdelay(1);
1353                                 write_phy_ofdm(dev, 0x24, 0x96);        mdelay(1);
1354                                 write_phy_ofdm(dev, 0x05, 0xfc);        mdelay(1);
1355                                 break;
1356
1357                         case 7: //m74dBm
1358                                 //DMESG("RTL8187 + 8225 Initial Gain State 7: -66 dBm \n");
1359                                 write_phy_ofdm(dev, 0x17, 0x56);        mdelay(1);
1360                                 write_phy_ofdm(dev, 0x24, 0xa6);        mdelay(1);
1361                                 write_phy_ofdm(dev, 0x05, 0xfc);        mdelay(1);
1362                                 break;
1363
1364                         case 8:
1365                                 //DMESG("RTL8187 + 8225 Initial Gain State 8:\n");
1366                                 write_phy_ofdm(dev, 0x17, 0x66);        mdelay(1);
1367                                 write_phy_ofdm(dev, 0x24, 0xb6);        mdelay(1);
1368                                 write_phy_ofdm(dev, 0x05, 0xfc);        mdelay(1);
1369                                 break;
1370
1371
1372                         default:        //MP
1373                                 //DMESG("RTL8187 + 8225 Initial Gain State 1: -82 dBm (default)\n");
1374                                 write_phy_ofdm(dev, 0x17, 0x26);        mdelay(1);
1375                                 write_phy_ofdm(dev, 0x24, 0x86);        mdelay(1);
1376                                 write_phy_ofdm(dev, 0x05, 0xfa);        mdelay(1);
1377                                 break;
1378                 }
1379                 break;
1380
1381
1382         default:
1383                 DMESG("UpdateInitialGain(): unknown RFChipID: %#X\n", priv->rf_chip);
1384                 break;
1385         }
1386 }
1387 //
1388 //      Description:
1389 //              Tx Power tracking mechanism routine on 87SE.
1390 //      Created by Roger, 2007.12.11.
1391 //
1392 void
1393 InitTxPwrTracking87SE(
1394         struct net_device *dev
1395 )
1396 {
1397         //struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1398         u32     u4bRfReg;
1399
1400         u4bRfReg = RF_ReadReg(dev, 0x02);
1401
1402         // Enable Thermal meter indication.
1403         //printk("InitTxPwrTracking87SE(): Enable thermal meter indication, Write RF[0x02] = %#x", u4bRfReg|PWR_METER_EN);
1404         RF_WriteReg(dev, 0x02, u4bRfReg|PWR_METER_EN);                  mdelay(1);
1405 }
1406
1407 void
1408 PhyConfig8185(
1409         struct net_device *dev
1410         )
1411 {
1412         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1413        write_nic_dword(dev, RCR, priv->ReceiveConfig);
1414            priv->RFProgType = read_nic_byte(dev, CONFIG4) & 0x03;
1415         // RF config
1416         switch(priv->rf_chip)
1417         {
1418         case RF_ZEBRA2:
1419         case RF_ZEBRA4:
1420                 ZEBRA_Config_85BASIC_HardCode( dev);
1421                 break;
1422         }
1423 //{by amy 080312
1424         // Set default initial gain state to 4, approved by SD3 DZ, by Bruce, 2007-06-06.
1425         if(priv->bDigMechanism)
1426         {
1427                 if(priv->InitialGain == 0)
1428                         priv->InitialGain = 4;
1429                 //printk("PhyConfig8185(): DIG is enabled, set default initial gain index to %d\n", priv->InitialGain);
1430         }
1431
1432         //
1433         // Enable thermal meter indication to implement TxPower tracking on 87SE.
1434         // We initialize thermal meter here to avoid unsuccessful configuration.
1435         // Added by Roger, 2007.12.11.
1436         //
1437         if(priv->bTxPowerTrack)
1438                 InitTxPwrTracking87SE(dev);
1439
1440 //by amy 080312}
1441         priv->InitialGainBackUp= priv->InitialGain;
1442         UpdateInitialGain(dev);
1443
1444         return;
1445 }
1446
1447
1448
1449
1450 void
1451 HwConfigureRTL8185(
1452                 struct net_device *dev
1453                 )
1454 {
1455         //RTL8185_TODO: Determine Retrylimit, TxAGC, AutoRateFallback control.
1456 //      u8              bUNIVERSAL_CONTROL_RL = 1;
1457         u8              bUNIVERSAL_CONTROL_RL = 0;
1458
1459         u8              bUNIVERSAL_CONTROL_AGC = 1;
1460         u8              bUNIVERSAL_CONTROL_ANT = 1;
1461         u8              bAUTO_RATE_FALLBACK_CTL = 1;
1462         u8              val8;
1463         //struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1464         //struct ieee80211_device *ieee = priv->ieee80211;
1465         //if(IS_WIRELESS_MODE_A(dev) || IS_WIRELESS_MODE_G(dev))
1466 //{by amy 080312        if((ieee->mode == IEEE_G)||(ieee->mode == IEEE_A))
1467 //      {
1468 //              write_nic_word(dev, BRSR, 0xffff);
1469 //      }
1470 //      else
1471 //      {
1472 //              write_nic_word(dev, BRSR, 0x000f);
1473 //      }
1474 //by amy 080312}
1475         write_nic_word(dev, BRSR, 0x0fff);
1476         // Retry limit
1477         val8 = read_nic_byte(dev, CW_CONF);
1478
1479         if(bUNIVERSAL_CONTROL_RL)
1480                 val8 = val8 & 0xfd;
1481         else
1482                 val8 = val8 | 0x02;
1483
1484         write_nic_byte(dev, CW_CONF, val8);
1485
1486         // Tx AGC
1487         val8 = read_nic_byte(dev, TXAGC_CTL);
1488         if(bUNIVERSAL_CONTROL_AGC)
1489         {
1490                 write_nic_byte(dev, CCK_TXAGC, 128);
1491                 write_nic_byte(dev, OFDM_TXAGC, 128);
1492                 val8 = val8 & 0xfe;
1493         }
1494         else
1495         {
1496                 val8 = val8 | 0x01 ;
1497         }
1498
1499
1500         write_nic_byte(dev, TXAGC_CTL, val8);
1501
1502         // Tx Antenna including Feedback control
1503         val8 = read_nic_byte(dev, TXAGC_CTL );
1504
1505         if(bUNIVERSAL_CONTROL_ANT)
1506         {
1507                 write_nic_byte(dev, ANTSEL, 0x00);
1508                 val8 = val8 & 0xfd;
1509         }
1510         else
1511         {
1512                 val8 = val8 & (val8|0x02); //xiong-2006-11-15
1513         }
1514
1515         write_nic_byte(dev, TXAGC_CTL, val8);
1516
1517         // Auto Rate fallback control
1518         val8 = read_nic_byte(dev, RATE_FALLBACK);
1519         val8 &= 0x7c;
1520         if( bAUTO_RATE_FALLBACK_CTL )
1521         {
1522                 val8 |= RATE_FALLBACK_CTL_ENABLE | RATE_FALLBACK_CTL_AUTO_STEP1;
1523
1524                 // <RJ_TODO_8185B> We shall set up the ARFR according to user's setting.
1525                 //write_nic_word(dev, ARFR, 0x0fff); // set 1M ~ 54M
1526 //by amy
1527                 // Aadded by Roger, 2007.11.15.
1528                 PlatformIOWrite2Byte(dev, ARFR, 0x0fff); //set 1M ~ 54Mbps.
1529 //by amy
1530         }
1531         else
1532         {
1533         }
1534         write_nic_byte(dev, RATE_FALLBACK, val8);
1535 }
1536
1537
1538
1539 static void
1540 MacConfig_85BASIC_HardCode(
1541         struct net_device *dev)
1542 {
1543         //============================================================================
1544         // MACREG.TXT
1545         //============================================================================
1546         int                     nLinesRead = 0;
1547
1548         u32     u4bRegOffset, u4bRegValue,u4bPageIndex = 0;
1549         int     i;
1550
1551         nLinesRead=sizeof(MAC_REG_TABLE)/2;
1552
1553         for(i = 0; i < nLinesRead; i++)  //nLinesRead=101
1554         {
1555                 u4bRegOffset=MAC_REG_TABLE[i][0];
1556                 u4bRegValue=MAC_REG_TABLE[i][1];
1557
1558                 if(u4bRegOffset == 0x5e)
1559                 {
1560                     u4bPageIndex = u4bRegValue;
1561                 }
1562                 else
1563                 {
1564                     u4bRegOffset |= (u4bPageIndex << 8);
1565                 }
1566                 //DbgPrint("MAC - 0x%x = 0x%x\n", u4bRegOffset, u4bRegValue);
1567                 write_nic_byte(dev, u4bRegOffset, (u8)u4bRegValue);
1568         }
1569         //============================================================================
1570 }
1571
1572
1573
1574 static void
1575 MacConfig_85BASIC(
1576         struct net_device *dev)
1577 {
1578
1579        u8                       u1DA;
1580         MacConfig_85BASIC_HardCode(dev);
1581
1582         //============================================================================
1583
1584         // Follow TID_AC_MAP of WMac.
1585         write_nic_word(dev, TID_AC_MAP, 0xfa50);
1586
1587         // Interrupt Migration, Jong suggested we use set 0x0000 first, 2005.12.14, by rcnjko.
1588         write_nic_word(dev, IntMig, 0x0000);
1589
1590         // Prevent TPC to cause CRC error. Added by Annie, 2006-06-10.
1591         PlatformIOWrite4Byte(dev, 0x1F0, 0x00000000);
1592         PlatformIOWrite4Byte(dev, 0x1F4, 0x00000000);
1593         PlatformIOWrite1Byte(dev, 0x1F8, 0x00);
1594
1595         // Asked for by SD3 CM Lin, 2006.06.27, by rcnjko.
1596         //PlatformIOWrite4Byte(dev, RFTiming, 0x00004001);
1597 //by amy
1598         // power save parameter based on "87SE power save parameters 20071127.doc", as follow.
1599
1600         //Enable DA10 TX power saving
1601         u1DA = read_nic_byte(dev, PHYPR);
1602         write_nic_byte(dev, PHYPR, (u1DA | BIT2) );
1603
1604         //POWER:
1605         write_nic_word(dev, 0x360, 0x1000);
1606         write_nic_word(dev, 0x362, 0x1000);
1607
1608         // AFE.
1609         write_nic_word(dev, 0x370, 0x0560);
1610         write_nic_word(dev, 0x372, 0x0560);
1611         write_nic_word(dev, 0x374, 0x0DA4);
1612         write_nic_word(dev, 0x376, 0x0DA4);
1613         write_nic_word(dev, 0x378, 0x0560);
1614         write_nic_word(dev, 0x37A, 0x0560);
1615         write_nic_word(dev, 0x37C, 0x00EC);
1616 //      write_nic_word(dev, 0x37E, 0x00FE);//-edward
1617         write_nic_word(dev, 0x37E, 0x00EC);//+edward
1618        write_nic_byte(dev, 0x24E,0x01);
1619 //by amy
1620
1621 }
1622
1623
1624
1625
1626 u8
1627 GetSupportedWirelessMode8185(
1628         struct net_device *dev
1629 )
1630 {
1631         u8                      btSupportedWirelessMode = 0;
1632         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1633
1634         switch(priv->rf_chip)
1635         {
1636         case RF_ZEBRA2:
1637         case RF_ZEBRA4:
1638                 btSupportedWirelessMode = (WIRELESS_MODE_B | WIRELESS_MODE_G);
1639                 break;
1640         default:
1641                 btSupportedWirelessMode = WIRELESS_MODE_B;
1642                 break;
1643         }
1644
1645         return btSupportedWirelessMode;
1646 }
1647
1648 void
1649 ActUpdateChannelAccessSetting(
1650         struct net_device *dev,
1651         WIRELESS_MODE                   WirelessMode,
1652         PCHANNEL_ACCESS_SETTING ChnlAccessSetting
1653         )
1654 {
1655         struct r8180_priv *priv = ieee80211_priv(dev);
1656         struct ieee80211_device *ieee = priv->ieee80211;
1657         AC_CODING       eACI;
1658         AC_PARAM        AcParam;
1659         //PSTA_QOS      pStaQos = Adapter->MgntInfo.pStaQos;
1660         u8      bFollowLegacySetting = 0;
1661         u8   u1bAIFS;
1662
1663         //
1664         // <RJ_TODO_8185B>
1665         // TODO: We still don't know how to set up these registers, just follow WMAC to
1666         // verify 8185B FPAG.
1667         //
1668         // <RJ_TODO_8185B>
1669         // Jong said CWmin/CWmax register are not functional in 8185B,
1670         // so we shall fill channel access realted register into AC parameter registers,
1671         // even in nQBss.
1672         //
1673         ChnlAccessSetting->SIFS_Timer = 0x22; // Suggested by Jong, 2005.12.08.
1674         ChnlAccessSetting->DIFS_Timer = 0x1C; // 2006.06.02, by rcnjko.
1675         ChnlAccessSetting->SlotTimeTimer = 9; // 2006.06.02, by rcnjko.
1676         ChnlAccessSetting->EIFS_Timer = 0x5B; // Suggested by wcchu, it is the default value of EIFS register, 2005.12.08.
1677         ChnlAccessSetting->CWminIndex = 3; // 2006.06.02, by rcnjko.
1678         ChnlAccessSetting->CWmaxIndex = 7; // 2006.06.02, by rcnjko.
1679
1680         write_nic_byte(dev, SIFS, ChnlAccessSetting->SIFS_Timer);
1681         //Adapter->HalFunc.SetHwRegHandler( Adapter, HW_VAR_SLOT_TIME, &ChnlAccessSetting->SlotTimeTimer );     // Rewrited from directly use PlatformEFIOWrite1Byte(), by Annie, 2006-03-29.
1682         write_nic_byte(dev, SLOT, ChnlAccessSetting->SlotTimeTimer);    // Rewrited from directly use PlatformEFIOWrite1Byte(), by Annie, 2006-03-29.
1683
1684         u1bAIFS = aSifsTime + (2 * ChnlAccessSetting->SlotTimeTimer );
1685
1686         //write_nic_byte(dev, AC_VO_PARAM, u1bAIFS);
1687         //write_nic_byte(dev, AC_VI_PARAM, u1bAIFS);
1688         //write_nic_byte(dev, AC_BE_PARAM, u1bAIFS);
1689         //write_nic_byte(dev, AC_BK_PARAM, u1bAIFS);
1690
1691         write_nic_byte(dev, EIFS, ChnlAccessSetting->EIFS_Timer);
1692
1693         write_nic_byte(dev, AckTimeOutReg, 0x5B); // <RJ_EXPR_QOS> Suggested by wcchu, it is the default value of EIFS register, 2005.12.08.
1694
1695 #ifdef TODO
1696         // <RJ_TODO_NOW_8185B> Update ECWmin/ECWmax, AIFS, TXOP Limit of each AC to the value defined by SPEC.
1697         if( pStaQos->CurrentQosMode > QOS_DISABLE )
1698         { // QoS mode.
1699                 if(pStaQos->QBssWirelessMode == WirelessMode)
1700                 {
1701                         // Follow AC Parameters of the QBSS.
1702                         for(eACI = 0; eACI < AC_MAX; eACI++)
1703                         {
1704                                 Adapter->HalFunc.SetHwRegHandler(Adapter, HW_VAR_AC_PARAM, (pu1Byte)(&(pStaQos->WMMParamEle.AcParam[eACI])) );
1705                         }
1706                 }
1707                 else
1708                 {
1709                         // Follow Default WMM AC Parameters.
1710                         bFollowLegacySetting = 1;
1711                 }
1712         }
1713         else
1714 #endif
1715         { // Legacy 802.11.
1716                 bFollowLegacySetting = 1;
1717
1718         }
1719
1720         // this setting is copied from rtl8187B.  xiong-2006-11-13
1721         if(bFollowLegacySetting)
1722         {
1723
1724
1725                 //
1726                 // Follow 802.11 seeting to AC parameter, all AC shall use the same parameter.
1727                 // 2005.12.01, by rcnjko.
1728                 //
1729                 AcParam.longData = 0;
1730                 AcParam.f.AciAifsn.f.AIFSN = 2; // Follow 802.11 DIFS.
1731                 AcParam.f.AciAifsn.f.ACM = 0;
1732                 AcParam.f.Ecw.f.ECWmin = ChnlAccessSetting->CWminIndex; // Follow 802.11 CWmin.
1733                 AcParam.f.Ecw.f.ECWmax = ChnlAccessSetting->CWmaxIndex; // Follow 802.11 CWmax.
1734                 AcParam.f.TXOPLimit = 0;
1735
1736                 //lzm reserved 080826
1737 #if 1
1738                 // For turbo mode setting. port from 87B by Isaiah 2008-08-01
1739                 if( ieee->current_network.Turbo_Enable == 1 )
1740                         AcParam.f.TXOPLimit = 0x01FF;
1741                 // For 87SE with Intel 4965  Ad-Hoc mode have poor throughput (19MB)
1742                 if (ieee->iw_mode == IW_MODE_ADHOC)
1743                         AcParam.f.TXOPLimit = 0x0020;
1744 #endif
1745
1746                 for(eACI = 0; eACI < AC_MAX; eACI++)
1747                 {
1748                         AcParam.f.AciAifsn.f.ACI = (u8)eACI;
1749                         {
1750                                 PAC_PARAM       pAcParam = (PAC_PARAM)(&AcParam);
1751                                 AC_CODING       eACI;
1752                                 u8              u1bAIFS;
1753                                 u32             u4bAcParam;
1754
1755                                 // Retrive paramters to udpate.
1756                                 eACI = pAcParam->f.AciAifsn.f.ACI;
1757                                 u1bAIFS = pAcParam->f.AciAifsn.f.AIFSN * ChnlAccessSetting->SlotTimeTimer + aSifsTime;
1758                                 u4bAcParam = (  (((u32)(pAcParam->f.TXOPLimit)) << AC_PARAM_TXOP_LIMIT_OFFSET)  |
1759                                                 (((u32)(pAcParam->f.Ecw.f.ECWmax)) << AC_PARAM_ECW_MAX_OFFSET)  |
1760                                                 (((u32)(pAcParam->f.Ecw.f.ECWmin)) << AC_PARAM_ECW_MIN_OFFSET)  |
1761                                                 (((u32)u1bAIFS) << AC_PARAM_AIFS_OFFSET));
1762
1763                                 switch(eACI)
1764                                 {
1765                                         case AC1_BK:
1766                                                 //write_nic_dword(dev, AC_BK_PARAM, u4bAcParam);
1767                                                 break;
1768
1769                                         case AC0_BE:
1770                                                 //write_nic_dword(dev, AC_BE_PARAM, u4bAcParam);
1771                                                 break;
1772
1773                                         case AC2_VI:
1774                                                 //write_nic_dword(dev, AC_VI_PARAM, u4bAcParam);
1775                                                 break;
1776
1777                                         case AC3_VO:
1778                                                 //write_nic_dword(dev, AC_VO_PARAM, u4bAcParam);
1779                                                 break;
1780
1781                                         default:
1782                                                 DMESGW( "SetHwReg8185(): invalid ACI: %d !\n", eACI);
1783                                                 break;
1784                                 }
1785
1786                                 // Cehck ACM bit.
1787                                 // If it is set, immediately set ACM control bit to downgrading AC for passing WMM testplan. Annie, 2005-12-13.
1788                                 //write_nic_byte(dev, ACM_CONTROL, pAcParam->f.AciAifsn);
1789                                 {
1790                                         PACI_AIFSN      pAciAifsn = (PACI_AIFSN)(&pAcParam->f.AciAifsn);
1791                                         AC_CODING       eACI = pAciAifsn->f.ACI;
1792
1793                                         //modified Joseph
1794                                         //for 8187B AsynIORead issue
1795 #ifdef TODO
1796                                         u8      AcmCtrl = pHalData->AcmControl;
1797 #else
1798                                         u8      AcmCtrl = 0;
1799 #endif
1800                                         if( pAciAifsn->f.ACM )
1801                                         { // ACM bit is 1.
1802                                                 switch(eACI)
1803                                                 {
1804                                                         case AC0_BE:
1805                                                                 AcmCtrl |= (BEQ_ACM_EN|BEQ_ACM_CTL|ACM_HW_EN);  // or 0x21
1806                                                                 break;
1807
1808                                                         case AC2_VI:
1809                                                                 AcmCtrl |= (VIQ_ACM_EN|VIQ_ACM_CTL|ACM_HW_EN);  // or 0x42
1810                                                                 break;
1811
1812                                                         case AC3_VO:
1813                                                                 AcmCtrl |= (VOQ_ACM_EN|VOQ_ACM_CTL|ACM_HW_EN);  // or 0x84
1814                                                                 break;
1815
1816                                                         default:
1817                                                                 DMESGW("SetHwReg8185(): [HW_VAR_ACM_CTRL] ACM set failed: eACI is %d\n", eACI );
1818                                                                 break;
1819                                                 }
1820                                         }
1821                                         else
1822                                         { // ACM bit is 0.
1823                                                 switch(eACI)
1824                                                 {
1825                                                         case AC0_BE:
1826                                                                 AcmCtrl &= ( (~BEQ_ACM_EN) & (~BEQ_ACM_CTL) & (~ACM_HW_EN) );   // and 0xDE
1827                                                                 break;
1828
1829                                                         case AC2_VI:
1830                                                                 AcmCtrl &= ( (~VIQ_ACM_EN) & (~VIQ_ACM_CTL) & (~ACM_HW_EN) );   // and 0xBD
1831                                                                 break;
1832
1833                                                         case AC3_VO:
1834                                                                 AcmCtrl &= ( (~VOQ_ACM_EN) & (~VOQ_ACM_CTL) & (~ACM_HW_EN) );   // and 0x7B
1835                                                                 break;
1836
1837                                                         default:
1838                                                                 break;
1839                                                 }
1840                                         }
1841
1842                                         //printk(KERN_WARNING "SetHwReg8185(): [HW_VAR_ACM_CTRL] Write 0x%X\n", AcmCtrl);
1843
1844 #ifdef TO_DO
1845                                         pHalData->AcmControl = AcmCtrl;
1846 #endif
1847                                         //write_nic_byte(dev, ACM_CONTROL, AcmCtrl);
1848                                         write_nic_byte(dev, ACM_CONTROL, 0);
1849                                 }
1850                         }
1851                 }
1852
1853
1854         }
1855 }
1856
1857 void
1858 ActSetWirelessMode8185(
1859         struct net_device *dev,
1860         u8                              btWirelessMode
1861         )
1862 {
1863         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1864         struct ieee80211_device *ieee = priv->ieee80211;
1865         //PMGNT_INFO            pMgntInfo = &(Adapter->MgntInfo);
1866         u8      btSupportedWirelessMode = GetSupportedWirelessMode8185(dev);
1867
1868         if( (btWirelessMode & btSupportedWirelessMode) == 0 )
1869         { // Don't switch to unsupported wireless mode, 2006.02.15, by rcnjko.
1870                 DMESGW("ActSetWirelessMode8185(): WirelessMode(%d) is not supported (%d)!\n",
1871                         btWirelessMode, btSupportedWirelessMode);
1872                 return;
1873         }
1874
1875         // 1. Assign wireless mode to swtich if necessary.
1876         if (btWirelessMode == WIRELESS_MODE_AUTO)
1877         {
1878                 if((btSupportedWirelessMode & WIRELESS_MODE_A))
1879                 {
1880                         btWirelessMode = WIRELESS_MODE_A;
1881                 }
1882                 else if((btSupportedWirelessMode & WIRELESS_MODE_G))
1883                 {
1884                         btWirelessMode = WIRELESS_MODE_G;
1885                 }
1886                 else if((btSupportedWirelessMode & WIRELESS_MODE_B))
1887                 {
1888                         btWirelessMode = WIRELESS_MODE_B;
1889                 }
1890                 else
1891                 {
1892                         DMESGW("ActSetWirelessMode8185(): No valid wireless mode supported, btSupportedWirelessMode(%x)!!!\n",
1893                                          btSupportedWirelessMode);
1894                         btWirelessMode = WIRELESS_MODE_B;
1895                 }
1896         }
1897
1898
1899         // 2. Swtich band: RF or BB specific actions,
1900         // for example, refresh tables in omc8255, or change initial gain if necessary.
1901         switch(priv->rf_chip)
1902         {
1903         case RF_ZEBRA2:
1904         case RF_ZEBRA4:
1905                 {
1906                         // Nothing to do for Zebra to switch band.
1907                         // Update current wireless mode if we swtich to specified band successfully.
1908                         ieee->mode = (WIRELESS_MODE)btWirelessMode;
1909                 }
1910                 break;
1911
1912         default:
1913                 DMESGW("ActSetWirelessMode8185(): unsupported RF: 0x%X !!!\n", priv->rf_chip);
1914                 break;
1915         }
1916
1917         // 3. Change related setting.
1918         if( ieee->mode == WIRELESS_MODE_A ){
1919                 DMESG("WIRELESS_MODE_A\n");
1920         }
1921         else if( ieee->mode == WIRELESS_MODE_B ){
1922                 DMESG("WIRELESS_MODE_B\n");
1923         }
1924         else if( ieee->mode == WIRELESS_MODE_G ){
1925                 DMESG("WIRELESS_MODE_G\n");
1926         }
1927
1928         ActUpdateChannelAccessSetting( dev, ieee->mode, &priv->ChannelAccessSetting);
1929 }
1930
1931 void rtl8185b_irq_enable(struct net_device *dev)
1932 {
1933         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1934
1935         priv->irq_enabled = 1;
1936         write_nic_dword(dev, IMR, priv->IntrMask);
1937 }
1938 //by amy for power save
1939 void
1940 DrvIFIndicateDisassociation(
1941         struct net_device *dev,
1942         u16                     reason
1943         )
1944 {
1945         //printk("==> DrvIFIndicateDisassociation()\n");
1946
1947         // nothing is needed after disassociation request.
1948
1949         //printk("<== DrvIFIndicateDisassociation()\n");
1950 }
1951 void
1952 MgntDisconnectIBSS(
1953         struct net_device *dev
1954 )
1955 {
1956         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1957         u8                      i;
1958
1959         //printk("XXXXXXXXXX MgntDisconnect IBSS\n");
1960
1961         DrvIFIndicateDisassociation(dev, unspec_reason);
1962
1963 //      PlatformZeroMemory( pMgntInfo->Bssid, 6 );
1964         for(i=0;i<6;i++)  priv->ieee80211->current_network.bssid[i] = 0x55;
1965
1966         priv->ieee80211->state = IEEE80211_NOLINK;
1967
1968         //Stop Beacon.
1969
1970         // Vista add a Adhoc profile, HW radio off untill OID_DOT11_RESET_REQUEST
1971         // Driver would set MSR=NO_LINK, then HW Radio ON, MgntQueue Stuck.
1972         // Because Bcn DMA isn't complete, mgnt queue would stuck until Bcn packet send.
1973
1974         // Disable Beacon Queue Own bit, suggested by jong
1975 //      Adapter->HalFunc.SetTxDescOWNHandler(Adapter, BEACON_QUEUE, 0, 0);
1976         ieee80211_stop_send_beacons(priv->ieee80211);
1977
1978         priv->ieee80211->link_change(dev);
1979         notify_wx_assoc_event(priv->ieee80211);
1980
1981         // Stop SW Beacon.Use hw beacon so do not need to do so.by amy
1982
1983 //              MgntIndicateMediaStatus( Adapter, RT_MEDIA_DISCONNECT, GENERAL_INDICATE );
1984
1985 }
1986 void
1987 MlmeDisassociateRequest(
1988         struct net_device *dev,
1989         u8*                     asSta,
1990         u8                      asRsn
1991         )
1992 {
1993         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1994         u8 i;
1995
1996         SendDisassociation(priv->ieee80211, asSta, asRsn );
1997
1998         if( memcmp(priv->ieee80211->current_network.bssid, asSta, 6 ) == 0 ){
1999                 //ShuChen TODO: change media status.
2000                 //ShuChen TODO: What to do when disassociate.
2001                 DrvIFIndicateDisassociation(dev, unspec_reason);
2002
2003
2004         //      pMgntInfo->AsocTimestamp = 0;
2005                 for(i=0;i<6;i++)  priv->ieee80211->current_network.bssid[i] = 0x22;
2006 //              pMgntInfo->mBrates.Length = 0;
2007 //              Adapter->HalFunc.SetHwRegHandler( Adapter, HW_VAR_BASIC_RATE, (pu1Byte)(&pMgntInfo->mBrates) );
2008
2009                 ieee80211_disassociate(priv->ieee80211);
2010
2011
2012         }
2013
2014 }
2015
2016 void
2017 MgntDisconnectAP(
2018         struct net_device *dev,
2019         u8                      asRsn
2020 )
2021 {
2022         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
2023
2024 //
2025 // Commented out by rcnjko, 2005.01.27:
2026 // I move SecClearAllKeys() to MgntActSet_802_11_DISASSOCIATE().
2027 //
2028 //      //2004/09/15, kcwu, the key should be cleared, or the new handshaking will not success
2029 //      SecClearAllKeys(Adapter);
2030
2031         // In WPA WPA2 need to Clear all key ... because new key will set after new handshaking.
2032 #ifdef TODO
2033         if(   pMgntInfo->SecurityInfo.AuthMode > RT_802_11AuthModeAutoSwitch ||
2034                 (pMgntInfo->bAPSuportCCKM && pMgntInfo->bCCX8021xenable) )  // In CCKM mode will Clear key
2035         {
2036                 SecClearAllKeys(Adapter);
2037                 RT_TRACE(COMP_SEC, DBG_LOUD,("======>CCKM clear key..."))
2038         }
2039 #endif
2040         // 2004.10.11, by rcnjko.
2041         //MlmeDisassociateRequest( Adapter, pMgntInfo->Bssid, disas_lv_ss );
2042         MlmeDisassociateRequest( dev, priv->ieee80211->current_network.bssid, asRsn );
2043
2044         priv->ieee80211->state = IEEE80211_NOLINK;
2045 //      pMgntInfo->AsocTimestamp = 0;
2046 }
2047 bool
2048 MgntDisconnect(
2049         struct net_device *dev,
2050         u8                      asRsn
2051 )
2052 {
2053         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
2054         //
2055         // Schedule an workitem to wake up for ps mode, 070109, by rcnjko.
2056         //
2057 #ifdef TODO
2058         if(pMgntInfo->mPss != eAwake)
2059         {
2060                 //
2061                 // Using AwkaeTimer to prevent mismatch ps state.
2062                 // In the timer the state will be changed according to the RF is being awoke or not. By Bruce, 2007-10-31.
2063                 //
2064                 // PlatformScheduleWorkItem( &(pMgntInfo->AwakeWorkItem) );
2065                 PlatformSetTimer( Adapter, &(pMgntInfo->AwakeTimer), 0 );
2066         }
2067 #endif
2068
2069         // Indication of disassociation event.
2070         //DrvIFIndicateDisassociation(Adapter, asRsn);
2071         if(IS_DOT11D_ENABLE(priv->ieee80211))
2072                 Dot11d_Reset(priv->ieee80211);
2073         // In adhoc mode, update beacon frame.
2074         if( priv->ieee80211->state == IEEE80211_LINKED )
2075         {
2076                 if( priv->ieee80211->iw_mode == IW_MODE_ADHOC )
2077                 {
2078 //                      RT_TRACE(COMP_MLME, DBG_LOUD, ("MgntDisconnect() ===> MgntDisconnectIBSS\n"));
2079                         //printk("MgntDisconnect() ===> MgntDisconnectIBSS\n");
2080                         MgntDisconnectIBSS(dev);
2081                 }
2082                 if( priv->ieee80211->iw_mode == IW_MODE_INFRA )
2083                 {
2084                         // We clear key here instead of MgntDisconnectAP() because that
2085                         // MgntActSet_802_11_DISASSOCIATE() is an interface called by OS,
2086                         // e.g. OID_802_11_DISASSOCIATE in Windows while as MgntDisconnectAP() is
2087                         // used to handle disassociation related things to AP, e.g. send Disassoc
2088                         // frame to AP.  2005.01.27, by rcnjko.
2089 //                      SecClearAllKeys(Adapter);
2090
2091 //                      RT_TRACE(COMP_MLME, DBG_LOUD, ("MgntDisconnect() ===> MgntDisconnectAP\n"));
2092                         //printk("MgntDisconnect() ===> MgntDisconnectAP\n");
2093                         MgntDisconnectAP(dev, asRsn);
2094                 }
2095
2096                 // Inidicate Disconnect, 2005.02.23, by rcnjko.
2097 //              MgntIndicateMediaStatus( Adapter, RT_MEDIA_DISCONNECT, GENERAL_INDICATE);
2098         }
2099
2100         return true;
2101 }
2102 //
2103 //      Description:
2104 //              Chang RF Power State.
2105 //              Note that, only MgntActSet_RF_State() is allowed to set HW_VAR_RF_STATE.
2106 //
2107 //      Assumption:
2108 //              PASSIVE LEVEL.
2109 //
2110 bool
2111 SetRFPowerState(
2112         struct net_device *dev,
2113         RT_RF_POWER_STATE       eRFPowerState
2114         )
2115 {
2116         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
2117         bool                    bResult = false;
2118
2119 //      printk("---------> SetRFPowerState(): eRFPowerState(%d)\n", eRFPowerState);
2120         if(eRFPowerState == priv->eRFPowerState)
2121         {
2122 //              printk("<--------- SetRFPowerState(): discard the request for eRFPowerState(%d) is the same.\n", eRFPowerState);
2123                 return bResult;
2124         }
2125
2126         switch(priv->rf_chip)
2127         {
2128                 case RF_ZEBRA2:
2129                 case RF_ZEBRA4:
2130                          bResult = SetZebraRFPowerState8185(dev, eRFPowerState);
2131                         break;
2132
2133                 default:
2134                         printk("SetRFPowerState8185(): unknown RFChipID: 0x%X!!!\n", priv->rf_chip);
2135                         break;;
2136 }
2137 //      printk("<--------- SetRFPowerState(): bResult(%d)\n", bResult);
2138
2139         return bResult;
2140 }
2141 void
2142 HalEnableRx8185Dummy(
2143         struct net_device *dev
2144         )
2145 {
2146 }
2147 void
2148 HalDisableRx8185Dummy(
2149         struct net_device *dev
2150         )
2151 {
2152 }
2153
2154 bool
2155 MgntActSet_RF_State(
2156         struct net_device *dev,
2157         RT_RF_POWER_STATE       StateToSet,
2158         u32     ChangeSource
2159         )
2160 {
2161         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
2162         bool                            bActionAllowed = false;
2163         bool                            bConnectBySSID = false;
2164         RT_RF_POWER_STATE       rtState;
2165         u16                             RFWaitCounter = 0;
2166         unsigned long flag;
2167 //       printk("===>MgntActSet_RF_State(): StateToSet(%d), ChangeSource(0x%x)\n",StateToSet, ChangeSource);
2168         //
2169         // Prevent the race condition of RF state change. By Bruce, 2007-11-28.
2170         // Only one thread can change the RF state at one time, and others should wait to be executed.
2171         //
2172 #if 1
2173         while(true)
2174         {
2175 //              down(&priv->rf_state);
2176                 spin_lock_irqsave(&priv->rf_ps_lock,flag);
2177                 if(priv->RFChangeInProgress)
2178                 {
2179 //                      printk("====================>haha111111111\n");
2180 //                      up(&priv->rf_state);
2181 //                      RT_TRACE(COMP_RF, DBG_LOUD, ("MgntActSet_RF_State(): RF Change in progress! Wait to set..StateToSet(%d).\n", StateToSet));
2182                         spin_unlock_irqrestore(&priv->rf_ps_lock,flag);
2183                         // Set RF after the previous action is done.
2184                         while(priv->RFChangeInProgress)
2185                         {
2186                                 RFWaitCounter ++;
2187 //                              RT_TRACE(COMP_RF, DBG_LOUD, ("MgntActSet_RF_State(): Wait 1 ms (%d times)...\n", RFWaitCounter));
2188                                 udelay(1000); // 1 ms
2189
2190                                 // Wait too long, return FALSE to avoid to be stuck here.
2191                                 if(RFWaitCounter > 1000) // 1sec
2192                                 {
2193 //                                      RT_ASSERT(FALSE, ("MgntActSet_RF_State(): Wait too logn to set RF\n"));
2194                                         printk("MgntActSet_RF_State(): Wait too long to set RF\n");
2195                                         // TODO: Reset RF state?
2196                                         return false;
2197                                 }
2198                         }
2199                 }
2200                 else
2201                 {
2202 //                      printk("========================>haha2\n");
2203                         priv->RFChangeInProgress = true;
2204 //                      up(&priv->rf_state);
2205                         spin_unlock_irqrestore(&priv->rf_ps_lock,flag);
2206                         break;
2207                 }
2208         }
2209 #endif
2210         rtState = priv->eRFPowerState;
2211
2212
2213         switch(StateToSet)
2214         {
2215         case eRfOn:
2216                 //
2217                 // Turn On RF no matter the IPS setting because we need to update the RF state to Ndis under Vista, or
2218                 // the Windows does not allow the driver to perform site survey any more. By Bruce, 2007-10-02.
2219                 //
2220                 priv->RfOffReason &= (~ChangeSource);
2221
2222                 if(! priv->RfOffReason)
2223                 {
2224                         priv->RfOffReason = 0;
2225                         bActionAllowed = true;
2226
2227                         if(rtState == eRfOff && ChangeSource >=RF_CHANGE_BY_HW && !priv->bInHctTest)
2228                         {
2229                                 bConnectBySSID = true;
2230                         }
2231                 }
2232                 else
2233 //                      RT_TRACE(COMP_RF, DBG_LOUD, ("MgntActSet_RF_State - eRfon reject pMgntInfo->RfOffReason= 0x%x, ChangeSource=0x%X\n", pMgntInfo->RfOffReason, ChangeSource));
2234                         ;
2235                 break;
2236
2237         case eRfOff:
2238                  // 070125, rcnjko: we always keep connected in AP mode.
2239
2240                         if (priv->RfOffReason > RF_CHANGE_BY_IPS)
2241                         {
2242                                 //
2243                                 // 060808, Annie:
2244                                 // Disconnect to current BSS when radio off. Asked by QuanTa.
2245                                 //
2246
2247                                 //
2248                                 // Calling MgntDisconnect() instead of MgntActSet_802_11_DISASSOCIATE(),
2249                                 // because we do NOT need to set ssid to dummy ones.
2250                                 // Revised by Roger, 2007.12.04.
2251                                 //
2252                                 MgntDisconnect( dev, disas_lv_ss );
2253
2254                                 // Clear content of bssDesc[] and bssDesc4Query[] to avoid reporting old bss to UI.
2255                                 // 2007.05.28, by shien chang.
2256 //                              PlatformZeroMemory( pMgntInfo->bssDesc, sizeof(RT_WLAN_BSS)*MAX_BSS_DESC );
2257 //                              pMgntInfo->NumBssDesc = 0;
2258 //                              PlatformZeroMemory( pMgntInfo->bssDesc4Query, sizeof(RT_WLAN_BSS)*MAX_BSS_DESC );
2259 //                              pMgntInfo->NumBssDesc4Query = 0;
2260                         }
2261
2262
2263
2264                 priv->RfOffReason |= ChangeSource;
2265                 bActionAllowed = true;
2266                 break;
2267
2268         case eRfSleep:
2269                 priv->RfOffReason |= ChangeSource;
2270                 bActionAllowed = true;
2271                 break;
2272
2273         default:
2274                 break;
2275         }
2276
2277         if(bActionAllowed)
2278         {
2279 //              RT_TRACE(COMP_RF, DBG_LOUD, ("MgntActSet_RF_State(): Action is allowed.... StateToSet(%d), RfOffReason(%#X)\n", StateToSet, pMgntInfo->RfOffReason));
2280                 // Config HW to the specified mode.
2281 //              printk("MgntActSet_RF_State(): Action is allowed.... StateToSet(%d), RfOffReason(%#X)\n", StateToSet, priv->RfOffReason);
2282                 SetRFPowerState(dev, StateToSet);
2283
2284                 // Turn on RF.
2285                 if(StateToSet == eRfOn)
2286                 {
2287                         HalEnableRx8185Dummy(dev);
2288                         if(bConnectBySSID)
2289                         {
2290                         // by amy not supported
2291 //                              MgntActSet_802_11_SSID(Adapter, Adapter->MgntInfo.Ssid.Octet, Adapter->MgntInfo.Ssid.Length, TRUE );
2292                         }
2293                 }
2294                 // Turn off RF.
2295                 else if(StateToSet == eRfOff)
2296                 {
2297                         HalDisableRx8185Dummy(dev);
2298                 }
2299         }
2300         else
2301         {
2302         //      printk("MgntActSet_RF_State(): Action is rejected.... StateToSet(%d), ChangeSource(%#X), RfOffReason(%#X)\n", StateToSet, ChangeSource, priv->RfOffReason);
2303         }
2304
2305         // Release RF spinlock
2306 //      down(&priv->rf_state);
2307         spin_lock_irqsave(&priv->rf_ps_lock,flag);
2308         priv->RFChangeInProgress = false;
2309 //      up(&priv->rf_state);
2310         spin_unlock_irqrestore(&priv->rf_ps_lock,flag);
2311 //      printk("<===MgntActSet_RF_State()\n");
2312         return bActionAllowed;
2313 }
2314 void
2315 InactivePowerSave(
2316         struct net_device *dev
2317         )
2318 {
2319         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
2320         //u8 index = 0;
2321
2322         //
2323         // This flag "bSwRfProcessing", indicates the status of IPS procedure, should be set if the IPS workitem
2324         // is really scheduled.
2325         // The old code, sets this flag before scheduling the IPS workitem and however, at the same time the
2326         // previous IPS workitem did not end yet, fails to schedule the current workitem. Thus, bSwRfProcessing
2327         // blocks the IPS procedure of switching RF.
2328         // By Bruce, 2007-12-25.
2329         //
2330         priv->bSwRfProcessing = true;
2331
2332         MgntActSet_RF_State(dev, priv->eInactivePowerState, RF_CHANGE_BY_IPS);
2333
2334         //
2335         // To solve CAM values miss in RF OFF, rewrite CAM values after RF ON. By Bruce, 2007-09-20.
2336         //
2337
2338         priv->bSwRfProcessing = false;
2339 }
2340
2341 //
2342 //      Description:
2343 //              Enter the inactive power save mode. RF will be off
2344 //      2007.08.17, by shien chang.
2345 //
2346 void
2347 IPSEnter(
2348         struct net_device *dev
2349         )
2350 {
2351         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
2352         RT_RF_POWER_STATE rtState;
2353         //printk("==============================>enter IPS\n");
2354         if (priv->bInactivePs)
2355         {
2356                 rtState = priv->eRFPowerState;
2357
2358                 //
2359                 // Added by Bruce, 2007-12-25.
2360                 // Do not enter IPS in the following conditions:
2361                 // (1) RF is already OFF or Sleep
2362                 // (2) bSwRfProcessing (indicates the IPS is still under going)
2363                 // (3) Connectted (only disconnected can trigger IPS)
2364                 // (4) IBSS (send Beacon)
2365                 // (5) AP mode (send Beacon)
2366                 //
2367                 if (rtState == eRfOn && !priv->bSwRfProcessing
2368                         && (priv->ieee80211->state != IEEE80211_LINKED ))
2369                 {
2370         //              printk("IPSEnter(): Turn off RF.\n");
2371                         priv->eInactivePowerState = eRfOff;
2372                         InactivePowerSave(dev);
2373                 }
2374         }
2375 //      printk("priv->eRFPowerState is %d\n",priv->eRFPowerState);
2376 }
2377 void
2378 IPSLeave(
2379         struct net_device *dev
2380         )
2381 {
2382         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
2383         RT_RF_POWER_STATE rtState;
2384         //printk("===================================>leave IPS\n");
2385         if (priv->bInactivePs)
2386         {
2387                 rtState = priv->eRFPowerState;
2388                 if ((rtState == eRfOff || rtState == eRfSleep) && (!priv->bSwRfProcessing) && priv->RfOffReason <= RF_CHANGE_BY_IPS)
2389                 {
2390 //                      printk("IPSLeave(): Turn on RF.\n");
2391                         priv->eInactivePowerState = eRfOn;
2392                         InactivePowerSave(dev);
2393                 }
2394         }
2395 //      printk("priv->eRFPowerState is %d\n",priv->eRFPowerState);
2396 }
2397 //by amy for power save
2398 void rtl8185b_adapter_start(struct net_device *dev)
2399 {
2400       struct r8180_priv *priv = ieee80211_priv(dev);
2401         struct ieee80211_device *ieee = priv->ieee80211;
2402
2403         u8 SupportedWirelessMode;
2404         u8                      InitWirelessMode;
2405         u8                      bInvalidWirelessMode = 0;
2406         //int i;
2407         u8 tmpu8;
2408         //u8 u1tmp,u2tmp;
2409         u8 btCR9346;
2410         u8 TmpU1b;
2411         u8 btPSR;
2412
2413         //rtl8180_rtx_disable(dev);
2414 //{by amy 080312
2415         write_nic_byte(dev,0x24e, (BIT5|BIT6|BIT0));
2416 //by amy 080312}
2417         rtl8180_reset(dev);
2418
2419         priv->dma_poll_mask = 0;
2420         priv->dma_poll_stop_mask = 0;
2421
2422         //rtl8180_beacon_tx_disable(dev);
2423
2424         HwConfigureRTL8185(dev);
2425
2426         write_nic_dword(dev, MAC0, ((u32*)dev->dev_addr)[0]);
2427         write_nic_word(dev, MAC4, ((u32*)dev->dev_addr)[1] & 0xffff );
2428
2429         write_nic_byte(dev, MSR, read_nic_byte(dev, MSR) & 0xf3);       // default network type to 'No  Link'
2430
2431         //write_nic_byte(dev, BRSR, 0x0);               // Set BRSR= 1M
2432
2433         write_nic_word(dev, BcnItv, 100);
2434         write_nic_word(dev, AtimWnd, 2);
2435
2436         //PlatformEFIOWrite2Byte(dev, FEMR, 0xFFFF);
2437         PlatformIOWrite2Byte(dev, FEMR, 0xFFFF);
2438
2439         write_nic_byte(dev, WPA_CONFIG, 0);
2440
2441         MacConfig_85BASIC(dev);
2442
2443         // Override the RFSW_CTRL (MAC offset 0x272-0x273), 2006.06.07, by rcnjko.
2444         // BT_DEMO_BOARD type
2445         PlatformIOWrite2Byte(dev, RFSW_CTRL, 0x569a);
2446 //by amy
2447 //#ifdef CONFIG_RTL818X_S
2448                 // for jong required
2449 //      PlatformIOWrite2Byte(dev, RFSW_CTRL, 0x9a56);
2450 //#endif
2451 //by amy
2452         //BT_QA_BOARD
2453         //PlatformIOWrite2Byte(dev, RFSW_CTRL, 0x9a56);
2454
2455         //-----------------------------------------------------------------------------
2456         // Set up PHY related.
2457         //-----------------------------------------------------------------------------
2458         // Enable Config3.PARAM_En to revise AnaaParm.
2459         write_nic_byte(dev, CR9346, 0xc0);      // enable config register write
2460 //by amy
2461         tmpu8 = read_nic_byte(dev, CONFIG3);
2462         write_nic_byte(dev, CONFIG3, (tmpu8 |CONFIG3_PARM_En) );
2463 //by amy
2464         // Turn on Analog power.
2465         // Asked for by William, otherwise, MAC 3-wire can't work, 2006.06.27, by rcnjko.
2466         write_nic_dword(dev, ANAPARAM2, ANAPARM2_ASIC_ON);
2467         write_nic_dword(dev, ANAPARAM, ANAPARM_ASIC_ON);
2468 //by amy
2469         write_nic_word(dev, ANAPARAM3, 0x0010);
2470 //by amy
2471
2472         write_nic_byte(dev, CONFIG3, tmpu8);
2473         write_nic_byte(dev, CR9346, 0x00);
2474 //{by amy 080312 for led
2475         // enable EEM0 and EEM1 in 9346CR
2476         btCR9346 = read_nic_byte(dev, CR9346);
2477         write_nic_byte(dev, CR9346, (btCR9346|0xC0) );
2478
2479         // B cut use LED1 to control HW RF on/off
2480         TmpU1b = read_nic_byte(dev, CONFIG5);
2481         TmpU1b = TmpU1b & ~BIT3;
2482         write_nic_byte(dev,CONFIG5, TmpU1b);
2483
2484         // disable EEM0 and EEM1 in 9346CR
2485         btCR9346 &= ~(0xC0);
2486         write_nic_byte(dev, CR9346, btCR9346);
2487
2488         //Enable Led (suggested by Jong)
2489         // B-cut RF Radio on/off  5e[3]=0
2490         btPSR = read_nic_byte(dev, PSR);
2491         write_nic_byte(dev, PSR, (btPSR | BIT3));
2492 //by amy 080312 for led}
2493         // setup initial timing for RFE.
2494         write_nic_word(dev, RFPinsOutput, 0x0480);
2495         SetOutputEnableOfRfPins(dev);
2496         write_nic_word(dev, RFPinsSelect, 0x2488);
2497
2498         // PHY config.
2499         PhyConfig8185(dev);
2500
2501         // We assume RegWirelessMode has already been initialized before,
2502         // however, we has to validate the wireless mode here and provide a reasonble
2503         // initialized value if necessary. 2005.01.13, by rcnjko.
2504         SupportedWirelessMode = GetSupportedWirelessMode8185(dev);
2505         if(     (ieee->mode != WIRELESS_MODE_B) &&
2506                 (ieee->mode != WIRELESS_MODE_G) &&
2507                 (ieee->mode != WIRELESS_MODE_A) &&
2508                 (ieee->mode != WIRELESS_MODE_AUTO))
2509         { // It should be one of B, G, A, or AUTO.
2510                 bInvalidWirelessMode = 1;
2511         }
2512         else
2513         { // One of B, G, A, or AUTO.
2514                 // Check if the wireless mode is supported by RF.
2515                 if( (ieee->mode != WIRELESS_MODE_AUTO) &&
2516                         (ieee->mode & SupportedWirelessMode) == 0 )
2517                 {
2518                         bInvalidWirelessMode = 1;
2519                 }
2520         }
2521
2522         if(bInvalidWirelessMode || ieee->mode==WIRELESS_MODE_AUTO)
2523         { // Auto or other invalid value.
2524                 // Assigne a wireless mode to initialize.
2525                 if((SupportedWirelessMode & WIRELESS_MODE_A))
2526                 {
2527                         InitWirelessMode = WIRELESS_MODE_A;
2528                 }
2529                 else if((SupportedWirelessMode & WIRELESS_MODE_G))
2530                 {
2531                         InitWirelessMode = WIRELESS_MODE_G;
2532                 }
2533                 else if((SupportedWirelessMode & WIRELESS_MODE_B))
2534                 {
2535                         InitWirelessMode = WIRELESS_MODE_B;
2536                 }
2537                 else
2538                 {
2539                         DMESGW("InitializeAdapter8185(): No valid wireless mode supported, SupportedWirelessMode(%x)!!!\n",
2540                                  SupportedWirelessMode);
2541                         InitWirelessMode = WIRELESS_MODE_B;
2542                 }
2543
2544                 // Initialize RegWirelessMode if it is not a valid one.
2545                 if(bInvalidWirelessMode)
2546                 {
2547                         ieee->mode = (WIRELESS_MODE)InitWirelessMode;
2548                 }
2549         }
2550         else
2551         { // One of B, G, A.
2552                 InitWirelessMode = ieee->mode;
2553         }
2554 //by amy for power save
2555 #ifdef ENABLE_IPS
2556 //      printk("initialize ENABLE_IPS\n");
2557         priv->eRFPowerState = eRfOff;
2558         priv->RfOffReason = 0;
2559         {
2560         //      u32 tmp2;
2561         //      u32 tmp = jiffies;
2562                 MgntActSet_RF_State(dev, eRfOn, 0);
2563         //      tmp2 = jiffies;
2564         //      printk("rf on cost jiffies:%lx\n", (tmp2-tmp)*1000/HZ);
2565         }
2566 //      DrvIFIndicateCurrentPhyStatus(priv);
2567                 //
2568                 // If inactive power mode is enabled, disable rf while in disconnected state.
2569                 // 2007.07.16, by shien chang.
2570                 //
2571         if (priv->bInactivePs)
2572         {
2573         //      u32 tmp2;
2574         //      u32 tmp = jiffies;
2575                 MgntActSet_RF_State(dev,eRfOff, RF_CHANGE_BY_IPS);
2576         //      tmp2 = jiffies;
2577         //      printk("rf off cost jiffies:%lx\n", (tmp2-tmp)*1000/HZ);
2578
2579         }
2580 #endif
2581 //      IPSEnter(dev);
2582 //by amy for power save
2583 #ifdef TODO
2584         // Turn off RF if necessary. 2005.08.23, by rcnjko.
2585         // We shall turn off RF after setting CMDR, otherwise,
2586         // RF will be turnned on after we enable MAC Tx/Rx.
2587         if(Adapter->MgntInfo.RegRfOff == TRUE)
2588         {
2589                 SetRFPowerState8185(Adapter, RF_OFF);
2590         }
2591         else
2592         {
2593                 SetRFPowerState8185(Adapter, RF_ON);
2594         }
2595 #endif
2596
2597 /*   //these is equal with above TODO.
2598         write_nic_byte(dev, CR9346, 0xc0);      // enable config register write
2599         write_nic_byte(dev, CONFIG3, read_nic_byte(dev, CONFIG3) | CONFIG3_PARM_En);
2600         RF_WriteReg(dev, 0x4, 0x9FF);
2601         write_nic_dword(dev, ANAPARAM2, ANAPARM2_ASIC_ON);
2602         write_nic_dword(dev, ANAPARAM, ANAPARM_ASIC_ON);
2603         write_nic_byte(dev, CONFIG3, (read_nic_byte(dev, CONFIG3)&(~CONFIG3_PARM_En)));
2604         write_nic_byte(dev, CR9346, 0x00);
2605 */
2606
2607         ActSetWirelessMode8185(dev, (u8)(InitWirelessMode));
2608
2609         //-----------------------------------------------------------------------------
2610
2611         rtl8185b_irq_enable(dev);
2612
2613         netif_start_queue(dev);
2614
2615  }
2616
2617
2618 void rtl8185b_rx_enable(struct net_device *dev)
2619 {
2620         u8 cmd;
2621         //u32 rxconf;
2622         /* for now we accept data, management & ctl frame*/
2623         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
2624
2625         if (dev->flags & IFF_PROMISC) DMESG ("NIC in promisc mode");
2626
2627         if(priv->ieee80211->iw_mode == IW_MODE_MONITOR || \
2628            dev->flags & IFF_PROMISC){
2629                 priv->ReceiveConfig = priv->ReceiveConfig & (~RCR_APM);
2630                 priv->ReceiveConfig = priv->ReceiveConfig | RCR_AAP;
2631         }
2632
2633         /*if(priv->ieee80211->iw_mode == IW_MODE_MASTER){
2634                 rxconf = rxconf | (1<<ACCEPT_ALLMAC_FRAME_SHIFT);
2635                 rxconf = rxconf | (1<<RX_CHECK_BSSID_SHIFT);
2636         }*/
2637
2638         if(priv->ieee80211->iw_mode == IW_MODE_MONITOR){
2639                 priv->ReceiveConfig = priv->ReceiveConfig | RCR_ACF | RCR_APWRMGT | RCR_AICV;
2640         }
2641
2642         if( priv->crcmon == 1 && priv->ieee80211->iw_mode == IW_MODE_MONITOR)
2643                 priv->ReceiveConfig = priv->ReceiveConfig | RCR_ACRC32;
2644
2645         write_nic_dword(dev, RCR, priv->ReceiveConfig);
2646
2647         fix_rx_fifo(dev);
2648
2649 #ifdef DEBUG_RX
2650         DMESG("rxconf: %x %x",priv->ReceiveConfig ,read_nic_dword(dev,RCR));
2651 #endif
2652         cmd=read_nic_byte(dev,CMD);
2653         write_nic_byte(dev,CMD,cmd | (1<<CMD_RX_ENABLE_SHIFT));
2654
2655 }
2656
2657 void rtl8185b_tx_enable(struct net_device *dev)
2658 {
2659         u8 cmd;
2660         //u8 tx_agc_ctl;
2661         u8 byte;
2662         //u32 txconf;
2663         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
2664
2665         write_nic_dword(dev, TCR, priv->TransmitConfig);
2666         byte = read_nic_byte(dev, MSR);
2667         byte |= MSR_LINK_ENEDCA;
2668         write_nic_byte(dev, MSR, byte);
2669
2670         fix_tx_fifo(dev);
2671
2672 #ifdef DEBUG_TX
2673         DMESG("txconf: %x %x",priv->TransmitConfig,read_nic_dword(dev,TCR));
2674 #endif
2675
2676         cmd=read_nic_byte(dev,CMD);
2677         write_nic_byte(dev,CMD,cmd | (1<<CMD_TX_ENABLE_SHIFT));
2678
2679         //write_nic_dword(dev,TX_CONF,txconf);
2680
2681
2682 /*
2683         rtl8180_set_mode(dev,EPROM_CMD_CONFIG);
2684         write_nic_byte(dev, TX_DMA_POLLING, priv->dma_poll_mask);
2685         rtl8180_set_mode(dev,EPROM_CMD_NORMAL);
2686         */
2687 }
2688
2689