SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/net/sfc/nic.c

   1 /****************************************************************************
   2  * Driver for Solarflare Solarstorm network controllers and boards
   3  * Copyright 2005-2006 Fen Systems Ltd.
   4  * Copyright 2006-2009 Solarflare Communications Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License version 2 as published
   8  * by the Free Software Foundation, incorporated herein by reference.
   9  */
  10
  11 #include <linux/bitops.h>
  12 #include <linux/delay.h>
  13 #include <linux/pci.h>
  14 #include <linux/module.h>
  15 #include <linux/seq_file.h>
  16 #include "net_driver.h"
  17 #include "bitfield.h"
  18 #include "efx.h"
  19 #include "nic.h"
  20 #include "regs.h"
  21 #include "io.h"
  22 #include "workarounds.h"
  23
  24 /**************************************************************************
  25  *
  26  * Configurable values
  27  *
  28  **************************************************************************
  29  */
  30
  31 /* This is set to 16 for a good reason.  In summary, if larger than
  32  * 16, the descriptor cache holds more than a default socket
  33  * buffer's worth of packets (for UDP we can only have at most one
  34  * socket buffer's worth outstanding).  This combined with the fact
  35  * that we only get 1 TX event per descriptor cache means the NIC
  36  * goes idle.
  37  */
  38 #define TX_DC_ENTRIES 16
  39 #define TX_DC_ENTRIES_ORDER 1
  40
  41 #define RX_DC_ENTRIES 64
  42 #define RX_DC_ENTRIES_ORDER 3
  43
  44 /* RX FIFO XOFF watermark
  45  *
  46  * When the amount of the RX FIFO increases used increases past this
  47  * watermark send XOFF. Only used if RX flow control is enabled (ethtool -A)
  48  * This also has an effect on RX/TX arbitration
  49  */
  50 int efx_nic_rx_xoff_thresh = -1;
  51 module_param_named(rx_xoff_thresh_bytes, efx_nic_rx_xoff_thresh, int, 0644);
  52 MODULE_PARM_DESC(rx_xoff_thresh_bytes, "RX fifo XOFF threshold");
  53
  54 /* RX FIFO XON watermark
  55  *
  56  * When the amount of the RX FIFO used decreases below this
  57  * watermark send XON. Only used if TX flow control is enabled (ethtool -A)
  58  * This also has an effect on RX/TX arbitration
  59  */
  60 int efx_nic_rx_xon_thresh = -1;
  61 module_param_named(rx_xon_thresh_bytes, efx_nic_rx_xon_thresh, int, 0644);
  62 MODULE_PARM_DESC(rx_xon_thresh_bytes, "RX fifo XON threshold");
  63
  64 /* If EFX_MAX_INT_ERRORS internal errors occur within
  65  * EFX_INT_ERROR_EXPIRE seconds, we consider the NIC broken and
  66  * disable it.
  67  */
  68 #define EFX_INT_ERROR_EXPIRE 3600
  69 #define EFX_MAX_INT_ERRORS 5
  70
  71 /* We poll for events every FLUSH_INTERVAL ms, and check FLUSH_POLL_COUNT times
  72  */
  73 #define EFX_FLUSH_INTERVAL 10
  74 #define EFX_FLUSH_POLL_COUNT 100
  75
  76 /* Size and alignment of special buffers (4KB) */
  77 #define EFX_BUF_SIZE 4096
  78
  79 /* Depth of RX flush request fifo */
  80 #define EFX_RX_FLUSH_COUNT 4
  81
  82 /**************************************************************************
  83  *
  84  * Solarstorm hardware access
  85  *
  86  **************************************************************************/
  87
  88 static inline void efx_write_buf_tbl(struct efx_nic *efx, efx_qword_t *value,
  89                                      unsigned int index)
  90 {
  91         efx_sram_writeq(efx, efx->membase + efx->type->buf_tbl_base,
  92                         value, index);
  93 }
  94
  95 /* Read the current event from the event queue */
  96 static inline efx_qword_t *efx_event(struct efx_channel *channel,
  97                                      unsigned int index)
  98 {
  99         return (((efx_qword_t *) (channel->eventq.addr)) + index);
 100 }
 101
 102 /* See if an event is present
 103  *
 104  * We check both the high and low dword of the event for all ones.  We
 105  * wrote all ones when we cleared the event, and no valid event can
 106  * have all ones in either its high or low dwords.  This approach is
 107  * robust against reordering.
 108  *
 109  * Note that using a single 64-bit comparison is incorrect; even
 110  * though the CPU read will be atomic, the DMA write may not be.
 111  */
 112 static inline int efx_event_present(efx_qword_t *event)
 113 {
 114         return (!(EFX_DWORD_IS_ALL_ONES(event->dword[0]) |
 115                   EFX_DWORD_IS_ALL_ONES(event->dword[1])));
 116 }
 117
 118 static bool efx_masked_compare_oword(const efx_oword_t *a, const efx_oword_t *b,
 119                                      const efx_oword_t *mask)
 120 {
 121         return ((a->u64[0] ^ b->u64[0]) & mask->u64[0]) ||
 122                 ((a->u64[1] ^ b->u64[1]) & mask->u64[1]);
 123 }
 124
 125 int efx_nic_test_registers(struct efx_nic *efx,
 126                            const struct efx_nic_register_test *regs,
 127                            size_t n_regs)
 128 {
 129         unsigned address = 0, i, j;
 130         efx_oword_t mask, imask, original, reg, buf;
 131
 132         /* Falcon should be in loopback to isolate the XMAC from the PHY */
 133         WARN_ON(!LOOPBACK_INTERNAL(efx));
 134
 135         for (i = 0; i < n_regs; ++i) {
 136                 address = regs[i].address;
 137                 mask = imask = regs[i].mask;
 138                 EFX_INVERT_OWORD(imask);
 139
 140                 efx_reado(efx, &original, address);
 141
 142                 /* bit sweep on and off */
 143                 for (j = 0; j < 128; j++) {
 144                         if (!EFX_EXTRACT_OWORD32(mask, j, j))
 145                                 continue;
 146
 147                         /* Test this testable bit can be set in isolation */
 148                         EFX_AND_OWORD(reg, original, mask);
 149                         EFX_SET_OWORD32(reg, j, j, 1);
 150
 151                         efx_writeo(efx, &reg, address);
 152                         efx_reado(efx, &buf, address);
 153
 154                         if (efx_masked_compare_oword(&reg, &buf, &mask))
 155                                 goto fail;
 156
 157                         /* Test this testable bit can be cleared in isolation */
 158                         EFX_OR_OWORD(reg, original, mask);
 159                         EFX_SET_OWORD32(reg, j, j, 0);
 160
 161                         efx_writeo(efx, &reg, address);
 162                         efx_reado(efx, &buf, address);
 163
 164                         if (efx_masked_compare_oword(&reg, &buf, &mask))
 165                                 goto fail;
 166                 }
 167
 168                 efx_writeo(efx, &original, address);
 169         }
 170
 171         return 0;
 172
 173 fail:
 174         EFX_ERR(efx, "wrote "EFX_OWORD_FMT" read "EFX_OWORD_FMT
 175                 " at address 0x%x mask "EFX_OWORD_FMT"\n", EFX_OWORD_VAL(reg),
 176                 EFX_OWORD_VAL(buf), address, EFX_OWORD_VAL(mask));
 177         return -EIO;
 178 }
 179
 180 /**************************************************************************
 181  *
 182  * Special buffer handling
 183  * Special buffers are used for event queues and the TX and RX
 184  * descriptor rings.
 185  *
 186  *************************************************************************/
 187
 188 /*
 189  * Initialise a special buffer
 190  *
 191  * This will define a buffer (previously allocated via
 192  * efx_alloc_special_buffer()) in the buffer table, allowing
 193  * it to be used for event queues, descriptor rings etc.
 194  */
 195 static void
 196 efx_init_special_buffer(struct efx_nic *efx, struct efx_special_buffer *buffer)
 197 {
 198         efx_qword_t buf_desc;
 199         int index;
 200         dma_addr_t dma_addr;
 201         int i;
 202
 203         EFX_BUG_ON_PARANOID(!buffer->addr);
 204
 205         /* Write buffer descriptors to NIC */
 206         for (i = 0; i < buffer->entries; i++) {
 207                 index = buffer->index + i;
 208                 dma_addr = buffer->dma_addr + (i * 4096);
 209                 EFX_LOG(efx, "mapping special buffer %d at %llx\n",
 210                         index, (unsigned long long)dma_addr);
 211                 EFX_POPULATE_QWORD_3(buf_desc,
 212                                      FRF_AZ_BUF_ADR_REGION, 0,
 213                                      FRF_AZ_BUF_ADR_FBUF, dma_addr >> 12,
 214                                      FRF_AZ_BUF_OWNER_ID_FBUF, 0);
 215                 efx_write_buf_tbl(efx, &buf_desc, index);
 216         }
 217 }
 218
 219 /* Unmaps a buffer and clears the buffer table entries */
 220 static void
 221 efx_fini_special_buffer(struct efx_nic *efx, struct efx_special_buffer *buffer)
 222 {
 223         efx_oword_t buf_tbl_upd;
 224         unsigned int start = buffer->index;
 225         unsigned int end = (buffer->index + buffer->entries - 1);
 226
 227         if (!buffer->entries)
 228                 return;
 229
 230         EFX_LOG(efx, "unmapping special buffers %d-%d\n",
 231                 buffer->index, buffer->index + buffer->entries - 1);
 232
 233         EFX_POPULATE_OWORD_4(buf_tbl_upd,
 234                              FRF_AZ_BUF_UPD_CMD, 0,
 235                              FRF_AZ_BUF_CLR_CMD, 1,
 236                              FRF_AZ_BUF_CLR_END_ID, end,
 237                              FRF_AZ_BUF_CLR_START_ID, start);
 238         efx_writeo(efx, &buf_tbl_upd, FR_AZ_BUF_TBL_UPD);
 239 }
 240
 241 /*
 242  * Allocate a new special buffer
 243  *
 244  * This allocates memory for a new buffer, clears it and allocates a
 245  * new buffer ID range.  It does not write into the buffer table.
 246  *
 247  * This call will allocate 4KB buffers, since 8KB buffers can't be
 248  * used for event queues and descriptor rings.
 249  */
 250 static int efx_alloc_special_buffer(struct efx_nic *efx,
 251                                     struct efx_special_buffer *buffer,
 252                                     unsigned int len)
 253 {
 254         len = ALIGN(len, EFX_BUF_SIZE);
 255
 256         buffer->addr = pci_alloc_consistent(efx->pci_dev, len,
 257                                             &buffer->dma_addr);
 258         if (!buffer->addr)
 259                 return -ENOMEM;
 260         buffer->len = len;
 261         buffer->entries = len / EFX_BUF_SIZE;
 262         BUG_ON(buffer->dma_addr & (EFX_BUF_SIZE - 1));
 263
 264         /* All zeros is a potentially valid event so memset to 0xff */
 265         memset(buffer->addr, 0xff, len);
 266
 267         /* Select new buffer ID */
 268         buffer->index = efx->next_buffer_table;
 269         efx->next_buffer_table += buffer->entries;
 270
 271         EFX_LOG(efx, "allocating special buffers %d-%d at %llx+%x "
 272                 "(virt %p phys %llx)\n", buffer->index,
 273                 buffer->index + buffer->entries - 1,
 274                 (u64)buffer->dma_addr, len,
 275                 buffer->addr, (u64)virt_to_phys(buffer->addr));
 276
 277         return 0;
 278 }
 279
 280 static void
 281 efx_free_special_buffer(struct efx_nic *efx, struct efx_special_buffer *buffer)
 282 {
 283         if (!buffer->addr)
 284                 return;
 285
 286         EFX_LOG(efx, "deallocating special buffers %d-%d at %llx+%x "
 287                 "(virt %p phys %llx)\n", buffer->index,
 288                 buffer->index + buffer->entries - 1,
 289                 (u64)buffer->dma_addr, buffer->len,
 290                 buffer->addr, (u64)virt_to_phys(buffer->addr));
 291
 292         pci_free_consistent(efx->pci_dev, buffer->len, buffer->addr,
 293                             buffer->dma_addr);
 294         buffer->addr = NULL;
 295         buffer->entries = 0;
 296 }
 297
 298 /**************************************************************************
 299  *
 300  * Generic buffer handling
 301  * These buffers are used for interrupt status and MAC stats
 302  *
 303  **************************************************************************/
 304
 305 int efx_nic_alloc_buffer(struct efx_nic *efx, struct efx_buffer *buffer,
 306                          unsigned int len)
 307 {
 308         buffer->addr = pci_alloc_consistent(efx->pci_dev, len,
 309                                             &buffer->dma_addr);
 310         if (!buffer->addr)
 311                 return -ENOMEM;
 312         buffer->len = len;
 313         memset(buffer->addr, 0, len);
 314         return 0;
 315 }
 316
 317 void efx_nic_free_buffer(struct efx_nic *efx, struct efx_buffer *buffer)
 318 {
 319         if (buffer->addr) {
 320                 pci_free_consistent(efx->pci_dev, buffer->len,
 321                                     buffer->addr, buffer->dma_addr);
 322                 buffer->addr = NULL;
 323         }
 324 }
 325
 326 /**************************************************************************
 327  *
 328  * TX path
 329  *
 330  **************************************************************************/
 331
 332 /* Returns a pointer to the specified transmit descriptor in the TX
 333  * descriptor queue belonging to the specified channel.
 334  */
 335 static inline efx_qword_t *
 336 efx_tx_desc(struct efx_tx_queue *tx_queue, unsigned int index)
 337 {
 338         return (((efx_qword_t *) (tx_queue->txd.addr)) + index);
 339 }
 340
 341 /* This writes to the TX_DESC_WPTR; write pointer for TX descriptor ring */
 342 static inline void efx_notify_tx_desc(struct efx_tx_queue *tx_queue)
 343 {
 344         unsigned write_ptr;
 345         efx_dword_t reg;
 346
 347         write_ptr = tx_queue->write_count & EFX_TXQ_MASK;
 348         EFX_POPULATE_DWORD_1(reg, FRF_AZ_TX_DESC_WPTR_DWORD, write_ptr);
 349         efx_writed_page(tx_queue->efx, &reg,
 350                         FR_AZ_TX_DESC_UPD_DWORD_P0, tx_queue->queue);
 351 }
 352
 353
 354 /* For each entry inserted into the software descriptor ring, create a
 355  * descriptor in the hardware TX descriptor ring (in host memory), and
 356  * write a doorbell.
 357  */
 358 void efx_nic_push_buffers(struct efx_tx_queue *tx_queue)
 359 {
 360
 361         struct efx_tx_buffer *buffer;
 362         efx_qword_t *txd;
 363         unsigned write_ptr;
 364
 365         BUG_ON(tx_queue->write_count == tx_queue->insert_count);
 366
 367         do {
 368                 write_ptr = tx_queue->write_count & EFX_TXQ_MASK;
 369                 buffer = &tx_queue->buffer[write_ptr];
 370                 txd = efx_tx_desc(tx_queue, write_ptr);
 371                 ++tx_queue->write_count;
 372
 373                 /* Create TX descriptor ring entry */
 374                 EFX_POPULATE_QWORD_4(*txd,
 375                                      FSF_AZ_TX_KER_CONT, buffer->continuation,
 376                                      FSF_AZ_TX_KER_BYTE_COUNT, buffer->len,
 377                                      FSF_AZ_TX_KER_BUF_REGION, 0,
 378                                      FSF_AZ_TX_KER_BUF_ADDR, buffer->dma_addr);
 379         } while (tx_queue->write_count != tx_queue->insert_count);
 380
 381         wmb(); /* Ensure descriptors are written before they are fetched */
 382         efx_notify_tx_desc(tx_queue);
 383 }
 384
 385 /* Allocate hardware resources for a TX queue */
 386 int efx_nic_probe_tx(struct efx_tx_queue *tx_queue)
 387 {
 388         struct efx_nic *efx = tx_queue->efx;
 389         BUILD_BUG_ON(EFX_TXQ_SIZE < 512 || EFX_TXQ_SIZE > 4096 ||
 390                      EFX_TXQ_SIZE & EFX_TXQ_MASK);
 391         return efx_alloc_special_buffer(efx, &tx_queue->txd,
 392                                         EFX_TXQ_SIZE * sizeof(efx_qword_t));
 393 }
 394
 395 void efx_nic_init_tx(struct efx_tx_queue *tx_queue)
 396 {
 397         efx_oword_t tx_desc_ptr;
 398         struct efx_nic *efx = tx_queue->efx;
 399
 400         tx_queue->flushed = FLUSH_NONE;
 401
 402         /* Pin TX descriptor ring */
 403         efx_init_special_buffer(efx, &tx_queue->txd);
 404
 405         /* Push TX descriptor ring to card */
 406         EFX_POPULATE_OWORD_10(tx_desc_ptr,
 407                               FRF_AZ_TX_DESCQ_EN, 1,
 408                               FRF_AZ_TX_ISCSI_DDIG_EN, 0,
 409                               FRF_AZ_TX_ISCSI_HDIG_EN, 0,
 410                               FRF_AZ_TX_DESCQ_BUF_BASE_ID, tx_queue->txd.index,
 411                               FRF_AZ_TX_DESCQ_EVQ_ID,
 412                               tx_queue->channel->channel,
 413                               FRF_AZ_TX_DESCQ_OWNER_ID, 0,
 414                               FRF_AZ_TX_DESCQ_LABEL, tx_queue->queue,
 415                               FRF_AZ_TX_DESCQ_SIZE,
 416                               __ffs(tx_queue->txd.entries),
 417                               FRF_AZ_TX_DESCQ_TYPE, 0,
 418                               FRF_BZ_TX_NON_IP_DROP_DIS, 1);
 419
 420         if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0) {
 421                 int csum = tx_queue->queue == EFX_TX_QUEUE_OFFLOAD_CSUM;
 422                 EFX_SET_OWORD_FIELD(tx_desc_ptr, FRF_BZ_TX_IP_CHKSM_DIS, !csum);
 423                 EFX_SET_OWORD_FIELD(tx_desc_ptr, FRF_BZ_TX_TCP_CHKSM_DIS,
 424                                     !csum);
 425         }
 426
 427         efx_writeo_table(efx, &tx_desc_ptr, efx->type->txd_ptr_tbl_base,
 428                          tx_queue->queue);
 429
 430         if (efx_nic_rev(efx) < EFX_REV_FALCON_B0) {
 431                 efx_oword_t reg;
 432
 433                 /* Only 128 bits in this register */
 434                 BUILD_BUG_ON(EFX_TX_QUEUE_COUNT >= 128);
 435
 436                 efx_reado(efx, &reg, FR_AA_TX_CHKSM_CFG);
 437                 if (tx_queue->queue == EFX_TX_QUEUE_OFFLOAD_CSUM)
 438                         clear_bit_le(tx_queue->queue, (void *)&reg);
 439                 else
 440                         set_bit_le(tx_queue->queue, (void *)&reg);
 441                 efx_writeo(efx, &reg, FR_AA_TX_CHKSM_CFG);
 442         }
 443 }
 444
 445 static void efx_flush_tx_queue(struct efx_tx_queue *tx_queue)
 446 {
 447         struct efx_nic *efx = tx_queue->efx;
 448         efx_oword_t tx_flush_descq;
 449
 450         tx_queue->flushed = FLUSH_PENDING;
 451
 452         /* Post a flush command */
 453         EFX_POPULATE_OWORD_2(tx_flush_descq,
 454                              FRF_AZ_TX_FLUSH_DESCQ_CMD, 1,
 455                              FRF_AZ_TX_FLUSH_DESCQ, tx_queue->queue);
 456         efx_writeo(efx, &tx_flush_descq, FR_AZ_TX_FLUSH_DESCQ);
 457 }
 458
 459 void efx_nic_fini_tx(struct efx_tx_queue *tx_queue)
 460 {
 461         struct efx_nic *efx = tx_queue->efx;
 462         efx_oword_t tx_desc_ptr;
 463
 464         /* The queue should have been flushed */
 465         WARN_ON(tx_queue->flushed != FLUSH_DONE);
 466
 467         /* Remove TX descriptor ring from card */
 468         EFX_ZERO_OWORD(tx_desc_ptr);
 469         efx_writeo_table(efx, &tx_desc_ptr, efx->type->txd_ptr_tbl_base,
 470                          tx_queue->queue);
 471
 472         /* Unpin TX descriptor ring */
 473         efx_fini_special_buffer(efx, &tx_queue->txd);
 474 }
 475
 476 /* Free buffers backing TX queue */
 477 void efx_nic_remove_tx(struct efx_tx_queue *tx_queue)
 478 {
 479         efx_free_special_buffer(tx_queue->efx, &tx_queue->txd);
 480 }
 481
 482 /**************************************************************************
 483  *
 484  * RX path
 485  *
 486  **************************************************************************/
 487
 488 /* Returns a pointer to the specified descriptor in the RX descriptor queue */
 489 static inline efx_qword_t *
 490 efx_rx_desc(struct efx_rx_queue *rx_queue, unsigned int index)
 491 {
 492         return (((efx_qword_t *) (rx_queue->rxd.addr)) + index);
 493 }
 494
 495 /* This creates an entry in the RX descriptor queue */
 496 static inline void
 497 efx_build_rx_desc(struct efx_rx_queue *rx_queue, unsigned index)
 498 {
 499         struct efx_rx_buffer *rx_buf;
 500         efx_qword_t *rxd;
 501
 502         rxd = efx_rx_desc(rx_queue, index);
 503         rx_buf = efx_rx_buffer(rx_queue, index);
 504         EFX_POPULATE_QWORD_3(*rxd,
 505                              FSF_AZ_RX_KER_BUF_SIZE,
 506                              rx_buf->len -
 507                              rx_queue->efx->type->rx_buffer_padding,
 508                              FSF_AZ_RX_KER_BUF_REGION, 0,
 509                              FSF_AZ_RX_KER_BUF_ADDR, rx_buf->dma_addr);
 510 }
 511
 512 /* This writes to the RX_DESC_WPTR register for the specified receive
 513  * descriptor ring.
 514  */
 515 void efx_nic_notify_rx_desc(struct efx_rx_queue *rx_queue)
 516 {
 517         efx_dword_t reg;
 518         unsigned write_ptr;
 519
 520         while (rx_queue->notified_count != rx_queue->added_count) {
 521                 efx_build_rx_desc(rx_queue,
 522                                   rx_queue->notified_count &
 523                                   EFX_RXQ_MASK);
 524                 ++rx_queue->notified_count;
 525         }
 526
 527         wmb();
 528         write_ptr = rx_queue->added_count & EFX_RXQ_MASK;
 529         EFX_POPULATE_DWORD_1(reg, FRF_AZ_RX_DESC_WPTR_DWORD, write_ptr);
 530         efx_writed_page(rx_queue->efx, &reg,
 531                         FR_AZ_RX_DESC_UPD_DWORD_P0, rx_queue->queue);
 532 }
 533
 534 int efx_nic_probe_rx(struct efx_rx_queue *rx_queue)
 535 {
 536         struct efx_nic *efx = rx_queue->efx;
 537         BUILD_BUG_ON(EFX_RXQ_SIZE < 512 || EFX_RXQ_SIZE > 4096 ||
 538                      EFX_RXQ_SIZE & EFX_RXQ_MASK);
 539         return efx_alloc_special_buffer(efx, &rx_queue->rxd,
 540                                         EFX_RXQ_SIZE * sizeof(efx_qword_t));
 541 }
 542
 543 void efx_nic_init_rx(struct efx_rx_queue *rx_queue)
 544 {
 545         efx_oword_t rx_desc_ptr;
 546         struct efx_nic *efx = rx_queue->efx;
 547         bool is_b0 = efx_nic_rev(efx) >= EFX_REV_FALCON_B0;
 548         bool iscsi_digest_en = is_b0;
 549
 550         EFX_LOG(efx, "RX queue %d ring in special buffers %d-%d\n",
 551                 rx_queue->queue, rx_queue->rxd.index,
 552                 rx_queue->rxd.index + rx_queue->rxd.entries - 1);
 553
 554         rx_queue->flushed = FLUSH_NONE;
 555
 556         /* Pin RX descriptor ring */
 557         efx_init_special_buffer(efx, &rx_queue->rxd);
 558
 559         /* Push RX descriptor ring to card */
 560         EFX_POPULATE_OWORD_10(rx_desc_ptr,
 561                               FRF_AZ_RX_ISCSI_DDIG_EN, iscsi_digest_en,
 562                               FRF_AZ_RX_ISCSI_HDIG_EN, iscsi_digest_en,
 563                               FRF_AZ_RX_DESCQ_BUF_BASE_ID, rx_queue->rxd.index,
 564                               FRF_AZ_RX_DESCQ_EVQ_ID,
 565                               rx_queue->channel->channel,
 566                               FRF_AZ_RX_DESCQ_OWNER_ID, 0,
 567                               FRF_AZ_RX_DESCQ_LABEL, rx_queue->queue,
 568                               FRF_AZ_RX_DESCQ_SIZE,
 569                               __ffs(rx_queue->rxd.entries),
 570                               FRF_AZ_RX_DESCQ_TYPE, 0 /* kernel queue */ ,
 571                               /* For >=B0 this is scatter so disable */
 572                               FRF_AZ_RX_DESCQ_JUMBO, !is_b0,
 573                               FRF_AZ_RX_DESCQ_EN, 1);
 574         efx_writeo_table(efx, &rx_desc_ptr, efx->type->rxd_ptr_tbl_base,
 575                          rx_queue->queue);
 576 }
 577
 578 static void efx_flush_rx_queue(struct efx_rx_queue *rx_queue)
 579 {
 580         struct efx_nic *efx = rx_queue->efx;
 581         efx_oword_t rx_flush_descq;
 582
 583         rx_queue->flushed = FLUSH_PENDING;
 584
 585         /* Post a flush command */
 586         EFX_POPULATE_OWORD_2(rx_flush_descq,
 587                              FRF_AZ_RX_FLUSH_DESCQ_CMD, 1,
 588                              FRF_AZ_RX_FLUSH_DESCQ, rx_queue->queue);
 589         efx_writeo(efx, &rx_flush_descq, FR_AZ_RX_FLUSH_DESCQ);
 590 }
 591
 592 void efx_nic_fini_rx(struct efx_rx_queue *rx_queue)
 593 {
 594         efx_oword_t rx_desc_ptr;
 595         struct efx_nic *efx = rx_queue->efx;
 596
 597         /* The queue should already have been flushed */
 598         WARN_ON(rx_queue->flushed != FLUSH_DONE);
 599
 600         /* Remove RX descriptor ring from card */
 601         EFX_ZERO_OWORD(rx_desc_ptr);
 602         efx_writeo_table(efx, &rx_desc_ptr, efx->type->rxd_ptr_tbl_base,
 603                          rx_queue->queue);
 604
 605         /* Unpin RX descriptor ring */
 606         efx_fini_special_buffer(efx, &rx_queue->rxd);
 607 }
 608
 609 /* Free buffers backing RX queue */
 610 void efx_nic_remove_rx(struct efx_rx_queue *rx_queue)
 611 {
 612         efx_free_special_buffer(rx_queue->efx, &rx_queue->rxd);
 613 }
 614
 615 /**************************************************************************
 616  *
 617  * Event queue processing
 618  * Event queues are processed by per-channel tasklets.
 619  *
 620  **************************************************************************/
 621
 622 /* Update a channel's event queue's read pointer (RPTR) register
 623  *
 624  * This writes the EVQ_RPTR_REG register for the specified channel's
 625  * event queue.
 626  */
 627 void efx_nic_eventq_read_ack(struct efx_channel *channel)
 628 {
 629         efx_dword_t reg;
 630         struct efx_nic *efx = channel->efx;
 631
 632         EFX_POPULATE_DWORD_1(reg, FRF_AZ_EVQ_RPTR, channel->eventq_read_ptr);
 633         efx_writed_table(efx, &reg, efx->type->evq_rptr_tbl_base,
 634                          channel->channel);
 635 }
 636
 637 /* Use HW to insert a SW defined event */
 638 void efx_generate_event(struct efx_channel *channel, efx_qword_t *event)
 639 {
 640         efx_oword_t drv_ev_reg;
 641
 642         BUILD_BUG_ON(FRF_AZ_DRV_EV_DATA_LBN != 0 ||
 643                      FRF_AZ_DRV_EV_DATA_WIDTH != 64);
 644         drv_ev_reg.u32[0] = event->u32[0];
 645         drv_ev_reg.u32[1] = event->u32[1];
 646         drv_ev_reg.u32[2] = 0;
 647         drv_ev_reg.u32[3] = 0;
 648         EFX_SET_OWORD_FIELD(drv_ev_reg, FRF_AZ_DRV_EV_QID, channel->channel);
 649         efx_writeo(channel->efx, &drv_ev_reg, FR_AZ_DRV_EV);
 650 }
 651
 652 /* Handle a transmit completion event
 653  *
 654  * The NIC batches TX completion events; the message we receive is of
 655  * the form "complete all TX events up to this index".
 656  */
 657 static void
 658 efx_handle_tx_event(struct efx_channel *channel, efx_qword_t *event)
 659 {
 660         unsigned int tx_ev_desc_ptr;
 661         unsigned int tx_ev_q_label;
 662         struct efx_tx_queue *tx_queue;
 663         struct efx_nic *efx = channel->efx;
 664
 665         if (likely(EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_COMP))) {
 666                 /* Transmit completion */
 667                 tx_ev_desc_ptr = EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_DESC_PTR);
 668                 tx_ev_q_label = EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_Q_LABEL);
 669                 tx_queue = &efx->tx_queue[tx_ev_q_label];
 670                 channel->irq_mod_score +=
 671                         (tx_ev_desc_ptr - tx_queue->read_count) &
 672                         EFX_TXQ_MASK;
 673                 efx_xmit_done(tx_queue, tx_ev_desc_ptr);
 674         } else if (EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_WQ_FF_FULL)) {
 675                 /* Rewrite the FIFO write pointer */
 676                 tx_ev_q_label = EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_Q_LABEL);
 677                 tx_queue = &efx->tx_queue[tx_ev_q_label];
 678
 679                 if (efx_dev_registered(efx))
 680                         netif_tx_lock(efx->net_dev);
 681                 efx_notify_tx_desc(tx_queue);
 682                 if (efx_dev_registered(efx))
 683                         netif_tx_unlock(efx->net_dev);
 684         } else if (EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_PKT_ERR) &&
 685                    EFX_WORKAROUND_10727(efx)) {
 686                 efx_schedule_reset(efx, RESET_TYPE_TX_DESC_FETCH);
 687         } else {
 688                 EFX_ERR(efx, "channel %d unexpected TX event "
 689                         EFX_QWORD_FMT"\n", channel->channel,
 690                         EFX_QWORD_VAL(*event));
 691         }
 692 }
 693
 694 /* Detect errors included in the rx_evt_pkt_ok bit. */
 695 static void efx_handle_rx_not_ok(struct efx_rx_queue *rx_queue,
 696                                  const efx_qword_t *event,
 697                                  bool *rx_ev_pkt_ok,
 698                                  bool *discard)
 699 {
 700         struct efx_nic *efx = rx_queue->efx;
 701         bool rx_ev_buf_owner_id_err, rx_ev_ip_hdr_chksum_err;
 702         bool rx_ev_tcp_udp_chksum_err, rx_ev_eth_crc_err;
 703         bool rx_ev_frm_trunc, rx_ev_drib_nib, rx_ev_tobe_disc;
 704         bool rx_ev_other_err, rx_ev_pause_frm;
 705         bool rx_ev_hdr_type, rx_ev_mcast_pkt;
 706         unsigned rx_ev_pkt_type;
 707
 708         rx_ev_hdr_type = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_HDR_TYPE);
 709         rx_ev_mcast_pkt = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_MCAST_PKT);
 710         rx_ev_tobe_disc = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_TOBE_DISC);
 711         rx_ev_pkt_type = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_PKT_TYPE);
 712         rx_ev_buf_owner_id_err = EFX_QWORD_FIELD(*event,
 713                                                  FSF_AZ_RX_EV_BUF_OWNER_ID_ERR);
 714         rx_ev_ip_hdr_chksum_err = EFX_QWORD_FIELD(*event,
 715                                                   FSF_AZ_RX_EV_IP_HDR_CHKSUM_ERR);
 716         rx_ev_tcp_udp_chksum_err = EFX_QWORD_FIELD(*event,
 717                                                    FSF_AZ_RX_EV_TCP_UDP_CHKSUM_ERR);
 718         rx_ev_eth_crc_err = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_ETH_CRC_ERR);
 719         rx_ev_frm_trunc = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_FRM_TRUNC);
 720         rx_ev_drib_nib = ((efx_nic_rev(efx) >= EFX_REV_FALCON_B0) ?
 721                           0 : EFX_QWORD_FIELD(*event, FSF_AA_RX_EV_DRIB_NIB));
 722         rx_ev_pause_frm = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_PAUSE_FRM_ERR);
 723
 724         /* Every error apart from tobe_disc and pause_frm */
 725         rx_ev_other_err = (rx_ev_drib_nib | rx_ev_tcp_udp_chksum_err |
 726                            rx_ev_buf_owner_id_err | rx_ev_eth_crc_err |
 727                            rx_ev_frm_trunc | rx_ev_ip_hdr_chksum_err);
 728
 729         /* Count errors that are not in MAC stats.  Ignore expected
 730          * checksum errors during self-test. */
 731         if (rx_ev_frm_trunc)
 732                 ++rx_queue->channel->n_rx_frm_trunc;
 733         else if (rx_ev_tobe_disc)
 734                 ++rx_queue->channel->n_rx_tobe_disc;
 735         else if (!efx->loopback_selftest) {
 736                 if (rx_ev_ip_hdr_chksum_err)
 737                         ++rx_queue->channel->n_rx_ip_hdr_chksum_err;
 738                 else if (rx_ev_tcp_udp_chksum_err)
 739                         ++rx_queue->channel->n_rx_tcp_udp_chksum_err;
 740         }
 741
 742         /* The frame must be discarded if any of these are true. */
 743         *discard = (rx_ev_eth_crc_err | rx_ev_frm_trunc | rx_ev_drib_nib |
 744                     rx_ev_tobe_disc | rx_ev_pause_frm);
 745
 746         /* TOBE_DISC is expected on unicast mismatches; don't print out an
 747          * error message.  FRM_TRUNC indicates RXDP dropped the packet due
 748          * to a FIFO overflow.
 749          */
 750 #ifdef EFX_ENABLE_DEBUG
 751         if (rx_ev_other_err) {
 752                 EFX_INFO_RL(efx, " RX queue %d unexpected RX event "
 753                             EFX_QWORD_FMT "%s%s%s%s%s%s%s%s\n",
 754                             rx_queue->queue, EFX_QWORD_VAL(*event),
 755                             rx_ev_buf_owner_id_err ? " [OWNER_ID_ERR]" : "",
 756                             rx_ev_ip_hdr_chksum_err ?
 757                             " [IP_HDR_CHKSUM_ERR]" : "",
 758                             rx_ev_tcp_udp_chksum_err ?
 759                             " [TCP_UDP_CHKSUM_ERR]" : "",
 760                             rx_ev_eth_crc_err ? " [ETH_CRC_ERR]" : "",
 761                             rx_ev_frm_trunc ? " [FRM_TRUNC]" : "",
 762                             rx_ev_drib_nib ? " [DRIB_NIB]" : "",
 763                             rx_ev_tobe_disc ? " [TOBE_DISC]" : "",
 764                             rx_ev_pause_frm ? " [PAUSE]" : "");
 765         }
 766 #endif
 767 }
 768
 769 /* Handle receive events that are not in-order. */
 770 static void
 771 efx_handle_rx_bad_index(struct efx_rx_queue *rx_queue, unsigned index)
 772 {
 773         struct efx_nic *efx = rx_queue->efx;
 774         unsigned expected, dropped;
 775
 776         expected = rx_queue->removed_count & EFX_RXQ_MASK;
 777         dropped = (index - expected) & EFX_RXQ_MASK;
 778         EFX_INFO(efx, "dropped %d events (index=%d expected=%d)\n",
 779                 dropped, index, expected);
 780
 781         efx_schedule_reset(efx, EFX_WORKAROUND_5676(efx) ?
 782                            RESET_TYPE_RX_RECOVERY : RESET_TYPE_DISABLE);
 783 }
 784
 785 /* Handle a packet received event
 786  *
 787  * The NIC gives a "discard" flag if it's a unicast packet with the
 788  * wrong destination address
 789  * Also "is multicast" and "matches multicast filter" flags can be used to
 790  * discard non-matching multicast packets.
 791  */
 792 static void
 793 efx_handle_rx_event(struct efx_channel *channel, const efx_qword_t *event)
 794 {
 795         unsigned int rx_ev_desc_ptr, rx_ev_byte_cnt;
 796         unsigned int rx_ev_hdr_type, rx_ev_mcast_pkt;
 797         unsigned expected_ptr;
 798         bool rx_ev_pkt_ok, discard = false, checksummed;
 799         struct efx_rx_queue *rx_queue;
 800         struct efx_nic *efx = channel->efx;
 801
 802         /* Basic packet information */
 803         rx_ev_byte_cnt = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_BYTE_CNT);
 804         rx_ev_pkt_ok = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_PKT_OK);
 805         rx_ev_hdr_type = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_HDR_TYPE);
 806         WARN_ON(EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_JUMBO_CONT));
 807         WARN_ON(EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_SOP) != 1);
 808         WARN_ON(EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_Q_LABEL) !=
 809                 channel->channel);
 810
 811         rx_queue = &efx->rx_queue[channel->channel];
 812
 813         rx_ev_desc_ptr = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_DESC_PTR);
 814         expected_ptr = rx_queue->removed_count & EFX_RXQ_MASK;
 815         if (unlikely(rx_ev_desc_ptr != expected_ptr))
 816                 efx_handle_rx_bad_index(rx_queue, rx_ev_desc_ptr);
 817
 818         if (likely(rx_ev_pkt_ok)) {
 819                 /* If packet is marked as OK and packet type is TCP/IP or
 820                  * UDP/IP, then we can rely on the hardware checksum.
 821                  */
 822                 checksummed =
 823                         likely(efx->rx_checksum_enabled) &&
 824                         (rx_ev_hdr_type == FSE_CZ_RX_EV_HDR_TYPE_IPV4V6_TCP ||
 825                          rx_ev_hdr_type == FSE_CZ_RX_EV_HDR_TYPE_IPV4V6_UDP);
 826         } else {
 827                 efx_handle_rx_not_ok(rx_queue, event, &rx_ev_pkt_ok, &discard);
 828                 checksummed = false;
 829         }
 830
 831         /* Detect multicast packets that didn't match the filter */
 832         rx_ev_mcast_pkt = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_MCAST_PKT);
 833         if (rx_ev_mcast_pkt) {
 834                 unsigned int rx_ev_mcast_hash_match =
 835                         EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_MCAST_HASH_MATCH);
 836
 837                 if (unlikely(!rx_ev_mcast_hash_match)) {
 838                         ++channel->n_rx_mcast_mismatch;
 839                         discard = true;
 840                 }
 841         }
 842
 843         channel->irq_mod_score += 2;
 844
 845         /* Handle received packet */
 846         efx_rx_packet(rx_queue, rx_ev_desc_ptr, rx_ev_byte_cnt,
 847                       checksummed, discard);
 848 }
 849
 850 /* Global events are basically PHY events */
 851 static void
 852 efx_handle_global_event(struct efx_channel *channel, efx_qword_t *event)
 853 {
 854         struct efx_nic *efx = channel->efx;
 855         bool handled = false;
 856
 857         if (EFX_QWORD_FIELD(*event, FSF_AB_GLB_EV_G_PHY0_INTR) ||
 858             EFX_QWORD_FIELD(*event, FSF_AB_GLB_EV_XG_PHY0_INTR) ||
 859             EFX_QWORD_FIELD(*event, FSF_AB_GLB_EV_XFP_PHY0_INTR)) {
 860                 /* Ignored */
 861                 handled = true;
 862         }
 863
 864         if ((efx_nic_rev(efx) >= EFX_REV_FALCON_B0) &&
 865             EFX_QWORD_FIELD(*event, FSF_BB_GLB_EV_XG_MGT_INTR)) {
 866                 efx->xmac_poll_required = true;
 867                 handled = true;
 868         }
 869
 870         if (efx_nic_rev(efx) <= EFX_REV_FALCON_A1 ?
 871             EFX_QWORD_FIELD(*event, FSF_AA_GLB_EV_RX_RECOVERY) :
 872             EFX_QWORD_FIELD(*event, FSF_BB_GLB_EV_RX_RECOVERY)) {
 873                 EFX_ERR(efx, "channel %d seen global RX_RESET "
 874                         "event. Resetting.\n", channel->channel);
 875
 876                 atomic_inc(&efx->rx_reset);
 877                 efx_schedule_reset(efx, EFX_WORKAROUND_6555(efx) ?
 878                                    RESET_TYPE_RX_RECOVERY : RESET_TYPE_DISABLE);
 879                 handled = true;
 880         }
 881
 882         if (!handled)
 883                 EFX_ERR(efx, "channel %d unknown global event "
 884                         EFX_QWORD_FMT "\n", channel->channel,
 885                         EFX_QWORD_VAL(*event));
 886 }
 887
 888 static void
 889 efx_handle_driver_event(struct efx_channel *channel, efx_qword_t *event)
 890 {
 891         struct efx_nic *efx = channel->efx;
 892         unsigned int ev_sub_code;
 893         unsigned int ev_sub_data;
 894
 895         ev_sub_code = EFX_QWORD_FIELD(*event, FSF_AZ_DRIVER_EV_SUBCODE);
 896         ev_sub_data = EFX_QWORD_FIELD(*event, FSF_AZ_DRIVER_EV_SUBDATA);
 897
 898         switch (ev_sub_code) {
 899         case FSE_AZ_TX_DESCQ_FLS_DONE_EV:
 900                 EFX_TRACE(efx, "channel %d TXQ %d flushed\n",
 901                           channel->channel, ev_sub_data);
 902                 break;
 903         case FSE_AZ_RX_DESCQ_FLS_DONE_EV:
 904                 EFX_TRACE(efx, "channel %d RXQ %d flushed\n",
 905                           channel->channel, ev_sub_data);
 906                 break;
 907         case FSE_AZ_EVQ_INIT_DONE_EV:
 908                 EFX_LOG(efx, "channel %d EVQ %d initialised\n",
 909                         channel->channel, ev_sub_data);
 910                 break;
 911         case FSE_AZ_SRM_UPD_DONE_EV:
 912                 EFX_TRACE(efx, "channel %d SRAM update done\n",
 913                           channel->channel);
 914                 break;
 915         case FSE_AZ_WAKE_UP_EV:
 916                 EFX_TRACE(efx, "channel %d RXQ %d wakeup event\n",
 917                           channel->channel, ev_sub_data);
 918                 break;
 919         case FSE_AZ_TIMER_EV:
 920                 EFX_TRACE(efx, "channel %d RX queue %d timer expired\n",
 921                           channel->channel, ev_sub_data);
 922                 break;
 923         case FSE_AA_RX_RECOVER_EV:
 924                 EFX_ERR(efx, "channel %d seen DRIVER RX_RESET event. "
 925                         "Resetting.\n", channel->channel);
 926                 atomic_inc(&efx->rx_reset);
 927                 efx_schedule_reset(efx,
 928                                    EFX_WORKAROUND_6555(efx) ?
 929                                    RESET_TYPE_RX_RECOVERY :
 930                                    RESET_TYPE_DISABLE);
 931                 break;
 932         case FSE_BZ_RX_DSC_ERROR_EV:
 933                 EFX_ERR(efx, "RX DMA Q %d reports descriptor fetch error."
 934                         " RX Q %d is disabled.\n", ev_sub_data, ev_sub_data);
 935                 efx_schedule_reset(efx, RESET_TYPE_RX_DESC_FETCH);
 936                 break;
 937         case FSE_BZ_TX_DSC_ERROR_EV:
 938                 EFX_ERR(efx, "TX DMA Q %d reports descriptor fetch error."
 939                         " TX Q %d is disabled.\n", ev_sub_data, ev_sub_data);
 940                 efx_schedule_reset(efx, RESET_TYPE_TX_DESC_FETCH);
 941                 break;
 942         default:
 943                 EFX_TRACE(efx, "channel %d unknown driver event code %d "
 944                           "data %04x\n", channel->channel, ev_sub_code,
 945                           ev_sub_data);
 946                 break;
 947         }
 948 }
 949
 950 int efx_nic_process_eventq(struct efx_channel *channel, int rx_quota)
 951 {
 952         unsigned int read_ptr;
 953         efx_qword_t event, *p_event;
 954         int ev_code;
 955         int rx_packets = 0;
 956
 957         read_ptr = channel->eventq_read_ptr;
 958
 959         do {
 960                 p_event = efx_event(channel, read_ptr);
 961                 event = *p_event;
 962
 963                 if (!efx_event_present(&event))
 964                         /* End of events */
 965                         break;
 966
 967                 EFX_TRACE(channel->efx, "channel %d event is "EFX_QWORD_FMT"\n",
 968                           channel->channel, EFX_QWORD_VAL(event));
 969
 970                 /* Clear this event by marking it all ones */
 971                 EFX_SET_QWORD(*p_event);
 972
 973                 ev_code = EFX_QWORD_FIELD(event, FSF_AZ_EV_CODE);
 974
 975                 switch (ev_code) {
 976                 case FSE_AZ_EV_CODE_RX_EV:
 977                         efx_handle_rx_event(channel, &event);
 978                         ++rx_packets;
 979                         break;
 980                 case FSE_AZ_EV_CODE_TX_EV:
 981                         efx_handle_tx_event(channel, &event);
 982                         break;
 983                 case FSE_AZ_EV_CODE_DRV_GEN_EV:
 984                         channel->eventq_magic = EFX_QWORD_FIELD(
 985                                 event, FSF_AZ_DRV_GEN_EV_MAGIC);
 986                         EFX_LOG(channel->efx, "channel %d received generated "
 987                                 "event "EFX_QWORD_FMT"\n", channel->channel,
 988                                 EFX_QWORD_VAL(event));
 989                         break;
 990                 case FSE_AZ_EV_CODE_GLOBAL_EV:
 991                         efx_handle_global_event(channel, &event);
 992                         break;
 993                 case FSE_AZ_EV_CODE_DRIVER_EV:
 994                         efx_handle_driver_event(channel, &event);
 995                         break;
 996                 case FSE_CZ_EV_CODE_MCDI_EV:
 997                         efx_mcdi_process_event(channel, &event);
 998                         break;
 999                 default:
1000                         EFX_ERR(channel->efx, "channel %d unknown event type %d"
1001                                 " (data " EFX_QWORD_FMT ")\n", channel->channel,
1002                                 ev_code, EFX_QWORD_VAL(event));
1003                 }
1004
1005                 /* Increment read pointer */
1006                 read_ptr = (read_ptr + 1) & EFX_EVQ_MASK;
1007
1008         } while (rx_packets < rx_quota);
1009
1010         channel->eventq_read_ptr = read_ptr;
1011         return rx_packets;
1012 }
1013
1014
1015 /* Allocate buffer table entries for event queue */
1016 int efx_nic_probe_eventq(struct efx_channel *channel)
1017 {
1018         struct efx_nic *efx = channel->efx;
1019         BUILD_BUG_ON(EFX_EVQ_SIZE < 512 || EFX_EVQ_SIZE > 32768 ||
1020                      EFX_EVQ_SIZE & EFX_EVQ_MASK);
1021         return efx_alloc_special_buffer(efx, &channel->eventq,
1022                                         EFX_EVQ_SIZE * sizeof(efx_qword_t));
1023 }
1024
1025 void efx_nic_init_eventq(struct efx_channel *channel)
1026 {
1027         efx_oword_t reg;
1028         struct efx_nic *efx = channel->efx;
1029
1030         EFX_LOG(efx, "channel %d event queue in special buffers %d-%d\n",
1031                 channel->channel, channel->eventq.index,
1032                 channel->eventq.index + channel->eventq.entries - 1);
1033
1034         if (efx_nic_rev(efx) >= EFX_REV_SIENA_A0) {
1035                 EFX_POPULATE_OWORD_3(reg,
1036                                      FRF_CZ_TIMER_Q_EN, 1,
1037                                      FRF_CZ_HOST_NOTIFY_MODE, 0,
1038                                      FRF_CZ_TIMER_MODE, FFE_CZ_TIMER_MODE_DIS);
1039                 efx_writeo_table(efx, &reg, FR_BZ_TIMER_TBL, channel->channel);
1040         }
1041
1042         /* Pin event queue buffer */
1043         efx_init_special_buffer(efx, &channel->eventq);
1044
1045         /* Fill event queue with all ones (i.e. empty events) */
1046         memset(channel->eventq.addr, 0xff, channel->eventq.len);
1047
1048         /* Push event queue to card */
1049         EFX_POPULATE_OWORD_3(reg,
1050                              FRF_AZ_EVQ_EN, 1,
1051                              FRF_AZ_EVQ_SIZE, __ffs(channel->eventq.entries),
1052                              FRF_AZ_EVQ_BUF_BASE_ID, channel->eventq.index);
1053         efx_writeo_table(efx, &reg, efx->type->evq_ptr_tbl_base,
1054                          channel->channel);
1055
1056         efx->type->push_irq_moderation(channel);
1057 }
1058
1059 void efx_nic_fini_eventq(struct efx_channel *channel)
1060 {
1061         efx_oword_t reg;
1062         struct efx_nic *efx = channel->efx;
1063
1064         /* Remove event queue from card */
1065         EFX_ZERO_OWORD(reg);
1066         efx_writeo_table(efx, &reg, efx->type->evq_ptr_tbl_base,
1067                          channel->channel);
1068         if (efx_nic_rev(efx) >= EFX_REV_SIENA_A0)
1069                 efx_writeo_table(efx, &reg, FR_BZ_TIMER_TBL, channel->channel);
1070
1071         /* Unpin event queue */
1072         efx_fini_special_buffer(efx, &channel->eventq);
1073 }
1074
1075 /* Free buffers backing event queue */
1076 void efx_nic_remove_eventq(struct efx_channel *channel)
1077 {
1078         efx_free_special_buffer(channel->efx, &channel->eventq);
1079 }
1080
1081
1082 /* Generates a test event on the event queue.  A subsequent call to
1083  * process_eventq() should pick up the event and place the value of
1084  * "magic" into channel->eventq_magic;
1085  */
1086 void efx_nic_generate_test_event(struct efx_channel *channel, unsigned int magic)
1087 {
1088         efx_qword_t test_event;
1089
1090         EFX_POPULATE_QWORD_2(test_event, FSF_AZ_EV_CODE,
1091                              FSE_AZ_EV_CODE_DRV_GEN_EV,
1092                              FSF_AZ_DRV_GEN_EV_MAGIC, magic);
1093         efx_generate_event(channel, &test_event);
1094 }
1095
1096 /**************************************************************************
1097  *
1098  * Flush handling
1099  *
1100  **************************************************************************/
1101
1102
1103 static void efx_poll_flush_events(struct efx_nic *efx)
1104 {
1105         struct efx_channel *channel = &efx->channel[0];
1106         struct efx_tx_queue *tx_queue;
1107         struct efx_rx_queue *rx_queue;
1108         unsigned int read_ptr = channel->eventq_read_ptr;
1109         unsigned int end_ptr = (read_ptr - 1) & EFX_EVQ_MASK;
1110
1111         do {
1112                 efx_qword_t *event = efx_event(channel, read_ptr);
1113                 int ev_code, ev_sub_code, ev_queue;
1114                 bool ev_failed;
1115
1116                 if (!efx_event_present(event))
1117                         break;
1118
1119                 ev_code = EFX_QWORD_FIELD(*event, FSF_AZ_EV_CODE);
1120                 ev_sub_code = EFX_QWORD_FIELD(*event,
1121                                               FSF_AZ_DRIVER_EV_SUBCODE);
1122                 if (ev_code == FSE_AZ_EV_CODE_DRIVER_EV &&
1123                     ev_sub_code == FSE_AZ_TX_DESCQ_FLS_DONE_EV) {
1124                         ev_queue = EFX_QWORD_FIELD(*event,
1125                                                    FSF_AZ_DRIVER_EV_SUBDATA);
1126                         if (ev_queue < EFX_TX_QUEUE_COUNT) {
1127                                 tx_queue = efx->tx_queue + ev_queue;
1128                                 tx_queue->flushed = FLUSH_DONE;
1129                         }
1130                 } else if (ev_code == FSE_AZ_EV_CODE_DRIVER_EV &&
1131                            ev_sub_code == FSE_AZ_RX_DESCQ_FLS_DONE_EV) {
1132                         ev_queue = EFX_QWORD_FIELD(
1133                                 *event, FSF_AZ_DRIVER_EV_RX_DESCQ_ID);
1134                         ev_failed = EFX_QWORD_FIELD(
1135                                 *event, FSF_AZ_DRIVER_EV_RX_FLUSH_FAIL);
1136                         if (ev_queue < efx->n_rx_queues) {
1137                                 rx_queue = efx->rx_queue + ev_queue;
1138                                 rx_queue->flushed =
1139                                         ev_failed ? FLUSH_FAILED : FLUSH_DONE;
1140                         }
1141                 }
1142
1143                 /* We're about to destroy the queue anyway, so
1144                  * it's ok to throw away every non-flush event */
1145                 EFX_SET_QWORD(*event);
1146
1147                 read_ptr = (read_ptr + 1) & EFX_EVQ_MASK;
1148         } while (read_ptr != end_ptr);
1149
1150         channel->eventq_read_ptr = read_ptr;
1151 }
1152
1153 /* Handle tx and rx flushes at the same time, since they run in
1154  * parallel in the hardware and there's no reason for us to
1155  * serialise them */
1156 int efx_nic_flush_queues(struct efx_nic *efx)
1157 {
1158         struct efx_rx_queue *rx_queue;
1159         struct efx_tx_queue *tx_queue;
1160         int i, tx_pending, rx_pending;
1161
1162         /* If necessary prepare the hardware for flushing */
1163         efx->type->prepare_flush(efx);
1164
1165         /* Flush all tx queues in parallel */
1166         efx_for_each_tx_queue(tx_queue, efx)
1167                 efx_flush_tx_queue(tx_queue);
1168
1169         /* The hardware supports four concurrent rx flushes, each of which may
1170          * need to be retried if there is an outstanding descriptor fetch */
1171         for (i = 0; i < EFX_FLUSH_POLL_COUNT; ++i) {
1172                 rx_pending = tx_pending = 0;
1173                 efx_for_each_rx_queue(rx_queue, efx) {
1174                         if (rx_queue->flushed == FLUSH_PENDING)
1175                                 ++rx_pending;
1176                 }
1177                 efx_for_each_rx_queue(rx_queue, efx) {
1178                         if (rx_pending == EFX_RX_FLUSH_COUNT)
1179                                 break;
1180                         if (rx_queue->flushed == FLUSH_FAILED ||
1181                             rx_queue->flushed == FLUSH_NONE) {
1182                                 efx_flush_rx_queue(rx_queue);
1183                                 ++rx_pending;
1184                         }
1185                 }
1186                 efx_for_each_tx_queue(tx_queue, efx) {
1187                         if (tx_queue->flushed != FLUSH_DONE)
1188                                 ++tx_pending;
1189                 }
1190
1191                 if (rx_pending == 0 && tx_pending == 0)
1192                         return 0;
1193
1194                 msleep(EFX_FLUSH_INTERVAL);
1195                 efx_poll_flush_events(efx);
1196         }
1197
1198         /* Mark the queues as all flushed. We're going to return failure
1199          * leading to a reset, or fake up success anyway */
1200         efx_for_each_tx_queue(tx_queue, efx) {
1201                 if (tx_queue->flushed != FLUSH_DONE)
1202                         EFX_ERR(efx, "tx queue %d flush command timed out\n",
1203                                 tx_queue->queue);
1204                 tx_queue->flushed = FLUSH_DONE;
1205         }
1206         efx_for_each_rx_queue(rx_queue, efx) {
1207                 if (rx_queue->flushed != FLUSH_DONE)
1208                         EFX_ERR(efx, "rx queue %d flush command timed out\n",
1209                                 rx_queue->queue);
1210                 rx_queue->flushed = FLUSH_DONE;
1211         }
1212
1213         if (EFX_WORKAROUND_7803(efx))
1214                 return 0;
1215
1216         return -ETIMEDOUT;
1217 }
1218
1219 /**************************************************************************
1220  *
1221  * Hardware interrupts
1222  * The hardware interrupt handler does very little work; all the event
1223  * queue processing is carried out by per-channel tasklets.
1224  *
1225  **************************************************************************/
1226
1227 /* Enable/disable/generate interrupts */
1228 static inline void efx_nic_interrupts(struct efx_nic *efx,
1229                                       bool enabled, bool force)
1230 {
1231         efx_oword_t int_en_reg_ker;
1232         unsigned int level = 0;
1233
1234         if (EFX_WORKAROUND_17213(efx) && !EFX_INT_MODE_USE_MSI(efx))
1235                 /* Set the level always even if we're generating a test
1236                  * interrupt, because our legacy interrupt handler is safe */
1237                 level = 0x1f;
1238
1239         EFX_POPULATE_OWORD_3(int_en_reg_ker,
1240                              FRF_AZ_KER_INT_LEVE_SEL, level,
1241                              FRF_AZ_KER_INT_KER, force,
1242                              FRF_AZ_DRV_INT_EN_KER, enabled);
1243         efx_writeo(efx, &int_en_reg_ker, FR_AZ_INT_EN_KER);
1244 }
1245
1246 void efx_nic_enable_interrupts(struct efx_nic *efx)
1247 {
1248         struct efx_channel *channel;
1249
1250         EFX_ZERO_OWORD(*((efx_oword_t *) efx->irq_status.addr));
1251         wmb(); /* Ensure interrupt vector is clear before interrupts enabled */
1252
1253         /* Enable interrupts */
1254         efx_nic_interrupts(efx, true, false);
1255
1256         /* Force processing of all the channels to get the EVQ RPTRs up to
1257            date */
1258         efx_for_each_channel(channel, efx)
1259                 efx_schedule_channel(channel);
1260 }
1261
1262 void efx_nic_disable_interrupts(struct efx_nic *efx)
1263 {
1264         /* Disable interrupts */
1265         efx_nic_interrupts(efx, false, false);
1266 }
1267
1268 /* Generate a test interrupt
1269  * Interrupt must already have been enabled, otherwise nasty things
1270  * may happen.
1271  */
1272 void efx_nic_generate_interrupt(struct efx_nic *efx)
1273 {
1274         efx_nic_interrupts(efx, true, true);
1275 }
1276
1277 /* Process a fatal interrupt
1278  * Disable bus mastering ASAP and schedule a reset
1279  */
1280 irqreturn_t efx_nic_fatal_interrupt(struct efx_nic *efx)
1281 {
1282         struct falcon_nic_data *nic_data = efx->nic_data;
1283         efx_oword_t *int_ker = efx->irq_status.addr;
1284         efx_oword_t fatal_intr;
1285         int error, mem_perr;
1286
1287         efx_reado(efx, &fatal_intr, FR_AZ_FATAL_INTR_KER);
1288         error = EFX_OWORD_FIELD(fatal_intr, FRF_AZ_FATAL_INTR);
1289
1290         EFX_ERR(efx, "SYSTEM ERROR " EFX_OWORD_FMT " status "
1291                 EFX_OWORD_FMT ": %s\n", EFX_OWORD_VAL(*int_ker),
1292                 EFX_OWORD_VAL(fatal_intr),
1293                 error ? "disabling bus mastering" : "no recognised error");
1294         if (error == 0)
1295                 goto out;
1296
1297         /* If this is a memory parity error dump which blocks are offending */
1298         mem_perr = EFX_OWORD_FIELD(fatal_intr, FRF_AZ_MEM_PERR_INT_KER);
1299         if (mem_perr) {
1300                 efx_oword_t reg;
1301                 efx_reado(efx, &reg, FR_AZ_MEM_STAT);
1302                 EFX_ERR(efx, "SYSTEM ERROR: memory parity error "
1303                         EFX_OWORD_FMT "\n", EFX_OWORD_VAL(reg));
1304         }
1305
1306         /* Disable both devices */
1307         pci_clear_master(efx->pci_dev);
1308         if (efx_nic_is_dual_func(efx))
1309                 pci_clear_master(nic_data->pci_dev2);
1310         efx_nic_disable_interrupts(efx);
1311
1312         /* Count errors and reset or disable the NIC accordingly */
1313         if (efx->int_error_count == 0 ||
1314             time_after(jiffies, efx->int_error_expire)) {
1315                 efx->int_error_count = 0;
1316                 efx->int_error_expire =
1317                         jiffies + EFX_INT_ERROR_EXPIRE * HZ;
1318         }
1319         if (++efx->int_error_count < EFX_MAX_INT_ERRORS) {
1320                 EFX_ERR(efx, "SYSTEM ERROR - reset scheduled\n");
1321                 efx_schedule_reset(efx, RESET_TYPE_INT_ERROR);
1322         } else {
1323                 EFX_ERR(efx, "SYSTEM ERROR - max number of errors seen."
1324                         "NIC will be disabled\n");
1325                 efx_schedule_reset(efx, RESET_TYPE_DISABLE);
1326         }
1327 out:
1328         return IRQ_HANDLED;
1329 }
1330
1331 /* Handle a legacy interrupt
1332  * Acknowledges the interrupt and schedule event queue processing.
1333  */
1334 static irqreturn_t efx_legacy_interrupt(int irq, void *dev_id)
1335 {
1336         struct efx_nic *efx = dev_id;
1337         efx_oword_t *int_ker = efx->irq_status.addr;
1338         irqreturn_t result = IRQ_NONE;
1339         struct efx_channel *channel;
1340         efx_dword_t reg;
1341         u32 queues;
1342         int syserr;
1343
1344         /* Read the ISR which also ACKs the interrupts */
1345         efx_readd(efx, &reg, FR_BZ_INT_ISR0);
1346         queues = EFX_EXTRACT_DWORD(reg, 0, 31);
1347
1348         /* Check to see if we have a serious error condition */
1349         syserr = EFX_OWORD_FIELD(*int_ker, FSF_AZ_NET_IVEC_FATAL_INT);
1350         if (unlikely(syserr))
1351                 return efx_nic_fatal_interrupt(efx);
1352
1353         if (queues != 0) {
1354                 if (EFX_WORKAROUND_15783(efx))
1355                         efx->irq_zero_count = 0;
1356
1357                 /* Schedule processing of any interrupting queues */
1358                 efx_for_each_channel(channel, efx) {
1359                         if (queues & 1)
1360                                 efx_schedule_channel(channel);
1361                         queues >>= 1;
1362                 }
1363                 result = IRQ_HANDLED;
1364
1365         } else if (EFX_WORKAROUND_15783(efx) &&
1366                    efx->irq_zero_count++ == 0) {
1367                 efx_qword_t *event;
1368
1369                 /* Ensure we rearm all event queues */
1370                 efx_for_each_channel(channel, efx) {
1371                         event = efx_event(channel, channel->eventq_read_ptr);
1372                         if (efx_event_present(event))
1373                                 efx_schedule_channel(channel);
1374                 }
1375
1376                 result = IRQ_HANDLED;
1377         }
1378
1379         if (result == IRQ_HANDLED) {
1380                 efx->last_irq_cpu = raw_smp_processor_id();
1381                 EFX_TRACE(efx, "IRQ %d on CPU %d status " EFX_DWORD_FMT "\n",
1382                           irq, raw_smp_processor_id(), EFX_DWORD_VAL(reg));
1383         } else if (EFX_WORKAROUND_15783(efx)) {
1384                 /* We can't return IRQ_HANDLED more than once on seeing ISR0=0
1385                  * because this might be a shared interrupt, but we do need to
1386                  * check the channel every time and preemptively rearm it if
1387                  * it's idle. */
1388                 efx_for_each_channel(channel, efx) {
1389                         if (!channel->work_pending)
1390                                 efx_nic_eventq_read_ack(channel);
1391                 }
1392         }
1393
1394         return result;
1395 }
1396
1397 /* Handle an MSI interrupt
1398  *
1399  * Handle an MSI hardware interrupt.  This routine schedules event
1400  * queue processing.  No interrupt acknowledgement cycle is necessary.
1401  * Also, we never need to check that the interrupt is for us, since
1402  * MSI interrupts cannot be shared.
1403  */
1404 static irqreturn_t efx_msi_interrupt(int irq, void *dev_id)
1405 {
1406         struct efx_channel *channel = dev_id;
1407         struct efx_nic *efx = channel->efx;
1408         efx_oword_t *int_ker = efx->irq_status.addr;
1409         int syserr;
1410
1411         efx->last_irq_cpu = raw_smp_processor_id();
1412         EFX_TRACE(efx, "IRQ %d on CPU %d status " EFX_OWORD_FMT "\n",
1413                   irq, raw_smp_processor_id(), EFX_OWORD_VAL(*int_ker));
1414
1415         /* Check to see if we have a serious error condition */
1416         syserr = EFX_OWORD_FIELD(*int_ker, FSF_AZ_NET_IVEC_FATAL_INT);
1417         if (unlikely(syserr))
1418                 return efx_nic_fatal_interrupt(efx);
1419
1420         /* Schedule processing of the channel */
1421         efx_schedule_channel(channel);
1422
1423         return IRQ_HANDLED;
1424 }
1425
1426
1427 /* Setup RSS indirection table.
1428  * This maps from the hash value of the packet to RXQ
1429  */
1430 static void efx_setup_rss_indir_table(struct efx_nic *efx)
1431 {
1432         int i = 0;
1433         unsigned long offset;
1434         efx_dword_t dword;
1435
1436         if (efx_nic_rev(efx) < EFX_REV_FALCON_B0)
1437                 return;
1438
1439         for (offset = FR_BZ_RX_INDIRECTION_TBL;
1440              offset < FR_BZ_RX_INDIRECTION_TBL + 0x800;
1441              offset += 0x10) {
1442                 EFX_POPULATE_DWORD_1(dword, FRF_BZ_IT_QUEUE,
1443                                      i % efx->n_rx_queues);
1444                 efx_writed(efx, &dword, offset);
1445                 i++;
1446         }
1447 }
1448
1449 /* Hook interrupt handler(s)
1450  * Try MSI and then legacy interrupts.
1451  */
1452 int efx_nic_init_interrupt(struct efx_nic *efx)
1453 {
1454         struct efx_channel *channel;
1455         int rc;
1456
1457         if (!EFX_INT_MODE_USE_MSI(efx)) {
1458                 irq_handler_t handler;
1459                 if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0)
1460                         handler = efx_legacy_interrupt;
1461                 else
1462                         handler = falcon_legacy_interrupt_a1;
1463
1464                 rc = request_irq(efx->legacy_irq, handler, IRQF_SHARED,
1465                                  efx->name, efx);
1466                 if (rc) {
1467                         EFX_ERR(efx, "failed to hook legacy IRQ %d\n",
1468                                 efx->pci_dev->irq);
1469                         goto fail1;
1470                 }
1471                 return 0;
1472         }
1473
1474         /* Hook MSI or MSI-X interrupt */
1475         efx_for_each_channel(channel, efx) {
1476                 rc = request_irq(channel->irq, efx_msi_interrupt,
1477                                  IRQF_PROBE_SHARED, /* Not shared */
1478                                  channel->name, channel);
1479                 if (rc) {
1480                         EFX_ERR(efx, "failed to hook IRQ %d\n", channel->irq);
1481                         goto fail2;
1482                 }
1483         }
1484
1485         return 0;
1486
1487  fail2:
1488         efx_for_each_channel(channel, efx)
1489                 free_irq(channel->irq, channel);
1490  fail1:
1491         return rc;
1492 }
1493
1494 void efx_nic_fini_interrupt(struct efx_nic *efx)
1495 {
1496         struct efx_channel *channel;
1497         efx_oword_t reg;
1498
1499         /* Disable MSI/MSI-X interrupts */
1500         efx_for_each_channel(channel, efx) {
1501                 if (channel->irq)
1502                         free_irq(channel->irq, channel);
1503         }
1504
1505         /* ACK legacy interrupt */
1506         if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0)
1507                 efx_reado(efx, &reg, FR_BZ_INT_ISR0);
1508         else
1509                 falcon_irq_ack_a1(efx);
1510
1511         /* Disable legacy interrupt */
1512         if (efx->legacy_irq)
1513                 free_irq(efx->legacy_irq, efx);
1514 }
1515
1516 u32 efx_nic_fpga_ver(struct efx_nic *efx)
1517 {
1518         efx_oword_t altera_build;
1519         efx_reado(efx, &altera_build, FR_AZ_ALTERA_BUILD);
1520         return EFX_OWORD_FIELD(altera_build, FRF_AZ_ALTERA_BUILD_VER);
1521 }
1522
1523 void efx_nic_init_common(struct efx_nic *efx)
1524 {
1525         efx_oword_t temp;
1526
1527         /* Set positions of descriptor caches in SRAM. */
1528         EFX_POPULATE_OWORD_1(temp, FRF_AZ_SRM_TX_DC_BASE_ADR,
1529                              efx->type->tx_dc_base / 8);
1530         efx_writeo(efx, &temp, FR_AZ_SRM_TX_DC_CFG);
1531         EFX_POPULATE_OWORD_1(temp, FRF_AZ_SRM_RX_DC_BASE_ADR,
1532                              efx->type->rx_dc_base / 8);
1533         efx_writeo(efx, &temp, FR_AZ_SRM_RX_DC_CFG);
1534
1535         /* Set TX descriptor cache size. */
1536         BUILD_BUG_ON(TX_DC_ENTRIES != (8 << TX_DC_ENTRIES_ORDER));
1537         EFX_POPULATE_OWORD_1(temp, FRF_AZ_TX_DC_SIZE, TX_DC_ENTRIES_ORDER);
1538         efx_writeo(efx, &temp, FR_AZ_TX_DC_CFG);
1539
1540         /* Set RX descriptor cache size.  Set low watermark to size-8, as
1541          * this allows most efficient prefetching.
1542          */
1543         BUILD_BUG_ON(RX_DC_ENTRIES != (8 << RX_DC_ENTRIES_ORDER));
1544         EFX_POPULATE_OWORD_1(temp, FRF_AZ_RX_DC_SIZE, RX_DC_ENTRIES_ORDER);
1545         efx_writeo(efx, &temp, FR_AZ_RX_DC_CFG);
1546         EFX_POPULATE_OWORD_1(temp, FRF_AZ_RX_DC_PF_LWM, RX_DC_ENTRIES - 8);
1547         efx_writeo(efx, &temp, FR_AZ_RX_DC_PF_WM);
1548
1549         /* Program INT_KER address */
1550         EFX_POPULATE_OWORD_2(temp,
1551                              FRF_AZ_NORM_INT_VEC_DIS_KER,
1552                              EFX_INT_MODE_USE_MSI(efx),
1553                              FRF_AZ_INT_ADR_KER, efx->irq_status.dma_addr);
1554         efx_writeo(efx, &temp, FR_AZ_INT_ADR_KER);
1555
1556         /* Enable all the genuinely fatal interrupts.  (They are still
1557          * masked by the overall interrupt mask, controlled by
1558          * falcon_interrupts()).
1559          *
1560          * Note: All other fatal interrupts are enabled
1561          */
1562         EFX_POPULATE_OWORD_3(temp,
1563                              FRF_AZ_ILL_ADR_INT_KER_EN, 1,
1564                              FRF_AZ_RBUF_OWN_INT_KER_EN, 1,
1565                              FRF_AZ_TBUF_OWN_INT_KER_EN, 1);
1566         EFX_INVERT_OWORD(temp);
1567         efx_writeo(efx, &temp, FR_AZ_FATAL_INTR_KER);
1568
1569         efx_setup_rss_indir_table(efx);
1570
1571         /* Disable the ugly timer-based TX DMA backoff and allow TX DMA to be
1572          * controlled by the RX FIFO fill level. Set arbitration to one pkt/Q.
1573          */
1574         efx_reado(efx, &temp, FR_AZ_TX_RESERVED);
1575         EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_RX_SPACER, 0xfe);
1576         EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_RX_SPACER_EN, 1);
1577         EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_ONE_PKT_PER_Q, 1);
1578         EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_PUSH_EN, 0);
1579         EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_DIS_NON_IP_EV, 1);
1580         /* Enable SW_EV to inherit in char driver - assume harmless here */
1581         EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_SOFT_EVT_EN, 1);
1582         /* Prefetch threshold 2 => fetch when descriptor cache half empty */
1583         EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_PREF_THRESHOLD, 2);
1584         /* Disable hardware watchdog which can misfire */
1585         EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_PREF_WD_TMR, 0x3fffff);
1586         /* Squash TX of packets of 16 bytes or less */
1587         if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0)
1588                 EFX_SET_OWORD_FIELD(temp, FRF_BZ_TX_FLUSH_MIN_LEN_EN, 1);
1589         efx_writeo(efx, &temp, FR_AZ_TX_RESERVED);
1590 }