SAFE public projects git trees. - safe/jmp/linux-2.6/blob - arch/x86/kvm/vmx.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * This module enables machines with Intel VT-x extensions to run virtual
   5  * machines without emulation or binary translation.
   6  *
   7  * Copyright (C) 2006 Qumranet, Inc.
   8  *
   9  * Authors:
  10  *   Avi Kivity   <avi@qumranet.com>
  11  *   Yaniv Kamay  <yaniv@qumranet.com>
  12  *
  13  * This work is licensed under the terms of the GNU GPL, version 2.  See
  14  * the COPYING file in the top-level directory.
  15  *
  16  */
  17
  18 #include "irq.h"
  19 #include "mmu.h"
  20
  21 #include <linux/kvm_host.h>
  22 #include <linux/module.h>
  23 #include <linux/kernel.h>
  24 #include <linux/mm.h>
  25 #include <linux/highmem.h>
  26 #include <linux/sched.h>
  27 #include <linux/moduleparam.h>
  28 #include "kvm_cache_regs.h"
  29 #include "x86.h"
  30
  31 #include <asm/io.h>
  32 #include <asm/desc.h>
  33 #include <asm/vmx.h>
  34 #include <asm/virtext.h>
  35
  36 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  37
  38 MODULE_AUTHOR("Qumranet");
  39 MODULE_LICENSE("GPL");
  40
  41 static int bypass_guest_pf = 1;
  42 module_param(bypass_guest_pf, bool, 0);
  43
  44 static int enable_vpid = 1;
  45 module_param(enable_vpid, bool, 0);
  46
  47 static int flexpriority_enabled = 1;
  48 module_param(flexpriority_enabled, bool, 0);
  49
  50 static int enable_ept = 1;
  51 module_param(enable_ept, bool, 0);
  52
  53 static int emulate_invalid_guest_state = 0;
  54 module_param(emulate_invalid_guest_state, bool, 0);
  55
  56 struct vmcs {
  57         u32 revision_id;
  58         u32 abort;
  59         char data[0];
  60 };
  61
  62 struct vcpu_vmx {
  63         struct kvm_vcpu       vcpu;
  64         struct list_head      local_vcpus_link;
  65         unsigned long         host_rsp;
  66         int                   launched;
  67         u8                    fail;
  68         u32                   idt_vectoring_info;
  69         struct kvm_msr_entry *guest_msrs;
  70         struct kvm_msr_entry *host_msrs;
  71         int                   nmsrs;
  72         int                   save_nmsrs;
  73         int                   msr_offset_efer;
  74 #ifdef CONFIG_X86_64
  75         int                   msr_offset_kernel_gs_base;
  76 #endif
  77         struct vmcs          *vmcs;
  78         struct {
  79                 int           loaded;
  80                 u16           fs_sel, gs_sel, ldt_sel;
  81                 int           gs_ldt_reload_needed;
  82                 int           fs_reload_needed;
  83                 int           guest_efer_loaded;
  84         } host_state;
  85         struct {
  86                 struct {
  87                         bool pending;
  88                         u8 vector;
  89                         unsigned rip;
  90                 } irq;
  91         } rmode;
  92         int vpid;
  93         bool emulation_required;
  94
  95         /* Support for vnmi-less CPUs */
  96         int soft_vnmi_blocked;
  97         ktime_t entry_time;
  98         s64 vnmi_blocked_time;
  99 };
 100
 101 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
 102 {
 103         return container_of(vcpu, struct vcpu_vmx, vcpu);
 104 }
 105
 106 static int init_rmode(struct kvm *kvm);
 107 static u64 construct_eptp(unsigned long root_hpa);
 108
 109 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
 110 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
 111 static DEFINE_PER_CPU(struct list_head, vcpus_on_cpu);
 112
 113 static struct page *vmx_io_bitmap_a;
 114 static struct page *vmx_io_bitmap_b;
 115 static struct page *vmx_msr_bitmap;
 116
 117 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
 118 static DEFINE_SPINLOCK(vmx_vpid_lock);
 119
 120 static struct vmcs_config {
 121         int size;
 122         int order;
 123         u32 revision_id;
 124         u32 pin_based_exec_ctrl;
 125         u32 cpu_based_exec_ctrl;
 126         u32 cpu_based_2nd_exec_ctrl;
 127         u32 vmexit_ctrl;
 128         u32 vmentry_ctrl;
 129 } vmcs_config;
 130
 131 static struct vmx_capability {
 132         u32 ept;
 133         u32 vpid;
 134 } vmx_capability;
 135
 136 #define VMX_SEGMENT_FIELD(seg)                                  \
 137         [VCPU_SREG_##seg] = {                                   \
 138                 .selector = GUEST_##seg##_SELECTOR,             \
 139                 .base = GUEST_##seg##_BASE,                     \
 140                 .limit = GUEST_##seg##_LIMIT,                   \
 141                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
 142         }
 143
 144 static struct kvm_vmx_segment_field {
 145         unsigned selector;
 146         unsigned base;
 147         unsigned limit;
 148         unsigned ar_bytes;
 149 } kvm_vmx_segment_fields[] = {
 150         VMX_SEGMENT_FIELD(CS),
 151         VMX_SEGMENT_FIELD(DS),
 152         VMX_SEGMENT_FIELD(ES),
 153         VMX_SEGMENT_FIELD(FS),
 154         VMX_SEGMENT_FIELD(GS),
 155         VMX_SEGMENT_FIELD(SS),
 156         VMX_SEGMENT_FIELD(TR),
 157         VMX_SEGMENT_FIELD(LDTR),
 158 };
 159
 160 /*
 161  * Keep MSR_K6_STAR at the end, as setup_msrs() will try to optimize it
 162  * away by decrementing the array size.
 163  */
 164 static const u32 vmx_msr_index[] = {
 165 #ifdef CONFIG_X86_64
 166         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR, MSR_KERNEL_GS_BASE,
 167 #endif
 168         MSR_EFER, MSR_K6_STAR,
 169 };
 170 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
 171
 172 static void load_msrs(struct kvm_msr_entry *e, int n)
 173 {
 174         int i;
 175
 176         for (i = 0; i < n; ++i)
 177                 wrmsrl(e[i].index, e[i].data);
 178 }
 179
 180 static void save_msrs(struct kvm_msr_entry *e, int n)
 181 {
 182         int i;
 183
 184         for (i = 0; i < n; ++i)
 185                 rdmsrl(e[i].index, e[i].data);
 186 }
 187
 188 static inline int is_page_fault(u32 intr_info)
 189 {
 190         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 191                              INTR_INFO_VALID_MASK)) ==
 192                 (INTR_TYPE_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
 193 }
 194
 195 static inline int is_no_device(u32 intr_info)
 196 {
 197         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 198                              INTR_INFO_VALID_MASK)) ==
 199                 (INTR_TYPE_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
 200 }
 201
 202 static inline int is_invalid_opcode(u32 intr_info)
 203 {
 204         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 205                              INTR_INFO_VALID_MASK)) ==
 206                 (INTR_TYPE_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
 207 }
 208
 209 static inline int is_external_interrupt(u32 intr_info)
 210 {
 211         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
 212                 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
 213 }
 214
 215 static inline int cpu_has_vmx_msr_bitmap(void)
 216 {
 217         return (vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS);
 218 }
 219
 220 static inline int cpu_has_vmx_tpr_shadow(void)
 221 {
 222         return (vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW);
 223 }
 224
 225 static inline int vm_need_tpr_shadow(struct kvm *kvm)
 226 {
 227         return ((cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm)));
 228 }
 229
 230 static inline int cpu_has_secondary_exec_ctrls(void)
 231 {
 232         return (vmcs_config.cpu_based_exec_ctrl &
 233                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS);
 234 }
 235
 236 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
 237 {
 238         return flexpriority_enabled
 239                 && (vmcs_config.cpu_based_2nd_exec_ctrl &
 240                     SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
 241 }
 242
 243 static inline int cpu_has_vmx_invept_individual_addr(void)
 244 {
 245         return (!!(vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT));
 246 }
 247
 248 static inline int cpu_has_vmx_invept_context(void)
 249 {
 250         return (!!(vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT));
 251 }
 252
 253 static inline int cpu_has_vmx_invept_global(void)
 254 {
 255         return (!!(vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT));
 256 }
 257
 258 static inline int cpu_has_vmx_ept(void)
 259 {
 260         return (vmcs_config.cpu_based_2nd_exec_ctrl &
 261                 SECONDARY_EXEC_ENABLE_EPT);
 262 }
 263
 264 static inline int vm_need_ept(void)
 265 {
 266         return (cpu_has_vmx_ept() && enable_ept);
 267 }
 268
 269 static inline int vm_need_virtualize_apic_accesses(struct kvm *kvm)
 270 {
 271         return ((cpu_has_vmx_virtualize_apic_accesses()) &&
 272                 (irqchip_in_kernel(kvm)));
 273 }
 274
 275 static inline int cpu_has_vmx_vpid(void)
 276 {
 277         return (vmcs_config.cpu_based_2nd_exec_ctrl &
 278                 SECONDARY_EXEC_ENABLE_VPID);
 279 }
 280
 281 static inline int cpu_has_virtual_nmis(void)
 282 {
 283         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
 284 }
 285
 286 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
 287 {
 288         int i;
 289
 290         for (i = 0; i < vmx->nmsrs; ++i)
 291                 if (vmx->guest_msrs[i].index == msr)
 292                         return i;
 293         return -1;
 294 }
 295
 296 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
 297 {
 298     struct {
 299         u64 vpid : 16;
 300         u64 rsvd : 48;
 301         u64 gva;
 302     } operand = { vpid, 0, gva };
 303
 304     asm volatile (__ex(ASM_VMX_INVVPID)
 305                   /* CF==1 or ZF==1 --> rc = -1 */
 306                   "; ja 1f ; ud2 ; 1:"
 307                   : : "a"(&operand), "c"(ext) : "cc", "memory");
 308 }
 309
 310 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
 311 {
 312         struct {
 313                 u64 eptp, gpa;
 314         } operand = {eptp, gpa};
 315
 316         asm volatile (__ex(ASM_VMX_INVEPT)
 317                         /* CF==1 or ZF==1 --> rc = -1 */
 318                         "; ja 1f ; ud2 ; 1:\n"
 319                         : : "a" (&operand), "c" (ext) : "cc", "memory");
 320 }
 321
 322 static struct kvm_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
 323 {
 324         int i;
 325
 326         i = __find_msr_index(vmx, msr);
 327         if (i >= 0)
 328                 return &vmx->guest_msrs[i];
 329         return NULL;
 330 }
 331
 332 static void vmcs_clear(struct vmcs *vmcs)
 333 {
 334         u64 phys_addr = __pa(vmcs);
 335         u8 error;
 336
 337         asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
 338                       : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
 339                       : "cc", "memory");
 340         if (error)
 341                 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
 342                        vmcs, phys_addr);
 343 }
 344
 345 static void __vcpu_clear(void *arg)
 346 {
 347         struct vcpu_vmx *vmx = arg;
 348         int cpu = raw_smp_processor_id();
 349
 350         if (vmx->vcpu.cpu == cpu)
 351                 vmcs_clear(vmx->vmcs);
 352         if (per_cpu(current_vmcs, cpu) == vmx->vmcs)
 353                 per_cpu(current_vmcs, cpu) = NULL;
 354         rdtscll(vmx->vcpu.arch.host_tsc);
 355         list_del(&vmx->local_vcpus_link);
 356         vmx->vcpu.cpu = -1;
 357         vmx->launched = 0;
 358 }
 359
 360 static void vcpu_clear(struct vcpu_vmx *vmx)
 361 {
 362         if (vmx->vcpu.cpu == -1)
 363                 return;
 364         smp_call_function_single(vmx->vcpu.cpu, __vcpu_clear, vmx, 1);
 365 }
 366
 367 static inline void vpid_sync_vcpu_all(struct vcpu_vmx *vmx)
 368 {
 369         if (vmx->vpid == 0)
 370                 return;
 371
 372         __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
 373 }
 374
 375 static inline void ept_sync_global(void)
 376 {
 377         if (cpu_has_vmx_invept_global())
 378                 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
 379 }
 380
 381 static inline void ept_sync_context(u64 eptp)
 382 {
 383         if (vm_need_ept()) {
 384                 if (cpu_has_vmx_invept_context())
 385                         __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
 386                 else
 387                         ept_sync_global();
 388         }
 389 }
 390
 391 static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
 392 {
 393         if (vm_need_ept()) {
 394                 if (cpu_has_vmx_invept_individual_addr())
 395                         __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
 396                                         eptp, gpa);
 397                 else
 398                         ept_sync_context(eptp);
 399         }
 400 }
 401
 402 static unsigned long vmcs_readl(unsigned long field)
 403 {
 404         unsigned long value;
 405
 406         asm volatile (__ex(ASM_VMX_VMREAD_RDX_RAX)
 407                       : "=a"(value) : "d"(field) : "cc");
 408         return value;
 409 }
 410
 411 static u16 vmcs_read16(unsigned long field)
 412 {
 413         return vmcs_readl(field);
 414 }
 415
 416 static u32 vmcs_read32(unsigned long field)
 417 {
 418         return vmcs_readl(field);
 419 }
 420
 421 static u64 vmcs_read64(unsigned long field)
 422 {
 423 #ifdef CONFIG_X86_64
 424         return vmcs_readl(field);
 425 #else
 426         return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
 427 #endif
 428 }
 429
 430 static noinline void vmwrite_error(unsigned long field, unsigned long value)
 431 {
 432         printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
 433                field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
 434         dump_stack();
 435 }
 436
 437 static void vmcs_writel(unsigned long field, unsigned long value)
 438 {
 439         u8 error;
 440
 441         asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
 442                        : "=q"(error) : "a"(value), "d"(field) : "cc");
 443         if (unlikely(error))
 444                 vmwrite_error(field, value);
 445 }
 446
 447 static void vmcs_write16(unsigned long field, u16 value)
 448 {
 449         vmcs_writel(field, value);
 450 }
 451
 452 static void vmcs_write32(unsigned long field, u32 value)
 453 {
 454         vmcs_writel(field, value);
 455 }
 456
 457 static void vmcs_write64(unsigned long field, u64 value)
 458 {
 459         vmcs_writel(field, value);
 460 #ifndef CONFIG_X86_64
 461         asm volatile ("");
 462         vmcs_writel(field+1, value >> 32);
 463 #endif
 464 }
 465
 466 static void vmcs_clear_bits(unsigned long field, u32 mask)
 467 {
 468         vmcs_writel(field, vmcs_readl(field) & ~mask);
 469 }
 470
 471 static void vmcs_set_bits(unsigned long field, u32 mask)
 472 {
 473         vmcs_writel(field, vmcs_readl(field) | mask);
 474 }
 475
 476 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
 477 {
 478         u32 eb;
 479
 480         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR);
 481         if (!vcpu->fpu_active)
 482                 eb |= 1u << NM_VECTOR;
 483         if (vcpu->guest_debug.enabled)
 484                 eb |= 1u << DB_VECTOR;
 485         if (vcpu->arch.rmode.active)
 486                 eb = ~0;
 487         if (vm_need_ept())
 488                 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
 489         vmcs_write32(EXCEPTION_BITMAP, eb);
 490 }
 491
 492 static void reload_tss(void)
 493 {
 494         /*
 495          * VT restores TR but not its size.  Useless.
 496          */
 497         struct descriptor_table gdt;
 498         struct desc_struct *descs;
 499
 500         kvm_get_gdt(&gdt);
 501         descs = (void *)gdt.base;
 502         descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
 503         load_TR_desc();
 504 }
 505
 506 static void load_transition_efer(struct vcpu_vmx *vmx)
 507 {
 508         int efer_offset = vmx->msr_offset_efer;
 509         u64 host_efer = vmx->host_msrs[efer_offset].data;
 510         u64 guest_efer = vmx->guest_msrs[efer_offset].data;
 511         u64 ignore_bits;
 512
 513         if (efer_offset < 0)
 514                 return;
 515         /*
 516          * NX is emulated; LMA and LME handled by hardware; SCE meaninless
 517          * outside long mode
 518          */
 519         ignore_bits = EFER_NX | EFER_SCE;
 520 #ifdef CONFIG_X86_64
 521         ignore_bits |= EFER_LMA | EFER_LME;
 522         /* SCE is meaningful only in long mode on Intel */
 523         if (guest_efer & EFER_LMA)
 524                 ignore_bits &= ~(u64)EFER_SCE;
 525 #endif
 526         if ((guest_efer & ~ignore_bits) == (host_efer & ~ignore_bits))
 527                 return;
 528
 529         vmx->host_state.guest_efer_loaded = 1;
 530         guest_efer &= ~ignore_bits;
 531         guest_efer |= host_efer & ignore_bits;
 532         wrmsrl(MSR_EFER, guest_efer);
 533         vmx->vcpu.stat.efer_reload++;
 534 }
 535
 536 static void reload_host_efer(struct vcpu_vmx *vmx)
 537 {
 538         if (vmx->host_state.guest_efer_loaded) {
 539                 vmx->host_state.guest_efer_loaded = 0;
 540                 load_msrs(vmx->host_msrs + vmx->msr_offset_efer, 1);
 541         }
 542 }
 543
 544 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
 545 {
 546         struct vcpu_vmx *vmx = to_vmx(vcpu);
 547
 548         if (vmx->host_state.loaded)
 549                 return;
 550
 551         vmx->host_state.loaded = 1;
 552         /*
 553          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
 554          * allow segment selectors with cpl > 0 or ti == 1.
 555          */
 556         vmx->host_state.ldt_sel = kvm_read_ldt();
 557         vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
 558         vmx->host_state.fs_sel = kvm_read_fs();
 559         if (!(vmx->host_state.fs_sel & 7)) {
 560                 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
 561                 vmx->host_state.fs_reload_needed = 0;
 562         } else {
 563                 vmcs_write16(HOST_FS_SELECTOR, 0);
 564                 vmx->host_state.fs_reload_needed = 1;
 565         }
 566         vmx->host_state.gs_sel = kvm_read_gs();
 567         if (!(vmx->host_state.gs_sel & 7))
 568                 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
 569         else {
 570                 vmcs_write16(HOST_GS_SELECTOR, 0);
 571                 vmx->host_state.gs_ldt_reload_needed = 1;
 572         }
 573
 574 #ifdef CONFIG_X86_64
 575         vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
 576         vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
 577 #else
 578         vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
 579         vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
 580 #endif
 581
 582 #ifdef CONFIG_X86_64
 583         if (is_long_mode(&vmx->vcpu))
 584                 save_msrs(vmx->host_msrs +
 585                           vmx->msr_offset_kernel_gs_base, 1);
 586
 587 #endif
 588         load_msrs(vmx->guest_msrs, vmx->save_nmsrs);
 589         load_transition_efer(vmx);
 590 }
 591
 592 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
 593 {
 594         unsigned long flags;
 595
 596         if (!vmx->host_state.loaded)
 597                 return;
 598
 599         ++vmx->vcpu.stat.host_state_reload;
 600         vmx->host_state.loaded = 0;
 601         if (vmx->host_state.fs_reload_needed)
 602                 kvm_load_fs(vmx->host_state.fs_sel);
 603         if (vmx->host_state.gs_ldt_reload_needed) {
 604                 kvm_load_ldt(vmx->host_state.ldt_sel);
 605                 /*
 606                  * If we have to reload gs, we must take care to
 607                  * preserve our gs base.
 608                  */
 609                 local_irq_save(flags);
 610                 kvm_load_gs(vmx->host_state.gs_sel);
 611 #ifdef CONFIG_X86_64
 612                 wrmsrl(MSR_GS_BASE, vmcs_readl(HOST_GS_BASE));
 613 #endif
 614                 local_irq_restore(flags);
 615         }
 616         reload_tss();
 617         save_msrs(vmx->guest_msrs, vmx->save_nmsrs);
 618         load_msrs(vmx->host_msrs, vmx->save_nmsrs);
 619         reload_host_efer(vmx);
 620 }
 621
 622 static void vmx_load_host_state(struct vcpu_vmx *vmx)
 623 {
 624         preempt_disable();
 625         __vmx_load_host_state(vmx);
 626         preempt_enable();
 627 }
 628
 629 /*
 630  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
 631  * vcpu mutex is already taken.
 632  */
 633 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
 634 {
 635         struct vcpu_vmx *vmx = to_vmx(vcpu);
 636         u64 phys_addr = __pa(vmx->vmcs);
 637         u64 tsc_this, delta, new_offset;
 638
 639         if (vcpu->cpu != cpu) {
 640                 vcpu_clear(vmx);
 641                 kvm_migrate_timers(vcpu);
 642                 vpid_sync_vcpu_all(vmx);
 643                 local_irq_disable();
 644                 list_add(&vmx->local_vcpus_link,
 645                          &per_cpu(vcpus_on_cpu, cpu));
 646                 local_irq_enable();
 647         }
 648
 649         if (per_cpu(current_vmcs, cpu) != vmx->vmcs) {
 650                 u8 error;
 651
 652                 per_cpu(current_vmcs, cpu) = vmx->vmcs;
 653                 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
 654                               : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
 655                               : "cc");
 656                 if (error)
 657                         printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
 658                                vmx->vmcs, phys_addr);
 659         }
 660
 661         if (vcpu->cpu != cpu) {
 662                 struct descriptor_table dt;
 663                 unsigned long sysenter_esp;
 664
 665                 vcpu->cpu = cpu;
 666                 /*
 667                  * Linux uses per-cpu TSS and GDT, so set these when switching
 668                  * processors.
 669                  */
 670                 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
 671                 kvm_get_gdt(&dt);
 672                 vmcs_writel(HOST_GDTR_BASE, dt.base);   /* 22.2.4 */
 673
 674                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
 675                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
 676
 677                 /*
 678                  * Make sure the time stamp counter is monotonous.
 679                  */
 680                 rdtscll(tsc_this);
 681                 if (tsc_this < vcpu->arch.host_tsc) {
 682                         delta = vcpu->arch.host_tsc - tsc_this;
 683                         new_offset = vmcs_read64(TSC_OFFSET) + delta;
 684                         vmcs_write64(TSC_OFFSET, new_offset);
 685                 }
 686         }
 687 }
 688
 689 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
 690 {
 691         __vmx_load_host_state(to_vmx(vcpu));
 692 }
 693
 694 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
 695 {
 696         if (vcpu->fpu_active)
 697                 return;
 698         vcpu->fpu_active = 1;
 699         vmcs_clear_bits(GUEST_CR0, X86_CR0_TS);
 700         if (vcpu->arch.cr0 & X86_CR0_TS)
 701                 vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
 702         update_exception_bitmap(vcpu);
 703 }
 704
 705 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
 706 {
 707         if (!vcpu->fpu_active)
 708                 return;
 709         vcpu->fpu_active = 0;
 710         vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
 711         update_exception_bitmap(vcpu);
 712 }
 713
 714 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
 715 {
 716         return vmcs_readl(GUEST_RFLAGS);
 717 }
 718
 719 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
 720 {
 721         if (vcpu->arch.rmode.active)
 722                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
 723         vmcs_writel(GUEST_RFLAGS, rflags);
 724 }
 725
 726 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
 727 {
 728         unsigned long rip;
 729         u32 interruptibility;
 730
 731         rip = kvm_rip_read(vcpu);
 732         rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
 733         kvm_rip_write(vcpu, rip);
 734
 735         /*
 736          * We emulated an instruction, so temporary interrupt blocking
 737          * should be removed, if set.
 738          */
 739         interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
 740         if (interruptibility & 3)
 741                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
 742                              interruptibility & ~3);
 743         vcpu->arch.interrupt_window_open = 1;
 744 }
 745
 746 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
 747                                 bool has_error_code, u32 error_code)
 748 {
 749         struct vcpu_vmx *vmx = to_vmx(vcpu);
 750
 751         if (has_error_code)
 752                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
 753
 754         if (vcpu->arch.rmode.active) {
 755                 vmx->rmode.irq.pending = true;
 756                 vmx->rmode.irq.vector = nr;
 757                 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
 758                 if (nr == BP_VECTOR)
 759                         vmx->rmode.irq.rip++;
 760                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
 761                              nr | INTR_TYPE_SOFT_INTR
 762                              | (has_error_code ? INTR_INFO_DELIVER_CODE_MASK : 0)
 763                              | INTR_INFO_VALID_MASK);
 764                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
 765                 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
 766                 return;
 767         }
 768
 769         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
 770                      nr | INTR_TYPE_EXCEPTION
 771                      | (has_error_code ? INTR_INFO_DELIVER_CODE_MASK : 0)
 772                      | INTR_INFO_VALID_MASK);
 773 }
 774
 775 static bool vmx_exception_injected(struct kvm_vcpu *vcpu)
 776 {
 777         return false;
 778 }
 779
 780 /*
 781  * Swap MSR entry in host/guest MSR entry array.
 782  */
 783 #ifdef CONFIG_X86_64
 784 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
 785 {
 786         struct kvm_msr_entry tmp;
 787
 788         tmp = vmx->guest_msrs[to];
 789         vmx->guest_msrs[to] = vmx->guest_msrs[from];
 790         vmx->guest_msrs[from] = tmp;
 791         tmp = vmx->host_msrs[to];
 792         vmx->host_msrs[to] = vmx->host_msrs[from];
 793         vmx->host_msrs[from] = tmp;
 794 }
 795 #endif
 796
 797 /*
 798  * Set up the vmcs to automatically save and restore system
 799  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
 800  * mode, as fiddling with msrs is very expensive.
 801  */
 802 static void setup_msrs(struct vcpu_vmx *vmx)
 803 {
 804         int save_nmsrs;
 805
 806         vmx_load_host_state(vmx);
 807         save_nmsrs = 0;
 808 #ifdef CONFIG_X86_64
 809         if (is_long_mode(&vmx->vcpu)) {
 810                 int index;
 811
 812                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
 813                 if (index >= 0)
 814                         move_msr_up(vmx, index, save_nmsrs++);
 815                 index = __find_msr_index(vmx, MSR_LSTAR);
 816                 if (index >= 0)
 817                         move_msr_up(vmx, index, save_nmsrs++);
 818                 index = __find_msr_index(vmx, MSR_CSTAR);
 819                 if (index >= 0)
 820                         move_msr_up(vmx, index, save_nmsrs++);
 821                 index = __find_msr_index(vmx, MSR_KERNEL_GS_BASE);
 822                 if (index >= 0)
 823                         move_msr_up(vmx, index, save_nmsrs++);
 824                 /*
 825                  * MSR_K6_STAR is only needed on long mode guests, and only
 826                  * if efer.sce is enabled.
 827                  */
 828                 index = __find_msr_index(vmx, MSR_K6_STAR);
 829                 if ((index >= 0) && (vmx->vcpu.arch.shadow_efer & EFER_SCE))
 830                         move_msr_up(vmx, index, save_nmsrs++);
 831         }
 832 #endif
 833         vmx->save_nmsrs = save_nmsrs;
 834
 835 #ifdef CONFIG_X86_64
 836         vmx->msr_offset_kernel_gs_base =
 837                 __find_msr_index(vmx, MSR_KERNEL_GS_BASE);
 838 #endif
 839         vmx->msr_offset_efer = __find_msr_index(vmx, MSR_EFER);
 840 }
 841
 842 /*
 843  * reads and returns guest's timestamp counter "register"
 844  * guest_tsc = host_tsc + tsc_offset    -- 21.3
 845  */
 846 static u64 guest_read_tsc(void)
 847 {
 848         u64 host_tsc, tsc_offset;
 849
 850         rdtscll(host_tsc);
 851         tsc_offset = vmcs_read64(TSC_OFFSET);
 852         return host_tsc + tsc_offset;
 853 }
 854
 855 /*
 856  * writes 'guest_tsc' into guest's timestamp counter "register"
 857  * guest_tsc = host_tsc + tsc_offset ==> tsc_offset = guest_tsc - host_tsc
 858  */
 859 static void guest_write_tsc(u64 guest_tsc)
 860 {
 861         u64 host_tsc;
 862
 863         rdtscll(host_tsc);
 864         vmcs_write64(TSC_OFFSET, guest_tsc - host_tsc);
 865 }
 866
 867 /*
 868  * Reads an msr value (of 'msr_index') into 'pdata'.
 869  * Returns 0 on success, non-0 otherwise.
 870  * Assumes vcpu_load() was already called.
 871  */
 872 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
 873 {
 874         u64 data;
 875         struct kvm_msr_entry *msr;
 876
 877         if (!pdata) {
 878                 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
 879                 return -EINVAL;
 880         }
 881
 882         switch (msr_index) {
 883 #ifdef CONFIG_X86_64
 884         case MSR_FS_BASE:
 885                 data = vmcs_readl(GUEST_FS_BASE);
 886                 break;
 887         case MSR_GS_BASE:
 888                 data = vmcs_readl(GUEST_GS_BASE);
 889                 break;
 890         case MSR_EFER:
 891                 return kvm_get_msr_common(vcpu, msr_index, pdata);
 892 #endif
 893         case MSR_IA32_TIME_STAMP_COUNTER:
 894                 data = guest_read_tsc();
 895                 break;
 896         case MSR_IA32_SYSENTER_CS:
 897                 data = vmcs_read32(GUEST_SYSENTER_CS);
 898                 break;
 899         case MSR_IA32_SYSENTER_EIP:
 900                 data = vmcs_readl(GUEST_SYSENTER_EIP);
 901                 break;
 902         case MSR_IA32_SYSENTER_ESP:
 903                 data = vmcs_readl(GUEST_SYSENTER_ESP);
 904                 break;
 905         default:
 906                 msr = find_msr_entry(to_vmx(vcpu), msr_index);
 907                 if (msr) {
 908                         data = msr->data;
 909                         break;
 910                 }
 911                 return kvm_get_msr_common(vcpu, msr_index, pdata);
 912         }
 913
 914         *pdata = data;
 915         return 0;
 916 }
 917
 918 /*
 919  * Writes msr value into into the appropriate "register".
 920  * Returns 0 on success, non-0 otherwise.
 921  * Assumes vcpu_load() was already called.
 922  */
 923 static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
 924 {
 925         struct vcpu_vmx *vmx = to_vmx(vcpu);
 926         struct kvm_msr_entry *msr;
 927         int ret = 0;
 928
 929         switch (msr_index) {
 930 #ifdef CONFIG_X86_64
 931         case MSR_EFER:
 932                 vmx_load_host_state(vmx);
 933                 ret = kvm_set_msr_common(vcpu, msr_index, data);
 934                 break;
 935         case MSR_FS_BASE:
 936                 vmcs_writel(GUEST_FS_BASE, data);
 937                 break;
 938         case MSR_GS_BASE:
 939                 vmcs_writel(GUEST_GS_BASE, data);
 940                 break;
 941 #endif
 942         case MSR_IA32_SYSENTER_CS:
 943                 vmcs_write32(GUEST_SYSENTER_CS, data);
 944                 break;
 945         case MSR_IA32_SYSENTER_EIP:
 946                 vmcs_writel(GUEST_SYSENTER_EIP, data);
 947                 break;
 948         case MSR_IA32_SYSENTER_ESP:
 949                 vmcs_writel(GUEST_SYSENTER_ESP, data);
 950                 break;
 951         case MSR_IA32_TIME_STAMP_COUNTER:
 952                 guest_write_tsc(data);
 953                 break;
 954         case MSR_P6_PERFCTR0:
 955         case MSR_P6_PERFCTR1:
 956         case MSR_P6_EVNTSEL0:
 957         case MSR_P6_EVNTSEL1:
 958                 /*
 959                  * Just discard all writes to the performance counters; this
 960                  * should keep both older linux and windows 64-bit guests
 961                  * happy
 962                  */
 963                 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: 0x%x data 0x%llx\n", msr_index, data);
 964
 965                 break;
 966         case MSR_IA32_CR_PAT:
 967                 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
 968                         vmcs_write64(GUEST_IA32_PAT, data);
 969                         vcpu->arch.pat = data;
 970                         break;
 971                 }
 972                 /* Otherwise falls through to kvm_set_msr_common */
 973         default:
 974                 vmx_load_host_state(vmx);
 975                 msr = find_msr_entry(vmx, msr_index);
 976                 if (msr) {
 977                         msr->data = data;
 978                         break;
 979                 }
 980                 ret = kvm_set_msr_common(vcpu, msr_index, data);
 981         }
 982
 983         return ret;
 984 }
 985
 986 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
 987 {
 988         __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
 989         switch (reg) {
 990         case VCPU_REGS_RSP:
 991                 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
 992                 break;
 993         case VCPU_REGS_RIP:
 994                 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
 995                 break;
 996         default:
 997                 break;
 998         }
 999 }
1000
1001 static int set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_debug_guest *dbg)
1002 {
1003         unsigned long dr7 = 0x400;
1004         int old_singlestep;
1005
1006         old_singlestep = vcpu->guest_debug.singlestep;
1007
1008         vcpu->guest_debug.enabled = dbg->enabled;
1009         if (vcpu->guest_debug.enabled) {
1010                 int i;
1011
1012                 dr7 |= 0x200;  /* exact */
1013                 for (i = 0; i < 4; ++i) {
1014                         if (!dbg->breakpoints[i].enabled)
1015                                 continue;
1016                         vcpu->guest_debug.bp[i] = dbg->breakpoints[i].address;
1017                         dr7 |= 2 << (i*2);    /* global enable */
1018                         dr7 |= 0 << (i*4+16); /* execution breakpoint */
1019                 }
1020
1021                 vcpu->guest_debug.singlestep = dbg->singlestep;
1022         } else
1023                 vcpu->guest_debug.singlestep = 0;
1024
1025         if (old_singlestep && !vcpu->guest_debug.singlestep) {
1026                 unsigned long flags;
1027
1028                 flags = vmcs_readl(GUEST_RFLAGS);
1029                 flags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1030                 vmcs_writel(GUEST_RFLAGS, flags);
1031         }
1032
1033         update_exception_bitmap(vcpu);
1034         vmcs_writel(GUEST_DR7, dr7);
1035
1036         return 0;
1037 }
1038
1039 static int vmx_get_irq(struct kvm_vcpu *vcpu)
1040 {
1041         if (!vcpu->arch.interrupt.pending)
1042                 return -1;
1043         return vcpu->arch.interrupt.nr;
1044 }
1045
1046 static __init int cpu_has_kvm_support(void)
1047 {
1048         return cpu_has_vmx();
1049 }
1050
1051 static __init int vmx_disabled_by_bios(void)
1052 {
1053         u64 msr;
1054
1055         rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
1056         return (msr & (FEATURE_CONTROL_LOCKED |
1057                        FEATURE_CONTROL_VMXON_ENABLED))
1058             == FEATURE_CONTROL_LOCKED;
1059         /* locked but not enabled */
1060 }
1061
1062 static void hardware_enable(void *garbage)
1063 {
1064         int cpu = raw_smp_processor_id();
1065         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1066         u64 old;
1067
1068         INIT_LIST_HEAD(&per_cpu(vcpus_on_cpu, cpu));
1069         rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
1070         if ((old & (FEATURE_CONTROL_LOCKED |
1071                     FEATURE_CONTROL_VMXON_ENABLED))
1072             != (FEATURE_CONTROL_LOCKED |
1073                 FEATURE_CONTROL_VMXON_ENABLED))
1074                 /* enable and lock */
1075                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old |
1076                        FEATURE_CONTROL_LOCKED |
1077                        FEATURE_CONTROL_VMXON_ENABLED);
1078         write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
1079         asm volatile (ASM_VMX_VMXON_RAX
1080                       : : "a"(&phys_addr), "m"(phys_addr)
1081                       : "memory", "cc");
1082 }
1083
1084 static void vmclear_local_vcpus(void)
1085 {
1086         int cpu = raw_smp_processor_id();
1087         struct vcpu_vmx *vmx, *n;
1088
1089         list_for_each_entry_safe(vmx, n, &per_cpu(vcpus_on_cpu, cpu),
1090                                  local_vcpus_link)
1091                 __vcpu_clear(vmx);
1092 }
1093
1094
1095 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
1096  * tricks.
1097  */
1098 static void kvm_cpu_vmxoff(void)
1099 {
1100         asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
1101         write_cr4(read_cr4() & ~X86_CR4_VMXE);
1102 }
1103
1104 static void hardware_disable(void *garbage)
1105 {
1106         vmclear_local_vcpus();
1107         kvm_cpu_vmxoff();
1108 }
1109
1110 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
1111                                       u32 msr, u32 *result)
1112 {
1113         u32 vmx_msr_low, vmx_msr_high;
1114         u32 ctl = ctl_min | ctl_opt;
1115
1116         rdmsr(msr, vmx_msr_low, vmx_msr_high);
1117
1118         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
1119         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
1120
1121         /* Ensure minimum (required) set of control bits are supported. */
1122         if (ctl_min & ~ctl)
1123                 return -EIO;
1124
1125         *result = ctl;
1126         return 0;
1127 }
1128
1129 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
1130 {
1131         u32 vmx_msr_low, vmx_msr_high;
1132         u32 min, opt, min2, opt2;
1133         u32 _pin_based_exec_control = 0;
1134         u32 _cpu_based_exec_control = 0;
1135         u32 _cpu_based_2nd_exec_control = 0;
1136         u32 _vmexit_control = 0;
1137         u32 _vmentry_control = 0;
1138
1139         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
1140         opt = PIN_BASED_VIRTUAL_NMIS;
1141         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
1142                                 &_pin_based_exec_control) < 0)
1143                 return -EIO;
1144
1145         min = CPU_BASED_HLT_EXITING |
1146 #ifdef CONFIG_X86_64
1147               CPU_BASED_CR8_LOAD_EXITING |
1148               CPU_BASED_CR8_STORE_EXITING |
1149 #endif
1150               CPU_BASED_CR3_LOAD_EXITING |
1151               CPU_BASED_CR3_STORE_EXITING |
1152               CPU_BASED_USE_IO_BITMAPS |
1153               CPU_BASED_MOV_DR_EXITING |
1154               CPU_BASED_USE_TSC_OFFSETING |
1155               CPU_BASED_INVLPG_EXITING;
1156         opt = CPU_BASED_TPR_SHADOW |
1157               CPU_BASED_USE_MSR_BITMAPS |
1158               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1159         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
1160                                 &_cpu_based_exec_control) < 0)
1161                 return -EIO;
1162 #ifdef CONFIG_X86_64
1163         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
1164                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
1165                                            ~CPU_BASED_CR8_STORE_EXITING;
1166 #endif
1167         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
1168                 min2 = 0;
1169                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
1170                         SECONDARY_EXEC_WBINVD_EXITING |
1171                         SECONDARY_EXEC_ENABLE_VPID |
1172                         SECONDARY_EXEC_ENABLE_EPT;
1173                 if (adjust_vmx_controls(min2, opt2,
1174                                         MSR_IA32_VMX_PROCBASED_CTLS2,
1175                                         &_cpu_based_2nd_exec_control) < 0)
1176                         return -EIO;
1177         }
1178 #ifndef CONFIG_X86_64
1179         if (!(_cpu_based_2nd_exec_control &
1180                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
1181                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
1182 #endif
1183         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
1184                 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
1185                    enabled */
1186                 min &= ~(CPU_BASED_CR3_LOAD_EXITING |
1187                          CPU_BASED_CR3_STORE_EXITING |
1188                          CPU_BASED_INVLPG_EXITING);
1189                 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
1190                                         &_cpu_based_exec_control) < 0)
1191                         return -EIO;
1192                 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
1193                       vmx_capability.ept, vmx_capability.vpid);
1194         }
1195
1196         min = 0;
1197 #ifdef CONFIG_X86_64
1198         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
1199 #endif
1200         opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
1201         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
1202                                 &_vmexit_control) < 0)
1203                 return -EIO;
1204
1205         min = 0;
1206         opt = VM_ENTRY_LOAD_IA32_PAT;
1207         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
1208                                 &_vmentry_control) < 0)
1209                 return -EIO;
1210
1211         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1212
1213         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
1214         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
1215                 return -EIO;
1216
1217 #ifdef CONFIG_X86_64
1218         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
1219         if (vmx_msr_high & (1u<<16))
1220                 return -EIO;
1221 #endif
1222
1223         /* Require Write-Back (WB) memory type for VMCS accesses. */
1224         if (((vmx_msr_high >> 18) & 15) != 6)
1225                 return -EIO;
1226
1227         vmcs_conf->size = vmx_msr_high & 0x1fff;
1228         vmcs_conf->order = get_order(vmcs_config.size);
1229         vmcs_conf->revision_id = vmx_msr_low;
1230
1231         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
1232         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
1233         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
1234         vmcs_conf->vmexit_ctrl         = _vmexit_control;
1235         vmcs_conf->vmentry_ctrl        = _vmentry_control;
1236
1237         return 0;
1238 }
1239
1240 static struct vmcs *alloc_vmcs_cpu(int cpu)
1241 {
1242         int node = cpu_to_node(cpu);
1243         struct page *pages;
1244         struct vmcs *vmcs;
1245
1246         pages = alloc_pages_node(node, GFP_KERNEL, vmcs_config.order);
1247         if (!pages)
1248                 return NULL;
1249         vmcs = page_address(pages);
1250         memset(vmcs, 0, vmcs_config.size);
1251         vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
1252         return vmcs;
1253 }
1254
1255 static struct vmcs *alloc_vmcs(void)
1256 {
1257         return alloc_vmcs_cpu(raw_smp_processor_id());
1258 }
1259
1260 static void free_vmcs(struct vmcs *vmcs)
1261 {
1262         free_pages((unsigned long)vmcs, vmcs_config.order);
1263 }
1264
1265 static void free_kvm_area(void)
1266 {
1267         int cpu;
1268
1269         for_each_online_cpu(cpu)
1270                 free_vmcs(per_cpu(vmxarea, cpu));
1271 }
1272
1273 static __init int alloc_kvm_area(void)
1274 {
1275         int cpu;
1276
1277         for_each_online_cpu(cpu) {
1278                 struct vmcs *vmcs;
1279
1280                 vmcs = alloc_vmcs_cpu(cpu);
1281                 if (!vmcs) {
1282                         free_kvm_area();
1283                         return -ENOMEM;
1284                 }
1285
1286                 per_cpu(vmxarea, cpu) = vmcs;
1287         }
1288         return 0;
1289 }
1290
1291 static __init int hardware_setup(void)
1292 {
1293         if (setup_vmcs_config(&vmcs_config) < 0)
1294                 return -EIO;
1295
1296         if (boot_cpu_has(X86_FEATURE_NX))
1297                 kvm_enable_efer_bits(EFER_NX);
1298
1299         return alloc_kvm_area();
1300 }
1301
1302 static __exit void hardware_unsetup(void)
1303 {
1304         free_kvm_area();
1305 }
1306
1307 static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
1308 {
1309         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1310
1311         if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
1312                 vmcs_write16(sf->selector, save->selector);
1313                 vmcs_writel(sf->base, save->base);
1314                 vmcs_write32(sf->limit, save->limit);
1315                 vmcs_write32(sf->ar_bytes, save->ar);
1316         } else {
1317                 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
1318                         << AR_DPL_SHIFT;
1319                 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
1320         }
1321 }
1322
1323 static void enter_pmode(struct kvm_vcpu *vcpu)
1324 {
1325         unsigned long flags;
1326         struct vcpu_vmx *vmx = to_vmx(vcpu);
1327
1328         vmx->emulation_required = 1;
1329         vcpu->arch.rmode.active = 0;
1330
1331         vmcs_writel(GUEST_TR_BASE, vcpu->arch.rmode.tr.base);
1332         vmcs_write32(GUEST_TR_LIMIT, vcpu->arch.rmode.tr.limit);
1333         vmcs_write32(GUEST_TR_AR_BYTES, vcpu->arch.rmode.tr.ar);
1334
1335         flags = vmcs_readl(GUEST_RFLAGS);
1336         flags &= ~(X86_EFLAGS_IOPL | X86_EFLAGS_VM);
1337         flags |= (vcpu->arch.rmode.save_iopl << IOPL_SHIFT);
1338         vmcs_writel(GUEST_RFLAGS, flags);
1339
1340         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
1341                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
1342
1343         update_exception_bitmap(vcpu);
1344
1345         if (emulate_invalid_guest_state)
1346                 return;
1347
1348         fix_pmode_dataseg(VCPU_SREG_ES, &vcpu->arch.rmode.es);
1349         fix_pmode_dataseg(VCPU_SREG_DS, &vcpu->arch.rmode.ds);
1350         fix_pmode_dataseg(VCPU_SREG_GS, &vcpu->arch.rmode.gs);
1351         fix_pmode_dataseg(VCPU_SREG_FS, &vcpu->arch.rmode.fs);
1352
1353         vmcs_write16(GUEST_SS_SELECTOR, 0);
1354         vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
1355
1356         vmcs_write16(GUEST_CS_SELECTOR,
1357                      vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
1358         vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1359 }
1360
1361 static gva_t rmode_tss_base(struct kvm *kvm)
1362 {
1363         if (!kvm->arch.tss_addr) {
1364                 gfn_t base_gfn = kvm->memslots[0].base_gfn +
1365                                  kvm->memslots[0].npages - 3;
1366                 return base_gfn << PAGE_SHIFT;
1367         }
1368         return kvm->arch.tss_addr;
1369 }
1370
1371 static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
1372 {
1373         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1374
1375         save->selector = vmcs_read16(sf->selector);
1376         save->base = vmcs_readl(sf->base);
1377         save->limit = vmcs_read32(sf->limit);
1378         save->ar = vmcs_read32(sf->ar_bytes);
1379         vmcs_write16(sf->selector, save->base >> 4);
1380         vmcs_write32(sf->base, save->base & 0xfffff);
1381         vmcs_write32(sf->limit, 0xffff);
1382         vmcs_write32(sf->ar_bytes, 0xf3);
1383 }
1384
1385 static void enter_rmode(struct kvm_vcpu *vcpu)
1386 {
1387         unsigned long flags;
1388         struct vcpu_vmx *vmx = to_vmx(vcpu);
1389
1390         vmx->emulation_required = 1;
1391         vcpu->arch.rmode.active = 1;
1392
1393         vcpu->arch.rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
1394         vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
1395
1396         vcpu->arch.rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
1397         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
1398
1399         vcpu->arch.rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
1400         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1401
1402         flags = vmcs_readl(GUEST_RFLAGS);
1403         vcpu->arch.rmode.save_iopl
1404                 = (flags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
1405
1406         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1407
1408         vmcs_writel(GUEST_RFLAGS, flags);
1409         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
1410         update_exception_bitmap(vcpu);
1411
1412         if (emulate_invalid_guest_state)
1413                 goto continue_rmode;
1414
1415         vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
1416         vmcs_write32(GUEST_SS_LIMIT, 0xffff);
1417         vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
1418
1419         vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
1420         vmcs_write32(GUEST_CS_LIMIT, 0xffff);
1421         if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
1422                 vmcs_writel(GUEST_CS_BASE, 0xf0000);
1423         vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
1424
1425         fix_rmode_seg(VCPU_SREG_ES, &vcpu->arch.rmode.es);
1426         fix_rmode_seg(VCPU_SREG_DS, &vcpu->arch.rmode.ds);
1427         fix_rmode_seg(VCPU_SREG_GS, &vcpu->arch.rmode.gs);
1428         fix_rmode_seg(VCPU_SREG_FS, &vcpu->arch.rmode.fs);
1429
1430 continue_rmode:
1431         kvm_mmu_reset_context(vcpu);
1432         init_rmode(vcpu->kvm);
1433 }
1434
1435 #ifdef CONFIG_X86_64
1436
1437 static void enter_lmode(struct kvm_vcpu *vcpu)
1438 {
1439         u32 guest_tr_ar;
1440
1441         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
1442         if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
1443                 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
1444                        __func__);
1445                 vmcs_write32(GUEST_TR_AR_BYTES,
1446                              (guest_tr_ar & ~AR_TYPE_MASK)
1447                              | AR_TYPE_BUSY_64_TSS);
1448         }
1449
1450         vcpu->arch.shadow_efer |= EFER_LMA;
1451
1452         find_msr_entry(to_vmx(vcpu), MSR_EFER)->data |= EFER_LMA | EFER_LME;
1453         vmcs_write32(VM_ENTRY_CONTROLS,
1454                      vmcs_read32(VM_ENTRY_CONTROLS)
1455                      | VM_ENTRY_IA32E_MODE);
1456 }
1457
1458 static void exit_lmode(struct kvm_vcpu *vcpu)
1459 {
1460         vcpu->arch.shadow_efer &= ~EFER_LMA;
1461
1462         vmcs_write32(VM_ENTRY_CONTROLS,
1463                      vmcs_read32(VM_ENTRY_CONTROLS)
1464                      & ~VM_ENTRY_IA32E_MODE);
1465 }
1466
1467 #endif
1468
1469 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
1470 {
1471         vpid_sync_vcpu_all(to_vmx(vcpu));
1472         if (vm_need_ept())
1473                 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
1474 }
1475
1476 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1477 {
1478         vcpu->arch.cr4 &= KVM_GUEST_CR4_MASK;
1479         vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & ~KVM_GUEST_CR4_MASK;
1480 }
1481
1482 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
1483 {
1484         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1485                 if (!load_pdptrs(vcpu, vcpu->arch.cr3)) {
1486                         printk(KERN_ERR "EPT: Fail to load pdptrs!\n");
1487                         return;
1488                 }
1489                 vmcs_write64(GUEST_PDPTR0, vcpu->arch.pdptrs[0]);
1490                 vmcs_write64(GUEST_PDPTR1, vcpu->arch.pdptrs[1]);
1491                 vmcs_write64(GUEST_PDPTR2, vcpu->arch.pdptrs[2]);
1492                 vmcs_write64(GUEST_PDPTR3, vcpu->arch.pdptrs[3]);
1493         }
1494 }
1495
1496 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1497
1498 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
1499                                         unsigned long cr0,
1500                                         struct kvm_vcpu *vcpu)
1501 {
1502         if (!(cr0 & X86_CR0_PG)) {
1503                 /* From paging/starting to nonpaging */
1504                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
1505                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1506                              (CPU_BASED_CR3_LOAD_EXITING |
1507                               CPU_BASED_CR3_STORE_EXITING));
1508                 vcpu->arch.cr0 = cr0;
1509                 vmx_set_cr4(vcpu, vcpu->arch.cr4);
1510                 *hw_cr0 |= X86_CR0_PE | X86_CR0_PG;
1511                 *hw_cr0 &= ~X86_CR0_WP;
1512         } else if (!is_paging(vcpu)) {
1513                 /* From nonpaging to paging */
1514                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
1515                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1516                              ~(CPU_BASED_CR3_LOAD_EXITING |
1517                                CPU_BASED_CR3_STORE_EXITING));
1518                 vcpu->arch.cr0 = cr0;
1519                 vmx_set_cr4(vcpu, vcpu->arch.cr4);
1520                 if (!(vcpu->arch.cr0 & X86_CR0_WP))
1521                         *hw_cr0 &= ~X86_CR0_WP;
1522         }
1523 }
1524
1525 static void ept_update_paging_mode_cr4(unsigned long *hw_cr4,
1526                                         struct kvm_vcpu *vcpu)
1527 {
1528         if (!is_paging(vcpu)) {
1529                 *hw_cr4 &= ~X86_CR4_PAE;
1530                 *hw_cr4 |= X86_CR4_PSE;
1531         } else if (!(vcpu->arch.cr4 & X86_CR4_PAE))
1532                 *hw_cr4 &= ~X86_CR4_PAE;
1533 }
1534
1535 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1536 {
1537         unsigned long hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) |
1538                                 KVM_VM_CR0_ALWAYS_ON;
1539
1540         vmx_fpu_deactivate(vcpu);
1541
1542         if (vcpu->arch.rmode.active && (cr0 & X86_CR0_PE))
1543                 enter_pmode(vcpu);
1544
1545         if (!vcpu->arch.rmode.active && !(cr0 & X86_CR0_PE))
1546                 enter_rmode(vcpu);
1547
1548 #ifdef CONFIG_X86_64
1549         if (vcpu->arch.shadow_efer & EFER_LME) {
1550                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
1551                         enter_lmode(vcpu);
1552                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
1553                         exit_lmode(vcpu);
1554         }
1555 #endif
1556
1557         if (vm_need_ept())
1558                 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
1559
1560         vmcs_writel(CR0_READ_SHADOW, cr0);
1561         vmcs_writel(GUEST_CR0, hw_cr0);
1562         vcpu->arch.cr0 = cr0;
1563
1564         if (!(cr0 & X86_CR0_TS) || !(cr0 & X86_CR0_PE))
1565                 vmx_fpu_activate(vcpu);
1566 }
1567
1568 static u64 construct_eptp(unsigned long root_hpa)
1569 {
1570         u64 eptp;
1571
1572         /* TODO write the value reading from MSR */
1573         eptp = VMX_EPT_DEFAULT_MT |
1574                 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
1575         eptp |= (root_hpa & PAGE_MASK);
1576
1577         return eptp;
1578 }
1579
1580 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
1581 {
1582         unsigned long guest_cr3;
1583         u64 eptp;
1584
1585         guest_cr3 = cr3;
1586         if (vm_need_ept()) {
1587                 eptp = construct_eptp(cr3);
1588                 vmcs_write64(EPT_POINTER, eptp);
1589                 ept_sync_context(eptp);
1590                 ept_load_pdptrs(vcpu);
1591                 guest_cr3 = is_paging(vcpu) ? vcpu->arch.cr3 :
1592                         VMX_EPT_IDENTITY_PAGETABLE_ADDR;
1593         }
1594
1595         vmx_flush_tlb(vcpu);
1596         vmcs_writel(GUEST_CR3, guest_cr3);
1597         if (vcpu->arch.cr0 & X86_CR0_PE)
1598                 vmx_fpu_deactivate(vcpu);
1599 }
1600
1601 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1602 {
1603         unsigned long hw_cr4 = cr4 | (vcpu->arch.rmode.active ?
1604                     KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
1605
1606         vcpu->arch.cr4 = cr4;
1607         if (vm_need_ept())
1608                 ept_update_paging_mode_cr4(&hw_cr4, vcpu);
1609
1610         vmcs_writel(CR4_READ_SHADOW, cr4);
1611         vmcs_writel(GUEST_CR4, hw_cr4);
1612 }
1613
1614 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
1615 {
1616         struct vcpu_vmx *vmx = to_vmx(vcpu);
1617         struct kvm_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
1618
1619         vcpu->arch.shadow_efer = efer;
1620         if (!msr)
1621                 return;
1622         if (efer & EFER_LMA) {
1623                 vmcs_write32(VM_ENTRY_CONTROLS,
1624                                      vmcs_read32(VM_ENTRY_CONTROLS) |
1625                                      VM_ENTRY_IA32E_MODE);
1626                 msr->data = efer;
1627
1628         } else {
1629                 vmcs_write32(VM_ENTRY_CONTROLS,
1630                                      vmcs_read32(VM_ENTRY_CONTROLS) &
1631                                      ~VM_ENTRY_IA32E_MODE);
1632
1633                 msr->data = efer & ~EFER_LME;
1634         }
1635         setup_msrs(vmx);
1636 }
1637
1638 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1639 {
1640         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1641
1642         return vmcs_readl(sf->base);
1643 }
1644
1645 static void vmx_get_segment(struct kvm_vcpu *vcpu,
1646                             struct kvm_segment *var, int seg)
1647 {
1648         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1649         u32 ar;
1650
1651         var->base = vmcs_readl(sf->base);
1652         var->limit = vmcs_read32(sf->limit);
1653         var->selector = vmcs_read16(sf->selector);
1654         ar = vmcs_read32(sf->ar_bytes);
1655         if (ar & AR_UNUSABLE_MASK)
1656                 ar = 0;
1657         var->type = ar & 15;
1658         var->s = (ar >> 4) & 1;
1659         var->dpl = (ar >> 5) & 3;
1660         var->present = (ar >> 7) & 1;
1661         var->avl = (ar >> 12) & 1;
1662         var->l = (ar >> 13) & 1;
1663         var->db = (ar >> 14) & 1;
1664         var->g = (ar >> 15) & 1;
1665         var->unusable = (ar >> 16) & 1;
1666 }
1667
1668 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
1669 {
1670         struct kvm_segment kvm_seg;
1671
1672         if (!(vcpu->arch.cr0 & X86_CR0_PE)) /* if real mode */
1673                 return 0;
1674
1675         if (vmx_get_rflags(vcpu) & X86_EFLAGS_VM) /* if virtual 8086 */
1676                 return 3;
1677
1678         vmx_get_segment(vcpu, &kvm_seg, VCPU_SREG_CS);
1679         return kvm_seg.selector & 3;
1680 }
1681
1682 static u32 vmx_segment_access_rights(struct kvm_segment *var)
1683 {
1684         u32 ar;
1685
1686         if (var->unusable)
1687                 ar = 1 << 16;
1688         else {
1689                 ar = var->type & 15;
1690                 ar |= (var->s & 1) << 4;
1691                 ar |= (var->dpl & 3) << 5;
1692                 ar |= (var->present & 1) << 7;
1693                 ar |= (var->avl & 1) << 12;
1694                 ar |= (var->l & 1) << 13;
1695                 ar |= (var->db & 1) << 14;
1696                 ar |= (var->g & 1) << 15;
1697         }
1698         if (ar == 0) /* a 0 value means unusable */
1699                 ar = AR_UNUSABLE_MASK;
1700
1701         return ar;
1702 }
1703
1704 static void vmx_set_segment(struct kvm_vcpu *vcpu,
1705                             struct kvm_segment *var, int seg)
1706 {
1707         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1708         u32 ar;
1709
1710         if (vcpu->arch.rmode.active && seg == VCPU_SREG_TR) {
1711                 vcpu->arch.rmode.tr.selector = var->selector;
1712                 vcpu->arch.rmode.tr.base = var->base;
1713                 vcpu->arch.rmode.tr.limit = var->limit;
1714                 vcpu->arch.rmode.tr.ar = vmx_segment_access_rights(var);
1715                 return;
1716         }
1717         vmcs_writel(sf->base, var->base);
1718         vmcs_write32(sf->limit, var->limit);
1719         vmcs_write16(sf->selector, var->selector);
1720         if (vcpu->arch.rmode.active && var->s) {
1721                 /*
1722                  * Hack real-mode segments into vm86 compatibility.
1723                  */
1724                 if (var->base == 0xffff0000 && var->selector == 0xf000)
1725                         vmcs_writel(sf->base, 0xf0000);
1726                 ar = 0xf3;
1727         } else
1728                 ar = vmx_segment_access_rights(var);
1729         vmcs_write32(sf->ar_bytes, ar);
1730 }
1731
1732 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
1733 {
1734         u32 ar = vmcs_read32(GUEST_CS_AR_BYTES);
1735
1736         *db = (ar >> 14) & 1;
1737         *l = (ar >> 13) & 1;
1738 }
1739
1740 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1741 {
1742         dt->limit = vmcs_read32(GUEST_IDTR_LIMIT);
1743         dt->base = vmcs_readl(GUEST_IDTR_BASE);
1744 }
1745
1746 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1747 {
1748         vmcs_write32(GUEST_IDTR_LIMIT, dt->limit);
1749         vmcs_writel(GUEST_IDTR_BASE, dt->base);
1750 }
1751
1752 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1753 {
1754         dt->limit = vmcs_read32(GUEST_GDTR_LIMIT);
1755         dt->base = vmcs_readl(GUEST_GDTR_BASE);
1756 }
1757
1758 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1759 {
1760         vmcs_write32(GUEST_GDTR_LIMIT, dt->limit);
1761         vmcs_writel(GUEST_GDTR_BASE, dt->base);
1762 }
1763
1764 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
1765 {
1766         struct kvm_segment var;
1767         u32 ar;
1768
1769         vmx_get_segment(vcpu, &var, seg);
1770         ar = vmx_segment_access_rights(&var);
1771
1772         if (var.base != (var.selector << 4))
1773                 return false;
1774         if (var.limit != 0xffff)
1775                 return false;
1776         if (ar != 0xf3)
1777                 return false;
1778
1779         return true;
1780 }
1781
1782 static bool code_segment_valid(struct kvm_vcpu *vcpu)
1783 {
1784         struct kvm_segment cs;
1785         unsigned int cs_rpl;
1786
1787         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
1788         cs_rpl = cs.selector & SELECTOR_RPL_MASK;
1789
1790         if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
1791                 return false;
1792         if (!cs.s)
1793                 return false;
1794         if (!(~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK))) {
1795                 if (cs.dpl > cs_rpl)
1796                         return false;
1797         } else if (cs.type & AR_TYPE_CODE_MASK) {
1798                 if (cs.dpl != cs_rpl)
1799                         return false;
1800         }
1801         if (!cs.present)
1802                 return false;
1803
1804         /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
1805         return true;
1806 }
1807
1808 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
1809 {
1810         struct kvm_segment ss;
1811         unsigned int ss_rpl;
1812
1813         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
1814         ss_rpl = ss.selector & SELECTOR_RPL_MASK;
1815
1816         if ((ss.type != 3) || (ss.type != 7))
1817                 return false;
1818         if (!ss.s)
1819                 return false;
1820         if (ss.dpl != ss_rpl) /* DPL != RPL */
1821                 return false;
1822         if (!ss.present)
1823                 return false;
1824
1825         return true;
1826 }
1827
1828 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
1829 {
1830         struct kvm_segment var;
1831         unsigned int rpl;
1832
1833         vmx_get_segment(vcpu, &var, seg);
1834         rpl = var.selector & SELECTOR_RPL_MASK;
1835
1836         if (!var.s)
1837                 return false;
1838         if (!var.present)
1839                 return false;
1840         if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
1841                 if (var.dpl < rpl) /* DPL < RPL */
1842                         return false;
1843         }
1844
1845         /* TODO: Add other members to kvm_segment_field to allow checking for other access
1846          * rights flags
1847          */
1848         return true;
1849 }
1850
1851 static bool tr_valid(struct kvm_vcpu *vcpu)
1852 {
1853         struct kvm_segment tr;
1854
1855         vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
1856
1857         if (tr.selector & SELECTOR_TI_MASK)     /* TI = 1 */
1858                 return false;
1859         if ((tr.type != 3) || (tr.type != 11)) /* TODO: Check if guest is in IA32e mode */
1860                 return false;
1861         if (!tr.present)
1862                 return false;
1863
1864         return true;
1865 }
1866
1867 static bool ldtr_valid(struct kvm_vcpu *vcpu)
1868 {
1869         struct kvm_segment ldtr;
1870
1871         vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
1872
1873         if (ldtr.selector & SELECTOR_TI_MASK)   /* TI = 1 */
1874                 return false;
1875         if (ldtr.type != 2)
1876                 return false;
1877         if (!ldtr.present)
1878                 return false;
1879
1880         return true;
1881 }
1882
1883 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
1884 {
1885         struct kvm_segment cs, ss;
1886
1887         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
1888         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
1889
1890         return ((cs.selector & SELECTOR_RPL_MASK) ==
1891                  (ss.selector & SELECTOR_RPL_MASK));
1892 }
1893
1894 /*
1895  * Check if guest state is valid. Returns true if valid, false if
1896  * not.
1897  * We assume that registers are always usable
1898  */
1899 static bool guest_state_valid(struct kvm_vcpu *vcpu)
1900 {
1901         /* real mode guest state checks */
1902         if (!(vcpu->arch.cr0 & X86_CR0_PE)) {
1903                 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
1904                         return false;
1905                 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
1906                         return false;
1907                 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
1908                         return false;
1909                 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
1910                         return false;
1911                 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
1912                         return false;
1913                 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
1914                         return false;
1915         } else {
1916         /* protected mode guest state checks */
1917                 if (!cs_ss_rpl_check(vcpu))
1918                         return false;
1919                 if (!code_segment_valid(vcpu))
1920                         return false;
1921                 if (!stack_segment_valid(vcpu))
1922                         return false;
1923                 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
1924                         return false;
1925                 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
1926                         return false;
1927                 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
1928                         return false;
1929                 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
1930                         return false;
1931                 if (!tr_valid(vcpu))
1932                         return false;
1933                 if (!ldtr_valid(vcpu))
1934                         return false;
1935         }
1936         /* TODO:
1937          * - Add checks on RIP
1938          * - Add checks on RFLAGS
1939          */
1940
1941         return true;
1942 }
1943
1944 static int init_rmode_tss(struct kvm *kvm)
1945 {
1946         gfn_t fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
1947         u16 data = 0;
1948         int ret = 0;
1949         int r;
1950
1951         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
1952         if (r < 0)
1953                 goto out;
1954         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
1955         r = kvm_write_guest_page(kvm, fn++, &data,
1956                         TSS_IOPB_BASE_OFFSET, sizeof(u16));
1957         if (r < 0)
1958                 goto out;
1959         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
1960         if (r < 0)
1961                 goto out;
1962         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
1963         if (r < 0)
1964                 goto out;
1965         data = ~0;
1966         r = kvm_write_guest_page(kvm, fn, &data,
1967                                  RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
1968                                  sizeof(u8));
1969         if (r < 0)
1970                 goto out;
1971
1972         ret = 1;
1973 out:
1974         return ret;
1975 }
1976
1977 static int init_rmode_identity_map(struct kvm *kvm)
1978 {
1979         int i, r, ret;
1980         pfn_t identity_map_pfn;
1981         u32 tmp;
1982
1983         if (!vm_need_ept())
1984                 return 1;
1985         if (unlikely(!kvm->arch.ept_identity_pagetable)) {
1986                 printk(KERN_ERR "EPT: identity-mapping pagetable "
1987                         "haven't been allocated!\n");
1988                 return 0;
1989         }
1990         if (likely(kvm->arch.ept_identity_pagetable_done))
1991                 return 1;
1992         ret = 0;
1993         identity_map_pfn = VMX_EPT_IDENTITY_PAGETABLE_ADDR >> PAGE_SHIFT;
1994         r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
1995         if (r < 0)
1996                 goto out;
1997         /* Set up identity-mapping pagetable for EPT in real mode */
1998         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
1999                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
2000                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
2001                 r = kvm_write_guest_page(kvm, identity_map_pfn,
2002                                 &tmp, i * sizeof(tmp), sizeof(tmp));
2003                 if (r < 0)
2004                         goto out;
2005         }
2006         kvm->arch.ept_identity_pagetable_done = true;
2007         ret = 1;
2008 out:
2009         return ret;
2010 }
2011
2012 static void seg_setup(int seg)
2013 {
2014         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2015
2016         vmcs_write16(sf->selector, 0);
2017         vmcs_writel(sf->base, 0);
2018         vmcs_write32(sf->limit, 0xffff);
2019         vmcs_write32(sf->ar_bytes, 0xf3);
2020 }
2021
2022 static int alloc_apic_access_page(struct kvm *kvm)
2023 {
2024         struct kvm_userspace_memory_region kvm_userspace_mem;
2025         int r = 0;
2026
2027         down_write(&kvm->slots_lock);
2028         if (kvm->arch.apic_access_page)
2029                 goto out;
2030         kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
2031         kvm_userspace_mem.flags = 0;
2032         kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
2033         kvm_userspace_mem.memory_size = PAGE_SIZE;
2034         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2035         if (r)
2036                 goto out;
2037
2038         kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
2039 out:
2040         up_write(&kvm->slots_lock);
2041         return r;
2042 }
2043
2044 static int alloc_identity_pagetable(struct kvm *kvm)
2045 {
2046         struct kvm_userspace_memory_region kvm_userspace_mem;
2047         int r = 0;
2048
2049         down_write(&kvm->slots_lock);
2050         if (kvm->arch.ept_identity_pagetable)
2051                 goto out;
2052         kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
2053         kvm_userspace_mem.flags = 0;
2054         kvm_userspace_mem.guest_phys_addr = VMX_EPT_IDENTITY_PAGETABLE_ADDR;
2055         kvm_userspace_mem.memory_size = PAGE_SIZE;
2056         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2057         if (r)
2058                 goto out;
2059
2060         kvm->arch.ept_identity_pagetable = gfn_to_page(kvm,
2061                         VMX_EPT_IDENTITY_PAGETABLE_ADDR >> PAGE_SHIFT);
2062 out:
2063         up_write(&kvm->slots_lock);
2064         return r;
2065 }
2066
2067 static void allocate_vpid(struct vcpu_vmx *vmx)
2068 {
2069         int vpid;
2070
2071         vmx->vpid = 0;
2072         if (!enable_vpid || !cpu_has_vmx_vpid())
2073                 return;
2074         spin_lock(&vmx_vpid_lock);
2075         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
2076         if (vpid < VMX_NR_VPIDS) {
2077                 vmx->vpid = vpid;
2078                 __set_bit(vpid, vmx_vpid_bitmap);
2079         }
2080         spin_unlock(&vmx_vpid_lock);
2081 }
2082
2083 static void vmx_disable_intercept_for_msr(struct page *msr_bitmap, u32 msr)
2084 {
2085         void *va;
2086
2087         if (!cpu_has_vmx_msr_bitmap())
2088                 return;
2089
2090         /*
2091          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
2092          * have the write-low and read-high bitmap offsets the wrong way round.
2093          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
2094          */
2095         va = kmap(msr_bitmap);
2096         if (msr <= 0x1fff) {
2097                 __clear_bit(msr, va + 0x000); /* read-low */
2098                 __clear_bit(msr, va + 0x800); /* write-low */
2099         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
2100                 msr &= 0x1fff;
2101                 __clear_bit(msr, va + 0x400); /* read-high */
2102                 __clear_bit(msr, va + 0xc00); /* write-high */
2103         }
2104         kunmap(msr_bitmap);
2105 }
2106
2107 /*
2108  * Sets up the vmcs for emulated real mode.
2109  */
2110 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
2111 {
2112         u32 host_sysenter_cs, msr_low, msr_high;
2113         u32 junk;
2114         u64 host_pat;
2115         unsigned long a;
2116         struct descriptor_table dt;
2117         int i;
2118         unsigned long kvm_vmx_return;
2119         u32 exec_control;
2120
2121         /* I/O */
2122         vmcs_write64(IO_BITMAP_A, page_to_phys(vmx_io_bitmap_a));
2123         vmcs_write64(IO_BITMAP_B, page_to_phys(vmx_io_bitmap_b));
2124
2125         if (cpu_has_vmx_msr_bitmap())
2126                 vmcs_write64(MSR_BITMAP, page_to_phys(vmx_msr_bitmap));
2127
2128         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
2129
2130         /* Control */
2131         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
2132                 vmcs_config.pin_based_exec_ctrl);
2133
2134         exec_control = vmcs_config.cpu_based_exec_ctrl;
2135         if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
2136                 exec_control &= ~CPU_BASED_TPR_SHADOW;
2137 #ifdef CONFIG_X86_64
2138                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
2139                                 CPU_BASED_CR8_LOAD_EXITING;
2140 #endif
2141         }
2142         if (!vm_need_ept())
2143                 exec_control |= CPU_BASED_CR3_STORE_EXITING |
2144                                 CPU_BASED_CR3_LOAD_EXITING  |
2145                                 CPU_BASED_INVLPG_EXITING;
2146         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
2147
2148         if (cpu_has_secondary_exec_ctrls()) {
2149                 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
2150                 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2151                         exec_control &=
2152                                 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
2153                 if (vmx->vpid == 0)
2154                         exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
2155                 if (!vm_need_ept())
2156                         exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
2157                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
2158         }
2159
2160         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, !!bypass_guest_pf);
2161         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, !!bypass_guest_pf);
2162         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
2163
2164         vmcs_writel(HOST_CR0, read_cr0());  /* 22.2.3 */
2165         vmcs_writel(HOST_CR4, read_cr4());  /* 22.2.3, 22.2.5 */
2166         vmcs_writel(HOST_CR3, read_cr3());  /* 22.2.3  FIXME: shadow tables */
2167
2168         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
2169         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
2170         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
2171         vmcs_write16(HOST_FS_SELECTOR, kvm_read_fs());    /* 22.2.4 */
2172         vmcs_write16(HOST_GS_SELECTOR, kvm_read_gs());    /* 22.2.4 */
2173         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
2174 #ifdef CONFIG_X86_64
2175         rdmsrl(MSR_FS_BASE, a);
2176         vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
2177         rdmsrl(MSR_GS_BASE, a);
2178         vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
2179 #else
2180         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
2181         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
2182 #endif
2183
2184         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
2185
2186         kvm_get_idt(&dt);
2187         vmcs_writel(HOST_IDTR_BASE, dt.base);   /* 22.2.4 */
2188
2189         asm("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return));
2190         vmcs_writel(HOST_RIP, kvm_vmx_return); /* 22.2.5 */
2191         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
2192         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
2193         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
2194
2195         rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk);
2196         vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs);
2197         rdmsrl(MSR_IA32_SYSENTER_ESP, a);
2198         vmcs_writel(HOST_IA32_SYSENTER_ESP, a);   /* 22.2.3 */
2199         rdmsrl(MSR_IA32_SYSENTER_EIP, a);
2200         vmcs_writel(HOST_IA32_SYSENTER_EIP, a);   /* 22.2.3 */
2201
2202         if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
2203                 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2204                 host_pat = msr_low | ((u64) msr_high << 32);
2205                 vmcs_write64(HOST_IA32_PAT, host_pat);
2206         }
2207         if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2208                 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2209                 host_pat = msr_low | ((u64) msr_high << 32);
2210                 /* Write the default value follow host pat */
2211                 vmcs_write64(GUEST_IA32_PAT, host_pat);
2212                 /* Keep arch.pat sync with GUEST_IA32_PAT */
2213                 vmx->vcpu.arch.pat = host_pat;
2214         }
2215
2216         for (i = 0; i < NR_VMX_MSR; ++i) {
2217                 u32 index = vmx_msr_index[i];
2218                 u32 data_low, data_high;
2219                 u64 data;
2220                 int j = vmx->nmsrs;
2221
2222                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
2223                         continue;
2224                 if (wrmsr_safe(index, data_low, data_high) < 0)
2225                         continue;
2226                 data = data_low | ((u64)data_high << 32);
2227                 vmx->host_msrs[j].index = index;
2228                 vmx->host_msrs[j].reserved = 0;
2229                 vmx->host_msrs[j].data = data;
2230                 vmx->guest_msrs[j] = vmx->host_msrs[j];
2231                 ++vmx->nmsrs;
2232         }
2233
2234         vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
2235
2236         /* 22.2.1, 20.8.1 */
2237         vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
2238
2239         vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
2240         vmcs_writel(CR4_GUEST_HOST_MASK, KVM_GUEST_CR4_MASK);
2241
2242
2243         return 0;
2244 }
2245
2246 static int init_rmode(struct kvm *kvm)
2247 {
2248         if (!init_rmode_tss(kvm))
2249                 return 0;
2250         if (!init_rmode_identity_map(kvm))
2251                 return 0;
2252         return 1;
2253 }
2254
2255 static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
2256 {
2257         struct vcpu_vmx *vmx = to_vmx(vcpu);
2258         u64 msr;
2259         int ret;
2260
2261         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
2262         down_read(&vcpu->kvm->slots_lock);
2263         if (!init_rmode(vmx->vcpu.kvm)) {
2264                 ret = -ENOMEM;
2265                 goto out;
2266         }
2267
2268         vmx->vcpu.arch.rmode.active = 0;
2269
2270         vmx->soft_vnmi_blocked = 0;
2271
2272         vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2273         kvm_set_cr8(&vmx->vcpu, 0);
2274         msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
2275         if (vmx->vcpu.vcpu_id == 0)
2276                 msr |= MSR_IA32_APICBASE_BSP;
2277         kvm_set_apic_base(&vmx->vcpu, msr);
2278
2279         fx_init(&vmx->vcpu);
2280
2281         seg_setup(VCPU_SREG_CS);
2282         /*
2283          * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
2284          * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4.  Sigh.
2285          */
2286         if (vmx->vcpu.vcpu_id == 0) {
2287                 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
2288                 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
2289         } else {
2290                 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
2291                 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
2292         }
2293
2294         seg_setup(VCPU_SREG_DS);
2295         seg_setup(VCPU_SREG_ES);
2296         seg_setup(VCPU_SREG_FS);
2297         seg_setup(VCPU_SREG_GS);
2298         seg_setup(VCPU_SREG_SS);
2299
2300         vmcs_write16(GUEST_TR_SELECTOR, 0);
2301         vmcs_writel(GUEST_TR_BASE, 0);
2302         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
2303         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2304
2305         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
2306         vmcs_writel(GUEST_LDTR_BASE, 0);
2307         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
2308         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
2309
2310         vmcs_write32(GUEST_SYSENTER_CS, 0);
2311         vmcs_writel(GUEST_SYSENTER_ESP, 0);
2312         vmcs_writel(GUEST_SYSENTER_EIP, 0);
2313
2314         vmcs_writel(GUEST_RFLAGS, 0x02);
2315         if (vmx->vcpu.vcpu_id == 0)
2316                 kvm_rip_write(vcpu, 0xfff0);
2317         else
2318                 kvm_rip_write(vcpu, 0);
2319         kvm_register_write(vcpu, VCPU_REGS_RSP, 0);
2320
2321         /* todo: dr0 = dr1 = dr2 = dr3 = 0; dr6 = 0xffff0ff0 */
2322         vmcs_writel(GUEST_DR7, 0x400);
2323
2324         vmcs_writel(GUEST_GDTR_BASE, 0);
2325         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
2326
2327         vmcs_writel(GUEST_IDTR_BASE, 0);
2328         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
2329
2330         vmcs_write32(GUEST_ACTIVITY_STATE, 0);
2331         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
2332         vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
2333
2334         guest_write_tsc(0);
2335
2336         /* Special registers */
2337         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
2338
2339         setup_msrs(vmx);
2340
2341         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
2342
2343         if (cpu_has_vmx_tpr_shadow()) {
2344                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
2345                 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
2346                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
2347                                 page_to_phys(vmx->vcpu.arch.apic->regs_page));
2348                 vmcs_write32(TPR_THRESHOLD, 0);
2349         }
2350
2351         if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2352                 vmcs_write64(APIC_ACCESS_ADDR,
2353                              page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
2354
2355         if (vmx->vpid != 0)
2356                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
2357
2358         vmx->vcpu.arch.cr0 = 0x60000010;
2359         vmx_set_cr0(&vmx->vcpu, vmx->vcpu.arch.cr0); /* enter rmode */
2360         vmx_set_cr4(&vmx->vcpu, 0);
2361         vmx_set_efer(&vmx->vcpu, 0);
2362         vmx_fpu_activate(&vmx->vcpu);
2363         update_exception_bitmap(&vmx->vcpu);
2364
2365         vpid_sync_vcpu_all(vmx);
2366
2367         ret = 0;
2368
2369         /* HACK: Don't enable emulation on guest boot/reset */
2370         vmx->emulation_required = 0;
2371
2372 out:
2373         up_read(&vcpu->kvm->slots_lock);
2374         return ret;
2375 }
2376
2377 static void enable_irq_window(struct kvm_vcpu *vcpu)
2378 {
2379         u32 cpu_based_vm_exec_control;
2380
2381         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2382         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
2383         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2384 }
2385
2386 static void enable_nmi_window(struct kvm_vcpu *vcpu)
2387 {
2388         u32 cpu_based_vm_exec_control;
2389
2390         if (!cpu_has_virtual_nmis()) {
2391                 enable_irq_window(vcpu);
2392                 return;
2393         }
2394
2395         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2396         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
2397         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2398 }
2399
2400 static void vmx_inject_irq(struct kvm_vcpu *vcpu, int irq)
2401 {
2402         struct vcpu_vmx *vmx = to_vmx(vcpu);
2403
2404         KVMTRACE_1D(INJ_VIRQ, vcpu, (u32)irq, handler);
2405
2406         ++vcpu->stat.irq_injections;
2407         if (vcpu->arch.rmode.active) {
2408                 vmx->rmode.irq.pending = true;
2409                 vmx->rmode.irq.vector = irq;
2410                 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
2411                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2412                              irq | INTR_TYPE_SOFT_INTR | INTR_INFO_VALID_MASK);
2413                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
2414                 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
2415                 return;
2416         }
2417         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2418                         irq | INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
2419 }
2420
2421 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
2422 {
2423         struct vcpu_vmx *vmx = to_vmx(vcpu);
2424
2425         if (!cpu_has_virtual_nmis()) {
2426                 /*
2427                  * Tracking the NMI-blocked state in software is built upon
2428                  * finding the next open IRQ window. This, in turn, depends on
2429                  * well-behaving guests: They have to keep IRQs disabled at
2430                  * least as long as the NMI handler runs. Otherwise we may
2431                  * cause NMI nesting, maybe breaking the guest. But as this is
2432                  * highly unlikely, we can live with the residual risk.
2433                  */
2434                 vmx->soft_vnmi_blocked = 1;
2435                 vmx->vnmi_blocked_time = 0;
2436         }
2437
2438         ++vcpu->stat.nmi_injections;
2439         if (vcpu->arch.rmode.active) {
2440                 vmx->rmode.irq.pending = true;
2441                 vmx->rmode.irq.vector = NMI_VECTOR;
2442                 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
2443                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2444                              NMI_VECTOR | INTR_TYPE_SOFT_INTR |
2445                              INTR_INFO_VALID_MASK);
2446                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
2447                 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
2448                 return;
2449         }
2450         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2451                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
2452 }
2453
2454 static void vmx_update_window_states(struct kvm_vcpu *vcpu)
2455 {
2456         u32 guest_intr = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2457
2458         vcpu->arch.nmi_window_open =
2459                 !(guest_intr & (GUEST_INTR_STATE_STI |
2460                                 GUEST_INTR_STATE_MOV_SS |
2461                                 GUEST_INTR_STATE_NMI));
2462         if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
2463                 vcpu->arch.nmi_window_open = 0;
2464
2465         vcpu->arch.interrupt_window_open =
2466                 ((vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
2467                  !(guest_intr & (GUEST_INTR_STATE_STI |
2468                                  GUEST_INTR_STATE_MOV_SS)));
2469 }
2470
2471 static void kvm_do_inject_irq(struct kvm_vcpu *vcpu)
2472 {
2473         int word_index = __ffs(vcpu->arch.irq_summary);
2474         int bit_index = __ffs(vcpu->arch.irq_pending[word_index]);
2475         int irq = word_index * BITS_PER_LONG + bit_index;
2476
2477         clear_bit(bit_index, &vcpu->arch.irq_pending[word_index]);
2478         if (!vcpu->arch.irq_pending[word_index])
2479                 clear_bit(word_index, &vcpu->arch.irq_summary);
2480         kvm_queue_interrupt(vcpu, irq);
2481 }
2482
2483 static void do_interrupt_requests(struct kvm_vcpu *vcpu,
2484                                        struct kvm_run *kvm_run)
2485 {
2486         vmx_update_window_states(vcpu);
2487
2488         if (vcpu->arch.nmi_pending && !vcpu->arch.nmi_injected) {
2489                 if (vcpu->arch.interrupt.pending) {
2490                         enable_nmi_window(vcpu);
2491                 } else if (vcpu->arch.nmi_window_open) {
2492                         vcpu->arch.nmi_pending = false;
2493                         vcpu->arch.nmi_injected = true;
2494                 } else {
2495                         enable_nmi_window(vcpu);
2496                         return;
2497                 }
2498         }
2499         if (vcpu->arch.nmi_injected) {
2500                 vmx_inject_nmi(vcpu);
2501                 if (vcpu->arch.nmi_pending || kvm_run->request_nmi_window)
2502                         enable_nmi_window(vcpu);
2503                 else if (vcpu->arch.irq_summary
2504                          || kvm_run->request_interrupt_window)
2505                         enable_irq_window(vcpu);
2506                 return;
2507         }
2508         if (!vcpu->arch.nmi_window_open || kvm_run->request_nmi_window)
2509                 enable_nmi_window(vcpu);
2510
2511         if (vcpu->arch.interrupt_window_open) {
2512                 if (vcpu->arch.irq_summary && !vcpu->arch.interrupt.pending)
2513                         kvm_do_inject_irq(vcpu);
2514
2515                 if (vcpu->arch.interrupt.pending)
2516                         vmx_inject_irq(vcpu, vcpu->arch.interrupt.nr);
2517         }
2518         if (!vcpu->arch.interrupt_window_open &&
2519             (vcpu->arch.irq_summary || kvm_run->request_interrupt_window))
2520                 enable_irq_window(vcpu);
2521 }
2522
2523 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
2524 {
2525         int ret;
2526         struct kvm_userspace_memory_region tss_mem = {
2527                 .slot = TSS_PRIVATE_MEMSLOT,
2528                 .guest_phys_addr = addr,
2529                 .memory_size = PAGE_SIZE * 3,
2530                 .flags = 0,
2531         };
2532
2533         ret = kvm_set_memory_region(kvm, &tss_mem, 0);
2534         if (ret)
2535                 return ret;
2536         kvm->arch.tss_addr = addr;
2537         return 0;
2538 }
2539
2540 static void kvm_guest_debug_pre(struct kvm_vcpu *vcpu)
2541 {
2542         struct kvm_guest_debug *dbg = &vcpu->guest_debug;
2543
2544         set_debugreg(dbg->bp[0], 0);
2545         set_debugreg(dbg->bp[1], 1);
2546         set_debugreg(dbg->bp[2], 2);
2547         set_debugreg(dbg->bp[3], 3);
2548
2549         if (dbg->singlestep) {
2550                 unsigned long flags;
2551
2552                 flags = vmcs_readl(GUEST_RFLAGS);
2553                 flags |= X86_EFLAGS_TF | X86_EFLAGS_RF;
2554                 vmcs_writel(GUEST_RFLAGS, flags);
2555         }
2556 }
2557
2558 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
2559                                   int vec, u32 err_code)
2560 {
2561         /*
2562          * Instruction with address size override prefix opcode 0x67
2563          * Cause the #SS fault with 0 error code in VM86 mode.
2564          */
2565         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
2566                 if (emulate_instruction(vcpu, NULL, 0, 0, 0) == EMULATE_DONE)
2567                         return 1;
2568         /*
2569          * Forward all other exceptions that are valid in real mode.
2570          * FIXME: Breaks guest debugging in real mode, needs to be fixed with
2571          *        the required debugging infrastructure rework.
2572          */
2573         switch (vec) {
2574         case DE_VECTOR:
2575         case DB_VECTOR:
2576         case BP_VECTOR:
2577         case OF_VECTOR:
2578         case BR_VECTOR:
2579         case UD_VECTOR:
2580         case DF_VECTOR:
2581         case SS_VECTOR:
2582         case GP_VECTOR:
2583         case MF_VECTOR:
2584                 kvm_queue_exception(vcpu, vec);
2585                 return 1;
2586         }
2587         return 0;
2588 }
2589
2590 static int handle_exception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2591 {
2592         struct vcpu_vmx *vmx = to_vmx(vcpu);
2593         u32 intr_info, error_code;
2594         unsigned long cr2, rip;
2595         u32 vect_info;
2596         enum emulation_result er;
2597
2598         vect_info = vmx->idt_vectoring_info;
2599         intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
2600
2601         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
2602                                                 !is_page_fault(intr_info))
2603                 printk(KERN_ERR "%s: unexpected, vectoring info 0x%x "
2604                        "intr info 0x%x\n", __func__, vect_info, intr_info);
2605
2606         if (!irqchip_in_kernel(vcpu->kvm) && is_external_interrupt(vect_info)) {
2607                 int irq = vect_info & VECTORING_INFO_VECTOR_MASK;
2608                 set_bit(irq, vcpu->arch.irq_pending);
2609                 set_bit(irq / BITS_PER_LONG, &vcpu->arch.irq_summary);
2610         }
2611
2612         if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
2613                 return 1;  /* already handled by vmx_vcpu_run() */
2614
2615         if (is_no_device(intr_info)) {
2616                 vmx_fpu_activate(vcpu);
2617                 return 1;
2618         }
2619
2620         if (is_invalid_opcode(intr_info)) {
2621                 er = emulate_instruction(vcpu, kvm_run, 0, 0, EMULTYPE_TRAP_UD);
2622                 if (er != EMULATE_DONE)
2623                         kvm_queue_exception(vcpu, UD_VECTOR);
2624                 return 1;
2625         }
2626
2627         error_code = 0;
2628         rip = kvm_rip_read(vcpu);
2629         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
2630                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
2631         if (is_page_fault(intr_info)) {
2632                 /* EPT won't cause page fault directly */
2633                 if (vm_need_ept())
2634                         BUG();
2635                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
2636                 KVMTRACE_3D(PAGE_FAULT, vcpu, error_code, (u32)cr2,
2637                             (u32)((u64)cr2 >> 32), handler);
2638                 if (vcpu->arch.interrupt.pending || vcpu->arch.exception.pending)
2639                         kvm_mmu_unprotect_page_virt(vcpu, cr2);
2640                 return kvm_mmu_page_fault(vcpu, cr2, error_code);
2641         }
2642
2643         if (vcpu->arch.rmode.active &&
2644             handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
2645                                                                 error_code)) {
2646                 if (vcpu->arch.halt_request) {
2647                         vcpu->arch.halt_request = 0;
2648                         return kvm_emulate_halt(vcpu);
2649                 }
2650                 return 1;
2651         }
2652
2653         if ((intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK)) ==
2654             (INTR_TYPE_EXCEPTION | 1)) {
2655                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
2656                 return 0;
2657         }
2658         kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
2659         kvm_run->ex.exception = intr_info & INTR_INFO_VECTOR_MASK;
2660         kvm_run->ex.error_code = error_code;
2661         return 0;
2662 }
2663
2664 static int handle_external_interrupt(struct kvm_vcpu *vcpu,
2665                                      struct kvm_run *kvm_run)
2666 {
2667         ++vcpu->stat.irq_exits;
2668         KVMTRACE_1D(INTR, vcpu, vmcs_read32(VM_EXIT_INTR_INFO), handler);
2669         return 1;
2670 }
2671
2672 static int handle_triple_fault(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2673 {
2674         kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
2675         return 0;
2676 }
2677
2678 static int handle_io(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2679 {
2680         unsigned long exit_qualification;
2681         int size, down, in, string, rep;
2682         unsigned port;
2683
2684         ++vcpu->stat.io_exits;
2685         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2686         string = (exit_qualification & 16) != 0;
2687
2688         if (string) {
2689                 if (emulate_instruction(vcpu,
2690                                         kvm_run, 0, 0, 0) == EMULATE_DO_MMIO)
2691                         return 0;
2692                 return 1;
2693         }
2694
2695         size = (exit_qualification & 7) + 1;
2696         in = (exit_qualification & 8) != 0;
2697         down = (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_DF) != 0;
2698         rep = (exit_qualification & 32) != 0;
2699         port = exit_qualification >> 16;
2700
2701         skip_emulated_instruction(vcpu);
2702         return kvm_emulate_pio(vcpu, kvm_run, in, size, port);
2703 }
2704
2705 static void
2706 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
2707 {
2708         /*
2709          * Patch in the VMCALL instruction:
2710          */
2711         hypercall[0] = 0x0f;
2712         hypercall[1] = 0x01;
2713         hypercall[2] = 0xc1;
2714 }
2715
2716 static int handle_cr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2717 {
2718         unsigned long exit_qualification;
2719         int cr;
2720         int reg;
2721
2722         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2723         cr = exit_qualification & 15;
2724         reg = (exit_qualification >> 8) & 15;
2725         switch ((exit_qualification >> 4) & 3) {
2726         case 0: /* mov to cr */
2727                 KVMTRACE_3D(CR_WRITE, vcpu, (u32)cr,
2728                             (u32)kvm_register_read(vcpu, reg),
2729                             (u32)((u64)kvm_register_read(vcpu, reg) >> 32),
2730                             handler);
2731                 switch (cr) {
2732                 case 0:
2733                         kvm_set_cr0(vcpu, kvm_register_read(vcpu, reg));
2734                         skip_emulated_instruction(vcpu);
2735                         return 1;
2736                 case 3:
2737                         kvm_set_cr3(vcpu, kvm_register_read(vcpu, reg));
2738                         skip_emulated_instruction(vcpu);
2739                         return 1;
2740                 case 4:
2741                         kvm_set_cr4(vcpu, kvm_register_read(vcpu, reg));
2742                         skip_emulated_instruction(vcpu);
2743                         return 1;
2744                 case 8:
2745                         kvm_set_cr8(vcpu, kvm_register_read(vcpu, reg));
2746                         skip_emulated_instruction(vcpu);
2747                         if (irqchip_in_kernel(vcpu->kvm))
2748                                 return 1;
2749                         kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2750                         return 0;
2751                 };
2752                 break;
2753         case 2: /* clts */
2754                 vmx_fpu_deactivate(vcpu);
2755                 vcpu->arch.cr0 &= ~X86_CR0_TS;
2756                 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
2757                 vmx_fpu_activate(vcpu);
2758                 KVMTRACE_0D(CLTS, vcpu, handler);
2759                 skip_emulated_instruction(vcpu);
2760                 return 1;
2761         case 1: /*mov from cr*/
2762                 switch (cr) {
2763                 case 3:
2764                         kvm_register_write(vcpu, reg, vcpu->arch.cr3);
2765                         KVMTRACE_3D(CR_READ, vcpu, (u32)cr,
2766                                     (u32)kvm_register_read(vcpu, reg),
2767                                     (u32)((u64)kvm_register_read(vcpu, reg) >> 32),
2768                                     handler);
2769                         skip_emulated_instruction(vcpu);
2770                         return 1;
2771                 case 8:
2772                         kvm_register_write(vcpu, reg, kvm_get_cr8(vcpu));
2773                         KVMTRACE_2D(CR_READ, vcpu, (u32)cr,
2774                                     (u32)kvm_register_read(vcpu, reg), handler);
2775                         skip_emulated_instruction(vcpu);
2776                         return 1;
2777                 }
2778                 break;
2779         case 3: /* lmsw */
2780                 kvm_lmsw(vcpu, (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f);
2781
2782                 skip_emulated_instruction(vcpu);
2783                 return 1;
2784         default:
2785                 break;
2786         }
2787         kvm_run->exit_reason = 0;
2788         pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
2789                (int)(exit_qualification >> 4) & 3, cr);
2790         return 0;
2791 }
2792
2793 static int handle_dr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2794 {
2795         unsigned long exit_qualification;
2796         unsigned long val;
2797         int dr, reg;
2798
2799         /*
2800          * FIXME: this code assumes the host is debugging the guest.
2801          *        need to deal with guest debugging itself too.
2802          */
2803         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2804         dr = exit_qualification & 7;
2805         reg = (exit_qualification >> 8) & 15;
2806         if (exit_qualification & 16) {
2807                 /* mov from dr */
2808                 switch (dr) {
2809                 case 6:
2810                         val = 0xffff0ff0;
2811                         break;
2812                 case 7:
2813                         val = 0x400;
2814                         break;
2815                 default:
2816                         val = 0;
2817                 }
2818                 kvm_register_write(vcpu, reg, val);
2819                 KVMTRACE_2D(DR_READ, vcpu, (u32)dr, (u32)val, handler);
2820         } else {
2821                 /* mov to dr */
2822         }
2823         skip_emulated_instruction(vcpu);
2824         return 1;
2825 }
2826
2827 static int handle_cpuid(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2828 {
2829         kvm_emulate_cpuid(vcpu);
2830         return 1;
2831 }
2832
2833 static int handle_rdmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2834 {
2835         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
2836         u64 data;
2837
2838         if (vmx_get_msr(vcpu, ecx, &data)) {
2839                 kvm_inject_gp(vcpu, 0);
2840                 return 1;
2841         }
2842
2843         KVMTRACE_3D(MSR_READ, vcpu, ecx, (u32)data, (u32)(data >> 32),
2844                     handler);
2845
2846         /* FIXME: handling of bits 32:63 of rax, rdx */
2847         vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
2848         vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
2849         skip_emulated_instruction(vcpu);
2850         return 1;
2851 }
2852
2853 static int handle_wrmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2854 {
2855         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
2856         u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
2857                 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
2858
2859         KVMTRACE_3D(MSR_WRITE, vcpu, ecx, (u32)data, (u32)(data >> 32),
2860                     handler);
2861
2862         if (vmx_set_msr(vcpu, ecx, data) != 0) {
2863                 kvm_inject_gp(vcpu, 0);
2864                 return 1;
2865         }
2866
2867         skip_emulated_instruction(vcpu);
2868         return 1;
2869 }
2870
2871 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu,
2872                                       struct kvm_run *kvm_run)
2873 {
2874         return 1;
2875 }
2876
2877 static int handle_interrupt_window(struct kvm_vcpu *vcpu,
2878                                    struct kvm_run *kvm_run)
2879 {
2880         u32 cpu_based_vm_exec_control;
2881
2882         /* clear pending irq */
2883         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2884         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
2885         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2886
2887         KVMTRACE_0D(PEND_INTR, vcpu, handler);
2888         ++vcpu->stat.irq_window_exits;
2889
2890         /*
2891          * If the user space waits to inject interrupts, exit as soon as
2892          * possible
2893          */
2894         if (kvm_run->request_interrupt_window &&
2895             !vcpu->arch.irq_summary) {
2896                 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
2897                 return 0;
2898         }
2899         return 1;
2900 }
2901
2902 static int handle_halt(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2903 {
2904         skip_emulated_instruction(vcpu);
2905         return kvm_emulate_halt(vcpu);
2906 }
2907
2908 static int handle_vmcall(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2909 {
2910         skip_emulated_instruction(vcpu);
2911         kvm_emulate_hypercall(vcpu);
2912         return 1;
2913 }
2914
2915 static int handle_invlpg(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2916 {
2917         u64 exit_qualification = vmcs_read64(EXIT_QUALIFICATION);
2918
2919         kvm_mmu_invlpg(vcpu, exit_qualification);
2920         skip_emulated_instruction(vcpu);
2921         return 1;
2922 }
2923
2924 static int handle_wbinvd(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2925 {
2926         skip_emulated_instruction(vcpu);
2927         /* TODO: Add support for VT-d/pass-through device */
2928         return 1;
2929 }
2930
2931 static int handle_apic_access(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2932 {
2933         u64 exit_qualification;
2934         enum emulation_result er;
2935         unsigned long offset;
2936
2937         exit_qualification = vmcs_read64(EXIT_QUALIFICATION);
2938         offset = exit_qualification & 0xffful;
2939
2940         er = emulate_instruction(vcpu, kvm_run, 0, 0, 0);
2941
2942         if (er !=  EMULATE_DONE) {
2943                 printk(KERN_ERR
2944                        "Fail to handle apic access vmexit! Offset is 0x%lx\n",
2945                        offset);
2946                 return -ENOTSUPP;
2947         }
2948         return 1;
2949 }
2950
2951 static int handle_task_switch(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2952 {
2953         struct vcpu_vmx *vmx = to_vmx(vcpu);
2954         unsigned long exit_qualification;
2955         u16 tss_selector;
2956         int reason;
2957
2958         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2959
2960         reason = (u32)exit_qualification >> 30;
2961         if (reason == TASK_SWITCH_GATE && vmx->vcpu.arch.nmi_injected &&
2962             (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
2963             (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK)
2964             == INTR_TYPE_NMI_INTR) {
2965                 vcpu->arch.nmi_injected = false;
2966                 if (cpu_has_virtual_nmis())
2967                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
2968                                       GUEST_INTR_STATE_NMI);
2969         }
2970         tss_selector = exit_qualification;
2971
2972         return kvm_task_switch(vcpu, tss_selector, reason);
2973 }
2974
2975 static int handle_ept_violation(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2976 {
2977         u64 exit_qualification;
2978         enum emulation_result er;
2979         gpa_t gpa;
2980         unsigned long hva;
2981         int gla_validity;
2982         int r;
2983
2984         exit_qualification = vmcs_read64(EXIT_QUALIFICATION);
2985
2986         if (exit_qualification & (1 << 6)) {
2987                 printk(KERN_ERR "EPT: GPA exceeds GAW!\n");
2988                 return -ENOTSUPP;
2989         }
2990
2991         gla_validity = (exit_qualification >> 7) & 0x3;
2992         if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
2993                 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
2994                 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
2995                         (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
2996                         (long unsigned int)vmcs_read64(GUEST_LINEAR_ADDRESS));
2997                 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
2998                         (long unsigned int)exit_qualification);
2999                 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
3000                 kvm_run->hw.hardware_exit_reason = 0;
3001                 return -ENOTSUPP;
3002         }
3003
3004         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
3005         hva = gfn_to_hva(vcpu->kvm, gpa >> PAGE_SHIFT);
3006         if (!kvm_is_error_hva(hva)) {
3007                 r = kvm_mmu_page_fault(vcpu, gpa & PAGE_MASK, 0);
3008                 if (r < 0) {
3009                         printk(KERN_ERR "EPT: Not enough memory!\n");
3010                         return -ENOMEM;
3011                 }
3012                 return 1;
3013         } else {
3014                 /* must be MMIO */
3015                 er = emulate_instruction(vcpu, kvm_run, 0, 0, 0);
3016
3017                 if (er == EMULATE_FAIL) {
3018                         printk(KERN_ERR
3019                          "EPT: Fail to handle EPT violation vmexit!er is %d\n",
3020                          er);
3021                         printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
3022                          (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
3023                          (long unsigned int)vmcs_read64(GUEST_LINEAR_ADDRESS));
3024                         printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
3025                                 (long unsigned int)exit_qualification);
3026                         return -ENOTSUPP;
3027                 } else if (er == EMULATE_DO_MMIO)
3028                         return 0;
3029         }
3030         return 1;
3031 }
3032
3033 static int handle_nmi_window(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3034 {
3035         u32 cpu_based_vm_exec_control;
3036
3037         /* clear pending NMI */
3038         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3039         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
3040         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3041         ++vcpu->stat.nmi_window_exits;
3042
3043         /*
3044          * If the user space waits to inject a NMI, exit as soon as possible
3045          */
3046         if (kvm_run->request_nmi_window && !vcpu->arch.nmi_pending) {
3047                 kvm_run->exit_reason = KVM_EXIT_NMI_WINDOW_OPEN;
3048                 return 0;
3049         }
3050
3051         return 1;
3052 }
3053
3054 static void handle_invalid_guest_state(struct kvm_vcpu *vcpu,
3055                                 struct kvm_run *kvm_run)
3056 {
3057         struct vcpu_vmx *vmx = to_vmx(vcpu);
3058         int err;
3059
3060         preempt_enable();
3061         local_irq_enable();
3062
3063         while (!guest_state_valid(vcpu)) {
3064                 err = emulate_instruction(vcpu, kvm_run, 0, 0, 0);
3065
3066                 if (err == EMULATE_DO_MMIO)
3067                         break;
3068
3069                 if (err != EMULATE_DONE) {
3070                         kvm_report_emulation_failure(vcpu, "emulation failure");
3071                         return;
3072                 }
3073
3074                 if (signal_pending(current))
3075                         break;
3076                 if (need_resched())
3077                         schedule();
3078         }
3079
3080         local_irq_disable();
3081         preempt_disable();
3082
3083         /* Guest state should be valid now except if we need to
3084          * emulate an MMIO */
3085         if (guest_state_valid(vcpu))
3086                 vmx->emulation_required = 0;
3087 }
3088
3089 /*
3090  * The exit handlers return 1 if the exit was handled fully and guest execution
3091  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
3092  * to be done to userspace and return 0.
3093  */
3094 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu,
3095                                       struct kvm_run *kvm_run) = {
3096         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception,
3097         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
3098         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
3099         [EXIT_REASON_NMI_WINDOW]              = handle_nmi_window,
3100         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
3101         [EXIT_REASON_CR_ACCESS]               = handle_cr,
3102         [EXIT_REASON_DR_ACCESS]               = handle_dr,
3103         [EXIT_REASON_CPUID]                   = handle_cpuid,
3104         [EXIT_REASON_MSR_READ]                = handle_rdmsr,
3105         [EXIT_REASON_MSR_WRITE]               = handle_wrmsr,
3106         [EXIT_REASON_PENDING_INTERRUPT]       = handle_interrupt_window,
3107         [EXIT_REASON_HLT]                     = handle_halt,
3108         [EXIT_REASON_INVLPG]                  = handle_invlpg,
3109         [EXIT_REASON_VMCALL]                  = handle_vmcall,
3110         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
3111         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
3112         [EXIT_REASON_WBINVD]                  = handle_wbinvd,
3113         [EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
3114         [EXIT_REASON_EPT_VIOLATION]           = handle_ept_violation,
3115 };
3116
3117 static const int kvm_vmx_max_exit_handlers =
3118         ARRAY_SIZE(kvm_vmx_exit_handlers);
3119
3120 /*
3121  * The guest has exited.  See if we can fix it or if we need userspace
3122  * assistance.
3123  */
3124 static int kvm_handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
3125 {
3126         u32 exit_reason = vmcs_read32(VM_EXIT_REASON);
3127         struct vcpu_vmx *vmx = to_vmx(vcpu);
3128         u32 vectoring_info = vmx->idt_vectoring_info;
3129
3130         KVMTRACE_3D(VMEXIT, vcpu, exit_reason, (u32)kvm_rip_read(vcpu),
3131                     (u32)((u64)kvm_rip_read(vcpu) >> 32), entryexit);
3132
3133         /* If we need to emulate an MMIO from handle_invalid_guest_state
3134          * we just return 0 */
3135         if (vmx->emulation_required && emulate_invalid_guest_state)
3136                 return 0;
3137
3138         /* Access CR3 don't cause VMExit in paging mode, so we need
3139          * to sync with guest real CR3. */
3140         if (vm_need_ept() && is_paging(vcpu)) {
3141                 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3142                 ept_load_pdptrs(vcpu);
3143         }
3144
3145         if (unlikely(vmx->fail)) {
3146                 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3147                 kvm_run->fail_entry.hardware_entry_failure_reason
3148                         = vmcs_read32(VM_INSTRUCTION_ERROR);
3149                 return 0;
3150         }
3151
3152         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
3153                         (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
3154                         exit_reason != EXIT_REASON_EPT_VIOLATION &&
3155                         exit_reason != EXIT_REASON_TASK_SWITCH))
3156                 printk(KERN_WARNING "%s: unexpected, valid vectoring info "
3157                        "(0x%x) and exit reason is 0x%x\n",
3158                        __func__, vectoring_info, exit_reason);
3159
3160         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked)) {
3161                 if (vcpu->arch.interrupt_window_open) {
3162                         vmx->soft_vnmi_blocked = 0;
3163                         vcpu->arch.nmi_window_open = 1;
3164                 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
3165                     (kvm_run->request_nmi_window || vcpu->arch.nmi_pending)) {
3166                         /*
3167                          * This CPU don't support us in finding the end of an
3168                          * NMI-blocked window if the guest runs with IRQs
3169                          * disabled. So we pull the trigger after 1 s of
3170                          * futile waiting, but inform the user about this.
3171                          */
3172                         printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
3173                                "state on VCPU %d after 1 s timeout\n",
3174                                __func__, vcpu->vcpu_id);
3175                         vmx->soft_vnmi_blocked = 0;
3176                         vmx->vcpu.arch.nmi_window_open = 1;
3177                 }
3178
3179                 /*
3180                  * If the user space waits to inject an NNI, exit ASAP
3181                  */
3182                 if (vcpu->arch.nmi_window_open && kvm_run->request_nmi_window
3183                     && !vcpu->arch.nmi_pending) {
3184                         kvm_run->exit_reason = KVM_EXIT_NMI_WINDOW_OPEN;
3185                         ++vcpu->stat.nmi_window_exits;
3186                         return 0;
3187                 }
3188         }
3189
3190         if (exit_reason < kvm_vmx_max_exit_handlers
3191             && kvm_vmx_exit_handlers[exit_reason])
3192                 return kvm_vmx_exit_handlers[exit_reason](vcpu, kvm_run);
3193         else {
3194                 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
3195                 kvm_run->hw.hardware_exit_reason = exit_reason;
3196         }
3197         return 0;
3198 }
3199
3200 static void update_tpr_threshold(struct kvm_vcpu *vcpu)
3201 {
3202         int max_irr, tpr;
3203
3204         if (!vm_need_tpr_shadow(vcpu->kvm))
3205                 return;
3206
3207         if (!kvm_lapic_enabled(vcpu) ||
3208             ((max_irr = kvm_lapic_find_highest_irr(vcpu)) == -1)) {
3209                 vmcs_write32(TPR_THRESHOLD, 0);
3210                 return;
3211         }
3212
3213         tpr = (kvm_lapic_get_cr8(vcpu) & 0x0f) << 4;
3214         vmcs_write32(TPR_THRESHOLD, (max_irr > tpr) ? tpr >> 4 : max_irr >> 4);
3215 }
3216
3217 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
3218 {
3219         u32 exit_intr_info;
3220         u32 idt_vectoring_info;
3221         bool unblock_nmi;
3222         u8 vector;
3223         int type;
3224         bool idtv_info_valid;
3225         u32 error;
3226
3227         exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
3228         if (cpu_has_virtual_nmis()) {
3229                 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
3230                 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
3231                 /*
3232                  * SDM 3: 25.7.1.2
3233                  * Re-set bit "block by NMI" before VM entry if vmexit caused by
3234                  * a guest IRET fault.
3235                  */
3236                 if (unblock_nmi && vector != DF_VECTOR)
3237                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3238                                       GUEST_INTR_STATE_NMI);
3239         } else if (unlikely(vmx->soft_vnmi_blocked))
3240                 vmx->vnmi_blocked_time +=
3241                         ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
3242
3243         idt_vectoring_info = vmx->idt_vectoring_info;
3244         idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
3245         vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
3246         type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
3247         if (vmx->vcpu.arch.nmi_injected) {
3248                 /*
3249                  * SDM 3: 25.7.1.2
3250                  * Clear bit "block by NMI" before VM entry if a NMI delivery
3251                  * faulted.
3252                  */
3253                 if (idtv_info_valid && type == INTR_TYPE_NMI_INTR)
3254                         vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
3255                                         GUEST_INTR_STATE_NMI);
3256                 else
3257                         vmx->vcpu.arch.nmi_injected = false;
3258         }
3259         kvm_clear_exception_queue(&vmx->vcpu);
3260         if (idtv_info_valid && type == INTR_TYPE_EXCEPTION) {
3261                 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
3262                         error = vmcs_read32(IDT_VECTORING_ERROR_CODE);
3263                         kvm_queue_exception_e(&vmx->vcpu, vector, error);
3264                 } else
3265                         kvm_queue_exception(&vmx->vcpu, vector);
3266                 vmx->idt_vectoring_info = 0;
3267         }
3268         kvm_clear_interrupt_queue(&vmx->vcpu);
3269         if (idtv_info_valid && type == INTR_TYPE_EXT_INTR) {
3270                 kvm_queue_interrupt(&vmx->vcpu, vector);
3271                 vmx->idt_vectoring_info = 0;
3272         }
3273 }
3274
3275 static void vmx_intr_assist(struct kvm_vcpu *vcpu)
3276 {
3277         update_tpr_threshold(vcpu);
3278
3279         vmx_update_window_states(vcpu);
3280
3281         if (vcpu->arch.nmi_pending && !vcpu->arch.nmi_injected) {
3282                 if (vcpu->arch.interrupt.pending) {
3283                         enable_nmi_window(vcpu);
3284                 } else if (vcpu->arch.nmi_window_open) {
3285                         vcpu->arch.nmi_pending = false;
3286                         vcpu->arch.nmi_injected = true;
3287                 } else {
3288                         enable_nmi_window(vcpu);
3289                         return;
3290                 }
3291         }
3292         if (vcpu->arch.nmi_injected) {
3293                 vmx_inject_nmi(vcpu);
3294                 if (vcpu->arch.nmi_pending)
3295                         enable_nmi_window(vcpu);
3296                 else if (kvm_cpu_has_interrupt(vcpu))
3297                         enable_irq_window(vcpu);
3298                 return;
3299         }
3300         if (!vcpu->arch.interrupt.pending && kvm_cpu_has_interrupt(vcpu)) {
3301                 if (vcpu->arch.interrupt_window_open)
3302                         kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu));
3303                 else
3304                         enable_irq_window(vcpu);
3305         }
3306         if (vcpu->arch.interrupt.pending) {
3307                 vmx_inject_irq(vcpu, vcpu->arch.interrupt.nr);
3308                 kvm_timer_intr_post(vcpu, vcpu->arch.interrupt.nr);
3309                 if (kvm_cpu_has_interrupt(vcpu))
3310                         enable_irq_window(vcpu);
3311         }
3312 }
3313
3314 /*
3315  * Failure to inject an interrupt should give us the information
3316  * in IDT_VECTORING_INFO_FIELD.  However, if the failure occurs
3317  * when fetching the interrupt redirection bitmap in the real-mode
3318  * tss, this doesn't happen.  So we do it ourselves.
3319  */
3320 static void fixup_rmode_irq(struct vcpu_vmx *vmx)
3321 {
3322         vmx->rmode.irq.pending = 0;
3323         if (kvm_rip_read(&vmx->vcpu) + 1 != vmx->rmode.irq.rip)
3324                 return;
3325         kvm_rip_write(&vmx->vcpu, vmx->rmode.irq.rip);
3326         if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) {
3327                 vmx->idt_vectoring_info &= ~VECTORING_INFO_TYPE_MASK;
3328                 vmx->idt_vectoring_info |= INTR_TYPE_EXT_INTR;
3329                 return;
3330         }
3331         vmx->idt_vectoring_info =
3332                 VECTORING_INFO_VALID_MASK
3333                 | INTR_TYPE_EXT_INTR
3334                 | vmx->rmode.irq.vector;
3335 }
3336
3337 #ifdef CONFIG_X86_64
3338 #define R "r"
3339 #define Q "q"
3340 #else
3341 #define R "e"
3342 #define Q "l"
3343 #endif
3344
3345 static void vmx_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3346 {
3347         struct vcpu_vmx *vmx = to_vmx(vcpu);
3348         u32 intr_info;
3349
3350         /* Record the guest's net vcpu time for enforced NMI injections. */
3351         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
3352                 vmx->entry_time = ktime_get();
3353
3354         /* Handle invalid guest state instead of entering VMX */
3355         if (vmx->emulation_required && emulate_invalid_guest_state) {
3356                 handle_invalid_guest_state(vcpu, kvm_run);
3357                 return;
3358         }
3359
3360         if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
3361                 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
3362         if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
3363                 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
3364
3365         /*
3366          * Loading guest fpu may have cleared host cr0.ts
3367          */
3368         vmcs_writel(HOST_CR0, read_cr0());
3369
3370         asm(
3371                 /* Store host registers */
3372                 "push %%"R"dx; push %%"R"bp;"
3373                 "push %%"R"cx \n\t"
3374                 "cmp %%"R"sp, %c[host_rsp](%0) \n\t"
3375                 "je 1f \n\t"
3376                 "mov %%"R"sp, %c[host_rsp](%0) \n\t"
3377                 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
3378                 "1: \n\t"
3379                 /* Check if vmlaunch of vmresume is needed */
3380                 "cmpl $0, %c[launched](%0) \n\t"
3381                 /* Load guest registers.  Don't clobber flags. */
3382                 "mov %c[cr2](%0), %%"R"ax \n\t"
3383                 "mov %%"R"ax, %%cr2 \n\t"
3384                 "mov %c[rax](%0), %%"R"ax \n\t"
3385                 "mov %c[rbx](%0), %%"R"bx \n\t"
3386                 "mov %c[rdx](%0), %%"R"dx \n\t"
3387                 "mov %c[rsi](%0), %%"R"si \n\t"
3388                 "mov %c[rdi](%0), %%"R"di \n\t"
3389                 "mov %c[rbp](%0), %%"R"bp \n\t"
3390 #ifdef CONFIG_X86_64
3391                 "mov %c[r8](%0),  %%r8  \n\t"
3392                 "mov %c[r9](%0),  %%r9  \n\t"
3393                 "mov %c[r10](%0), %%r10 \n\t"
3394                 "mov %c[r11](%0), %%r11 \n\t"
3395                 "mov %c[r12](%0), %%r12 \n\t"
3396                 "mov %c[r13](%0), %%r13 \n\t"
3397                 "mov %c[r14](%0), %%r14 \n\t"
3398                 "mov %c[r15](%0), %%r15 \n\t"
3399 #endif
3400                 "mov %c[rcx](%0), %%"R"cx \n\t" /* kills %0 (ecx) */
3401
3402                 /* Enter guest mode */
3403                 "jne .Llaunched \n\t"
3404                 __ex(ASM_VMX_VMLAUNCH) "\n\t"
3405                 "jmp .Lkvm_vmx_return \n\t"
3406                 ".Llaunched: " __ex(ASM_VMX_VMRESUME) "\n\t"
3407                 ".Lkvm_vmx_return: "
3408                 /* Save guest registers, load host registers, keep flags */
3409                 "xchg %0,     (%%"R"sp) \n\t"
3410                 "mov %%"R"ax, %c[rax](%0) \n\t"
3411                 "mov %%"R"bx, %c[rbx](%0) \n\t"
3412                 "push"Q" (%%"R"sp); pop"Q" %c[rcx](%0) \n\t"
3413                 "mov %%"R"dx, %c[rdx](%0) \n\t"
3414                 "mov %%"R"si, %c[rsi](%0) \n\t"
3415                 "mov %%"R"di, %c[rdi](%0) \n\t"
3416                 "mov %%"R"bp, %c[rbp](%0) \n\t"
3417 #ifdef CONFIG_X86_64
3418                 "mov %%r8,  %c[r8](%0) \n\t"
3419                 "mov %%r9,  %c[r9](%0) \n\t"
3420                 "mov %%r10, %c[r10](%0) \n\t"
3421                 "mov %%r11, %c[r11](%0) \n\t"
3422                 "mov %%r12, %c[r12](%0) \n\t"
3423                 "mov %%r13, %c[r13](%0) \n\t"
3424                 "mov %%r14, %c[r14](%0) \n\t"
3425                 "mov %%r15, %c[r15](%0) \n\t"
3426 #endif
3427                 "mov %%cr2, %%"R"ax   \n\t"
3428                 "mov %%"R"ax, %c[cr2](%0) \n\t"
3429
3430                 "pop  %%"R"bp; pop  %%"R"bp; pop  %%"R"dx \n\t"
3431                 "setbe %c[fail](%0) \n\t"
3432               : : "c"(vmx), "d"((unsigned long)HOST_RSP),
3433                 [launched]"i"(offsetof(struct vcpu_vmx, launched)),
3434                 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
3435                 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
3436                 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
3437                 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
3438                 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
3439                 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
3440                 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
3441                 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
3442                 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
3443 #ifdef CONFIG_X86_64
3444                 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
3445                 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
3446                 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
3447                 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
3448                 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
3449                 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
3450                 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
3451                 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
3452 #endif
3453                 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2))
3454               : "cc", "memory"
3455                 , R"bx", R"di", R"si"
3456 #ifdef CONFIG_X86_64
3457                 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3458 #endif
3459               );
3460
3461         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
3462         vcpu->arch.regs_dirty = 0;
3463
3464         vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
3465         if (vmx->rmode.irq.pending)
3466                 fixup_rmode_irq(vmx);
3467
3468         vmx_update_window_states(vcpu);
3469
3470         asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
3471         vmx->launched = 1;
3472
3473         intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
3474
3475         /* We need to handle NMIs before interrupts are enabled */
3476         if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
3477             (intr_info & INTR_INFO_VALID_MASK)) {
3478                 KVMTRACE_0D(NMI, vcpu, handler);
3479                 asm("int $2");
3480         }
3481
3482         vmx_complete_interrupts(vmx);
3483 }
3484
3485 #undef R
3486 #undef Q
3487
3488 static void vmx_free_vmcs(struct kvm_vcpu *vcpu)
3489 {
3490         struct vcpu_vmx *vmx = to_vmx(vcpu);
3491
3492         if (vmx->vmcs) {
3493                 vcpu_clear(vmx);
3494                 free_vmcs(vmx->vmcs);
3495                 vmx->vmcs = NULL;
3496         }
3497 }
3498
3499 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
3500 {
3501         struct vcpu_vmx *vmx = to_vmx(vcpu);
3502
3503         spin_lock(&vmx_vpid_lock);
3504         if (vmx->vpid != 0)
3505                 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
3506         spin_unlock(&vmx_vpid_lock);
3507         vmx_free_vmcs(vcpu);
3508         kfree(vmx->host_msrs);
3509         kfree(vmx->guest_msrs);
3510         kvm_vcpu_uninit(vcpu);
3511         kmem_cache_free(kvm_vcpu_cache, vmx);
3512 }
3513
3514 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
3515 {
3516         int err;
3517         struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
3518         int cpu;
3519
3520         if (!vmx)
3521                 return ERR_PTR(-ENOMEM);
3522
3523         allocate_vpid(vmx);
3524
3525         err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
3526         if (err)
3527                 goto free_vcpu;
3528
3529         vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
3530         if (!vmx->guest_msrs) {
3531                 err = -ENOMEM;
3532                 goto uninit_vcpu;
3533         }
3534
3535         vmx->host_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
3536         if (!vmx->host_msrs)
3537                 goto free_guest_msrs;
3538
3539         vmx->vmcs = alloc_vmcs();
3540         if (!vmx->vmcs)
3541                 goto free_msrs;
3542
3543         vmcs_clear(vmx->vmcs);
3544
3545         cpu = get_cpu();
3546         vmx_vcpu_load(&vmx->vcpu, cpu);
3547         err = vmx_vcpu_setup(vmx);
3548         vmx_vcpu_put(&vmx->vcpu);
3549         put_cpu();
3550         if (err)
3551                 goto free_vmcs;
3552         if (vm_need_virtualize_apic_accesses(kvm))
3553                 if (alloc_apic_access_page(kvm) != 0)
3554                         goto free_vmcs;
3555
3556         if (vm_need_ept())
3557                 if (alloc_identity_pagetable(kvm) != 0)
3558                         goto free_vmcs;
3559
3560         return &vmx->vcpu;
3561
3562 free_vmcs:
3563         free_vmcs(vmx->vmcs);
3564 free_msrs:
3565         kfree(vmx->host_msrs);
3566 free_guest_msrs:
3567         kfree(vmx->guest_msrs);
3568 uninit_vcpu:
3569         kvm_vcpu_uninit(&vmx->vcpu);
3570 free_vcpu:
3571         kmem_cache_free(kvm_vcpu_cache, vmx);
3572         return ERR_PTR(err);
3573 }
3574
3575 static void __init vmx_check_processor_compat(void *rtn)
3576 {
3577         struct vmcs_config vmcs_conf;
3578
3579         *(int *)rtn = 0;
3580         if (setup_vmcs_config(&vmcs_conf) < 0)
3581                 *(int *)rtn = -EIO;
3582         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
3583                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
3584                                 smp_processor_id());
3585                 *(int *)rtn = -EIO;
3586         }
3587 }
3588
3589 static int get_ept_level(void)
3590 {
3591         return VMX_EPT_DEFAULT_GAW + 1;
3592 }
3593
3594 static int vmx_get_mt_mask_shift(void)
3595 {
3596         return VMX_EPT_MT_EPTE_SHIFT;
3597 }
3598
3599 static struct kvm_x86_ops vmx_x86_ops = {
3600         .cpu_has_kvm_support = cpu_has_kvm_support,
3601         .disabled_by_bios = vmx_disabled_by_bios,
3602         .hardware_setup = hardware_setup,
3603         .hardware_unsetup = hardware_unsetup,
3604         .check_processor_compatibility = vmx_check_processor_compat,
3605         .hardware_enable = hardware_enable,
3606         .hardware_disable = hardware_disable,
3607         .cpu_has_accelerated_tpr = cpu_has_vmx_virtualize_apic_accesses,
3608
3609         .vcpu_create = vmx_create_vcpu,
3610         .vcpu_free = vmx_free_vcpu,
3611         .vcpu_reset = vmx_vcpu_reset,
3612
3613         .prepare_guest_switch = vmx_save_host_state,
3614         .vcpu_load = vmx_vcpu_load,
3615         .vcpu_put = vmx_vcpu_put,
3616
3617         .set_guest_debug = set_guest_debug,
3618         .guest_debug_pre = kvm_guest_debug_pre,
3619         .get_msr = vmx_get_msr,
3620         .set_msr = vmx_set_msr,
3621         .get_segment_base = vmx_get_segment_base,
3622         .get_segment = vmx_get_segment,
3623         .set_segment = vmx_set_segment,
3624         .get_cpl = vmx_get_cpl,
3625         .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
3626         .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
3627         .set_cr0 = vmx_set_cr0,
3628         .set_cr3 = vmx_set_cr3,
3629         .set_cr4 = vmx_set_cr4,
3630         .set_efer = vmx_set_efer,
3631         .get_idt = vmx_get_idt,
3632         .set_idt = vmx_set_idt,
3633         .get_gdt = vmx_get_gdt,
3634         .set_gdt = vmx_set_gdt,
3635         .cache_reg = vmx_cache_reg,
3636         .get_rflags = vmx_get_rflags,
3637         .set_rflags = vmx_set_rflags,
3638
3639         .tlb_flush = vmx_flush_tlb,
3640
3641         .run = vmx_vcpu_run,
3642         .handle_exit = kvm_handle_exit,
3643         .skip_emulated_instruction = skip_emulated_instruction,
3644         .patch_hypercall = vmx_patch_hypercall,
3645         .get_irq = vmx_get_irq,
3646         .set_irq = vmx_inject_irq,
3647         .queue_exception = vmx_queue_exception,
3648         .exception_injected = vmx_exception_injected,
3649         .inject_pending_irq = vmx_intr_assist,
3650         .inject_pending_vectors = do_interrupt_requests,
3651
3652         .set_tss_addr = vmx_set_tss_addr,
3653         .get_tdp_level = get_ept_level,
3654         .get_mt_mask_shift = vmx_get_mt_mask_shift,
3655 };
3656
3657 static int __init vmx_init(void)
3658 {
3659         void *va;
3660         int r;
3661
3662         vmx_io_bitmap_a = alloc_page(GFP_KERNEL | __GFP_HIGHMEM);
3663         if (!vmx_io_bitmap_a)
3664                 return -ENOMEM;
3665
3666         vmx_io_bitmap_b = alloc_page(GFP_KERNEL | __GFP_HIGHMEM);
3667         if (!vmx_io_bitmap_b) {
3668                 r = -ENOMEM;
3669                 goto out;
3670         }
3671
3672         vmx_msr_bitmap = alloc_page(GFP_KERNEL | __GFP_HIGHMEM);
3673         if (!vmx_msr_bitmap) {
3674                 r = -ENOMEM;
3675                 goto out1;
3676         }
3677
3678         /*
3679          * Allow direct access to the PC debug port (it is often used for I/O
3680          * delays, but the vmexits simply slow things down).
3681          */
3682         va = kmap(vmx_io_bitmap_a);
3683         memset(va, 0xff, PAGE_SIZE);
3684         clear_bit(0x80, va);
3685         kunmap(vmx_io_bitmap_a);
3686
3687         va = kmap(vmx_io_bitmap_b);
3688         memset(va, 0xff, PAGE_SIZE);
3689         kunmap(vmx_io_bitmap_b);
3690
3691         va = kmap(vmx_msr_bitmap);
3692         memset(va, 0xff, PAGE_SIZE);
3693         kunmap(vmx_msr_bitmap);
3694
3695         set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
3696
3697         r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx), THIS_MODULE);
3698         if (r)
3699                 goto out2;
3700
3701         vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_FS_BASE);
3702         vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_GS_BASE);
3703         vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_IA32_SYSENTER_CS);
3704         vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_IA32_SYSENTER_ESP);
3705         vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_IA32_SYSENTER_EIP);
3706
3707         if (vm_need_ept()) {
3708                 bypass_guest_pf = 0;
3709                 kvm_mmu_set_base_ptes(VMX_EPT_READABLE_MASK |
3710                         VMX_EPT_WRITABLE_MASK |
3711                         VMX_EPT_IGMT_BIT);
3712                 kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull,
3713                                 VMX_EPT_EXECUTABLE_MASK,
3714                                 VMX_EPT_DEFAULT_MT << VMX_EPT_MT_EPTE_SHIFT);
3715                 kvm_enable_tdp();
3716         } else
3717                 kvm_disable_tdp();
3718
3719         if (bypass_guest_pf)
3720                 kvm_mmu_set_nonpresent_ptes(~0xffeull, 0ull);
3721
3722         ept_sync_global();
3723
3724         return 0;
3725
3726 out2:
3727         __free_page(vmx_msr_bitmap);
3728 out1:
3729         __free_page(vmx_io_bitmap_b);
3730 out:
3731         __free_page(vmx_io_bitmap_a);
3732         return r;
3733 }
3734
3735 static void __exit vmx_exit(void)
3736 {
3737         __free_page(vmx_msr_bitmap);
3738         __free_page(vmx_io_bitmap_b);
3739         __free_page(vmx_io_bitmap_a);
3740
3741         kvm_exit();
3742 }
3743
3744 module_init(vmx_init)
3745 module_exit(vmx_exit)