perf, x86: P4 PMU -- fix typo in unflagged NMI handling

Tested-by: Lin Ming <ming.m.lin@intel.com>
Signed-off-by: Cyrill Gorcunov <gorcunov@openvz.org>
Cc: Cyrill Gorcunov <gorcunov@gmail.com>
LKML-Reference: <1274174954.22793.17.camel@minggr.sh.intel.com>
Signed-off-by: Ingo Molnar <mingo@elte.hu>

diff --git a/arch/x86/kernel/cpu/perf_event_p4.c b/arch/x86/kernel/cpu/perf_event_p4.c
index 02f0728..87e1803 100644 (file)
--- a/arch/x86/kernel/cpu/perf_event_p4.c
+++ b/arch/x86/kernel/cpu/perf_event_p4.c
@@ -473,7 +473,7 @@ static inline int p4_pmu_clear_cccr_ovf(struct hw_perf_event *hwc)
        rdmsr(hwc->config_base + hwc->idx, low, high);
 
        /* we need to check high bit for unflagged overflows */
-       if ((low & P4_CCCR_OVF) || (high & (1 << 31))) {
+       if ((low & P4_CCCR_OVF) || !(high & (1 << 31))) {
                overflow = 1;
                (void)checking_wrmsrl(hwc->config_base + hwc->idx,
                        ((u64)low) & ~P4_CCCR_OVF);