[libata] sata_svw: update code comments relating to data corruption

Signed-off-by: Pavel Machek <pavel@suse.cz>
Signed-off-by: Jeff Garzik <jgarzik@redhat.com>

diff --git a/drivers/ata/sata_svw.c b/drivers/ata/sata_svw.c
index 16aa683..fb13b82 100644 (file)
--- a/drivers/ata/sata_svw.c
+++ b/drivers/ata/sata_svw.c
@@ -253,21 +253,29 @@ static void k2_bmdma_start_mmio(struct ata_queued_cmd *qc)
        /* start host DMA transaction */
        dmactl = readb(mmio + ATA_DMA_CMD);
        writeb(dmactl | ATA_DMA_START, mmio + ATA_DMA_CMD);
-       /* There is a race condition in certain SATA controllers that can
-          be seen when the r/w command is given to the controller before the
-          host DMA is started. On a Read command, the controller would initiate
-          the command to the drive even before it sees the DMA start. When there
-          are very fast drives connected to the controller, or when the data request
-          hits in the drive cache, there is the possibility that the drive returns a part
-          or all of the requested data to the controller before the DMA start is issued.
-          In this case, the controller would become confused as to what to do with the data.
-          In the worst case when all the data is returned back to the controller, the
-          controller could hang. In other cases it could return partial data returning
-          in data corruption. This problem has been seen in PPC systems and can also appear
-          on an system with very fast disks, where the SATA controller is sitting behind a
-          number of bridges, and hence there is significant latency between the r/w command
-          and the start command. */
-       /* issue r/w command if the access is to ATA*/
+       /* This works around possible data corruption.
+
+          On certain SATA controllers that can be seen when the r/w
+          command is given to the controller before the host DMA is
+          started.
+
+          On a Read command, the controller would initiate the
+          command to the drive even before it sees the DMA
+          start. When there are very fast drives connected to the
+          controller, or when the data request hits in the drive
+          cache, there is the possibility that the drive returns a
+          part or all of the requested data to the controller before
+          the DMA start is issued.  In this case, the controller
+          would become confused as to what to do with the data.  In
+          the worst case when all the data is returned back to the
+          controller, the controller could hang. In other cases it
+          could return partial data returning in data
+          corruption. This problem has been seen in PPC systems and
+          can also appear on an system with very fast disks, where
+          the SATA controller is sitting behind a number of bridges,
+          and hence there is significant latency between the r/w
+          command and the start command. */
+       /* issue r/w command if the access is to ATA */
        if (qc->tf.protocol == ATA_PROT_DMA)
                ap->ops->sff_exec_command(ap, &qc->tf);
 }