* 'upstream-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jgarzik/netdev-2.6: (48 commits)
LIB82596: correct data types for hardware addresses
via-velocity: don't oops on MTU change (resend)
Stop phy code from returning success to unknown ioctls.
SET_NETDEV_DEV() in fec_mpc52xx.c
net: smc911x: only enable for mpr2 on sh.
e1000: Fix NAPI state bug when Rx complete
sky2: turn of dynamic Tx watermark workaround (FE+ only)
sky2: don't use AER routines
sky2: revert to access PCI config via device space
cxgb - fix stats
cxgb - fix NAPI
cxgb - fix T2 GSO
ucc_geth: handle passing of RX-only and TX-only internal delay PHY connection type parameters
phylib: marvell: add support for TX-only and RX-only Internal Delay
phylib: add PHY interface modes for internal delay for tx and rx only
skge: MTU changing fix
skge: serial mode register values
skge version 1.13
skge: increase TX threshold for Jumbo
skge: fiber link up/down fix
...
KDUMP
P: Vivek Goyal
-M: vgoyal@in.ibm.com
+M: vgoyal@redhat.com
P: Haren Myneni
M: hbabu@us.ibm.com
L: kexec@lists.infradead.org
bool
default y
+config X86_32
+ bool
+ default y
+
+config RWSEM_XCHGADD_ALGORITHM
+ def_bool y
+
config 64BIT
bool
default n
int generic_console_write(int fd, const char *buf, int n)
{
+ sigset_t old, no_sigio;
struct termios save, new;
int err;
if (isatty(fd)) {
+ sigemptyset(&no_sigio);
+ sigaddset(&no_sigio, SIGIO);
+ if (sigprocmask(SIG_BLOCK, &no_sigio, &old))
+ goto error;
+
CATCH_EINTR(err = tcgetattr(fd, &save));
if (err)
goto error;
* Restore raw mode, in any case; we *must* ignore any error apart
* EINTR, except for debug.
*/
- if (isatty(fd))
+ if (isatty(fd)) {
CATCH_EINTR(tcsetattr(fd, TCSAFLUSH, &save));
+ sigprocmask(SIG_SETMASK, &old, NULL);
+ }
+
return err;
error:
return -errno;
#ifdef UML_CONFIG_NO_HZ
static int after_sleep_interval(struct timespec *ts)
{
+ return 0;
}
#else
static inline long long timespec_to_us(const struct timespec *ts)
},
},
{
+ .ident = "TECRA M3",
+ .matches = {
+ DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
+ DMI_MATCH(DMI_PRODUCT_NAME, "Tecra M3"),
+ },
+ },
+ {
.ident = "TECRA M5",
.matches = {
DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
},
},
{
+ .ident = "TECRA A8",
+ .matches = {
+ DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
+ DMI_MATCH(DMI_PRODUCT_NAME, "TECRA A8"),
+ },
+ },
+ {
+ .ident = "Satellite R25",
+ .matches = {
+ DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
+ DMI_MATCH(DMI_PRODUCT_NAME, "Satellite R25"),
+ },
+ },
+ {
.ident = "Satellite U200",
.matches = {
DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
},
},
{
+ .ident = "Satellite U200",
+ .matches = {
+ DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
+ DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE U200"),
+ },
+ },
+ {
.ident = "Satellite Pro U200",
.matches = {
DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
/* Devices which get the IVB wrong */
{ "QUANTUM FIREBALLlct10 05", "A03.0900", ATA_HORKAGE_IVB, },
{ "TSSTcorp CDDVDW SH-S202J", "SB00", ATA_HORKAGE_IVB, },
+ { "TSSTcorp CDDVDW SH-S202J", "SB01", ATA_HORKAGE_IVB, },
+ { "TSSTcorp CDDVDW SH-S202N", "SB00", ATA_HORKAGE_IVB, },
+ { "TSSTcorp CDDVDW SH-S202N", "SB01", ATA_HORKAGE_IVB, },
/* End Marker */
{ }
if (ap->ops->port_start) {
rc = ap->ops->port_start(ap);
if (rc) {
- ata_port_printk(ap, KERN_ERR, "failed to "
- "start port (errno=%d)\n", rc);
+ if (rc != -ENODEV)
+ dev_printk(KERN_ERR, host->dev, "failed to start port %d (errno=%d)\n", i, rc);
goto err_out;
}
}
-
ata_eh_freeze_port(ap);
}
ehc->i.serror & SERR_DEV_XCHG ? "DevExch " : "");
for (tag = 0; tag < ATA_MAX_QUEUE; tag++) {
- static const char *dma_str[] = {
- [DMA_BIDIRECTIONAL] = "bidi",
- [DMA_TO_DEVICE] = "out",
- [DMA_FROM_DEVICE] = "in",
- [DMA_NONE] = "",
- };
struct ata_queued_cmd *qc = __ata_qc_from_tag(ap, tag);
struct ata_taskfile *cmd = &qc->tf, *res = &qc->result_tf;
+ const u8 *cdb = qc->cdb;
+ char data_buf[20] = "";
+ char cdb_buf[70] = "";
if (!(qc->flags & ATA_QCFLAG_FAILED) ||
qc->dev->link != link || !qc->err_mask)
continue;
+ if (qc->dma_dir != DMA_NONE) {
+ static const char *dma_str[] = {
+ [DMA_BIDIRECTIONAL] = "bidi",
+ [DMA_TO_DEVICE] = "out",
+ [DMA_FROM_DEVICE] = "in",
+ };
+ static const char *prot_str[] = {
+ [ATA_PROT_PIO] = "pio",
+ [ATA_PROT_DMA] = "dma",
+ [ATA_PROT_NCQ] = "ncq",
+ [ATA_PROT_ATAPI] = "pio",
+ [ATA_PROT_ATAPI_DMA] = "dma",
+ };
+
+ snprintf(data_buf, sizeof(data_buf), " %s %u %s",
+ prot_str[qc->tf.protocol], qc->nbytes,
+ dma_str[qc->dma_dir]);
+ }
+
+ if (is_atapi_taskfile(&qc->tf))
+ snprintf(cdb_buf, sizeof(cdb_buf),
+ "cdb %02x %02x %02x %02x %02x %02x %02x %02x "
+ "%02x %02x %02x %02x %02x %02x %02x %02x\n ",
+ cdb[0], cdb[1], cdb[2], cdb[3],
+ cdb[4], cdb[5], cdb[6], cdb[7],
+ cdb[8], cdb[9], cdb[10], cdb[11],
+ cdb[12], cdb[13], cdb[14], cdb[15]);
+
ata_dev_printk(qc->dev, KERN_ERR,
"cmd %02x/%02x:%02x:%02x:%02x:%02x/%02x:%02x:%02x:%02x:%02x/%02x "
- "tag %d cdb 0x%x data %u %s\n "
+ "tag %d%s\n %s"
"res %02x/%02x:%02x:%02x:%02x:%02x/%02x:%02x:%02x:%02x:%02x/%02x "
"Emask 0x%x (%s)%s\n",
cmd->command, cmd->feature, cmd->nsect,
cmd->lbal, cmd->lbam, cmd->lbah,
cmd->hob_feature, cmd->hob_nsect,
cmd->hob_lbal, cmd->hob_lbam, cmd->hob_lbah,
- cmd->device, qc->tag, qc->cdb[0], qc->nbytes,
- dma_str[qc->dma_dir],
+ cmd->device, qc->tag, data_buf, cdb_buf,
res->command, res->feature, res->nsect,
res->lbal, res->lbam, res->lbah,
res->hob_feature, res->hob_nsect,
#include <asm/arch/smc.h>
#define DRV_NAME "pata_at32"
-#define DRV_VERSION "0.0.2"
+#define DRV_VERSION "0.0.3"
/*
* CompactFlash controller memory layout relative to the base address:
* Mode 2 | 8.3 | 240 ns | 0x07
* Mode 3 | 11.1 | 180 ns | 0x0f
* Mode 4 | 16.7 | 120 ns | 0x1f
+ *
+ * Alter PIO_MASK below according to table to set maximal PIO mode.
*/
#define PIO_MASK (0x1f)
*/
static int pata_at32_setup_timing(struct device *dev,
struct at32_ide_info *info,
- const struct ata_timing *timing)
+ const struct ata_timing *ata)
{
- /* These two values are found through testing */
- const int min_recover = 25;
- const int ncs_hold = 15;
-
struct smc_config *smc = &info->smc;
+ struct smc_timing timing;
int active;
int recover;
+ memset(&timing, 0, sizeof(struct smc_timing));
+
/* Total cycle time */
- smc->read_cycle = timing->cyc8b;
+ timing.read_cycle = ata->cyc8b;
/* DIOR <= CFIOR timings */
- smc->nrd_setup = timing->setup;
- smc->nrd_pulse = timing->act8b;
+ timing.nrd_setup = ata->setup;
+ timing.nrd_pulse = ata->act8b;
+ timing.nrd_recover = ata->rec8b;
+
+ /* Convert nanosecond timing to clock cycles */
+ smc_set_timing(smc, &timing);
- /* Compute recover, extend total cycle if needed */
- active = smc->nrd_setup + smc->nrd_pulse;
+ /* Add one extra cycle setup due to signal ring */
+ smc->nrd_setup = smc->nrd_setup + 1;
+
+ active = smc->nrd_setup + smc->nrd_pulse;
recover = smc->read_cycle - active;
- if (recover < min_recover) {
- smc->read_cycle = active + min_recover;
- recover = min_recover;
- }
+ /* Need at least two cycles recovery */
+ if (recover < 2)
+ smc->read_cycle = active + 2;
/* (CS0, CS1, DIR, OE) <= (CFCE1, CFCE2, CFRNW, NCSX) timings */
- smc->ncs_read_setup = 0;
- smc->ncs_read_pulse = active + ncs_hold;
+ smc->ncs_read_setup = 1;
+ smc->ncs_read_pulse = smc->read_cycle - 2;
/* Write timings same as read timings */
smc->write_cycle = smc->read_cycle;
smc->ncs_write_setup = smc->ncs_read_setup;
smc->ncs_write_pulse = smc->ncs_read_pulse;
- /* Do some debugging output */
- dev_dbg(dev, "SMC: C=%d S=%d P=%d R=%d NCSS=%d NCSP=%d NCSR=%d\n",
+ /* Do some debugging output of ATA and SMC timings */
+ dev_dbg(dev, "ATA: C=%d S=%d P=%d R=%d\n",
+ ata->cyc8b, ata->setup, ata->act8b, ata->rec8b);
+
+ dev_dbg(dev, "SMC: C=%d S=%d P=%d NS=%d NP=%d\n",
smc->read_cycle, smc->nrd_setup, smc->nrd_pulse,
- recover, smc->ncs_read_setup, smc->ncs_read_pulse,
- smc->read_cycle - smc->ncs_read_pulse);
+ smc->ncs_read_setup, smc->ncs_read_pulse);
/* Finally, configure the SMC */
return smc_set_configuration(info->cs, smc);
};
static struct ata_port_operations at32_port_ops = {
- .port_disable = ata_port_disable,
.set_piomode = pata_at32_set_piomode,
.tf_load = ata_tf_load,
.tf_read = ata_tf_read,
.irq_clear = pata_at32_irq_clear,
.irq_on = ata_irq_on,
- .irq_ack = ata_irq_ack,
.port_start = ata_sff_port_start,
};
/* Setup ATA bindings */
ap->ops = &at32_port_ops;
ap->pio_mask = PIO_MASK;
- ap->flags = ATA_FLAG_MMIO | ATA_FLAG_SLAVE_POSS
- | ATA_FLAG_PIO_POLLING;
+ ap->flags |= ATA_FLAG_MMIO | ATA_FLAG_SLAVE_POSS;
/*
* Since all 8-bit taskfile transfers has to go on the lower
info->smc.tdf_mode = 0; /* TDF optimization disabled */
info->smc.tdf_cycles = 0; /* No TDF wait cycles */
- /* Setup ATA timing */
+ /* Setup SMC to ATA timing */
ret = pata_at32_setup_timing(dev, info, &initial_timing);
if (ret)
goto err_setup_timing;
- /* Setup ATA addresses */
+ /* Map ATA address space */
ret = -ENOMEM;
info->ide_addr = devm_ioremap(dev, info->res_ide.start, 16);
info->alt_addr = devm_ioremap(dev, info->res_alt.start, 16);
pata_at32_debug_bus(dev, info);
#endif
- /* Register ATA device */
+ /* Setup and register ATA device */
ret = pata_at32_init_one(dev, info);
if (ret)
goto err_ata_device;
int board_idx = 0;
struct resource *res;
struct ata_host *host;
+ unsigned int fsclk = get_sclk();
+ int udma_mode = 5;
const struct ata_port_info *ppi[] =
{ &bfin_port_info[board_idx], NULL };
if (res == NULL)
return -EINVAL;
+ while (bfin_port_info[board_idx].udma_mask>0 && udma_fsclk[udma_mode] > fsclk) {
+ udma_mode--;
+ bfin_port_info[board_idx].udma_mask >>= 1;
+ }
+
/*
* Now that that's out of the way, wire up the port..
*/
MV_PCI_ERR_ATTRIBUTE = 0x1d48,
MV_PCI_ERR_COMMAND = 0x1d50,
- PCI_IRQ_CAUSE_OFS = 0x1d58,
- PCI_IRQ_MASK_OFS = 0x1d5c,
+ PCI_IRQ_CAUSE_OFS = 0x1d58,
+ PCI_IRQ_MASK_OFS = 0x1d5c,
PCI_UNMASK_ALL_IRQS = 0x7fffff, /* bits 22-0 */
+ PCIE_IRQ_CAUSE_OFS = 0x1900,
+ PCIE_IRQ_MASK_OFS = 0x1910,
+ PCIE_UNMASK_ALL_IRQS = 0x70a, /* assorted bits */
+
HC_MAIN_IRQ_CAUSE_OFS = 0x1d60,
HC_MAIN_IRQ_MASK_OFS = 0x1d64,
PORT0_ERR = (1 << 0), /* shift by port # */
MV_HP_GEN_I = (1 << 6), /* Generation I: 50xx */
MV_HP_GEN_II = (1 << 7), /* Generation II: 60xx */
MV_HP_GEN_IIE = (1 << 8), /* Generation IIE: 6042/7042 */
+ MV_HP_PCIE = (1 << 9), /* PCIe bus/regs: 7042 */
/* Port private flags (pp_flags) */
MV_PP_FLAG_EDMA_EN = (1 << 0), /* is EDMA engine enabled? */
u32 pre;
};
-struct mv_host_priv;
+struct mv_host_priv {
+ u32 hp_flags;
+ struct mv_port_signal signal[8];
+ const struct mv_hw_ops *ops;
+ u32 irq_cause_ofs;
+ u32 irq_mask_ofs;
+ u32 unmask_all_irqs;
+};
+
struct mv_hw_ops {
void (*phy_errata)(struct mv_host_priv *hpriv, void __iomem *mmio,
unsigned int port);
void (*reset_bus)(struct pci_dev *pdev, void __iomem *mmio);
};
-struct mv_host_priv {
- u32 hp_flags;
- struct mv_port_signal signal[8];
- const struct mv_hw_ops *ops;
-};
-
static void mv_irq_clear(struct ata_port *ap);
static int mv_scr_read(struct ata_port *ap, unsigned int sc_reg_in, u32 *val);
static int mv_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val);
/* Adaptec 1430SA */
{ PCI_VDEVICE(ADAPTEC2, 0x0243), chip_7042 },
- { PCI_VDEVICE(TTI, 0x2310), chip_7042 },
-
- /* add Marvell 7042 support */
+ /* Marvell 7042 support */
{ PCI_VDEVICE(MARVELL, 0x7042), chip_7042 },
+ /* Highpoint RocketRAID PCIe series */
+ { PCI_VDEVICE(TTI, 0x2300), chip_7042 },
+ { PCI_VDEVICE(TTI, 0x2310), chip_7042 },
+
{ } /* terminate list */
};
static void mv_pci_error(struct ata_host *host, void __iomem *mmio)
{
+ struct mv_host_priv *hpriv = host->private_data;
struct ata_port *ap;
struct ata_queued_cmd *qc;
struct ata_eh_info *ehi;
unsigned int i, err_mask, printed = 0;
u32 err_cause;
- err_cause = readl(mmio + PCI_IRQ_CAUSE_OFS);
+ err_cause = readl(mmio + hpriv->irq_cause_ofs);
dev_printk(KERN_ERR, host->dev, "PCI ERROR; PCI IRQ cause=0x%08x\n",
err_cause);
DPRINTK("All regs @ PCI error\n");
mv_dump_all_regs(mmio, -1, to_pci_dev(host->dev));
- writelfl(0, mmio + PCI_IRQ_CAUSE_OFS);
+ writelfl(0, mmio + hpriv->irq_cause_ofs);
for (i = 0; i < host->n_ports; i++) {
ap = host->ports[i];
#define ZERO(reg) writel(0, mmio + (reg))
static void mv_reset_pci_bus(struct pci_dev *pdev, void __iomem *mmio)
{
+ struct ata_host *host = dev_get_drvdata(&pdev->dev);
+ struct mv_host_priv *hpriv = host->private_data;
u32 tmp;
tmp = readl(mmio + MV_PCI_MODE);
writel(0x000100ff, mmio + MV_PCI_XBAR_TMOUT);
ZERO(HC_MAIN_IRQ_MASK_OFS);
ZERO(MV_PCI_SERR_MASK);
- ZERO(PCI_IRQ_CAUSE_OFS);
- ZERO(PCI_IRQ_MASK_OFS);
+ ZERO(hpriv->irq_cause_ofs);
+ ZERO(hpriv->irq_mask_ofs);
ZERO(MV_PCI_ERR_LOW_ADDRESS);
ZERO(MV_PCI_ERR_HIGH_ADDRESS);
ZERO(MV_PCI_ERR_ATTRIBUTE);
mv_scr_read(ap, SCR_ERROR, &serror);
mv_scr_read(ap, SCR_CONTROL, &scontrol);
DPRINTK("S-regs after ATA_RST: SStat 0x%08x SErr 0x%08x "
- "SCtrl 0x%08x\n", status, serror, scontrol);
+ "SCtrl 0x%08x\n", sstatus, serror, scontrol);
}
#endif
break;
case chip_7042:
+ hp_flags |= MV_HP_PCIE;
case chip_6042:
hpriv->ops = &mv6xxx_ops;
hp_flags |= MV_HP_GEN_IIE;
}
hpriv->hp_flags = hp_flags;
+ if (hp_flags & MV_HP_PCIE) {
+ hpriv->irq_cause_ofs = PCIE_IRQ_CAUSE_OFS;
+ hpriv->irq_mask_ofs = PCIE_IRQ_MASK_OFS;
+ hpriv->unmask_all_irqs = PCIE_UNMASK_ALL_IRQS;
+ } else {
+ hpriv->irq_cause_ofs = PCI_IRQ_CAUSE_OFS;
+ hpriv->irq_mask_ofs = PCI_IRQ_MASK_OFS;
+ hpriv->unmask_all_irqs = PCI_UNMASK_ALL_IRQS;
+ }
return 0;
}
}
/* Clear any currently outstanding host interrupt conditions */
- writelfl(0, mmio + PCI_IRQ_CAUSE_OFS);
+ writelfl(0, mmio + hpriv->irq_cause_ofs);
/* and unmask interrupt generation for host regs */
- writelfl(PCI_UNMASK_ALL_IRQS, mmio + PCI_IRQ_MASK_OFS);
+ writelfl(hpriv->unmask_all_irqs, mmio + hpriv->irq_mask_ofs);
if (IS_GEN_I(hpriv))
writelfl(~HC_MAIN_MASKED_IRQS_5, mmio + HC_MAIN_IRQ_MASK_OFS);
"PCI int cause/mask=0x%08x/0x%08x\n",
readl(mmio + HC_MAIN_IRQ_CAUSE_OFS),
readl(mmio + HC_MAIN_IRQ_MASK_OFS),
- readl(mmio + PCI_IRQ_CAUSE_OFS),
- readl(mmio + PCI_IRQ_MASK_OFS));
+ readl(mmio + hpriv->irq_cause_ofs),
+ readl(mmio + hpriv->irq_mask_ofs));
done:
return rc;
config CRYPTO_DEV_PADLOCK
tristate "Support for VIA PadLock ACE"
- depends on X86_32
+ depends on X86_32 && !UML
select CRYPTO_ALGAPI
help
Some VIA processors come with an integrated crypto engine
if (copy_from_user(&iocts, argp,
sizeof(isdn_ioctl_struct)))
return -EFAULT;
+ iocts.drvid[sizeof(iocts.drvid)-1] = 0;
if (strlen(iocts.drvid)) {
if ((p = strchr(iocts.drvid, ',')))
*p = 0;
if (copy_from_user(&iocts, argp,
sizeof(isdn_ioctl_struct)))
return -EFAULT;
+ iocts.drvid[sizeof(iocts.drvid)-1] = 0;
if (strlen(iocts.drvid)) {
drvidx = -1;
for (i = 0; i < ISDN_MAX_DRIVERS; i++)
} else {
p = (char __user *) iocts.arg;
for (i = 0; i < 10; i++) {
- sprintf(bname, "%s%s",
+ snprintf(bname, sizeof(bname), "%s%s",
strlen(dev->drv[drvidx]->msn2eaz[i]) ?
dev->drv[drvidx]->msn2eaz[i] : "_",
(i < 9) ? "," : "\0");
char *p;
if (copy_from_user(&iocts, argp, sizeof(isdn_ioctl_struct)))
return -EFAULT;
+ iocts.drvid[sizeof(iocts.drvid)-1] = 0;
if (strlen(iocts.drvid)) {
if ((p = strchr(iocts.drvid, ',')))
*p = 0;
config OPROFILE
tristate "OProfile system profiling (EXPERIMENTAL)"
depends on PROFILING
- depends on ALPHA || ARM || BLACKFIN || X86_32 || IA64 || M32R || MIPS || PARISC || PPC || S390 || SUPERH || SPARC || X86_64
+ depends on (ALPHA || ARM || BLACKFIN || X86_32 || IA64 || M32R || MIPS || PARISC || PPC || S390 || SUPERH || SPARC || X86_64) && !UML
help
OProfile is a profiling system capable of profiling the
whole system, include the kernel, kernel modules, libraries,
config KPROBES
bool "Kprobes"
depends on KALLSYMS && MODULES
- depends on X86_32 || IA64 || PPC || S390 || SPARC64 || X86_64 || AVR32
+ depends on (X86_32 || IA64 || PPC || S390 || SPARC64 || X86_64 || AVR32) && !UML
help
Kprobes allows you to trap at almost any kernel address and
execute a callback function. register_kprobe() establishes
git://ftp.safe.ca / safe / jmp / linux-2.6 / commitdiff