sh: sh7724: INTC setting update

This patch follows Rev 0.50 manual

Signed-off-by: Kuninori Morimoto <morimoto.kuninori@renesas.com>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>

diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7724.c b/arch/sh/kernel/cpu/sh4a/setup-sh7724.c
index 000f3b8..585dd85 100644 (file)
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7724.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7724.c
@@ -511,46 +511,46 @@ enum {
        IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
        HUDI,
        DMAC1A_DEI0, DMAC1A_DEI1, DMAC1A_DEI2, DMAC1A_DEI3,
-       _2DG_TRI, _2DG_INI, _2DG_CEI, _2DG_BRK,
+       _2DG_TRI, _2DG_INI, _2DG_CEI,
        DMAC0A_DEI0, DMAC0A_DEI1, DMAC0A_DEI2, DMAC0A_DEI3,
-       VIO_CEU20I, VIO_BEU20I, VIO_VEU3F1, VIO_VOUI,
-       SCIFA_SCIFA0,
-       VPU_VPUI,
-       TPU_TPUI,
-       CEU21I,
-       BEU21I,
-       USB_USI0,
+       VIO_CEU0, VIO_BEU0, VIO_VEU1, VIO_VOU,
+       SCIFA3,
+       VPU,
+       TPU,
+       CEU1,
+       BEU1,
+       USB0, USB1,
        ATAPI,
        RTC_ATI, RTC_PRI, RTC_CUI,
        DMAC1B_DEI4, DMAC1B_DEI5, DMAC1B_DADERR,
        DMAC0B_DEI4, DMAC0B_DEI5, DMAC0B_DADERR,
-       KEYSC_KEYI,
+       KEYSC,
        SCIF_SCIF0, SCIF_SCIF1, SCIF_SCIF2,
-       VEU3F0I,
+       VEU0,
        MSIOF_MSIOFI0, MSIOF_MSIOFI1,
        SPU_SPUI0, SPU_SPUI1,
-       SCIFA_SCIFA1,
-/*     ICB_ICBI, */
+       SCIFA4,
+       ICB,
        ETHI,
        I2C1_ALI, I2C1_TACKI, I2C1_WAITI, I2C1_DTEI,
        I2C0_ALI, I2C0_TACKI, I2C0_WAITI, I2C0_DTEI,
-       SDHI0_SDHII0, SDHI0_SDHII1, SDHI0_SDHII2,
-       CMT_CMTI,
-       TSIF_TSIFI,
-/*     ICB_LMBI, */
-       FSI_FSI,
-       SCIFA_SCIFA2,
+       SDHI0_SDHII0, SDHI0_SDHII1, SDHI0_SDHII2, SDHI0_SDHII3,
+       CMT,
+       TSIF,
+       FSI,
+       SCIFA5,
        TMU0_TUNI0, TMU0_TUNI1, TMU0_TUNI2,
-       IRDA_IRDAI,
+       IRDA,
        SDHI1_SDHII0, SDHI1_SDHII1, SDHI1_SDHII2,
-       JPU_JPUI,
-       MMC_MMCI0, MMC_MMCI1, MMC_MMCI2,
-       LCDC_LCDCI,
+       JPU,
+       _2DDMAC,
+       MMC_MMC2I, MMC_MMC3I,
+       LCDC,
        TMU1_TUNI0, TMU1_TUNI1, TMU1_TUNI2,
 
        /* interrupt groups */
-       DMAC1A, _2DG, DMAC0A, VIO, RTC,
-       DMAC1B, DMAC0B, I2C0, I2C1, SDHI0, SDHI1, SPU, MMC,
+       DMAC1A, _2DG, DMAC0A, VIO, USB, RTC,
+       DMAC1B, DMAC0B, I2C0, I2C1, SDHI0, SDHI1, SPU, MMCIF,
 };
 
 static struct intc_vect vectors[] __initdata = {
@@ -567,25 +567,25 @@ static struct intc_vect vectors[] __initdata = {
        INTC_VECT(_2DG_TRI, 0x780),
        INTC_VECT(_2DG_INI, 0x7A0),
        INTC_VECT(_2DG_CEI, 0x7C0),
-       INTC_VECT(_2DG_BRK, 0x7E0),
 
        INTC_VECT(DMAC0A_DEI0, 0x800),
        INTC_VECT(DMAC0A_DEI1, 0x820),
        INTC_VECT(DMAC0A_DEI2, 0x840),
        INTC_VECT(DMAC0A_DEI3, 0x860),
 
-       INTC_VECT(VIO_CEU20I, 0x880),
-       INTC_VECT(VIO_BEU20I, 0x8A0),
-       INTC_VECT(VIO_VEU3F1, 0x8C0),
-       INTC_VECT(VIO_VOUI, 0x8E0),
+       INTC_VECT(VIO_CEU0, 0x880),
+       INTC_VECT(VIO_BEU0, 0x8A0),
+       INTC_VECT(VIO_VEU1, 0x8C0),
+       INTC_VECT(VIO_VOU,  0x8E0),
 
-       INTC_VECT(SCIFA_SCIFA0, 0x900),
-       INTC_VECT(VPU_VPUI, 0x980),
-       INTC_VECT(TPU_TPUI, 0x9A0),
-       INTC_VECT(CEU21I, 0x9E0),
-       INTC_VECT(BEU21I, 0xA00),
-       INTC_VECT(USB_USI0, 0xA20),
-       INTC_VECT(ATAPI, 0xA60),
+       INTC_VECT(SCIFA3, 0x900),
+       INTC_VECT(VPU,    0x980),
+       INTC_VECT(TPU,    0x9A0),
+       INTC_VECT(CEU1,   0x9E0),
+       INTC_VECT(BEU1,   0xA00),
+       INTC_VECT(USB0,   0xA20),
+       INTC_VECT(USB1,   0xA40),
+       INTC_VECT(ATAPI,  0xA60),
 
        INTC_VECT(RTC_ATI, 0xA80),
        INTC_VECT(RTC_PRI, 0xAA0),
@@ -599,18 +599,18 @@ static struct intc_vect vectors[] __initdata = {
        INTC_VECT(DMAC0B_DEI5, 0xBA0),
        INTC_VECT(DMAC0B_DADERR, 0xBC0),
 
-       INTC_VECT(KEYSC_KEYI, 0xBE0),
+       INTC_VECT(KEYSC,      0xBE0),
        INTC_VECT(SCIF_SCIF0, 0xC00),
        INTC_VECT(SCIF_SCIF1, 0xC20),
        INTC_VECT(SCIF_SCIF2, 0xC40),
-       INTC_VECT(VEU3F0I, 0xC60),
+       INTC_VECT(VEU0,       0xC60),
        INTC_VECT(MSIOF_MSIOFI0, 0xC80),
        INTC_VECT(MSIOF_MSIOFI1, 0xCA0),
        INTC_VECT(SPU_SPUI0, 0xCC0),
        INTC_VECT(SPU_SPUI1, 0xCE0),
-       INTC_VECT(SCIFA_SCIFA1, 0xD00),
+       INTC_VECT(SCIFA4,    0xD00),
 
-/*     INTC_VECT(ICB_ICBI, 0xD20), */
+       INTC_VECT(ICB,  0xD20),
        INTC_VECT(ETHI, 0xD60),
 
        INTC_VECT(I2C1_ALI, 0xD80),
@@ -626,30 +626,30 @@ static struct intc_vect vectors[] __initdata = {
        INTC_VECT(SDHI0_SDHII0, 0xE80),
        INTC_VECT(SDHI0_SDHII1, 0xEA0),
        INTC_VECT(SDHI0_SDHII2, 0xEC0),
+       INTC_VECT(SDHI0_SDHII3, 0xEE0),
 
-       INTC_VECT(CMT_CMTI, 0xF00),
-       INTC_VECT(TSIF_TSIFI, 0xF20),
-/*     INTC_VECT(ICB_LMBI, 0xF60), */
-       INTC_VECT(FSI_FSI, 0xF80),
-       INTC_VECT(SCIFA_SCIFA2, 0xFA0),
+       INTC_VECT(CMT,    0xF00),
+       INTC_VECT(TSIF,   0xF20),
+       INTC_VECT(FSI,    0xF80),
+       INTC_VECT(SCIFA5, 0xFA0),
 
        INTC_VECT(TMU0_TUNI0, 0x400),
        INTC_VECT(TMU0_TUNI1, 0x420),
        INTC_VECT(TMU0_TUNI2, 0x440),
 
-       INTC_VECT(IRDA_IRDAI, 0x480),
+       INTC_VECT(IRDA,    0x480),
 
        INTC_VECT(SDHI1_SDHII0, 0x4E0),
        INTC_VECT(SDHI1_SDHII1, 0x500),
        INTC_VECT(SDHI1_SDHII2, 0x520),
 
-       INTC_VECT(JPU_JPUI, 0x560),
+       INTC_VECT(JPU, 0x560),
+       INTC_VECT(_2DDMAC, 0x4A0),
 
-       INTC_VECT(MMC_MMCI0, 0x580),
-       INTC_VECT(MMC_MMCI1, 0x5A0),
-       INTC_VECT(MMC_MMCI2, 0x5C0),
+       INTC_VECT(MMC_MMC2I, 0x5A0),
+       INTC_VECT(MMC_MMC3I, 0x5C0),
 
-       INTC_VECT(LCDC_LCDCI, 0xF40),
+       INTC_VECT(LCDC, 0xF40),
 
        INTC_VECT(TMU1_TUNI0, 0x920),
        INTC_VECT(TMU1_TUNI1, 0x940),
@@ -658,86 +658,79 @@ static struct intc_vect vectors[] __initdata = {
 
 static struct intc_group groups[] __initdata = {
        INTC_GROUP(DMAC1A, DMAC1A_DEI0, DMAC1A_DEI1, DMAC1A_DEI2, DMAC1A_DEI3),
-       INTC_GROUP(_2DG, _2DG_TRI, _2DG_INI, _2DG_CEI, _2DG_BRK),
+       INTC_GROUP(_2DG, _2DG_TRI, _2DG_INI, _2DG_CEI),
        INTC_GROUP(DMAC0A, DMAC0A_DEI0, DMAC0A_DEI1, DMAC0A_DEI2, DMAC0A_DEI3),
-       INTC_GROUP(VIO, VIO_CEU20I, VIO_BEU20I, VIO_VEU3F1, VIO_VOUI),
+       INTC_GROUP(VIO, VIO_CEU0, VIO_BEU0, VIO_VEU1, VIO_VOU),
+       INTC_GROUP(USB, USB0, USB1),
        INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI),
        INTC_GROUP(DMAC1B, DMAC1B_DEI4, DMAC1B_DEI5, DMAC1B_DADERR),
        INTC_GROUP(DMAC0B, DMAC0B_DEI4, DMAC0B_DEI5, DMAC0B_DADERR),
        INTC_GROUP(I2C0, I2C0_ALI, I2C0_TACKI, I2C0_WAITI, I2C0_DTEI),
        INTC_GROUP(I2C1, I2C1_ALI, I2C1_TACKI, I2C1_WAITI, I2C1_DTEI),
-       INTC_GROUP(SDHI0, SDHI0_SDHII0, SDHI0_SDHII1, SDHI0_SDHII2),
+       INTC_GROUP(SDHI0, SDHI0_SDHII0, SDHI0_SDHII1, SDHI0_SDHII2, SDHI0_SDHII3),
        INTC_GROUP(SDHI1, SDHI1_SDHII0, SDHI1_SDHII1, SDHI1_SDHII2),
        INTC_GROUP(SPU, SPU_SPUI0, SPU_SPUI1),
-       INTC_GROUP(MMC, MMC_MMCI0, MMC_MMCI1, MMC_MMCI2),
+       INTC_GROUP(MMCIF, MMC_MMC2I, MMC_MMC3I),
 };
 
-/* FIXMEEEEEEEEEEEEEEEEEEE !!!!! */
-/* very bad manual !! */
 static struct intc_mask_reg mask_registers[] __initdata = {
        { 0xa4080080, 0xa40800c0, 8, /* IMR0 / IMCR0 */
          { 0, TMU1_TUNI2, TMU1_TUNI1, TMU1_TUNI0,
-           /*SDHII3?*/0, SDHI1_SDHII2, SDHI1_SDHII1, SDHI1_SDHII0 } },
+           0, SDHI1_SDHII2, SDHI1_SDHII1, SDHI1_SDHII0 } },
        { 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */
-         { VIO_VOUI, VIO_VEU3F1, VIO_BEU20I, VIO_CEU20I,
+         { VIO_VOU, VIO_VEU1, VIO_BEU0, VIO_CEU0,
            DMAC0A_DEI3, DMAC0A_DEI2, DMAC0A_DEI1, DMAC0A_DEI0 } },
        { 0xa4080088, 0xa40800c8, 8, /* IMR2 / IMCR2 */
-         { 0, 0, 0, VPU_VPUI, ATAPI, ETHI, 0, /*SCIFA3*/SCIFA_SCIFA0 } },
+         { 0, 0, 0, VPU, ATAPI, ETHI, 0, SCIFA3 } },
        { 0xa408008c, 0xa40800cc, 8, /* IMR3 / IMCR3 */
          { DMAC1A_DEI3, DMAC1A_DEI2, DMAC1A_DEI1, DMAC1A_DEI0,
-           SPU_SPUI1, SPU_SPUI0, BEU21I, IRDA_IRDAI } },
+           SPU_SPUI1, SPU_SPUI0, BEU1, IRDA } },
        { 0xa4080090, 0xa40800d0, 8, /* IMR4 / IMCR4 */
          { 0, TMU0_TUNI2, TMU0_TUNI1, TMU0_TUNI0,
-           JPU_JPUI, 0, 0, LCDC_LCDCI } },
+           JPU, 0, 0, LCDC } },
        { 0xa4080094, 0xa40800d4, 8, /* IMR5 / IMCR5 */
-         { KEYSC_KEYI, DMAC0B_DADERR, DMAC0B_DEI5, DMAC0B_DEI4,
-           VEU3F0I, SCIF_SCIF2, SCIF_SCIF1, SCIF_SCIF0 } },
+         { KEYSC, DMAC0B_DADERR, DMAC0B_DEI5, DMAC0B_DEI4,
+           VEU0, SCIF_SCIF2, SCIF_SCIF1, SCIF_SCIF0 } },
        { 0xa4080098, 0xa40800d8, 8, /* IMR6 / IMCR6 */
-         { 0, 0, /*ICB_ICBI*/0, /*SCIFA4*/SCIFA_SCIFA1,
-           CEU21I, 0, MSIOF_MSIOFI1, MSIOF_MSIOFI0 } },
+         { 0, 0, ICB, SCIFA4,
+           CEU1, 0, MSIOF_MSIOFI1, MSIOF_MSIOFI0 } },
        { 0xa408009c, 0xa40800dc, 8, /* IMR7 / IMCR7 */
          { I2C0_DTEI, I2C0_WAITI, I2C0_TACKI, I2C0_ALI,
            I2C1_DTEI, I2C1_WAITI, I2C1_TACKI, I2C1_ALI } },
        { 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */
-         { /*SDHII3*/0, SDHI0_SDHII2, SDHI0_SDHII1, SDHI0_SDHII0,
-           0, 0, /*SCIFA5*/SCIFA_SCIFA2, FSI_FSI } },
+         { SDHI0_SDHII3, SDHI0_SDHII2, SDHI0_SDHII1, SDHI0_SDHII0,
+           0, 0, SCIFA5, FSI } },
        { 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */
-         { 0, 0, 0, CMT_CMTI, 0, /*USB1*/0, USB_USI0, 0 } },
+         { 0, 0, 0, CMT, 0, USB1, USB0, 0 } },
        { 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */
          { 0, DMAC1B_DADERR, DMAC1B_DEI5, DMAC1B_DEI4,
-           0, RTC_ATI, RTC_PRI, RTC_CUI } },
+           0, RTC_CUI, RTC_PRI, RTC_ATI } },
        { 0xa40800ac, 0xa40800ec, 8, /* IMR11 / IMCR11 */
-         { _2DG_BRK, _2DG_CEI, _2DG_INI, _2DG_TRI,
-           0, TPU_TPUI, /*ICB_LMBI*/0, TSIF_TSIFI } },
+         { 0, _2DG_CEI, _2DG_INI, _2DG_TRI,
+           0, TPU, 0, TSIF } },
        { 0xa40800b0, 0xa40800f0, 8, /* IMR12 / IMCR12 */
-         { 0, 0, 0, 0, 0, 0, 0, 0/*2DDMAC*/ } },
+         { 0, 0, MMC_MMC3I, MMC_MMC2I, 0, 0, 0, _2DDMAC } },
        { 0xa4140044, 0xa4140064, 8, /* INTMSK00 / INTMSKCLR00 */
          { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
 };
 
 static struct intc_prio_reg prio_registers[] __initdata = {
        { 0xa4080000, 0, 16, 4, /* IPRA */ { TMU0_TUNI0, TMU0_TUNI1,
-                                            TMU0_TUNI2, IRDA_IRDAI } },
-       { 0xa4080004, 0, 16, 4, /* IPRB */ { JPU_JPUI, LCDC_LCDCI,
-                                            DMAC1A, BEU21I } },
+                                            TMU0_TUNI2, IRDA } },
+       { 0xa4080004, 0, 16, 4, /* IPRB */ { JPU, LCDC, DMAC1A, BEU1 } },
        { 0xa4080008, 0, 16, 4, /* IPRC */ { TMU1_TUNI0, TMU1_TUNI1,
                                             TMU1_TUNI2, SPU } },
-       { 0xa408000c, 0, 16, 4, /* IPRD */ { 0, MMC, 0, ATAPI } },
-       { 0xa4080010, 0, 16, 4, /* IPRE */
-         { DMAC0A, /*BEU?VEU?*/VIO, /*SCIFA3*/SCIFA_SCIFA0, /*VPU5F*/
-           VPU_VPUI } },
-       { 0xa4080014, 0, 16, 4, /* IPRF */ { KEYSC_KEYI, DMAC0B,
-                                            USB_USI0, CMT_CMTI } },
+       { 0xa408000c, 0, 16, 4, /* IPRD */ { 0, MMCIF, 0, ATAPI } },
+       { 0xa4080010, 0, 16, 4, /* IPRE */ { DMAC0A, VIO, SCIFA3, VPU } },
+       { 0xa4080014, 0, 16, 4, /* IPRF */ { KEYSC, DMAC0B, USB, CMT } },
        { 0xa4080018, 0, 16, 4, /* IPRG */ { SCIF_SCIF0, SCIF_SCIF1,
-                                            SCIF_SCIF2, VEU3F0I } },
+                                            SCIF_SCIF2, VEU0 } },
        { 0xa408001c, 0, 16, 4, /* IPRH */ { MSIOF_MSIOFI0, MSIOF_MSIOFI1,
                                             I2C1, I2C0 } },
-       { 0xa4080020, 0, 16, 4, /* IPRI */ { /*SCIFA4*/SCIFA_SCIFA1, /*ICB*/0,
-                                            TSIF_TSIFI, _2DG/*ICB?*/ } },
-       { 0xa4080024, 0, 16, 4, /* IPRJ */ { CEU21I, ETHI, FSI_FSI, SDHI1 } },
-       { 0xa4080028, 0, 16, 4, /* IPRK */ { RTC, DMAC1B, /*ICB?*/0, SDHI0 } },
-       { 0xa408002c, 0, 16, 4, /* IPRL */ { /*SCIFA5*/SCIFA_SCIFA2, 0,
-                                            TPU_TPUI, /*2DDMAC*/0 } },
+       { 0xa4080020, 0, 16, 4, /* IPRI */ { SCIFA4, ICB, TSIF, _2DG } },
+       { 0xa4080024, 0, 16, 4, /* IPRJ */ { CEU1, ETHI, FSI, SDHI1 } },
+       { 0xa4080028, 0, 16, 4, /* IPRK */ { RTC, DMAC1B, 0, SDHI0 } },
+       { 0xa408002c, 0, 16, 4, /* IPRL */ { SCIFA5, 0, TPU, _2DDMAC } },
        { 0xa4140010, 0, 32, 4, /* INTPRI00 */
          { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
 };