cpumask: use modern cpumask style in drivers/edac/amd64_edac.c

cpumask_t -> struct cpumask, and don't put one on the stack.  (Note: this
is actually on the stack unless CONFIG_CPUMASK_OFFSTACK=y).

Signed-off-by: Rusty Russell <rusty@rustcorp.com.au>
Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>

diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c
index 3408b94..67541e7 100644 (file)
--- a/drivers/edac/amd64_edac.c
+++ b/drivers/edac/amd64_edac.c
@@ -2631,7 +2631,7 @@ static int amd64_init_csrows(struct mem_ctl_info *mci)
 static void amd64_enable_ecc_error_reporting(struct mem_ctl_info *mci)
 {
        struct amd64_pvt *pvt = mci->pvt_info;
-       const cpumask_t *cpumask = cpumask_of_node(pvt->mc_node_id);
+       const struct cpumask *cpumask = cpumask_of_node(pvt->mc_node_id);
        int cpu, idx = 0, err = 0;
        struct msr msrs[cpumask_weight(cpumask)];
        u32 value;
@@ -2707,7 +2707,7 @@ static void amd64_enable_ecc_error_reporting(struct mem_ctl_info *mci)
 
 static void amd64_restore_ecc_error_reporting(struct amd64_pvt *pvt)
 {
-       const cpumask_t *cpumask = cpumask_of_node(pvt->mc_node_id);
+       const struct cpumask *cpumask = cpumask_of_node(pvt->mc_node_id);
        int cpu, idx = 0, err = 0;
        struct msr msrs[cpumask_weight(cpumask)];
        u32 value;
@@ -2740,7 +2740,7 @@ static void amd64_restore_ecc_error_reporting(struct amd64_pvt *pvt)
 }
 
 /* get all cores on this DCT */
-static void get_cpus_on_this_dct_cpumask(cpumask_t *mask, int nid)
+static void get_cpus_on_this_dct_cpumask(struct cpumask *mask, int nid)
 {
        int cpu;
 
@@ -2752,25 +2752,30 @@ static void get_cpus_on_this_dct_cpumask(cpumask_t *mask, int nid)
 /* check MCG_CTL on all the cpus on this node */
 static bool amd64_nb_mce_bank_enabled_on_node(int nid)
 {
-       cpumask_t mask;
+       cpumask_var_t mask;
        struct msr *msrs;
        int cpu, nbe, idx = 0;
        bool ret = false;
 
-       cpumask_clear(&mask);
+       if (!zalloc_cpumask_var(&mask, GFP_KERNEL)) {
+               amd64_printk(KERN_WARNING, "%s: error allocating mask\n",
+                            __func__);
+               return false;
+       }
 
-       get_cpus_on_this_dct_cpumask(&mask, nid);
+       get_cpus_on_this_dct_cpumask(mask, nid);
 
-       msrs = kzalloc(sizeof(struct msr) * cpumask_weight(&mask), GFP_KERNEL);
+       msrs = kzalloc(sizeof(struct msr) * cpumask_weight(mask), GFP_KERNEL);
        if (!msrs) {
                amd64_printk(KERN_WARNING, "%s: error allocating msrs\n",
                              __func__);
+               free_cpumask_var(mask);
                 return false;
        }
 
-       rdmsr_on_cpus(&mask, MSR_IA32_MCG_CTL, msrs);
+       rdmsr_on_cpus(mask, MSR_IA32_MCG_CTL, msrs);
 
-       for_each_cpu(cpu, &mask) {
+       for_each_cpu(cpu, mask) {
                nbe = msrs[idx].l & K8_MSR_MCGCTL_NBE;
 
                debugf0("core: %u, MCG_CTL: 0x%llx, NB MSR is %s\n",
@@ -2786,6 +2791,7 @@ static bool amd64_nb_mce_bank_enabled_on_node(int nid)
 
 out:
        kfree(msrs);
+       free_cpumask_var(mask);
        return ret;
 }