powerpc/8xx: Always pin kernel instruction TLB

Various kernel asm modifies SRR0/SRR1 just before executing
a rfi. If such code crosses a page boundary you risk a TLB miss
which will clobber SRR0/SRR1. Avoid this by always pinning
kernel instruction TLB space.

Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>

diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S
index 678f98c..a2ed342 100644 (file)
--- a/arch/powerpc/kernel/head_8xx.S
+++ b/arch/powerpc/kernel/head_8xx.S
@@ -768,12 +768,12 @@ start_here:
  */
 initial_mmu:
        tlbia                   /* Invalidate all TLB entries */
-#ifdef CONFIG_PIN_TLB
+/* Always pin the first 8 MB ITLB to prevent ITLB
+   misses while mucking around with SRR0/SRR1 in asm
+*/
        lis     r8, MI_RSV4I@h
        ori     r8, r8, 0x1c00
-#else
-       li      r8, 0
-#endif
+
        mtspr   SPRN_MI_CTR, r8 /* Set instruction MMU control */
 
 #ifdef CONFIG_PIN_TLB