x86, perf: Fix comments in Pentium-4 PMU definitions

Reported-by: Cyrill Gorcunov <gorcunov@openvz.org>
Signed-off-by: Lin Ming <ming.m.lin@intel.com>
Cc: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: Mike Galbraith <efault@gmx.de>
Cc: Paul Mackerras <paulus@samba.org>
Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
Cc: Frederic Weisbecker <fweisbec@gmail.com>
LKML-Reference: <1268705556.3379.8.camel@minggr.sh.intel.com>
Signed-off-by: Ingo Molnar <mingo@elte.hu>

diff --git a/arch/x86/include/asm/perf_event_p4.h b/arch/x86/include/asm/perf_event_p4.h
index b47b9e9..b842b32 100644 (file)
--- a/arch/x86/include/asm/perf_event_p4.h
+++ b/arch/x86/include/asm/perf_event_p4.h
@@ -319,6 +319,7 @@ static inline u32 p4_default_escr_conf(int cpu, int exclude_os, int exclude_usr)
 
 #define P4_BSQ_ACTIVE_ENTRIES          P4_EVENT_PACK(0x06, 0x07)
        /*
+        * NOTE: no ESCR name in docs, it's guessed
         * MSR_P4_BSU_ESCR1:    2, 3
         */
 
@@ -468,8 +469,8 @@ static inline u32 p4_default_escr_conf(int cpu, int exclude_os, int exclude_usr)
 
 #define P4_UOPS_RETIRED                        P4_EVENT_PACK(0x01, 0x04)
        /*
-        * MSR_P4_CRU_ESCR2:    12, 13, 16
-        * MSR_P4_CRU_ESCR3:    14, 15, 17
+        * MSR_P4_CRU_ESCR0:    12, 13, 16
+        * MSR_P4_CRU_ESCR1:    14, 15, 17
         */
 
 #define P4_UOP_TYPE                    P4_EVENT_PACK(0x02, 0x02)