drm/i915: Set up the documented clock gating on Sandybridge and Ironlake.

Signed-off-by: Eric Anholt <eric@anholt.net>

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 2720bc2..cbbf59f 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2176,6 +2176,14 @@
 #define DISPLAY_PORT_PLL_BIOS_1         0x46010
 #define DISPLAY_PORT_PLL_BIOS_2         0x46014
 
+#define PCH_DSPCLK_GATE_D      0x42020
+# define DPFDUNIT_CLOCK_GATE_DISABLE           (1 << 7)
+# define DPARBUNIT_CLOCK_GATE_DISABLE          (1 << 5)
+
+#define PCH_3DCGDIS0           0x46020
+# define MARIUNIT_CLOCK_GATE_DISABLE           (1 << 18)
+# define SVSMUNIT_CLOCK_GATE_DISABLE           (1 << 1)
+
 #define FDI_PLL_FREQ_CTL        0x46030
 #define  FDI_PLL_FREQ_CHANGE_REQUEST    (1<<24)
 #define  FDI_PLL_FREQ_LOCK_LIMIT_MASK   0xfff00

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 0e2c5da..58fc7fa 100644 (file)
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4717,6 +4717,20 @@ void intel_init_clock_gating(struct drm_device *dev)
         * specs, but enable as much else as we can.
         */
        if (HAS_PCH_SPLIT(dev)) {
+               uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
+
+               if (IS_IRONLAKE(dev)) {
+                       /* Required for FBC */
+                       dspclk_gate |= DPFDUNIT_CLOCK_GATE_DISABLE;
+                       /* Required for CxSR */
+                       dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
+
+                       I915_WRITE(PCH_3DCGDIS0,
+                                  MARIUNIT_CLOCK_GATE_DISABLE |
+                                  SVSMUNIT_CLOCK_GATE_DISABLE);
+               }
+
+               I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
                return;
        } else if (IS_G4X(dev)) {
                uint32_t dspclk_gate;