cxgb3: fix Gen2 pci default settings

Modify control register settings to accommodate the bridge's max read
requset size.

Signed-off-by: Divy Le Ray <divy@chelsio.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

diff --git a/drivers/net/cxgb3/t3_hw.c b/drivers/net/cxgb3/t3_hw.c
index e78d341..526e144 100644 (file)
--- a/drivers/net/cxgb3/t3_hw.c
+++ b/drivers/net/cxgb3/t3_hw.c
@@ -3465,7 +3465,7 @@ static void config_pcie(struct adapter *adap)
                {201, 321, 258, 450, 834, 1602}
        };
 
-       u16 val;
+       u16 val, devid;
        unsigned int log2_width, pldsize;
        unsigned int fst_trn_rx, fst_trn_tx, acklat, rpllmt;
 
@@ -3473,6 +3473,17 @@ static void config_pcie(struct adapter *adap)
                             adap->params.pci.pcie_cap_addr + PCI_EXP_DEVCTL,
                             &val);
        pldsize = (val & PCI_EXP_DEVCTL_PAYLOAD) >> 5;
+
+       pci_read_config_word(adap->pdev, 0x2, &devid);
+       if (devid == 0x37) {
+               pci_write_config_word(adap->pdev,
+                                     adap->params.pci.pcie_cap_addr +
+                                     PCI_EXP_DEVCTL,
+                                     val & ~PCI_EXP_DEVCTL_READRQ &
+                                     ~PCI_EXP_DEVCTL_PAYLOAD);
+               pldsize = 0;
+       }
+
        pci_read_config_word(adap->pdev,
                             adap->params.pci.pcie_cap_addr + PCI_EXP_LNKCTL,
                             &val);