drm/radeon/kms/evergreen: add soft reset function

Works pretty similarly to r6xx/r7xx.

Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c
index afcff06..a6130a4 100644 (file)
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -511,12 +511,81 @@ bool evergreen_gpu_is_lockup(struct radeon_device *rdev)
        return false;
 }
 
-int evergreen_asic_reset(struct radeon_device *rdev)
+static int evergreen_gpu_soft_reset(struct radeon_device *rdev)
 {
-       /* FIXME: implement for evergreen */
+       struct evergreen_mc_save save;
+       u32 srbm_reset = 0;
+       u32 grbm_reset = 0;
+
+       dev_info(rdev->dev, "GPU softreset \n");
+       dev_info(rdev->dev, "  GRBM_STATUS=0x%08X\n",
+               RREG32(GRBM_STATUS));
+       dev_info(rdev->dev, "  GRBM_STATUS_SE0=0x%08X\n",
+               RREG32(GRBM_STATUS_SE0));
+       dev_info(rdev->dev, "  GRBM_STATUS_SE1=0x%08X\n",
+               RREG32(GRBM_STATUS_SE1));
+       dev_info(rdev->dev, "  SRBM_STATUS=0x%08X\n",
+               RREG32(SRBM_STATUS));
+       evergreen_mc_stop(rdev, &save);
+       if (evergreen_mc_wait_for_idle(rdev)) {
+               dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
+       }
+       /* Disable CP parsing/prefetching */
+       WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT);
+
+       /* reset all the gfx blocks */
+       grbm_reset = (SOFT_RESET_CP |
+                     SOFT_RESET_CB |
+                     SOFT_RESET_DB |
+                     SOFT_RESET_PA |
+                     SOFT_RESET_SC |
+                     SOFT_RESET_SPI |
+                     SOFT_RESET_SH |
+                     SOFT_RESET_SX |
+                     SOFT_RESET_TC |
+                     SOFT_RESET_TA |
+                     SOFT_RESET_VC |
+                     SOFT_RESET_VGT);
+
+       dev_info(rdev->dev, "  GRBM_SOFT_RESET=0x%08X\n", grbm_reset);
+       WREG32(GRBM_SOFT_RESET, grbm_reset);
+       (void)RREG32(GRBM_SOFT_RESET);
+       udelay(50);
+       WREG32(GRBM_SOFT_RESET, 0);
+       (void)RREG32(GRBM_SOFT_RESET);
+
+       /* reset all the system blocks */
+       srbm_reset = SRBM_SOFT_RESET_ALL_MASK;
+
+       dev_info(rdev->dev, "  SRBM_SOFT_RESET=0x%08X\n", srbm_reset);
+       WREG32(SRBM_SOFT_RESET, srbm_reset);
+       (void)RREG32(SRBM_SOFT_RESET);
+       udelay(50);
+       WREG32(SRBM_SOFT_RESET, 0);
+       (void)RREG32(SRBM_SOFT_RESET);
+       /* Wait a little for things to settle down */
+       udelay(50);
+       dev_info(rdev->dev, "  GRBM_STATUS=0x%08X\n",
+               RREG32(GRBM_STATUS));
+       dev_info(rdev->dev, "  GRBM_STATUS_SE0=0x%08X\n",
+               RREG32(GRBM_STATUS_SE0));
+       dev_info(rdev->dev, "  GRBM_STATUS_SE1=0x%08X\n",
+               RREG32(GRBM_STATUS_SE1));
+       dev_info(rdev->dev, "  SRBM_STATUS=0x%08X\n",
+               RREG32(SRBM_STATUS));
+       /* After reset we need to reinit the asic as GPU often endup in an
+        * incoherent state.
+        */
+       atom_asic_init(rdev->mode_info.atom_context);
+       evergreen_mc_resume(rdev, &save);
        return 0;
 }
 
+int evergreen_asic_reset(struct radeon_device *rdev)
+{
+       return evergreen_gpu_soft_reset(rdev);
+}
+
 static int evergreen_startup(struct radeon_device *rdev)
 {
        int r;

diff --git a/drivers/gpu/drm/radeon/evergreend.h b/drivers/gpu/drm/radeon/evergreend.h
index 5cf707a..7c290a6 100644 (file)
--- a/drivers/gpu/drm/radeon/evergreend.h
+++ b/drivers/gpu/drm/radeon/evergreend.h
@@ -78,10 +78,53 @@
 #define        GRBM_CNTL                                       0x8000
 #define                GRBM_READ_TIMEOUT(x)                            ((x) << 0)
 #define        GRBM_SOFT_RESET                                 0x8020
-#define                SOFT_RESET_CP                                   (1<<0)
+#define                SOFT_RESET_CP                                   (1 << 0)
+#define                SOFT_RESET_CB                                   (1 << 1)
+#define                SOFT_RESET_DB                                   (1 << 3)
+#define                SOFT_RESET_PA                                   (1 << 5)
+#define                SOFT_RESET_SC                                   (1 << 6)
+#define                SOFT_RESET_SPI                                  (1 << 8)
+#define                SOFT_RESET_SH                                   (1 << 9)
+#define                SOFT_RESET_SX                                   (1 << 10)
+#define                SOFT_RESET_TC                                   (1 << 11)
+#define                SOFT_RESET_TA                                   (1 << 12)
+#define                SOFT_RESET_VC                                   (1 << 13)
+#define                SOFT_RESET_VGT                                  (1 << 14)
+
 #define        GRBM_STATUS                                     0x8010
 #define                CMDFIFO_AVAIL_MASK                              0x0000000F
-#define                GUI_ACTIVE                                      (1<<31)
+#define                SRBM_RQ_PENDING                                 (1 << 5)
+#define                CF_RQ_PENDING                                   (1 << 7)
+#define                PF_RQ_PENDING                                   (1 << 8)
+#define                GRBM_EE_BUSY                                    (1 << 10)
+#define                SX_CLEAN                                        (1 << 11)
+#define                DB_CLEAN                                        (1 << 12)
+#define                CB_CLEAN                                        (1 << 13)
+#define                TA_BUSY                                         (1 << 14)
+#define                VGT_BUSY_NO_DMA                                 (1 << 16)
+#define                VGT_BUSY                                        (1 << 17)
+#define                SX_BUSY                                         (1 << 20)
+#define                SH_BUSY                                         (1 << 21)
+#define                SPI_BUSY                                        (1 << 22)
+#define                SC_BUSY                                         (1 << 24)
+#define                PA_BUSY                                         (1 << 25)
+#define                DB_BUSY                                         (1 << 26)
+#define                CP_COHERENCY_BUSY                               (1 << 28)
+#define                CP_BUSY                                         (1 << 29)
+#define                CB_BUSY                                         (1 << 30)
+#define                GUI_ACTIVE                                      (1 << 31)
+#define        GRBM_STATUS_SE0                                 0x8014
+#define        GRBM_STATUS_SE1                                 0x8018
+#define                SE_SX_CLEAN                                     (1 << 0)
+#define                SE_DB_CLEAN                                     (1 << 1)
+#define                SE_CB_CLEAN                                     (1 << 2)
+#define                SE_TA_BUSY                                      (1 << 25)
+#define                SE_SX_BUSY                                      (1 << 26)
+#define                SE_SPI_BUSY                                     (1 << 27)
+#define                SE_SH_BUSY                                      (1 << 28)
+#define                SE_SC_BUSY                                      (1 << 29)
+#define                SE_DB_BUSY                                      (1 << 30)
+#define                SE_CB_BUSY                                      (1 << 31)
 
 #define        HDP_HOST_PATH_CNTL                              0x2C00
 #define        HDP_NONSURFACE_BASE                             0x2C04
@@ -266,5 +309,21 @@
 #define        WAIT_UNTIL                                      0x8040
 
 #define        SRBM_STATUS                                     0x0E50
+#define        SRBM_SOFT_RESET                                 0x0E60
+#define                SRBM_SOFT_RESET_ALL_MASK                0x00FEEFA6
+#define                SOFT_RESET_BIF                          (1 << 1)
+#define                SOFT_RESET_CG                           (1 << 2)
+#define                SOFT_RESET_DC                           (1 << 5)
+#define                SOFT_RESET_GRBM                         (1 << 8)
+#define                SOFT_RESET_HDP                          (1 << 9)
+#define                SOFT_RESET_IH                           (1 << 10)
+#define                SOFT_RESET_MC                           (1 << 11)
+#define                SOFT_RESET_RLC                          (1 << 13)
+#define                SOFT_RESET_ROM                          (1 << 14)
+#define                SOFT_RESET_SEM                          (1 << 15)
+#define                SOFT_RESET_VMC                          (1 << 17)
+#define                SOFT_RESET_TST                          (1 << 21)
+#define                SOFT_RESET_REGBB                        (1 << 22)
+#define                SOFT_RESET_ORB                          (1 << 23)
 
 #endif