microblaze: Fix cache_line_lenght

We used cache_line as cache_line_lenght. For this reason
we did cache flushing 4 times longer than was necessary.

Signed-off-by: Michal Simek <monstr@monstr.eu>

diff --git a/arch/microblaze/include/asm/cpuinfo.h b/arch/microblaze/include/asm/cpuinfo.h
index 52f28f6..aadf7a8 100644 (file)
--- a/arch/microblaze/include/asm/cpuinfo.h
+++ b/arch/microblaze/include/asm/cpuinfo.h
@@ -43,7 +43,7 @@ struct cpuinfo {
        u32 use_icache;
        u32 icache_tagbits;
        u32 icache_write;
-       u32 icache_line;
+       u32 icache_line_length;
        u32 icache_size;
        unsigned long icache_base;
        unsigned long icache_high;
@@ -51,7 +51,7 @@ struct cpuinfo {
        u32 use_dcache;
        u32 dcache_tagbits;
        u32 dcache_write;
-       u32 dcache_line;
+       u32 dcache_line_length;
        u32 dcache_size;
        unsigned long dcache_base;
        unsigned long dcache_high;

diff --git a/arch/microblaze/kernel/cpu/cache.c b/arch/microblaze/kernel/cpu/cache.c
index af866a4..538f1df 100644 (file)
--- a/arch/microblaze/kernel/cpu/cache.c
+++ b/arch/microblaze/kernel/cpu/cache.c
@@ -140,7 +140,7 @@ void __invalidate_icache_all(void)
                /* Just loop through cache size and invalidate, no need to add
                        CACHE_BASE address */
                for (i = 0; i < cpuinfo.icache_size;
-                       i += cpuinfo.icache_line)
+                       i += cpuinfo.icache_line_length)
                                __invalidate_icache(i);
 
                __enable_icache();
@@ -160,15 +160,15 @@ void __invalidate_icache_range(unsigned long start, unsigned long end)
                 * just cover cache footprint
                 */
                end = min(start + cpuinfo.icache_size, end);
-               align = ~(cpuinfo.icache_line - 1);
+               align = ~(cpuinfo.icache_line_length - 1);
                start &= align; /* Make sure we are aligned */
                /* Push end up to the next cache line */
-               end = ((end & align) + cpuinfo.icache_line);
+               end = ((end & align) + cpuinfo.icache_line_length);
 
                local_irq_save(flags);
                __disable_icache();
 
-               for (i = start; i < end; i += cpuinfo.icache_line)
+               for (i = start; i < end; i += cpuinfo.icache_line_length)
                        __invalidate_icache(i);
 
                __enable_icache();
@@ -207,7 +207,7 @@ void __invalidate_dcache_all(void)
                 * no need to add CACHE_BASE address
                 */
                for (i = 0; i < cpuinfo.dcache_size;
-                       i += cpuinfo.dcache_line)
+                       i += cpuinfo.dcache_line_length)
                                __invalidate_dcache(i);
 
                __enable_dcache();
@@ -227,14 +227,14 @@ void __invalidate_dcache_range(unsigned long start, unsigned long end)
                 * just cover cache footprint
                 */
                end = min(start + cpuinfo.dcache_size, end);
-               align = ~(cpuinfo.dcache_line - 1);
+               align = ~(cpuinfo.dcache_line_length - 1);
                start &= align; /* Make sure we are aligned */
                /* Push end up to the next cache line */
-               end = ((end & align) + cpuinfo.dcache_line);
+               end = ((end & align) + cpuinfo.dcache_line_length);
                local_irq_save(flags);
                __disable_dcache();
 
-               for (i = start; i < end; i += cpuinfo.dcache_line)
+               for (i = start; i < end; i += cpuinfo.dcache_line_length)
                        __invalidate_dcache(i);
 
                __enable_dcache();

diff --git a/arch/microblaze/kernel/cpu/cpuinfo-pvr-full.c b/arch/microblaze/kernel/cpu/cpuinfo-pvr-full.c
index c259786..c5acf2b 100644 (file)
--- a/arch/microblaze/kernel/cpu/cpuinfo-pvr-full.c
+++ b/arch/microblaze/kernel/cpu/cpuinfo-pvr-full.c
@@ -70,7 +70,7 @@ void set_cpuinfo_pvr_full(struct cpuinfo *ci, struct device_node *cpu)
        CI(use_icache, USE_ICACHE);
        CI(icache_tagbits, ICACHE_ADDR_TAG_BITS);
        CI(icache_write, ICACHE_ALLOW_WR);
-       CI(icache_line, ICACHE_LINE_LEN);
+       ci->icache_line_length = PVR_ICACHE_LINE_LEN(pvr) << 2;
        CI(icache_size, ICACHE_BYTE_SIZE);
        CI(icache_base, ICACHE_BASEADDR);
        CI(icache_high, ICACHE_HIGHADDR);
@@ -78,7 +78,7 @@ void set_cpuinfo_pvr_full(struct cpuinfo *ci, struct device_node *cpu)
        CI(use_dcache, USE_DCACHE);
        CI(dcache_tagbits, DCACHE_ADDR_TAG_BITS);
        CI(dcache_write, DCACHE_ALLOW_WR);
-       CI(dcache_line, DCACHE_LINE_LEN);
+       ci->dcache_line_length = PVR_DCACHE_LINE_LEN(pvr) << 2;
        CI(dcache_size, DCACHE_BYTE_SIZE);
        CI(dcache_base, DCACHE_BASEADDR);
        CI(dcache_high, DCACHE_HIGHADDR);

diff --git a/arch/microblaze/kernel/cpu/cpuinfo-static.c b/arch/microblaze/kernel/cpu/cpuinfo-static.c
index adb448f..6558429 100644 (file)
--- a/arch/microblaze/kernel/cpu/cpuinfo-static.c
+++ b/arch/microblaze/kernel/cpu/cpuinfo-static.c
@@ -72,12 +72,12 @@ void __init set_cpuinfo_static(struct cpuinfo *ci, struct device_node *cpu)
        ci->use_icache = fcpu(cpu, "xlnx,use-icache");
        ci->icache_tagbits = fcpu(cpu, "xlnx,addr-tag-bits");
        ci->icache_write = fcpu(cpu, "xlnx,allow-icache-wr");
-       ci->icache_line = fcpu(cpu, "xlnx,icache-line-len") << 2;
-       if (!ci->icache_line) {
+       ci->icache_line_length = fcpu(cpu, "xlnx,icache-line-len") << 2;
+       if (!ci->icache_line_length) {
                if (fcpu(cpu, "xlnx,icache-use-fsl"))
-                       ci->icache_line = 4 << 2;
+                       ci->icache_line_length = 4 << 2;
                else
-                       ci->icache_line = 1 << 2;
+                       ci->icache_line_length = 1 << 2;
        }
        ci->icache_size = fcpu(cpu, "i-cache-size");
        ci->icache_base = fcpu(cpu, "i-cache-baseaddr");
@@ -86,12 +86,12 @@ void __init set_cpuinfo_static(struct cpuinfo *ci, struct device_node *cpu)
        ci->use_dcache = fcpu(cpu, "xlnx,use-dcache");
        ci->dcache_tagbits = fcpu(cpu, "xlnx,dcache-addr-tag");
        ci->dcache_write = fcpu(cpu, "xlnx,allow-dcache-wr");
-       ci->dcache_line = fcpu(cpu, "xlnx,dcache-line-len") << 2;
-       if (!ci->dcache_line) {
+       ci->dcache_line_length = fcpu(cpu, "xlnx,dcache-line-len") << 2;
+       if (!ci->dcache_line_length) {
                if (fcpu(cpu, "xlnx,dcache-use-fsl"))
-                       ci->dcache_line = 4 << 2;
+                       ci->dcache_line_length = 4 << 2;
                else
-                       ci->dcache_line = 1 << 2;
+                       ci->dcache_line_length = 1 << 2;
        }
        ci->dcache_size = fcpu(cpu, "d-cache-size");
        ci->dcache_base = fcpu(cpu, "d-cache-baseaddr");