Merge branch 'drm-intel-next' of git://git.kernel.org/pub/scm/linux/kernel/git/anholt...

* 'drm-intel-next' of git://git.kernel.org/pub/scm/linux/kernel/git/anholt/drm-intel:
  i915: Set object to gtt domain when faulting it back in
  drm/i915: Apply a big hammer to 865 GEM object CPU cache flushing.
  drm/i915: Fix tiling pitch handling on 8xx.

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 717b6a8..670d128 100644 (file)
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1145,6 +1145,13 @@ int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
                        mutex_unlock(&dev->struct_mutex);
                        return VM_FAULT_SIGBUS;
                }
+
+               ret = i915_gem_object_set_to_gtt_domain(obj, write);
+               if (ret) {
+                       mutex_unlock(&dev->struct_mutex);
+                       return VM_FAULT_SIGBUS;
+               }
+
                list_add_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
        }
 
@@ -2128,8 +2135,10 @@ static void i830_write_fence_reg(struct drm_i915_fence_reg *reg)
                return;
        }
 
-       pitch_val = (obj_priv->stride / 128) - 1;
-       WARN_ON(pitch_val & ~0x0000000f);
+       pitch_val = obj_priv->stride / 128;
+       pitch_val = ffs(pitch_val) - 1;
+       WARN_ON(pitch_val > I830_FENCE_MAX_PITCH_VAL);
+
        val = obj_priv->gtt_offset;
        if (obj_priv->tiling_mode == I915_TILING_Y)
                val |= 1 << I830_FENCE_TILING_Y_SHIFT;
@@ -2421,6 +2430,16 @@ i915_gem_clflush_object(struct drm_gem_object *obj)
        if (obj_priv->pages == NULL)
                return;
 
+       /* XXX: The 865 in particular appears to be weird in how it handles
+        * cache flushing.  We haven't figured it out, but the
+        * clflush+agp_chipset_flush doesn't appear to successfully get the
+        * data visible to the PGU, while wbinvd + agp_chipset_flush does.
+        */
+       if (IS_I865G(obj->dev)) {
+               wbinvd();
+               return;
+       }
+
        drm_clflush_pages(obj_priv->pages, obj->size / PAGE_SIZE);
 }
 

diff --git a/drivers/gpu/drm/i915/i915_gem_tiling.c b/drivers/gpu/drm/i915/i915_gem_tiling.c
index 52a0593..540dd33 100644 (file)
--- a/drivers/gpu/drm/i915/i915_gem_tiling.c
+++ b/drivers/gpu/drm/i915/i915_gem_tiling.c
@@ -213,7 +213,8 @@ i915_tiling_ok(struct drm_device *dev, int stride, int size, int tiling_mode)
        if (tiling_mode == I915_TILING_NONE)
                return true;
 
-       if (tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))
+       if (!IS_I9XX(dev) ||
+           (tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev)))
                tile_width = 128;
        else
                tile_width = 512;
@@ -225,11 +226,18 @@ i915_tiling_ok(struct drm_device *dev, int stride, int size, int tiling_mode)
                if (stride / 128 > I965_FENCE_MAX_PITCH_VAL)
                        return false;
        } else if (IS_I9XX(dev)) {
-               if (stride / tile_width > I830_FENCE_MAX_PITCH_VAL ||
+               uint32_t pitch_val = ffs(stride / tile_width) - 1;
+
+               /* XXX: For Y tiling, FENCE_MAX_PITCH_VAL is actually 6 (8KB)
+                * instead of 4 (2KB) on 945s.
+                */
+               if (pitch_val > I915_FENCE_MAX_PITCH_VAL ||
                    size > (I830_FENCE_MAX_SIZE_VAL << 20))
                        return false;
        } else {
-               if (stride / 128 > I830_FENCE_MAX_PITCH_VAL ||
+               uint32_t pitch_val = ffs(stride / tile_width) - 1;
+
+               if (pitch_val > I830_FENCE_MAX_PITCH_VAL ||
                    size > (I830_FENCE_MAX_SIZE_VAL << 19))
                        return false;
        }

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 9668cc0..375569d 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -190,7 +190,8 @@
 #define   I830_FENCE_SIZE_BITS(size)   ((ffs((size) >> 19) - 1) << 8)
 #define   I830_FENCE_PITCH_SHIFT       4
 #define   I830_FENCE_REG_VALID         (1<<0)
-#define   I830_FENCE_MAX_PITCH_VAL     0x10
+#define   I915_FENCE_MAX_PITCH_VAL     0x10
+#define   I830_FENCE_MAX_PITCH_VAL     6
 #define   I830_FENCE_MAX_SIZE_VAL      (1<<8)
 
 #define   I915_FENCE_START_MASK                0x0ff00000