sh: multi-evt support for SH-X3 proto CPU.

This adds support for multiple vectors per unique IRQ masking source on
the SH-X3 proto CPU.

Signed-off-by: Paul Mundt <lethal@linux-sh.org>

diff --git a/arch/sh/kernel/cpu/sh4a/setup-shx3.c b/arch/sh/kernel/cpu/sh4a/setup-shx3.c
index 07f0789..e848443 100644 (file)
--- a/arch/sh/kernel/cpu/sh4a/setup-shx3.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-shx3.c
@@ -268,11 +268,7 @@ enum {
        UNUSED = 0,
 
        /* interrupt sources */
-       IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH,
-       IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH,
-       IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH,
-       IRL_HHLL, IRL_HHLH, IRL_HHHL,
-       IRQ0, IRQ1, IRQ2, IRQ3,
+       IRL, IRQ0, IRQ1, IRQ2, IRQ3,
        HUDII,
        TMU0, TMU1, TMU2, TMU3, TMU4, TMU5,
        PCII0, PCII1, PCII2, PCII3, PCII4,
@@ -287,10 +283,7 @@ enum {
        DMAC1_DMINT6, DMAC1_DMINT7, DMAC1_DMINT8, DMAC1_DMINT9,
        DMAC1_DMINT10, DMAC1_DMINT11, DMAC1_DMAE,
        IIC, VIN0, VIN1, VCORE0, ATAPI,
-       DTU0_TEND, DTU0_AE, DTU0_TMISS,
-       DTU1_TEND, DTU1_AE, DTU1_TMISS,
-       DTU2_TEND, DTU2_AE, DTU2_TMISS,
-       DTU3_TEND, DTU3_AE, DTU3_TMISS,
+       DTU0, DTU1, DTU2, DTU3,
        FE0, FE1,
        GPIO0, GPIO1, GPIO2, GPIO3,
        PAM, IRM,
@@ -298,8 +291,8 @@ enum {
        INTICI4, INTICI5, INTICI6, INTICI7,
 
        /* interrupt groups */
-       IRL, PCII56789, SCIF0, SCIF1, SCIF2, SCIF3,
-       DMAC0, DMAC1, DTU0, DTU1, DTU2, DTU3,
+       PCII56789, SCIF0, SCIF1, SCIF2, SCIF3,
+       DMAC0, DMAC1,
 };
 
 static struct intc_vect vectors[] __initdata = {
@@ -332,14 +325,14 @@ static struct intc_vect vectors[] __initdata = {
        INTC_VECT(IIC, 0xae0),
        INTC_VECT(VIN0, 0xb00), INTC_VECT(VIN1, 0xb20),
        INTC_VECT(VCORE0, 0xb00), INTC_VECT(ATAPI, 0xb60),
-       INTC_VECT(DTU0_TEND, 0xc00), INTC_VECT(DTU0_AE, 0xc20),
-       INTC_VECT(DTU0_TMISS, 0xc40),
-       INTC_VECT(DTU1_TEND, 0xc60), INTC_VECT(DTU1_AE, 0xc80),
-       INTC_VECT(DTU1_TMISS, 0xca0),
-       INTC_VECT(DTU2_TEND, 0xcc0), INTC_VECT(DTU2_AE, 0xce0),
-       INTC_VECT(DTU2_TMISS, 0xd00),
-       INTC_VECT(DTU3_TEND, 0xd20), INTC_VECT(DTU3_AE, 0xd40),
-       INTC_VECT(DTU3_TMISS, 0xd60),
+       INTC_VECT(DTU0, 0xc00), INTC_VECT(DTU0, 0xc20),
+       INTC_VECT(DTU0, 0xc40),
+       INTC_VECT(DTU1, 0xc60), INTC_VECT(DTU1, 0xc80),
+       INTC_VECT(DTU1, 0xca0),
+       INTC_VECT(DTU2, 0xcc0), INTC_VECT(DTU2, 0xce0),
+       INTC_VECT(DTU2, 0xd00),
+       INTC_VECT(DTU3, 0xd20), INTC_VECT(DTU3, 0xd40),
+       INTC_VECT(DTU3, 0xd60),
        INTC_VECT(FE0, 0xe00), INTC_VECT(FE1, 0xe20),
        INTC_VECT(GPIO0, 0xe40), INTC_VECT(GPIO1, 0xe60),
        INTC_VECT(GPIO2, 0xe80), INTC_VECT(GPIO3, 0xea0),
@@ -351,10 +344,6 @@ static struct intc_vect vectors[] __initdata = {
 };
 
 static struct intc_group groups[] __initdata = {
-       INTC_GROUP(IRL, IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH,
-                  IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH,
-                  IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH,
-                  IRL_HHLL, IRL_HHLH, IRL_HHHL),
        INTC_GROUP(PCII56789, PCII5, PCII6, PCII7, PCII8, PCII9),
        INTC_GROUP(SCIF0, SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI),
        INTC_GROUP(SCIF1, SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI),
@@ -364,10 +353,6 @@ static struct intc_group groups[] __initdata = {
                   DMAC0_DMINT3, DMAC0_DMINT4, DMAC0_DMINT5, DMAC0_DMAE),
        INTC_GROUP(DMAC1, DMAC1_DMINT6, DMAC1_DMINT7, DMAC1_DMINT8,
                   DMAC1_DMINT9, DMAC1_DMINT10, DMAC1_DMINT11),
-       INTC_GROUP(DTU0, DTU0_TEND, DTU0_AE, DTU0_TMISS),
-       INTC_GROUP(DTU1, DTU1_TEND, DTU1_AE, DTU1_TMISS),
-       INTC_GROUP(DTU2, DTU2_TEND, DTU2_AE, DTU2_TMISS),
-       INTC_GROUP(DTU3, DTU3_TEND, DTU3_AE, DTU3_TMISS),
 };
 
 static struct intc_mask_reg mask_registers[] __initdata = {
@@ -434,14 +419,14 @@ static DECLARE_INTC_DESC(intc_desc_irq, "shx3-irq", vectors_irq, groups,
 
 /* External interrupt pins in IRL mode */
 static struct intc_vect vectors_irl[] __initdata = {
-       INTC_VECT(IRL_LLLL, 0x200), INTC_VECT(IRL_LLLH, 0x220),
-       INTC_VECT(IRL_LLHL, 0x240), INTC_VECT(IRL_LLHH, 0x260),
-       INTC_VECT(IRL_LHLL, 0x280), INTC_VECT(IRL_LHLH, 0x2a0),
-       INTC_VECT(IRL_LHHL, 0x2c0), INTC_VECT(IRL_LHHH, 0x2e0),
-       INTC_VECT(IRL_HLLL, 0x300), INTC_VECT(IRL_HLLH, 0x320),
-       INTC_VECT(IRL_HLHL, 0x340), INTC_VECT(IRL_HLHH, 0x360),
-       INTC_VECT(IRL_HHLL, 0x380), INTC_VECT(IRL_HHLH, 0x3a0),
-       INTC_VECT(IRL_HHHL, 0x3c0),
+       INTC_VECT(IRL, 0x200), INTC_VECT(IRL, 0x220),
+       INTC_VECT(IRL, 0x240), INTC_VECT(IRL, 0x260),
+       INTC_VECT(IRL, 0x280), INTC_VECT(IRL, 0x2a0),
+       INTC_VECT(IRL, 0x2c0), INTC_VECT(IRL, 0x2e0),
+       INTC_VECT(IRL, 0x300), INTC_VECT(IRL, 0x320),
+       INTC_VECT(IRL, 0x340), INTC_VECT(IRL, 0x360),
+       INTC_VECT(IRL, 0x380), INTC_VECT(IRL, 0x3a0),
+       INTC_VECT(IRL, 0x3c0),
 };
 
 static DECLARE_INTC_DESC(intc_desc_irl, "shx3-irl", vectors_irl, groups,