e1000: Enable custom configuration bits for 82571/2 controllers

Enable custom configuration bits for 82571/2 controllers. The bits are
required for correct functionality of these controllers.

Signed-off-by: Mallikarjuna R Chilakala <mallikarjuna.chilakala@intel.com>
Signed-off-by: Ganesh Venkatesan <ganesh.venkatesan@intel.com>
Signed-off-by: John Ronciak <john.ronciak@intel.com>
Signed-off-by: Jeff Garzik <jgarzik@pobox.com>

diff --git a/drivers/net/e1000/e1000_main.c b/drivers/net/e1000/e1000_main.c
index ce1044a..ad92115 100644 (file)
--- a/drivers/net/e1000/e1000_main.c
+++ b/drivers/net/e1000/e1000_main.c
@@ -1151,6 +1151,7 @@ e1000_setup_tx_resources(struct e1000_adapter *adapter,
                return -ENOMEM;
        }
        memset(txdr->buffer_info, 0, size);
+       memset(&txdr->previous_buffer_info, 0, sizeof(struct e1000_buffer));
 
        /* round up to nearest 4K */
 
@@ -1199,6 +1200,7 @@ setup_tx_desc_die:
 
        txdr->next_to_use = 0;
        txdr->next_to_clean = 0;
+       spin_lock_init(&txdr->tx_lock);
 
        return 0;
 }
@@ -1312,6 +1314,19 @@ e1000_configure_tx(struct e1000_adapter *adapter)
 
        E1000_WRITE_REG(hw, TCTL, tctl);
 
+       if (hw->mac_type == e1000_82571 || hw->mac_type == e1000_82572) {
+               tarc = E1000_READ_REG(hw, TARC0);
+               tarc |= ((1 << 25) | (1 << 21));
+               E1000_WRITE_REG(hw, TARC0, tarc);
+               tarc = E1000_READ_REG(hw, TARC1);
+               tarc |= (1 << 25);
+               if (tctl & E1000_TCTL_MULR)
+                       tarc &= ~(1 << 28);
+               else
+                       tarc |= (1 << 28);
+               E1000_WRITE_REG(hw, TARC1, tarc);
+       }
+
        e1000_config_collision_dist(hw);
 
        /* Setup Transmit Descriptor Settings for eop descriptor */
@@ -1601,6 +1616,14 @@ e1000_configure_rx(struct e1000_adapter *adapter)
                                1000000000 / (adapter->itr * 256));
        }
 
+       if (hw->mac_type >= e1000_82571) {
+               /* Reset delay timers after every interrupt */
+               ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
+               ctrl_ext |= E1000_CTRL_EXT_CANC;
+               E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
+               E1000_WRITE_FLUSH(hw);
+       }
+
        /* Setup the HW Rx Head and Tail Descriptor Pointers and
         * the Base and Length of the Rx Descriptor Ring */
        switch (adapter->num_queues) {