2 * ALSA SoC I2S (McBSP) Audio Layer for TI DAVINCI processor
4 * Author: Vladimir Barinov, <vbarinov@embeddedalley.com>
5 * Copyright: (C) 2007 MontaVista Software, Inc., <source@mvista.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
12 #include <linux/init.h>
13 #include <linux/module.h>
14 #include <linux/device.h>
15 #include <linux/delay.h>
17 #include <linux/clk.h>
19 #include <sound/core.h>
20 #include <sound/pcm.h>
21 #include <sound/pcm_params.h>
22 #include <sound/initval.h>
23 #include <sound/soc.h>
27 #include "davinci-pcm.h"
31 * NOTE: terminology here is confusing.
33 * - This driver supports the "Audio Serial Port" (ASP),
34 * found on dm6446, dm355, and other DaVinci chips.
36 * - But it labels it a "Multi-channel Buffered Serial Port"
37 * (McBSP) as on older chips like the dm642 ... which was
38 * backward-compatible, possibly explaining that confusion.
40 * - OMAP chips have a controller called McBSP, which is
41 * incompatible with the DaVinci flavor of McBSP.
43 * - Newer DaVinci chips have a controller called McASP,
44 * incompatible with ASP and with either McBSP.
46 * In short: this uses ASP to implement I2S, not McBSP.
47 * And it won't be the only DaVinci implemention of I2S.
49 #define DAVINCI_MCBSP_DRR_REG 0x00
50 #define DAVINCI_MCBSP_DXR_REG 0x04
51 #define DAVINCI_MCBSP_SPCR_REG 0x08
52 #define DAVINCI_MCBSP_RCR_REG 0x0c
53 #define DAVINCI_MCBSP_XCR_REG 0x10
54 #define DAVINCI_MCBSP_SRGR_REG 0x14
55 #define DAVINCI_MCBSP_PCR_REG 0x24
57 #define DAVINCI_MCBSP_SPCR_RRST (1 << 0)
58 #define DAVINCI_MCBSP_SPCR_RINTM(v) ((v) << 4)
59 #define DAVINCI_MCBSP_SPCR_XRST (1 << 16)
60 #define DAVINCI_MCBSP_SPCR_XINTM(v) ((v) << 20)
61 #define DAVINCI_MCBSP_SPCR_GRST (1 << 22)
62 #define DAVINCI_MCBSP_SPCR_FRST (1 << 23)
63 #define DAVINCI_MCBSP_SPCR_FREE (1 << 25)
65 #define DAVINCI_MCBSP_RCR_RWDLEN1(v) ((v) << 5)
66 #define DAVINCI_MCBSP_RCR_RFRLEN1(v) ((v) << 8)
67 #define DAVINCI_MCBSP_RCR_RDATDLY(v) ((v) << 16)
68 #define DAVINCI_MCBSP_RCR_RFIG (1 << 18)
69 #define DAVINCI_MCBSP_RCR_RWDLEN2(v) ((v) << 21)
71 #define DAVINCI_MCBSP_XCR_XWDLEN1(v) ((v) << 5)
72 #define DAVINCI_MCBSP_XCR_XFRLEN1(v) ((v) << 8)
73 #define DAVINCI_MCBSP_XCR_XDATDLY(v) ((v) << 16)
74 #define DAVINCI_MCBSP_XCR_XFIG (1 << 18)
75 #define DAVINCI_MCBSP_XCR_XWDLEN2(v) ((v) << 21)
77 #define DAVINCI_MCBSP_SRGR_FWID(v) ((v) << 8)
78 #define DAVINCI_MCBSP_SRGR_FPER(v) ((v) << 16)
79 #define DAVINCI_MCBSP_SRGR_FSGM (1 << 28)
81 #define DAVINCI_MCBSP_PCR_CLKRP (1 << 0)
82 #define DAVINCI_MCBSP_PCR_CLKXP (1 << 1)
83 #define DAVINCI_MCBSP_PCR_FSRP (1 << 2)
84 #define DAVINCI_MCBSP_PCR_FSXP (1 << 3)
85 #define DAVINCI_MCBSP_PCR_SCLKME (1 << 7)
86 #define DAVINCI_MCBSP_PCR_CLKRM (1 << 8)
87 #define DAVINCI_MCBSP_PCR_CLKXM (1 << 9)
88 #define DAVINCI_MCBSP_PCR_FSRM (1 << 10)
89 #define DAVINCI_MCBSP_PCR_FSXM (1 << 11)
92 DAVINCI_MCBSP_WORD_8 = 0,
93 DAVINCI_MCBSP_WORD_12,
94 DAVINCI_MCBSP_WORD_16,
95 DAVINCI_MCBSP_WORD_20,
96 DAVINCI_MCBSP_WORD_24,
97 DAVINCI_MCBSP_WORD_32,
100 struct davinci_mcbsp_dev {
101 struct davinci_pcm_dma_params dma_params[2];
110 static inline void davinci_mcbsp_write_reg(struct davinci_mcbsp_dev *dev,
113 __raw_writel(val, dev->base + reg);
116 static inline u32 davinci_mcbsp_read_reg(struct davinci_mcbsp_dev *dev, int reg)
118 return __raw_readl(dev->base + reg);
121 static void toggle_clock(struct davinci_mcbsp_dev *dev, int playback)
123 u32 m = playback ? DAVINCI_MCBSP_PCR_CLKXP : DAVINCI_MCBSP_PCR_CLKRP;
124 /* The clock needs to toggle to complete reset.
125 * So, fake it by toggling the clk polarity.
127 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, dev->pcr ^ m);
128 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, dev->pcr);
131 static void davinci_mcbsp_start(struct davinci_mcbsp_dev *dev,
132 struct snd_pcm_substream *substream)
134 struct snd_soc_pcm_runtime *rtd = substream->private_data;
135 struct snd_soc_device *socdev = rtd->socdev;
136 struct snd_soc_platform *platform = socdev->card->platform;
137 int playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
139 u32 mask = playback ? DAVINCI_MCBSP_SPCR_XRST : DAVINCI_MCBSP_SPCR_RRST;
140 spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
142 /* start off disabled */
143 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG,
145 toggle_clock(dev, playback);
147 if (dev->pcr & (DAVINCI_MCBSP_PCR_FSXM | DAVINCI_MCBSP_PCR_FSRM |
148 DAVINCI_MCBSP_PCR_CLKXM | DAVINCI_MCBSP_PCR_CLKRM)) {
149 /* Start the sample generator */
150 spcr |= DAVINCI_MCBSP_SPCR_GRST;
151 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
155 /* Stop the DMA to avoid data loss */
156 /* while the transmitter is out of reset to handle XSYNCERR */
157 if (platform->pcm_ops->trigger) {
158 int ret = platform->pcm_ops->trigger(substream,
159 SNDRV_PCM_TRIGGER_STOP);
161 printk(KERN_DEBUG "Playback DMA stop failed\n");
164 /* Enable the transmitter */
165 spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
166 spcr |= DAVINCI_MCBSP_SPCR_XRST;
167 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
169 /* wait for any unexpected frame sync error to occur */
172 /* Disable the transmitter to clear any outstanding XSYNCERR */
173 spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
174 spcr &= ~DAVINCI_MCBSP_SPCR_XRST;
175 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
176 toggle_clock(dev, playback);
178 /* Restart the DMA */
179 if (platform->pcm_ops->trigger) {
180 int ret = platform->pcm_ops->trigger(substream,
181 SNDRV_PCM_TRIGGER_START);
183 printk(KERN_DEBUG "Playback DMA start failed\n");
187 /* Enable transmitter or receiver */
188 spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
191 if (dev->pcr & (DAVINCI_MCBSP_PCR_FSXM | DAVINCI_MCBSP_PCR_FSRM)) {
192 /* Start frame sync */
193 spcr |= DAVINCI_MCBSP_SPCR_FRST;
195 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
198 static void davinci_mcbsp_stop(struct davinci_mcbsp_dev *dev, int playback)
202 /* Reset transmitter/receiver and sample rate/frame sync generators */
203 spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
204 spcr &= ~(DAVINCI_MCBSP_SPCR_GRST | DAVINCI_MCBSP_SPCR_FRST);
205 spcr &= playback ? ~DAVINCI_MCBSP_SPCR_XRST : ~DAVINCI_MCBSP_SPCR_RRST;
206 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
207 toggle_clock(dev, playback);
210 #define DEFAULT_BITPERSAMPLE 16
212 static int davinci_i2s_set_dai_fmt(struct snd_soc_dai *cpu_dai,
215 struct davinci_mcbsp_dev *dev = cpu_dai->private_data;
218 srgr = DAVINCI_MCBSP_SRGR_FSGM |
219 DAVINCI_MCBSP_SRGR_FPER(DEFAULT_BITPERSAMPLE * 2 - 1) |
220 DAVINCI_MCBSP_SRGR_FWID(DEFAULT_BITPERSAMPLE - 1);
222 /* set master/slave audio interface */
223 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
224 case SND_SOC_DAIFMT_CBS_CFS:
226 pcr = DAVINCI_MCBSP_PCR_FSXM |
227 DAVINCI_MCBSP_PCR_FSRM |
228 DAVINCI_MCBSP_PCR_CLKXM |
229 DAVINCI_MCBSP_PCR_CLKRM;
231 case SND_SOC_DAIFMT_CBM_CFS:
232 /* McBSP CLKR pin is the input for the Sample Rate Generator.
233 * McBSP FSR and FSX are driven by the Sample Rate Generator. */
234 pcr = DAVINCI_MCBSP_PCR_SCLKME |
235 DAVINCI_MCBSP_PCR_FSXM |
236 DAVINCI_MCBSP_PCR_FSRM;
238 case SND_SOC_DAIFMT_CBM_CFM:
239 /* codec is master */
243 printk(KERN_ERR "%s:bad master\n", __func__);
247 /* interface format */
248 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
249 case SND_SOC_DAIFMT_I2S:
250 /* Davinci doesn't support TRUE I2S, but some codecs will have
251 * the left and right channels contiguous. This allows
252 * dsp_a mode to be used with an inverted normal frame clk.
253 * If your codec is master and does not have contiguous
254 * channels, then you will have sound on only one channel.
255 * Try using a different mode, or codec as slave.
257 * The TLV320AIC33 is an example of a codec where this works.
258 * It has a variable bit clock frequency allowing it to have
259 * valid data on every bit clock.
261 * The TLV320AIC23 is an example of a codec where this does not
262 * work. It has a fixed bit clock frequency with progressively
263 * more empty bit clock slots between channels as the sample
266 fmt ^= SND_SOC_DAIFMT_NB_IF;
267 case SND_SOC_DAIFMT_DSP_A:
268 dev->mode = MOD_DSP_A;
270 case SND_SOC_DAIFMT_DSP_B:
271 dev->mode = MOD_DSP_B;
274 printk(KERN_ERR "%s:bad format\n", __func__);
278 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
279 case SND_SOC_DAIFMT_NB_NF:
280 /* CLKRP Receive clock polarity,
281 * 1 - sampled on rising edge of CLKR
282 * valid on rising edge
283 * CLKXP Transmit clock polarity,
284 * 1 - clocked on falling edge of CLKX
285 * valid on rising edge
286 * FSRP Receive frame sync pol, 0 - active high
287 * FSXP Transmit frame sync pol, 0 - active high
289 pcr |= (DAVINCI_MCBSP_PCR_CLKXP | DAVINCI_MCBSP_PCR_CLKRP);
291 case SND_SOC_DAIFMT_IB_IF:
292 /* CLKRP Receive clock polarity,
293 * 0 - sampled on falling edge of CLKR
294 * valid on falling edge
295 * CLKXP Transmit clock polarity,
296 * 0 - clocked on rising edge of CLKX
297 * valid on falling edge
298 * FSRP Receive frame sync pol, 1 - active low
299 * FSXP Transmit frame sync pol, 1 - active low
301 pcr |= (DAVINCI_MCBSP_PCR_FSXP | DAVINCI_MCBSP_PCR_FSRP);
303 case SND_SOC_DAIFMT_NB_IF:
304 /* CLKRP Receive clock polarity,
305 * 1 - sampled on rising edge of CLKR
306 * valid on rising edge
307 * CLKXP Transmit clock polarity,
308 * 1 - clocked on falling edge of CLKX
309 * valid on rising edge
310 * FSRP Receive frame sync pol, 1 - active low
311 * FSXP Transmit frame sync pol, 1 - active low
313 pcr |= (DAVINCI_MCBSP_PCR_CLKXP | DAVINCI_MCBSP_PCR_CLKRP |
314 DAVINCI_MCBSP_PCR_FSXP | DAVINCI_MCBSP_PCR_FSRP);
316 case SND_SOC_DAIFMT_IB_NF:
317 /* CLKRP Receive clock polarity,
318 * 0 - sampled on falling edge of CLKR
319 * valid on falling edge
320 * CLKXP Transmit clock polarity,
321 * 0 - clocked on rising edge of CLKX
322 * valid on falling edge
323 * FSRP Receive frame sync pol, 0 - active high
324 * FSXP Transmit frame sync pol, 0 - active high
330 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SRGR_REG, srgr);
332 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, pcr);
336 static int davinci_i2s_hw_params(struct snd_pcm_substream *substream,
337 struct snd_pcm_hw_params *params,
338 struct snd_soc_dai *dai)
340 struct davinci_mcbsp_dev *dev = dai->private_data;
341 struct davinci_pcm_dma_params *dma_params =
342 &dev->dma_params[substream->stream];
343 struct snd_interval *i = NULL;
344 int mcbsp_word_length;
345 unsigned int rcr, xcr, srgr;
348 /* general line settings */
349 spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
350 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
351 spcr |= DAVINCI_MCBSP_SPCR_RINTM(3) | DAVINCI_MCBSP_SPCR_FREE;
352 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
354 spcr |= DAVINCI_MCBSP_SPCR_XINTM(3) | DAVINCI_MCBSP_SPCR_FREE;
355 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
358 i = hw_param_interval(params, SNDRV_PCM_HW_PARAM_SAMPLE_BITS);
359 srgr = DAVINCI_MCBSP_SRGR_FSGM;
360 srgr |= DAVINCI_MCBSP_SRGR_FWID(snd_interval_value(i) - 1);
362 i = hw_param_interval(params, SNDRV_PCM_HW_PARAM_FRAME_BITS);
363 srgr |= DAVINCI_MCBSP_SRGR_FPER(snd_interval_value(i) - 1);
364 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SRGR_REG, srgr);
366 rcr = DAVINCI_MCBSP_RCR_RFIG;
367 xcr = DAVINCI_MCBSP_XCR_XFIG;
368 if (dev->mode == MOD_DSP_B) {
369 rcr |= DAVINCI_MCBSP_RCR_RDATDLY(0);
370 xcr |= DAVINCI_MCBSP_XCR_XDATDLY(0);
372 rcr |= DAVINCI_MCBSP_RCR_RDATDLY(1);
373 xcr |= DAVINCI_MCBSP_XCR_XDATDLY(1);
375 /* Determine xfer data type */
376 switch (params_format(params)) {
377 case SNDRV_PCM_FORMAT_S8:
378 dma_params->data_type = 1;
379 mcbsp_word_length = DAVINCI_MCBSP_WORD_8;
381 case SNDRV_PCM_FORMAT_S16_LE:
382 dma_params->data_type = 2;
383 mcbsp_word_length = DAVINCI_MCBSP_WORD_16;
385 case SNDRV_PCM_FORMAT_S32_LE:
386 dma_params->data_type = 4;
387 mcbsp_word_length = DAVINCI_MCBSP_WORD_32;
390 printk(KERN_WARNING "davinci-i2s: unsupported PCM format\n");
394 dma_params->acnt = dma_params->data_type;
395 dma_params->fifo_level = 0;
397 rcr |= DAVINCI_MCBSP_RCR_RFRLEN1(1);
398 xcr |= DAVINCI_MCBSP_XCR_XFRLEN1(1);
400 rcr |= DAVINCI_MCBSP_RCR_RWDLEN1(mcbsp_word_length) |
401 DAVINCI_MCBSP_RCR_RWDLEN2(mcbsp_word_length);
402 xcr |= DAVINCI_MCBSP_XCR_XWDLEN1(mcbsp_word_length) |
403 DAVINCI_MCBSP_XCR_XWDLEN2(mcbsp_word_length);
405 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
406 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_XCR_REG, xcr);
408 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_RCR_REG, rcr);
412 static int davinci_i2s_prepare(struct snd_pcm_substream *substream,
413 struct snd_soc_dai *dai)
415 struct davinci_mcbsp_dev *dev = dai->private_data;
416 int playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
417 davinci_mcbsp_stop(dev, playback);
418 if ((dev->pcr & DAVINCI_MCBSP_PCR_FSXM) == 0) {
419 /* codec is master */
420 davinci_mcbsp_start(dev, substream);
425 static int davinci_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
426 struct snd_soc_dai *dai)
428 struct davinci_mcbsp_dev *dev = dai->private_data;
430 int playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
431 if ((dev->pcr & DAVINCI_MCBSP_PCR_FSXM) == 0)
432 return 0; /* return if codec is master */
435 case SNDRV_PCM_TRIGGER_START:
436 case SNDRV_PCM_TRIGGER_RESUME:
437 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
438 davinci_mcbsp_start(dev, substream);
440 case SNDRV_PCM_TRIGGER_STOP:
441 case SNDRV_PCM_TRIGGER_SUSPEND:
442 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
443 davinci_mcbsp_stop(dev, playback);
451 static void davinci_i2s_shutdown(struct snd_pcm_substream *substream,
452 struct snd_soc_dai *dai)
454 struct davinci_mcbsp_dev *dev = dai->private_data;
455 int playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
456 davinci_mcbsp_stop(dev, playback);
459 #define DAVINCI_I2S_RATES SNDRV_PCM_RATE_8000_96000
461 static struct snd_soc_dai_ops davinci_i2s_dai_ops = {
462 .shutdown = davinci_i2s_shutdown,
463 .prepare = davinci_i2s_prepare,
464 .trigger = davinci_i2s_trigger,
465 .hw_params = davinci_i2s_hw_params,
466 .set_fmt = davinci_i2s_set_dai_fmt,
470 struct snd_soc_dai davinci_i2s_dai = {
471 .name = "davinci-i2s",
476 .rates = DAVINCI_I2S_RATES,
477 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
481 .rates = DAVINCI_I2S_RATES,
482 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
483 .ops = &davinci_i2s_dai_ops,
486 EXPORT_SYMBOL_GPL(davinci_i2s_dai);
488 static int davinci_i2s_probe(struct platform_device *pdev)
490 struct snd_platform_data *pdata = pdev->dev.platform_data;
491 struct davinci_mcbsp_dev *dev;
492 struct resource *mem, *ioarea, *res;
495 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
497 dev_err(&pdev->dev, "no mem resource?\n");
501 ioarea = request_mem_region(mem->start, (mem->end - mem->start) + 1,
504 dev_err(&pdev->dev, "McBSP region already claimed\n");
508 dev = kzalloc(sizeof(struct davinci_mcbsp_dev), GFP_KERNEL);
511 goto err_release_region;
514 dev->clk = clk_get(&pdev->dev, NULL);
515 if (IS_ERR(dev->clk)) {
519 clk_enable(dev->clk);
521 dev->base = (void __iomem *)IO_ADDRESS(mem->start);
523 dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK].dma_addr =
524 (dma_addr_t)(io_v2p(dev->base) + DAVINCI_MCBSP_DXR_REG);
526 dev->dma_params[SNDRV_PCM_STREAM_CAPTURE].dma_addr =
527 (dma_addr_t)(io_v2p(dev->base) + DAVINCI_MCBSP_DRR_REG);
529 /* first TX, then RX */
530 res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
532 dev_err(&pdev->dev, "no DMA resource\n");
536 dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK].channel = res->start;
538 res = platform_get_resource(pdev, IORESOURCE_DMA, 1);
540 dev_err(&pdev->dev, "no DMA resource\n");
544 dev->dma_params[SNDRV_PCM_STREAM_CAPTURE].channel = res->start;
546 davinci_i2s_dai.private_data = dev;
547 davinci_i2s_dai.dma_data = dev->dma_params;
548 ret = snd_soc_register_dai(&davinci_i2s_dai);
557 release_mem_region(mem->start, (mem->end - mem->start) + 1);
562 static int davinci_i2s_remove(struct platform_device *pdev)
564 struct davinci_mcbsp_dev *dev = davinci_i2s_dai.private_data;
565 struct resource *mem;
567 snd_soc_unregister_dai(&davinci_i2s_dai);
568 clk_disable(dev->clk);
572 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
573 release_mem_region(mem->start, (mem->end - mem->start) + 1);
578 static struct platform_driver davinci_mcbsp_driver = {
579 .probe = davinci_i2s_probe,
580 .remove = davinci_i2s_remove,
582 .name = "davinci-asp",
583 .owner = THIS_MODULE,
587 static int __init davinci_i2s_init(void)
589 return platform_driver_register(&davinci_mcbsp_driver);
591 module_init(davinci_i2s_init);
593 static void __exit davinci_i2s_exit(void)
595 platform_driver_unregister(&davinci_mcbsp_driver);
597 module_exit(davinci_i2s_exit);
599 MODULE_AUTHOR("Vladimir Barinov");
600 MODULE_DESCRIPTION("TI DAVINCI I2S (McBSP) SoC Interface");
601 MODULE_LICENSE("GPL");