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   1 /*
   2  * wm8350.c -- WM8350 ALSA SoC audio driver
   3  *
   4  * Copyright (C) 2007, 2008 Wolfson Microelectronics PLC.
   5  *
   6  * Author: Liam Girdwood <lrg@slimlogic.co.uk>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  */
  12
  13 #include <linux/module.h>
  14 #include <linux/moduleparam.h>
  15 #include <linux/init.h>
  16 #include <linux/delay.h>
  17 #include <linux/pm.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/mfd/wm8350/audio.h>
  20 #include <linux/mfd/wm8350/core.h>
  21 #include <linux/regulator/consumer.h>
  22 #include <sound/core.h>
  23 #include <sound/pcm.h>
  24 #include <sound/pcm_params.h>
  25 #include <sound/soc.h>
  26 #include <sound/soc-dapm.h>
  27 #include <sound/initval.h>
  28 #include <sound/tlv.h>
  29
  30 #include "wm8350.h"
  31
  32 #define WM8350_OUTn_0dB 0x39
  33
  34 #define WM8350_RAMP_NONE        0
  35 #define WM8350_RAMP_UP          1
  36 #define WM8350_RAMP_DOWN        2
  37
  38 /* We only include the analogue supplies here; the digital supplies
  39  * need to be available well before this driver can be probed.
  40  */
  41 static const char *supply_names[] = {
  42         "AVDD",
  43         "HPVDD",
  44 };
  45
  46 struct wm8350_output {
  47         u16 active;
  48         u16 left_vol;
  49         u16 right_vol;
  50         u16 ramp;
  51         u16 mute;
  52 };
  53
  54 struct wm8350_jack_data {
  55         struct snd_soc_jack *jack;
  56         int report;
  57         int short_report;
  58 };
  59
  60 struct wm8350_data {
  61         struct snd_soc_codec codec;
  62         struct wm8350_output out1;
  63         struct wm8350_output out2;
  64         struct wm8350_jack_data hpl;
  65         struct wm8350_jack_data hpr;
  66         struct wm8350_jack_data mic;
  67         struct regulator_bulk_data supplies[ARRAY_SIZE(supply_names)];
  68         int fll_freq_out;
  69         int fll_freq_in;
  70 };
  71
  72 static unsigned int wm8350_codec_cache_read(struct snd_soc_codec *codec,
  73                                             unsigned int reg)
  74 {
  75         struct wm8350 *wm8350 = codec->control_data;
  76         return wm8350->reg_cache[reg];
  77 }
  78
  79 static unsigned int wm8350_codec_read(struct snd_soc_codec *codec,
  80                                       unsigned int reg)
  81 {
  82         struct wm8350 *wm8350 = codec->control_data;
  83         return wm8350_reg_read(wm8350, reg);
  84 }
  85
  86 static int wm8350_codec_write(struct snd_soc_codec *codec, unsigned int reg,
  87                               unsigned int value)
  88 {
  89         struct wm8350 *wm8350 = codec->control_data;
  90         return wm8350_reg_write(wm8350, reg, value);
  91 }
  92
  93 /*
  94  * Ramp OUT1 PGA volume to minimise pops at stream startup and shutdown.
  95  */
  96 static inline int wm8350_out1_ramp_step(struct snd_soc_codec *codec)
  97 {
  98         struct wm8350_data *wm8350_data = snd_soc_codec_get_drvdata(codec);
  99         struct wm8350_output *out1 = &wm8350_data->out1;
 100         struct wm8350 *wm8350 = codec->control_data;
 101         int left_complete = 0, right_complete = 0;
 102         u16 reg, val;
 103
 104         /* left channel */
 105         reg = wm8350_reg_read(wm8350, WM8350_LOUT1_VOLUME);
 106         val = (reg & WM8350_OUT1L_VOL_MASK) >> WM8350_OUT1L_VOL_SHIFT;
 107
 108         if (out1->ramp == WM8350_RAMP_UP) {
 109                 /* ramp step up */
 110                 if (val < out1->left_vol) {
 111                         val++;
 112                         reg &= ~WM8350_OUT1L_VOL_MASK;
 113                         wm8350_reg_write(wm8350, WM8350_LOUT1_VOLUME,
 114                                          reg | (val << WM8350_OUT1L_VOL_SHIFT));
 115                 } else
 116                         left_complete = 1;
 117         } else if (out1->ramp == WM8350_RAMP_DOWN) {
 118                 /* ramp step down */
 119                 if (val > 0) {
 120                         val--;
 121                         reg &= ~WM8350_OUT1L_VOL_MASK;
 122                         wm8350_reg_write(wm8350, WM8350_LOUT1_VOLUME,
 123                                          reg | (val << WM8350_OUT1L_VOL_SHIFT));
 124                 } else
 125                         left_complete = 1;
 126         } else
 127                 return 1;
 128
 129         /* right channel */
 130         reg = wm8350_reg_read(wm8350, WM8350_ROUT1_VOLUME);
 131         val = (reg & WM8350_OUT1R_VOL_MASK) >> WM8350_OUT1R_VOL_SHIFT;
 132         if (out1->ramp == WM8350_RAMP_UP) {
 133                 /* ramp step up */
 134                 if (val < out1->right_vol) {
 135                         val++;
 136                         reg &= ~WM8350_OUT1R_VOL_MASK;
 137                         wm8350_reg_write(wm8350, WM8350_ROUT1_VOLUME,
 138                                          reg | (val << WM8350_OUT1R_VOL_SHIFT));
 139                 } else
 140                         right_complete = 1;
 141         } else if (out1->ramp == WM8350_RAMP_DOWN) {
 142                 /* ramp step down */
 143                 if (val > 0) {
 144                         val--;
 145                         reg &= ~WM8350_OUT1R_VOL_MASK;
 146                         wm8350_reg_write(wm8350, WM8350_ROUT1_VOLUME,
 147                                          reg | (val << WM8350_OUT1R_VOL_SHIFT));
 148                 } else
 149                         right_complete = 1;
 150         }
 151
 152         /* only hit the update bit if either volume has changed this step */
 153         if (!left_complete || !right_complete)
 154                 wm8350_set_bits(wm8350, WM8350_LOUT1_VOLUME, WM8350_OUT1_VU);
 155
 156         return left_complete & right_complete;
 157 }
 158
 159 /*
 160  * Ramp OUT2 PGA volume to minimise pops at stream startup and shutdown.
 161  */
 162 static inline int wm8350_out2_ramp_step(struct snd_soc_codec *codec)
 163 {
 164         struct wm8350_data *wm8350_data = snd_soc_codec_get_drvdata(codec);
 165         struct wm8350_output *out2 = &wm8350_data->out2;
 166         struct wm8350 *wm8350 = codec->control_data;
 167         int left_complete = 0, right_complete = 0;
 168         u16 reg, val;
 169
 170         /* left channel */
 171         reg = wm8350_reg_read(wm8350, WM8350_LOUT2_VOLUME);
 172         val = (reg & WM8350_OUT2L_VOL_MASK) >> WM8350_OUT1L_VOL_SHIFT;
 173         if (out2->ramp == WM8350_RAMP_UP) {
 174                 /* ramp step up */
 175                 if (val < out2->left_vol) {
 176                         val++;
 177                         reg &= ~WM8350_OUT2L_VOL_MASK;
 178                         wm8350_reg_write(wm8350, WM8350_LOUT2_VOLUME,
 179                                          reg | (val << WM8350_OUT1L_VOL_SHIFT));
 180                 } else
 181                         left_complete = 1;
 182         } else if (out2->ramp == WM8350_RAMP_DOWN) {
 183                 /* ramp step down */
 184                 if (val > 0) {
 185                         val--;
 186                         reg &= ~WM8350_OUT2L_VOL_MASK;
 187                         wm8350_reg_write(wm8350, WM8350_LOUT2_VOLUME,
 188                                          reg | (val << WM8350_OUT1L_VOL_SHIFT));
 189                 } else
 190                         left_complete = 1;
 191         } else
 192                 return 1;
 193
 194         /* right channel */
 195         reg = wm8350_reg_read(wm8350, WM8350_ROUT2_VOLUME);
 196         val = (reg & WM8350_OUT2R_VOL_MASK) >> WM8350_OUT1R_VOL_SHIFT;
 197         if (out2->ramp == WM8350_RAMP_UP) {
 198                 /* ramp step up */
 199                 if (val < out2->right_vol) {
 200                         val++;
 201                         reg &= ~WM8350_OUT2R_VOL_MASK;
 202                         wm8350_reg_write(wm8350, WM8350_ROUT2_VOLUME,
 203                                          reg | (val << WM8350_OUT1R_VOL_SHIFT));
 204                 } else
 205                         right_complete = 1;
 206         } else if (out2->ramp == WM8350_RAMP_DOWN) {
 207                 /* ramp step down */
 208                 if (val > 0) {
 209                         val--;
 210                         reg &= ~WM8350_OUT2R_VOL_MASK;
 211                         wm8350_reg_write(wm8350, WM8350_ROUT2_VOLUME,
 212                                          reg | (val << WM8350_OUT1R_VOL_SHIFT));
 213                 } else
 214                         right_complete = 1;
 215         }
 216
 217         /* only hit the update bit if either volume has changed this step */
 218         if (!left_complete || !right_complete)
 219                 wm8350_set_bits(wm8350, WM8350_LOUT2_VOLUME, WM8350_OUT2_VU);
 220
 221         return left_complete & right_complete;
 222 }
 223
 224 /*
 225  * This work ramps both output PGAs at stream start/stop time to
 226  * minimise pop associated with DAPM power switching.
 227  * It's best to enable Zero Cross when ramping occurs to minimise any
 228  * zipper noises.
 229  */
 230 static void wm8350_pga_work(struct work_struct *work)
 231 {
 232         struct snd_soc_codec *codec =
 233             container_of(work, struct snd_soc_codec, delayed_work.work);
 234         struct wm8350_data *wm8350_data = snd_soc_codec_get_drvdata(codec);
 235         struct wm8350_output *out1 = &wm8350_data->out1,
 236             *out2 = &wm8350_data->out2;
 237         int i, out1_complete, out2_complete;
 238
 239         /* do we need to ramp at all ? */
 240         if (out1->ramp == WM8350_RAMP_NONE && out2->ramp == WM8350_RAMP_NONE)
 241                 return;
 242
 243         /* PGA volumes have 6 bits of resolution to ramp */
 244         for (i = 0; i <= 63; i++) {
 245                 out1_complete = 1, out2_complete = 1;
 246                 if (out1->ramp != WM8350_RAMP_NONE)
 247                         out1_complete = wm8350_out1_ramp_step(codec);
 248                 if (out2->ramp != WM8350_RAMP_NONE)
 249                         out2_complete = wm8350_out2_ramp_step(codec);
 250
 251                 /* ramp finished ? */
 252                 if (out1_complete && out2_complete)
 253                         break;
 254
 255                 /* we need to delay longer on the up ramp */
 256                 if (out1->ramp == WM8350_RAMP_UP ||
 257                     out2->ramp == WM8350_RAMP_UP) {
 258                         /* delay is longer over 0dB as increases are larger */
 259                         if (i >= WM8350_OUTn_0dB)
 260                                 schedule_timeout_interruptible(msecs_to_jiffies
 261                                                                (2));
 262                         else
 263                                 schedule_timeout_interruptible(msecs_to_jiffies
 264                                                                (1));
 265                 } else
 266                         udelay(50);     /* doesn't matter if we delay longer */
 267         }
 268
 269         out1->ramp = WM8350_RAMP_NONE;
 270         out2->ramp = WM8350_RAMP_NONE;
 271 }
 272
 273 /*
 274  * WM8350 Controls
 275  */
 276
 277 static int pga_event(struct snd_soc_dapm_widget *w,
 278                      struct snd_kcontrol *kcontrol, int event)
 279 {
 280         struct snd_soc_codec *codec = w->codec;
 281         struct wm8350_data *wm8350_data = snd_soc_codec_get_drvdata(codec);
 282         struct wm8350_output *out;
 283
 284         switch (w->shift) {
 285         case 0:
 286         case 1:
 287                 out = &wm8350_data->out1;
 288                 break;
 289         case 2:
 290         case 3:
 291                 out = &wm8350_data->out2;
 292                 break;
 293
 294         default:
 295                 BUG();
 296                 return -1;
 297         }
 298
 299         switch (event) {
 300         case SND_SOC_DAPM_POST_PMU:
 301                 out->ramp = WM8350_RAMP_UP;
 302                 out->active = 1;
 303
 304                 if (!delayed_work_pending(&codec->delayed_work))
 305                         schedule_delayed_work(&codec->delayed_work,
 306                                               msecs_to_jiffies(1));
 307                 break;
 308
 309         case SND_SOC_DAPM_PRE_PMD:
 310                 out->ramp = WM8350_RAMP_DOWN;
 311                 out->active = 0;
 312
 313                 if (!delayed_work_pending(&codec->delayed_work))
 314                         schedule_delayed_work(&codec->delayed_work,
 315                                               msecs_to_jiffies(1));
 316                 break;
 317         }
 318
 319         return 0;
 320 }
 321
 322 static int wm8350_put_volsw_2r_vu(struct snd_kcontrol *kcontrol,
 323                                   struct snd_ctl_elem_value *ucontrol)
 324 {
 325         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 326         struct wm8350_data *wm8350_priv = snd_soc_codec_get_drvdata(codec);
 327         struct wm8350_output *out = NULL;
 328         struct soc_mixer_control *mc =
 329                 (struct soc_mixer_control *)kcontrol->private_value;
 330         int ret;
 331         unsigned int reg = mc->reg;
 332         u16 val;
 333
 334         /* For OUT1 and OUT2 we shadow the values and only actually write
 335          * them out when active in order to ensure the amplifier comes on
 336          * as quietly as possible. */
 337         switch (reg) {
 338         case WM8350_LOUT1_VOLUME:
 339                 out = &wm8350_priv->out1;
 340                 break;
 341         case WM8350_LOUT2_VOLUME:
 342                 out = &wm8350_priv->out2;
 343                 break;
 344         default:
 345                 break;
 346         }
 347
 348         if (out) {
 349                 out->left_vol = ucontrol->value.integer.value[0];
 350                 out->right_vol = ucontrol->value.integer.value[1];
 351                 if (!out->active)
 352                         return 1;
 353         }
 354
 355         ret = snd_soc_put_volsw_2r(kcontrol, ucontrol);
 356         if (ret < 0)
 357                 return ret;
 358
 359         /* now hit the volume update bits (always bit 8) */
 360         val = wm8350_codec_read(codec, reg);
 361         wm8350_codec_write(codec, reg, val | WM8350_OUT1_VU);
 362         return 1;
 363 }
 364
 365 static int wm8350_get_volsw_2r(struct snd_kcontrol *kcontrol,
 366                                struct snd_ctl_elem_value *ucontrol)
 367 {
 368         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 369         struct wm8350_data *wm8350_priv = snd_soc_codec_get_drvdata(codec);
 370         struct wm8350_output *out1 = &wm8350_priv->out1;
 371         struct wm8350_output *out2 = &wm8350_priv->out2;
 372         struct soc_mixer_control *mc =
 373                 (struct soc_mixer_control *)kcontrol->private_value;
 374         unsigned int reg = mc->reg;
 375
 376         /* If these are cached registers use the cache */
 377         switch (reg) {
 378         case WM8350_LOUT1_VOLUME:
 379                 ucontrol->value.integer.value[0] = out1->left_vol;
 380                 ucontrol->value.integer.value[1] = out1->right_vol;
 381                 return 0;
 382
 383         case WM8350_LOUT2_VOLUME:
 384                 ucontrol->value.integer.value[0] = out2->left_vol;
 385                 ucontrol->value.integer.value[1] = out2->right_vol;
 386                 return 0;
 387
 388         default:
 389                 break;
 390         }
 391
 392         return snd_soc_get_volsw_2r(kcontrol, ucontrol);
 393 }
 394
 395 /* double control with volume update */
 396 #define SOC_WM8350_DOUBLE_R_TLV(xname, reg_left, reg_right, xshift, xmax, \
 397                                 xinvert, tlv_array) \
 398 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
 399         .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ | \
 400                 SNDRV_CTL_ELEM_ACCESS_READWRITE | \
 401                 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
 402         .tlv.p = (tlv_array), \
 403         .info = snd_soc_info_volsw_2r, \
 404         .get = wm8350_get_volsw_2r, .put = wm8350_put_volsw_2r_vu, \
 405         .private_value = (unsigned long)&(struct soc_mixer_control) \
 406                 {.reg = reg_left, .rreg = reg_right, .shift = xshift, \
 407                  .rshift = xshift, .max = xmax, .invert = xinvert}, }
 408
 409 static const char *wm8350_deemp[] = { "None", "32kHz", "44.1kHz", "48kHz" };
 410 static const char *wm8350_pol[] = { "Normal", "Inv R", "Inv L", "Inv L & R" };
 411 static const char *wm8350_dacmutem[] = { "Normal", "Soft" };
 412 static const char *wm8350_dacmutes[] = { "Fast", "Slow" };
 413 static const char *wm8350_adcfilter[] = { "None", "High Pass" };
 414 static const char *wm8350_adchp[] = { "44.1kHz", "8kHz", "16kHz", "32kHz" };
 415 static const char *wm8350_lr[] = { "Left", "Right" };
 416
 417 static const struct soc_enum wm8350_enum[] = {
 418         SOC_ENUM_SINGLE(WM8350_DAC_CONTROL, 4, 4, wm8350_deemp),
 419         SOC_ENUM_SINGLE(WM8350_DAC_CONTROL, 0, 4, wm8350_pol),
 420         SOC_ENUM_SINGLE(WM8350_DAC_MUTE_VOLUME, 14, 2, wm8350_dacmutem),
 421         SOC_ENUM_SINGLE(WM8350_DAC_MUTE_VOLUME, 13, 2, wm8350_dacmutes),
 422         SOC_ENUM_SINGLE(WM8350_ADC_CONTROL, 15, 2, wm8350_adcfilter),
 423         SOC_ENUM_SINGLE(WM8350_ADC_CONTROL, 8, 4, wm8350_adchp),
 424         SOC_ENUM_SINGLE(WM8350_ADC_CONTROL, 0, 4, wm8350_pol),
 425         SOC_ENUM_SINGLE(WM8350_INPUT_MIXER_VOLUME, 15, 2, wm8350_lr),
 426 };
 427
 428 static DECLARE_TLV_DB_LINEAR(pre_amp_tlv, -1200, 3525);
 429 static DECLARE_TLV_DB_LINEAR(out_pga_tlv, -5700, 600);
 430 static DECLARE_TLV_DB_SCALE(dac_pcm_tlv, -7163, 36, 1);
 431 static DECLARE_TLV_DB_SCALE(adc_pcm_tlv, -12700, 50, 1);
 432 static DECLARE_TLV_DB_SCALE(out_mix_tlv, -1500, 300, 1);
 433
 434 static const unsigned int capture_sd_tlv[] = {
 435         TLV_DB_RANGE_HEAD(2),
 436         0, 12, TLV_DB_SCALE_ITEM(-3600, 300, 1),
 437         13, 15, TLV_DB_SCALE_ITEM(0, 0, 0),
 438 };
 439
 440 static const struct snd_kcontrol_new wm8350_snd_controls[] = {
 441         SOC_ENUM("Playback Deemphasis", wm8350_enum[0]),
 442         SOC_ENUM("Playback DAC Inversion", wm8350_enum[1]),
 443         SOC_WM8350_DOUBLE_R_TLV("Playback PCM Volume",
 444                                 WM8350_DAC_DIGITAL_VOLUME_L,
 445                                 WM8350_DAC_DIGITAL_VOLUME_R,
 446                                 0, 255, 0, dac_pcm_tlv),
 447         SOC_ENUM("Playback PCM Mute Function", wm8350_enum[2]),
 448         SOC_ENUM("Playback PCM Mute Speed", wm8350_enum[3]),
 449         SOC_ENUM("Capture PCM Filter", wm8350_enum[4]),
 450         SOC_ENUM("Capture PCM HP Filter", wm8350_enum[5]),
 451         SOC_ENUM("Capture ADC Inversion", wm8350_enum[6]),
 452         SOC_WM8350_DOUBLE_R_TLV("Capture PCM Volume",
 453                                 WM8350_ADC_DIGITAL_VOLUME_L,
 454                                 WM8350_ADC_DIGITAL_VOLUME_R,
 455                                 0, 255, 0, adc_pcm_tlv),
 456         SOC_DOUBLE_TLV("Capture Sidetone Volume",
 457                        WM8350_ADC_DIVIDER,
 458                        8, 4, 15, 1, capture_sd_tlv),
 459         SOC_WM8350_DOUBLE_R_TLV("Capture Volume",
 460                                 WM8350_LEFT_INPUT_VOLUME,
 461                                 WM8350_RIGHT_INPUT_VOLUME,
 462                                 2, 63, 0, pre_amp_tlv),
 463         SOC_DOUBLE_R("Capture ZC Switch",
 464                      WM8350_LEFT_INPUT_VOLUME,
 465                      WM8350_RIGHT_INPUT_VOLUME, 13, 1, 0),
 466         SOC_SINGLE_TLV("Left Input Left Sidetone Volume",
 467                        WM8350_OUTPUT_LEFT_MIXER_VOLUME, 1, 7, 0, out_mix_tlv),
 468         SOC_SINGLE_TLV("Left Input Right Sidetone Volume",
 469                        WM8350_OUTPUT_LEFT_MIXER_VOLUME,
 470                        5, 7, 0, out_mix_tlv),
 471         SOC_SINGLE_TLV("Left Input Bypass Volume",
 472                        WM8350_OUTPUT_LEFT_MIXER_VOLUME,
 473                        9, 7, 0, out_mix_tlv),
 474         SOC_SINGLE_TLV("Right Input Left Sidetone Volume",
 475                        WM8350_OUTPUT_RIGHT_MIXER_VOLUME,
 476                        1, 7, 0, out_mix_tlv),
 477         SOC_SINGLE_TLV("Right Input Right Sidetone Volume",
 478                        WM8350_OUTPUT_RIGHT_MIXER_VOLUME,
 479                        5, 7, 0, out_mix_tlv),
 480         SOC_SINGLE_TLV("Right Input Bypass Volume",
 481                        WM8350_OUTPUT_RIGHT_MIXER_VOLUME,
 482                        13, 7, 0, out_mix_tlv),
 483         SOC_SINGLE("Left Input Mixer +20dB Switch",
 484                    WM8350_INPUT_MIXER_VOLUME_L, 0, 1, 0),
 485         SOC_SINGLE("Right Input Mixer +20dB Switch",
 486                    WM8350_INPUT_MIXER_VOLUME_R, 0, 1, 0),
 487         SOC_SINGLE_TLV("Out4 Capture Volume",
 488                        WM8350_INPUT_MIXER_VOLUME,
 489                        1, 7, 0, out_mix_tlv),
 490         SOC_WM8350_DOUBLE_R_TLV("Out1 Playback Volume",
 491                                 WM8350_LOUT1_VOLUME,
 492                                 WM8350_ROUT1_VOLUME,
 493                                 2, 63, 0, out_pga_tlv),
 494         SOC_DOUBLE_R("Out1 Playback ZC Switch",
 495                      WM8350_LOUT1_VOLUME,
 496                      WM8350_ROUT1_VOLUME, 13, 1, 0),
 497         SOC_WM8350_DOUBLE_R_TLV("Out2 Playback Volume",
 498                                 WM8350_LOUT2_VOLUME,
 499                                 WM8350_ROUT2_VOLUME,
 500                                 2, 63, 0, out_pga_tlv),
 501         SOC_DOUBLE_R("Out2 Playback ZC Switch", WM8350_LOUT2_VOLUME,
 502                      WM8350_ROUT2_VOLUME, 13, 1, 0),
 503         SOC_SINGLE("Out2 Right Invert Switch", WM8350_ROUT2_VOLUME, 10, 1, 0),
 504         SOC_SINGLE_TLV("Out2 Beep Volume", WM8350_BEEP_VOLUME,
 505                        5, 7, 0, out_mix_tlv),
 506
 507         SOC_DOUBLE_R("Out1 Playback Switch",
 508                      WM8350_LOUT1_VOLUME,
 509                      WM8350_ROUT1_VOLUME,
 510                      14, 1, 1),
 511         SOC_DOUBLE_R("Out2 Playback Switch",
 512                      WM8350_LOUT2_VOLUME,
 513                      WM8350_ROUT2_VOLUME,
 514                      14, 1, 1),
 515 };
 516
 517 /*
 518  * DAPM Controls
 519  */
 520
 521 /* Left Playback Mixer */
 522 static const struct snd_kcontrol_new wm8350_left_play_mixer_controls[] = {
 523         SOC_DAPM_SINGLE("Playback Switch",
 524                         WM8350_LEFT_MIXER_CONTROL, 11, 1, 0),
 525         SOC_DAPM_SINGLE("Left Bypass Switch",
 526                         WM8350_LEFT_MIXER_CONTROL, 2, 1, 0),
 527         SOC_DAPM_SINGLE("Right Playback Switch",
 528                         WM8350_LEFT_MIXER_CONTROL, 12, 1, 0),
 529         SOC_DAPM_SINGLE("Left Sidetone Switch",
 530                         WM8350_LEFT_MIXER_CONTROL, 0, 1, 0),
 531         SOC_DAPM_SINGLE("Right Sidetone Switch",
 532                         WM8350_LEFT_MIXER_CONTROL, 1, 1, 0),
 533 };
 534
 535 /* Right Playback Mixer */
 536 static const struct snd_kcontrol_new wm8350_right_play_mixer_controls[] = {
 537         SOC_DAPM_SINGLE("Playback Switch",
 538                         WM8350_RIGHT_MIXER_CONTROL, 12, 1, 0),
 539         SOC_DAPM_SINGLE("Right Bypass Switch",
 540                         WM8350_RIGHT_MIXER_CONTROL, 3, 1, 0),
 541         SOC_DAPM_SINGLE("Left Playback Switch",
 542                         WM8350_RIGHT_MIXER_CONTROL, 11, 1, 0),
 543         SOC_DAPM_SINGLE("Left Sidetone Switch",
 544                         WM8350_RIGHT_MIXER_CONTROL, 0, 1, 0),
 545         SOC_DAPM_SINGLE("Right Sidetone Switch",
 546                         WM8350_RIGHT_MIXER_CONTROL, 1, 1, 0),
 547 };
 548
 549 /* Out4 Mixer */
 550 static const struct snd_kcontrol_new wm8350_out4_mixer_controls[] = {
 551         SOC_DAPM_SINGLE("Right Playback Switch",
 552                         WM8350_OUT4_MIXER_CONTROL, 12, 1, 0),
 553         SOC_DAPM_SINGLE("Left Playback Switch",
 554                         WM8350_OUT4_MIXER_CONTROL, 11, 1, 0),
 555         SOC_DAPM_SINGLE("Right Capture Switch",
 556                         WM8350_OUT4_MIXER_CONTROL, 9, 1, 0),
 557         SOC_DAPM_SINGLE("Out3 Playback Switch",
 558                         WM8350_OUT4_MIXER_CONTROL, 2, 1, 0),
 559         SOC_DAPM_SINGLE("Right Mixer Switch",
 560                         WM8350_OUT4_MIXER_CONTROL, 1, 1, 0),
 561         SOC_DAPM_SINGLE("Left Mixer Switch",
 562                         WM8350_OUT4_MIXER_CONTROL, 0, 1, 0),
 563 };
 564
 565 /* Out3 Mixer */
 566 static const struct snd_kcontrol_new wm8350_out3_mixer_controls[] = {
 567         SOC_DAPM_SINGLE("Left Playback Switch",
 568                         WM8350_OUT3_MIXER_CONTROL, 11, 1, 0),
 569         SOC_DAPM_SINGLE("Left Capture Switch",
 570                         WM8350_OUT3_MIXER_CONTROL, 8, 1, 0),
 571         SOC_DAPM_SINGLE("Out4 Playback Switch",
 572                         WM8350_OUT3_MIXER_CONTROL, 3, 1, 0),
 573         SOC_DAPM_SINGLE("Left Mixer Switch",
 574                         WM8350_OUT3_MIXER_CONTROL, 0, 1, 0),
 575 };
 576
 577 /* Left Input Mixer */
 578 static const struct snd_kcontrol_new wm8350_left_capt_mixer_controls[] = {
 579         SOC_DAPM_SINGLE_TLV("L2 Capture Volume",
 580                             WM8350_INPUT_MIXER_VOLUME_L, 1, 7, 0, out_mix_tlv),
 581         SOC_DAPM_SINGLE_TLV("L3 Capture Volume",
 582                             WM8350_INPUT_MIXER_VOLUME_L, 9, 7, 0, out_mix_tlv),
 583         SOC_DAPM_SINGLE("PGA Capture Switch",
 584                         WM8350_LEFT_INPUT_VOLUME, 14, 1, 1),
 585 };
 586
 587 /* Right Input Mixer */
 588 static const struct snd_kcontrol_new wm8350_right_capt_mixer_controls[] = {
 589         SOC_DAPM_SINGLE_TLV("L2 Capture Volume",
 590                             WM8350_INPUT_MIXER_VOLUME_R, 5, 7, 0, out_mix_tlv),
 591         SOC_DAPM_SINGLE_TLV("L3 Capture Volume",
 592                             WM8350_INPUT_MIXER_VOLUME_R, 13, 7, 0, out_mix_tlv),
 593         SOC_DAPM_SINGLE("PGA Capture Switch",
 594                         WM8350_RIGHT_INPUT_VOLUME, 14, 1, 1),
 595 };
 596
 597 /* Left Mic Mixer */
 598 static const struct snd_kcontrol_new wm8350_left_mic_mixer_controls[] = {
 599         SOC_DAPM_SINGLE("INN Capture Switch", WM8350_INPUT_CONTROL, 1, 1, 0),
 600         SOC_DAPM_SINGLE("INP Capture Switch", WM8350_INPUT_CONTROL, 0, 1, 0),
 601         SOC_DAPM_SINGLE("IN2 Capture Switch", WM8350_INPUT_CONTROL, 2, 1, 0),
 602 };
 603
 604 /* Right Mic Mixer */
 605 static const struct snd_kcontrol_new wm8350_right_mic_mixer_controls[] = {
 606         SOC_DAPM_SINGLE("INN Capture Switch", WM8350_INPUT_CONTROL, 9, 1, 0),
 607         SOC_DAPM_SINGLE("INP Capture Switch", WM8350_INPUT_CONTROL, 8, 1, 0),
 608         SOC_DAPM_SINGLE("IN2 Capture Switch", WM8350_INPUT_CONTROL, 10, 1, 0),
 609 };
 610
 611 /* Beep Switch */
 612 static const struct snd_kcontrol_new wm8350_beep_switch_controls =
 613 SOC_DAPM_SINGLE("Switch", WM8350_BEEP_VOLUME, 15, 1, 1);
 614
 615 /* Out4 Capture Mux */
 616 static const struct snd_kcontrol_new wm8350_out4_capture_controls =
 617 SOC_DAPM_ENUM("Route", wm8350_enum[7]);
 618
 619 static const struct snd_soc_dapm_widget wm8350_dapm_widgets[] = {
 620
 621         SND_SOC_DAPM_PGA("IN3R PGA", WM8350_POWER_MGMT_2, 11, 0, NULL, 0),
 622         SND_SOC_DAPM_PGA("IN3L PGA", WM8350_POWER_MGMT_2, 10, 0, NULL, 0),
 623         SND_SOC_DAPM_PGA_E("Right Out2 PGA", WM8350_POWER_MGMT_3, 3, 0, NULL,
 624                            0, pga_event,
 625                            SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
 626         SND_SOC_DAPM_PGA_E("Left Out2 PGA", WM8350_POWER_MGMT_3, 2, 0, NULL, 0,
 627                            pga_event,
 628                            SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
 629         SND_SOC_DAPM_PGA_E("Right Out1 PGA", WM8350_POWER_MGMT_3, 1, 0, NULL,
 630                            0, pga_event,
 631                            SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
 632         SND_SOC_DAPM_PGA_E("Left Out1 PGA", WM8350_POWER_MGMT_3, 0, 0, NULL, 0,
 633                            pga_event,
 634                            SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
 635
 636         SND_SOC_DAPM_MIXER("Right Capture Mixer", WM8350_POWER_MGMT_2,
 637                            7, 0, &wm8350_right_capt_mixer_controls[0],
 638                            ARRAY_SIZE(wm8350_right_capt_mixer_controls)),
 639
 640         SND_SOC_DAPM_MIXER("Left Capture Mixer", WM8350_POWER_MGMT_2,
 641                            6, 0, &wm8350_left_capt_mixer_controls[0],
 642                            ARRAY_SIZE(wm8350_left_capt_mixer_controls)),
 643
 644         SND_SOC_DAPM_MIXER("Out4 Mixer", WM8350_POWER_MGMT_2, 5, 0,
 645                            &wm8350_out4_mixer_controls[0],
 646                            ARRAY_SIZE(wm8350_out4_mixer_controls)),
 647
 648         SND_SOC_DAPM_MIXER("Out3 Mixer", WM8350_POWER_MGMT_2, 4, 0,
 649                            &wm8350_out3_mixer_controls[0],
 650                            ARRAY_SIZE(wm8350_out3_mixer_controls)),
 651
 652         SND_SOC_DAPM_MIXER("Right Playback Mixer", WM8350_POWER_MGMT_2, 1, 0,
 653                            &wm8350_right_play_mixer_controls[0],
 654                            ARRAY_SIZE(wm8350_right_play_mixer_controls)),
 655
 656         SND_SOC_DAPM_MIXER("Left Playback Mixer", WM8350_POWER_MGMT_2, 0, 0,
 657                            &wm8350_left_play_mixer_controls[0],
 658                            ARRAY_SIZE(wm8350_left_play_mixer_controls)),
 659
 660         SND_SOC_DAPM_MIXER("Left Mic Mixer", WM8350_POWER_MGMT_2, 8, 0,
 661                            &wm8350_left_mic_mixer_controls[0],
 662                            ARRAY_SIZE(wm8350_left_mic_mixer_controls)),
 663
 664         SND_SOC_DAPM_MIXER("Right Mic Mixer", WM8350_POWER_MGMT_2, 9, 0,
 665                            &wm8350_right_mic_mixer_controls[0],
 666                            ARRAY_SIZE(wm8350_right_mic_mixer_controls)),
 667
 668         /* virtual mixer for Beep and Out2R */
 669         SND_SOC_DAPM_MIXER("Out2 Mixer", SND_SOC_NOPM, 0, 0, NULL, 0),
 670
 671         SND_SOC_DAPM_SWITCH("Beep", WM8350_POWER_MGMT_3, 7, 0,
 672                             &wm8350_beep_switch_controls),
 673
 674         SND_SOC_DAPM_ADC("Right ADC", "Right Capture",
 675                          WM8350_POWER_MGMT_4, 3, 0),
 676         SND_SOC_DAPM_ADC("Left ADC", "Left Capture",
 677                          WM8350_POWER_MGMT_4, 2, 0),
 678         SND_SOC_DAPM_DAC("Right DAC", "Right Playback",
 679                          WM8350_POWER_MGMT_4, 5, 0),
 680         SND_SOC_DAPM_DAC("Left DAC", "Left Playback",
 681                          WM8350_POWER_MGMT_4, 4, 0),
 682
 683         SND_SOC_DAPM_MICBIAS("Mic Bias", WM8350_POWER_MGMT_1, 4, 0),
 684
 685         SND_SOC_DAPM_MUX("Out4 Capture Channel", SND_SOC_NOPM, 0, 0,
 686                          &wm8350_out4_capture_controls),
 687
 688         SND_SOC_DAPM_OUTPUT("OUT1R"),
 689         SND_SOC_DAPM_OUTPUT("OUT1L"),
 690         SND_SOC_DAPM_OUTPUT("OUT2R"),
 691         SND_SOC_DAPM_OUTPUT("OUT2L"),
 692         SND_SOC_DAPM_OUTPUT("OUT3"),
 693         SND_SOC_DAPM_OUTPUT("OUT4"),
 694
 695         SND_SOC_DAPM_INPUT("IN1RN"),
 696         SND_SOC_DAPM_INPUT("IN1RP"),
 697         SND_SOC_DAPM_INPUT("IN2R"),
 698         SND_SOC_DAPM_INPUT("IN1LP"),
 699         SND_SOC_DAPM_INPUT("IN1LN"),
 700         SND_SOC_DAPM_INPUT("IN2L"),
 701         SND_SOC_DAPM_INPUT("IN3R"),
 702         SND_SOC_DAPM_INPUT("IN3L"),
 703 };
 704
 705 static const struct snd_soc_dapm_route audio_map[] = {
 706
 707         /* left playback mixer */
 708         {"Left Playback Mixer", "Playback Switch", "Left DAC"},
 709         {"Left Playback Mixer", "Left Bypass Switch", "IN3L PGA"},
 710         {"Left Playback Mixer", "Right Playback Switch", "Right DAC"},
 711         {"Left Playback Mixer", "Left Sidetone Switch", "Left Mic Mixer"},
 712         {"Left Playback Mixer", "Right Sidetone Switch", "Right Mic Mixer"},
 713
 714         /* right playback mixer */
 715         {"Right Playback Mixer", "Playback Switch", "Right DAC"},
 716         {"Right Playback Mixer", "Right Bypass Switch", "IN3R PGA"},
 717         {"Right Playback Mixer", "Left Playback Switch", "Left DAC"},
 718         {"Right Playback Mixer", "Left Sidetone Switch", "Left Mic Mixer"},
 719         {"Right Playback Mixer", "Right Sidetone Switch", "Right Mic Mixer"},
 720
 721         /* out4 playback mixer */
 722         {"Out4 Mixer", "Right Playback Switch", "Right DAC"},
 723         {"Out4 Mixer", "Left Playback Switch", "Left DAC"},
 724         {"Out4 Mixer", "Right Capture Switch", "Right Capture Mixer"},
 725         {"Out4 Mixer", "Out3 Playback Switch", "Out3 Mixer"},
 726         {"Out4 Mixer", "Right Mixer Switch", "Right Playback Mixer"},
 727         {"Out4 Mixer", "Left Mixer Switch", "Left Playback Mixer"},
 728         {"OUT4", NULL, "Out4 Mixer"},
 729
 730         /* out3 playback mixer */
 731         {"Out3 Mixer", "Left Playback Switch", "Left DAC"},
 732         {"Out3 Mixer", "Left Capture Switch", "Left Capture Mixer"},
 733         {"Out3 Mixer", "Left Mixer Switch", "Left Playback Mixer"},
 734         {"Out3 Mixer", "Out4 Playback Switch", "Out4 Mixer"},
 735         {"OUT3", NULL, "Out3 Mixer"},
 736
 737         /* out2 */
 738         {"Right Out2 PGA", NULL, "Right Playback Mixer"},
 739         {"Left Out2 PGA", NULL, "Left Playback Mixer"},
 740         {"OUT2L", NULL, "Left Out2 PGA"},
 741         {"OUT2R", NULL, "Right Out2 PGA"},
 742
 743         /* out1 */
 744         {"Right Out1 PGA", NULL, "Right Playback Mixer"},
 745         {"Left Out1 PGA", NULL, "Left Playback Mixer"},
 746         {"OUT1L", NULL, "Left Out1 PGA"},
 747         {"OUT1R", NULL, "Right Out1 PGA"},
 748
 749         /* ADCs */
 750         {"Left ADC", NULL, "Left Capture Mixer"},
 751         {"Right ADC", NULL, "Right Capture Mixer"},
 752
 753         /* Left capture mixer */
 754         {"Left Capture Mixer", "L2 Capture Volume", "IN2L"},
 755         {"Left Capture Mixer", "L3 Capture Volume", "IN3L PGA"},
 756         {"Left Capture Mixer", "PGA Capture Switch", "Left Mic Mixer"},
 757         {"Left Capture Mixer", NULL, "Out4 Capture Channel"},
 758
 759         /* Right capture mixer */
 760         {"Right Capture Mixer", "L2 Capture Volume", "IN2R"},
 761         {"Right Capture Mixer", "L3 Capture Volume", "IN3R PGA"},
 762         {"Right Capture Mixer", "PGA Capture Switch", "Right Mic Mixer"},
 763         {"Right Capture Mixer", NULL, "Out4 Capture Channel"},
 764
 765         /* L3 Inputs */
 766         {"IN3L PGA", NULL, "IN3L"},
 767         {"IN3R PGA", NULL, "IN3R"},
 768
 769         /* Left Mic mixer */
 770         {"Left Mic Mixer", "INN Capture Switch", "IN1LN"},
 771         {"Left Mic Mixer", "INP Capture Switch", "IN1LP"},
 772         {"Left Mic Mixer", "IN2 Capture Switch", "IN2L"},
 773
 774         /* Right Mic mixer */
 775         {"Right Mic Mixer", "INN Capture Switch", "IN1RN"},
 776         {"Right Mic Mixer", "INP Capture Switch", "IN1RP"},
 777         {"Right Mic Mixer", "IN2 Capture Switch", "IN2R"},
 778
 779         /* out 4 capture */
 780         {"Out4 Capture Channel", NULL, "Out4 Mixer"},
 781
 782         /* Beep */
 783         {"Beep", NULL, "IN3R PGA"},
 784 };
 785
 786 static int wm8350_add_widgets(struct snd_soc_codec *codec)
 787 {
 788         int ret;
 789
 790         ret = snd_soc_dapm_new_controls(codec,
 791                                         wm8350_dapm_widgets,
 792                                         ARRAY_SIZE(wm8350_dapm_widgets));
 793         if (ret != 0) {
 794                 dev_err(codec->dev, "dapm control register failed\n");
 795                 return ret;
 796         }
 797
 798         /* set up audio paths */
 799         ret = snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map));
 800         if (ret != 0) {
 801                 dev_err(codec->dev, "DAPM route register failed\n");
 802                 return ret;
 803         }
 804
 805         return 0;
 806 }
 807
 808 static int wm8350_set_dai_sysclk(struct snd_soc_dai *codec_dai,
 809                                  int clk_id, unsigned int freq, int dir)
 810 {
 811         struct snd_soc_codec *codec = codec_dai->codec;
 812         struct wm8350 *wm8350 = codec->control_data;
 813         u16 fll_4;
 814
 815         switch (clk_id) {
 816         case WM8350_MCLK_SEL_MCLK:
 817                 wm8350_clear_bits(wm8350, WM8350_CLOCK_CONTROL_1,
 818                                   WM8350_MCLK_SEL);
 819                 break;
 820         case WM8350_MCLK_SEL_PLL_MCLK:
 821         case WM8350_MCLK_SEL_PLL_DAC:
 822         case WM8350_MCLK_SEL_PLL_ADC:
 823         case WM8350_MCLK_SEL_PLL_32K:
 824                 wm8350_set_bits(wm8350, WM8350_CLOCK_CONTROL_1,
 825                                 WM8350_MCLK_SEL);
 826                 fll_4 = wm8350_codec_read(codec, WM8350_FLL_CONTROL_4) &
 827                     ~WM8350_FLL_CLK_SRC_MASK;
 828                 wm8350_codec_write(codec, WM8350_FLL_CONTROL_4, fll_4 | clk_id);
 829                 break;
 830         }
 831
 832         /* MCLK direction */
 833         if (dir == WM8350_MCLK_DIR_OUT)
 834                 wm8350_set_bits(wm8350, WM8350_CLOCK_CONTROL_2,
 835                                 WM8350_MCLK_DIR);
 836         else
 837                 wm8350_clear_bits(wm8350, WM8350_CLOCK_CONTROL_2,
 838                                   WM8350_MCLK_DIR);
 839
 840         return 0;
 841 }
 842
 843 static int wm8350_set_clkdiv(struct snd_soc_dai *codec_dai, int div_id, int div)
 844 {
 845         struct snd_soc_codec *codec = codec_dai->codec;
 846         u16 val;
 847
 848         switch (div_id) {
 849         case WM8350_ADC_CLKDIV:
 850                 val = wm8350_codec_read(codec, WM8350_ADC_DIVIDER) &
 851                     ~WM8350_ADC_CLKDIV_MASK;
 852                 wm8350_codec_write(codec, WM8350_ADC_DIVIDER, val | div);
 853                 break;
 854         case WM8350_DAC_CLKDIV:
 855                 val = wm8350_codec_read(codec, WM8350_DAC_CLOCK_CONTROL) &
 856                     ~WM8350_DAC_CLKDIV_MASK;
 857                 wm8350_codec_write(codec, WM8350_DAC_CLOCK_CONTROL, val | div);
 858                 break;
 859         case WM8350_BCLK_CLKDIV:
 860                 val = wm8350_codec_read(codec, WM8350_CLOCK_CONTROL_1) &
 861                     ~WM8350_BCLK_DIV_MASK;
 862                 wm8350_codec_write(codec, WM8350_CLOCK_CONTROL_1, val | div);
 863                 break;
 864         case WM8350_OPCLK_CLKDIV:
 865                 val = wm8350_codec_read(codec, WM8350_CLOCK_CONTROL_1) &
 866                     ~WM8350_OPCLK_DIV_MASK;
 867                 wm8350_codec_write(codec, WM8350_CLOCK_CONTROL_1, val | div);
 868                 break;
 869         case WM8350_SYS_CLKDIV:
 870                 val = wm8350_codec_read(codec, WM8350_CLOCK_CONTROL_1) &
 871                     ~WM8350_MCLK_DIV_MASK;
 872                 wm8350_codec_write(codec, WM8350_CLOCK_CONTROL_1, val | div);
 873                 break;
 874         case WM8350_DACLR_CLKDIV:
 875                 val = wm8350_codec_read(codec, WM8350_DAC_LR_RATE) &
 876                     ~WM8350_DACLRC_RATE_MASK;
 877                 wm8350_codec_write(codec, WM8350_DAC_LR_RATE, val | div);
 878                 break;
 879         case WM8350_ADCLR_CLKDIV:
 880                 val = wm8350_codec_read(codec, WM8350_ADC_LR_RATE) &
 881                     ~WM8350_ADCLRC_RATE_MASK;
 882                 wm8350_codec_write(codec, WM8350_ADC_LR_RATE, val | div);
 883                 break;
 884         default:
 885                 return -EINVAL;
 886         }
 887
 888         return 0;
 889 }
 890
 891 static int wm8350_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
 892 {
 893         struct snd_soc_codec *codec = codec_dai->codec;
 894         u16 iface = wm8350_codec_read(codec, WM8350_AI_FORMATING) &
 895             ~(WM8350_AIF_BCLK_INV | WM8350_AIF_LRCLK_INV | WM8350_AIF_FMT_MASK);
 896         u16 master = wm8350_codec_read(codec, WM8350_AI_DAC_CONTROL) &
 897             ~WM8350_BCLK_MSTR;
 898         u16 dac_lrc = wm8350_codec_read(codec, WM8350_DAC_LR_RATE) &
 899             ~WM8350_DACLRC_ENA;
 900         u16 adc_lrc = wm8350_codec_read(codec, WM8350_ADC_LR_RATE) &
 901             ~WM8350_ADCLRC_ENA;
 902
 903         /* set master/slave audio interface */
 904         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
 905         case SND_SOC_DAIFMT_CBM_CFM:
 906                 master |= WM8350_BCLK_MSTR;
 907                 dac_lrc |= WM8350_DACLRC_ENA;
 908                 adc_lrc |= WM8350_ADCLRC_ENA;
 909                 break;
 910         case SND_SOC_DAIFMT_CBS_CFS:
 911                 break;
 912         default:
 913                 return -EINVAL;
 914         }
 915
 916         /* interface format */
 917         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 918         case SND_SOC_DAIFMT_I2S:
 919                 iface |= 0x2 << 8;
 920                 break;
 921         case SND_SOC_DAIFMT_RIGHT_J:
 922                 break;
 923         case SND_SOC_DAIFMT_LEFT_J:
 924                 iface |= 0x1 << 8;
 925                 break;
 926         case SND_SOC_DAIFMT_DSP_A:
 927                 iface |= 0x3 << 8;
 928                 break;
 929         case SND_SOC_DAIFMT_DSP_B:
 930                 iface |= 0x3 << 8 | WM8350_AIF_LRCLK_INV;
 931                 break;
 932         default:
 933                 return -EINVAL;
 934         }
 935
 936         /* clock inversion */
 937         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
 938         case SND_SOC_DAIFMT_NB_NF:
 939                 break;
 940         case SND_SOC_DAIFMT_IB_IF:
 941                 iface |= WM8350_AIF_LRCLK_INV | WM8350_AIF_BCLK_INV;
 942                 break;
 943         case SND_SOC_DAIFMT_IB_NF:
 944                 iface |= WM8350_AIF_BCLK_INV;
 945                 break;
 946         case SND_SOC_DAIFMT_NB_IF:
 947                 iface |= WM8350_AIF_LRCLK_INV;
 948                 break;
 949         default:
 950                 return -EINVAL;
 951         }
 952
 953         wm8350_codec_write(codec, WM8350_AI_FORMATING, iface);
 954         wm8350_codec_write(codec, WM8350_AI_DAC_CONTROL, master);
 955         wm8350_codec_write(codec, WM8350_DAC_LR_RATE, dac_lrc);
 956         wm8350_codec_write(codec, WM8350_ADC_LR_RATE, adc_lrc);
 957         return 0;
 958 }
 959
 960 static int wm8350_pcm_trigger(struct snd_pcm_substream *substream,
 961                               int cmd, struct snd_soc_dai *codec_dai)
 962 {
 963         struct snd_soc_codec *codec = codec_dai->codec;
 964         int master = wm8350_codec_cache_read(codec, WM8350_AI_DAC_CONTROL) &
 965             WM8350_BCLK_MSTR;
 966         int enabled = 0;
 967
 968         /* Check that the DACs or ADCs are enabled since they are
 969          * required for LRC in master mode. The DACs or ADCs need a
 970          * valid audio path i.e. pin -> ADC or DAC -> pin before
 971          * the LRC will be enabled in master mode. */
 972         if (!master || cmd != SNDRV_PCM_TRIGGER_START)
 973                 return 0;
 974
 975         if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
 976                 enabled = wm8350_codec_cache_read(codec, WM8350_POWER_MGMT_4) &
 977                     (WM8350_ADCR_ENA | WM8350_ADCL_ENA);
 978         } else {
 979                 enabled = wm8350_codec_cache_read(codec, WM8350_POWER_MGMT_4) &
 980                     (WM8350_DACR_ENA | WM8350_DACL_ENA);
 981         }
 982
 983         if (!enabled) {
 984                 dev_err(codec->dev,
 985                        "%s: invalid audio path - no clocks available\n",
 986                        __func__);
 987                 return -EINVAL;
 988         }
 989         return 0;
 990 }
 991
 992 static int wm8350_pcm_hw_params(struct snd_pcm_substream *substream,
 993                                 struct snd_pcm_hw_params *params,
 994                                 struct snd_soc_dai *codec_dai)
 995 {
 996         struct snd_soc_codec *codec = codec_dai->codec;
 997         struct wm8350 *wm8350 = codec->control_data;
 998         u16 iface = wm8350_codec_read(codec, WM8350_AI_FORMATING) &
 999             ~WM8350_AIF_WL_MASK;
1000
1001         /* bit size */
1002         switch (params_format(params)) {
1003         case SNDRV_PCM_FORMAT_S16_LE:
1004                 break;
1005         case SNDRV_PCM_FORMAT_S20_3LE:
1006                 iface |= 0x1 << 10;
1007                 break;
1008         case SNDRV_PCM_FORMAT_S24_LE:
1009                 iface |= 0x2 << 10;
1010                 break;
1011         case SNDRV_PCM_FORMAT_S32_LE:
1012                 iface |= 0x3 << 10;
1013                 break;
1014         }
1015
1016         wm8350_codec_write(codec, WM8350_AI_FORMATING, iface);
1017
1018         /* The sloping stopband filter is recommended for use with
1019          * lower sample rates to improve performance.
1020          */
1021         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1022                 if (params_rate(params) < 24000)
1023                         wm8350_set_bits(wm8350, WM8350_DAC_MUTE_VOLUME,
1024                                         WM8350_DAC_SB_FILT);
1025                 else
1026                         wm8350_clear_bits(wm8350, WM8350_DAC_MUTE_VOLUME,
1027                                           WM8350_DAC_SB_FILT);
1028         }
1029
1030         return 0;
1031 }
1032
1033 static int wm8350_mute(struct snd_soc_dai *dai, int mute)
1034 {
1035         struct snd_soc_codec *codec = dai->codec;
1036         struct wm8350 *wm8350 = codec->control_data;
1037
1038         if (mute)
1039                 wm8350_set_bits(wm8350, WM8350_DAC_MUTE, WM8350_DAC_MUTE_ENA);
1040         else
1041                 wm8350_clear_bits(wm8350, WM8350_DAC_MUTE, WM8350_DAC_MUTE_ENA);
1042         return 0;
1043 }
1044
1045 /* FLL divisors */
1046 struct _fll_div {
1047         int div;                /* FLL_OUTDIV */
1048         int n;
1049         int k;
1050         int ratio;              /* FLL_FRATIO */
1051 };
1052
1053 /* The size in bits of the fll divide multiplied by 10
1054  * to allow rounding later */
1055 #define FIXED_FLL_SIZE ((1 << 16) * 10)
1056
1057 static inline int fll_factors(struct _fll_div *fll_div, unsigned int input,
1058                               unsigned int output)
1059 {
1060         u64 Kpart;
1061         unsigned int t1, t2, K, Nmod;
1062
1063         if (output >= 2815250 && output <= 3125000)
1064                 fll_div->div = 0x4;
1065         else if (output >= 5625000 && output <= 6250000)
1066                 fll_div->div = 0x3;
1067         else if (output >= 11250000 && output <= 12500000)
1068                 fll_div->div = 0x2;
1069         else if (output >= 22500000 && output <= 25000000)
1070                 fll_div->div = 0x1;
1071         else {
1072                 printk(KERN_ERR "wm8350: fll freq %d out of range\n", output);
1073                 return -EINVAL;
1074         }
1075
1076         if (input > 48000)
1077                 fll_div->ratio = 1;
1078         else
1079                 fll_div->ratio = 8;
1080
1081         t1 = output * (1 << (fll_div->div + 1));
1082         t2 = input * fll_div->ratio;
1083
1084         fll_div->n = t1 / t2;
1085         Nmod = t1 % t2;
1086
1087         if (Nmod) {
1088                 Kpart = FIXED_FLL_SIZE * (long long)Nmod;
1089                 do_div(Kpart, t2);
1090                 K = Kpart & 0xFFFFFFFF;
1091
1092                 /* Check if we need to round */
1093                 if ((K % 10) >= 5)
1094                         K += 5;
1095
1096                 /* Move down to proper range now rounding is done */
1097                 K /= 10;
1098                 fll_div->k = K;
1099         } else
1100                 fll_div->k = 0;
1101
1102         return 0;
1103 }
1104
1105 static int wm8350_set_fll(struct snd_soc_dai *codec_dai,
1106                           int pll_id, int source, unsigned int freq_in,
1107                           unsigned int freq_out)
1108 {
1109         struct snd_soc_codec *codec = codec_dai->codec;
1110         struct wm8350 *wm8350 = codec->control_data;
1111         struct wm8350_data *priv = snd_soc_codec_get_drvdata(codec);
1112         struct _fll_div fll_div;
1113         int ret = 0;
1114         u16 fll_1, fll_4;
1115
1116         if (freq_in == priv->fll_freq_in && freq_out == priv->fll_freq_out)
1117                 return 0;
1118
1119         /* power down FLL - we need to do this for reconfiguration */
1120         wm8350_clear_bits(wm8350, WM8350_POWER_MGMT_4,
1121                           WM8350_FLL_ENA | WM8350_FLL_OSC_ENA);
1122
1123         if (freq_out == 0 || freq_in == 0)
1124                 return ret;
1125
1126         ret = fll_factors(&fll_div, freq_in, freq_out);
1127         if (ret < 0)
1128                 return ret;
1129         dev_dbg(wm8350->dev,
1130                 "FLL in %u FLL out %u N 0x%x K 0x%x div %d ratio %d",
1131                 freq_in, freq_out, fll_div.n, fll_div.k, fll_div.div,
1132                 fll_div.ratio);
1133
1134         /* set up N.K & dividers */
1135         fll_1 = wm8350_codec_read(codec, WM8350_FLL_CONTROL_1) &
1136             ~(WM8350_FLL_OUTDIV_MASK | WM8350_FLL_RSP_RATE_MASK | 0xc000);
1137         wm8350_codec_write(codec, WM8350_FLL_CONTROL_1,
1138                            fll_1 | (fll_div.div << 8) | 0x50);
1139         wm8350_codec_write(codec, WM8350_FLL_CONTROL_2,
1140                            (fll_div.ratio << 11) | (fll_div.
1141                                                     n & WM8350_FLL_N_MASK));
1142         wm8350_codec_write(codec, WM8350_FLL_CONTROL_3, fll_div.k);
1143         fll_4 = wm8350_codec_read(codec, WM8350_FLL_CONTROL_4) &
1144             ~(WM8350_FLL_FRAC | WM8350_FLL_SLOW_LOCK_REF);
1145         wm8350_codec_write(codec, WM8350_FLL_CONTROL_4,
1146                            fll_4 | (fll_div.k ? WM8350_FLL_FRAC : 0) |
1147                            (fll_div.ratio == 8 ? WM8350_FLL_SLOW_LOCK_REF : 0));
1148
1149         /* power FLL on */
1150         wm8350_set_bits(wm8350, WM8350_POWER_MGMT_4, WM8350_FLL_OSC_ENA);
1151         wm8350_set_bits(wm8350, WM8350_POWER_MGMT_4, WM8350_FLL_ENA);
1152
1153         priv->fll_freq_out = freq_out;
1154         priv->fll_freq_in = freq_in;
1155
1156         return 0;
1157 }
1158
1159 static int wm8350_set_bias_level(struct snd_soc_codec *codec,
1160                                  enum snd_soc_bias_level level)
1161 {
1162         struct wm8350 *wm8350 = codec->control_data;
1163         struct wm8350_data *priv = snd_soc_codec_get_drvdata(codec);
1164         struct wm8350_audio_platform_data *platform =
1165                 wm8350->codec.platform_data;
1166         u16 pm1;
1167         int ret;
1168
1169         switch (level) {
1170         case SND_SOC_BIAS_ON:
1171                 pm1 = wm8350_reg_read(wm8350, WM8350_POWER_MGMT_1) &
1172                     ~(WM8350_VMID_MASK | WM8350_CODEC_ISEL_MASK);
1173                 wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1,
1174                                  pm1 | WM8350_VMID_50K |
1175                                  platform->codec_current_on << 14);
1176                 break;
1177
1178         case SND_SOC_BIAS_PREPARE:
1179                 pm1 = wm8350_reg_read(wm8350, WM8350_POWER_MGMT_1);
1180                 pm1 &= ~WM8350_VMID_MASK;
1181                 wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1,
1182                                  pm1 | WM8350_VMID_50K);
1183                 break;
1184
1185         case SND_SOC_BIAS_STANDBY:
1186                 if (codec->bias_level == SND_SOC_BIAS_OFF) {
1187                         ret = regulator_bulk_enable(ARRAY_SIZE(priv->supplies),
1188                                                     priv->supplies);
1189                         if (ret != 0)
1190                                 return ret;
1191
1192                         /* Enable the system clock */
1193                         wm8350_set_bits(wm8350, WM8350_POWER_MGMT_4,
1194                                         WM8350_SYSCLK_ENA);
1195
1196                         /* mute DAC & outputs */
1197                         wm8350_set_bits(wm8350, WM8350_DAC_MUTE,
1198                                         WM8350_DAC_MUTE_ENA);
1199
1200                         /* discharge cap memory */
1201                         wm8350_reg_write(wm8350, WM8350_ANTI_POP_CONTROL,
1202                                          platform->dis_out1 |
1203                                          (platform->dis_out2 << 2) |
1204                                          (platform->dis_out3 << 4) |
1205                                          (platform->dis_out4 << 6));
1206
1207                         /* wait for discharge */
1208                         schedule_timeout_interruptible(msecs_to_jiffies
1209                                                        (platform->
1210                                                         cap_discharge_msecs));
1211
1212                         /* enable antipop */
1213                         wm8350_reg_write(wm8350, WM8350_ANTI_POP_CONTROL,
1214                                          (platform->vmid_s_curve << 8));
1215
1216                         /* ramp up vmid */
1217                         wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1,
1218                                          (platform->
1219                                           codec_current_charge << 14) |
1220                                          WM8350_VMID_5K | WM8350_VMIDEN |
1221                                          WM8350_VBUFEN);
1222
1223                         /* wait for vmid */
1224                         schedule_timeout_interruptible(msecs_to_jiffies
1225                                                        (platform->
1226                                                         vmid_charge_msecs));
1227
1228                         /* turn on vmid 300k  */
1229                         pm1 = wm8350_reg_read(wm8350, WM8350_POWER_MGMT_1) &
1230                             ~(WM8350_VMID_MASK | WM8350_CODEC_ISEL_MASK);
1231                         pm1 |= WM8350_VMID_300K |
1232                                 (platform->codec_current_standby << 14);
1233                         wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1,
1234                                          pm1);
1235
1236
1237                         /* enable analogue bias */
1238                         pm1 |= WM8350_BIASEN;
1239                         wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1, pm1);
1240
1241                         /* disable antipop */
1242                         wm8350_reg_write(wm8350, WM8350_ANTI_POP_CONTROL, 0);
1243
1244                 } else {
1245                         /* turn on vmid 300k and reduce current */
1246                         pm1 = wm8350_reg_read(wm8350, WM8350_POWER_MGMT_1) &
1247                             ~(WM8350_VMID_MASK | WM8350_CODEC_ISEL_MASK);
1248                         wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1,
1249                                          pm1 | WM8350_VMID_300K |
1250                                          (platform->
1251                                           codec_current_standby << 14));
1252
1253                 }
1254                 break;
1255
1256         case SND_SOC_BIAS_OFF:
1257
1258                 /* mute DAC & enable outputs */
1259                 wm8350_set_bits(wm8350, WM8350_DAC_MUTE, WM8350_DAC_MUTE_ENA);
1260
1261                 wm8350_set_bits(wm8350, WM8350_POWER_MGMT_3,
1262                                 WM8350_OUT1L_ENA | WM8350_OUT1R_ENA |
1263                                 WM8350_OUT2L_ENA | WM8350_OUT2R_ENA);
1264
1265                 /* enable anti pop S curve */
1266                 wm8350_reg_write(wm8350, WM8350_ANTI_POP_CONTROL,
1267                                  (platform->vmid_s_curve << 8));
1268
1269                 /* turn off vmid  */
1270                 pm1 = wm8350_reg_read(wm8350, WM8350_POWER_MGMT_1) &
1271                     ~WM8350_VMIDEN;
1272                 wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1, pm1);
1273
1274                 /* wait */
1275                 schedule_timeout_interruptible(msecs_to_jiffies
1276                                                (platform->
1277                                                 vmid_discharge_msecs));
1278
1279                 wm8350_reg_write(wm8350, WM8350_ANTI_POP_CONTROL,
1280                                  (platform->vmid_s_curve << 8) |
1281                                  platform->dis_out1 |
1282                                  (platform->dis_out2 << 2) |
1283                                  (platform->dis_out3 << 4) |
1284                                  (platform->dis_out4 << 6));
1285
1286                 /* turn off VBuf and drain */
1287                 pm1 = wm8350_reg_read(wm8350, WM8350_POWER_MGMT_1) &
1288                     ~(WM8350_VBUFEN | WM8350_VMID_MASK);
1289                 wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1,
1290                                  pm1 | WM8350_OUTPUT_DRAIN_EN);
1291
1292                 /* wait */
1293                 schedule_timeout_interruptible(msecs_to_jiffies
1294                                                (platform->drain_msecs));
1295
1296                 pm1 &= ~WM8350_BIASEN;
1297                 wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1, pm1);
1298
1299                 /* disable anti-pop */
1300                 wm8350_reg_write(wm8350, WM8350_ANTI_POP_CONTROL, 0);
1301
1302                 wm8350_clear_bits(wm8350, WM8350_LOUT1_VOLUME,
1303                                   WM8350_OUT1L_ENA);
1304                 wm8350_clear_bits(wm8350, WM8350_ROUT1_VOLUME,
1305                                   WM8350_OUT1R_ENA);
1306                 wm8350_clear_bits(wm8350, WM8350_LOUT2_VOLUME,
1307                                   WM8350_OUT2L_ENA);
1308                 wm8350_clear_bits(wm8350, WM8350_ROUT2_VOLUME,
1309                                   WM8350_OUT2R_ENA);
1310
1311                 /* disable clock gen */
1312                 wm8350_clear_bits(wm8350, WM8350_POWER_MGMT_4,
1313                                   WM8350_SYSCLK_ENA);
1314
1315                 regulator_bulk_disable(ARRAY_SIZE(priv->supplies),
1316                                        priv->supplies);
1317                 break;
1318         }
1319         codec->bias_level = level;
1320         return 0;
1321 }
1322
1323 static int wm8350_suspend(struct platform_device *pdev, pm_message_t state)
1324 {
1325         struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1326         struct snd_soc_codec *codec = socdev->card->codec;
1327
1328         wm8350_set_bias_level(codec, SND_SOC_BIAS_OFF);
1329         return 0;
1330 }
1331
1332 static int wm8350_resume(struct platform_device *pdev)
1333 {
1334         struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1335         struct snd_soc_codec *codec = socdev->card->codec;
1336
1337         wm8350_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1338
1339         return 0;
1340 }
1341
1342 static irqreturn_t wm8350_hp_jack_handler(int irq, void *data)
1343 {
1344         struct wm8350_data *priv = data;
1345         struct wm8350 *wm8350 = priv->codec.control_data;
1346         u16 reg;
1347         int report;
1348         int mask;
1349         struct wm8350_jack_data *jack = NULL;
1350
1351         switch (irq - wm8350->irq_base) {
1352         case WM8350_IRQ_CODEC_JCK_DET_L:
1353                 jack = &priv->hpl;
1354                 mask = WM8350_JACK_L_LVL;
1355                 break;
1356
1357         case WM8350_IRQ_CODEC_JCK_DET_R:
1358                 jack = &priv->hpr;
1359                 mask = WM8350_JACK_R_LVL;
1360                 break;
1361
1362         default:
1363                 BUG();
1364         }
1365
1366         if (!jack->jack) {
1367                 dev_warn(wm8350->dev, "Jack interrupt called with no jack\n");
1368                 return IRQ_NONE;
1369         }
1370
1371         /* Debounce */
1372         msleep(200);
1373
1374         reg = wm8350_reg_read(wm8350, WM8350_JACK_PIN_STATUS);
1375         if (reg & mask)
1376                 report = jack->report;
1377         else
1378                 report = 0;
1379
1380         snd_soc_jack_report(jack->jack, report, jack->report);
1381
1382         return IRQ_HANDLED;
1383 }
1384
1385 /**
1386  * wm8350_hp_jack_detect - Enable headphone jack detection.
1387  *
1388  * @codec:  WM8350 codec
1389  * @which:  left or right jack detect signal
1390  * @jack:   jack to report detection events on
1391  * @report: value to report
1392  *
1393  * Enables the headphone jack detection of the WM8350.  If no report
1394  * is specified then detection is disabled.
1395  */
1396 int wm8350_hp_jack_detect(struct snd_soc_codec *codec, enum wm8350_jack which,
1397                           struct snd_soc_jack *jack, int report)
1398 {
1399         struct wm8350_data *priv = snd_soc_codec_get_drvdata(codec);
1400         struct wm8350 *wm8350 = codec->control_data;
1401         int irq;
1402         int ena;
1403
1404         switch (which) {
1405         case WM8350_JDL:
1406                 priv->hpl.jack = jack;
1407                 priv->hpl.report = report;
1408                 irq = WM8350_IRQ_CODEC_JCK_DET_L;
1409                 ena = WM8350_JDL_ENA;
1410                 break;
1411
1412         case WM8350_JDR:
1413                 priv->hpr.jack = jack;
1414                 priv->hpr.report = report;
1415                 irq = WM8350_IRQ_CODEC_JCK_DET_R;
1416                 ena = WM8350_JDR_ENA;
1417                 break;
1418
1419         default:
1420                 return -EINVAL;
1421         }
1422
1423         if (report) {
1424                 wm8350_set_bits(wm8350, WM8350_POWER_MGMT_4, WM8350_TOCLK_ENA);
1425                 wm8350_set_bits(wm8350, WM8350_JACK_DETECT, ena);
1426         } else {
1427                 wm8350_clear_bits(wm8350, WM8350_JACK_DETECT, ena);
1428         }
1429
1430         /* Sync status */
1431         wm8350_hp_jack_handler(irq + wm8350->irq_base, priv);
1432
1433         return 0;
1434 }
1435 EXPORT_SYMBOL_GPL(wm8350_hp_jack_detect);
1436
1437 static irqreturn_t wm8350_mic_handler(int irq, void *data)
1438 {
1439         struct wm8350_data *priv = data;
1440         struct wm8350 *wm8350 = priv->codec.control_data;
1441         u16 reg;
1442         int report = 0;
1443
1444         reg = wm8350_reg_read(wm8350, WM8350_JACK_PIN_STATUS);
1445         if (reg & WM8350_JACK_MICSCD_LVL)
1446                 report |= priv->mic.short_report;
1447         if (reg & WM8350_JACK_MICSD_LVL)
1448                 report |= priv->mic.report;
1449
1450         snd_soc_jack_report(priv->mic.jack, report,
1451                             priv->mic.report | priv->mic.short_report);
1452
1453         return IRQ_HANDLED;
1454 }
1455
1456 /**
1457  * wm8350_mic_jack_detect - Enable microphone jack detection.
1458  *
1459  * @codec:         WM8350 codec
1460  * @jack:          jack to report detection events on
1461  * @detect_report: value to report when presence detected
1462  * @short_report:  value to report when microphone short detected
1463  *
1464  * Enables the microphone jack detection of the WM8350.  If both reports
1465  * are specified as zero then detection is disabled.
1466  */
1467 int wm8350_mic_jack_detect(struct snd_soc_codec *codec,
1468                            struct snd_soc_jack *jack,
1469                            int detect_report, int short_report)
1470 {
1471         struct wm8350_data *priv = snd_soc_codec_get_drvdata(codec);
1472         struct wm8350 *wm8350 = codec->control_data;
1473
1474         priv->mic.jack = jack;
1475         priv->mic.report = detect_report;
1476         priv->mic.short_report = short_report;
1477
1478         if (detect_report || short_report) {
1479                 wm8350_set_bits(wm8350, WM8350_POWER_MGMT_4, WM8350_TOCLK_ENA);
1480                 wm8350_set_bits(wm8350, WM8350_POWER_MGMT_1,
1481                                 WM8350_MIC_DET_ENA);
1482         } else {
1483                 wm8350_clear_bits(wm8350, WM8350_POWER_MGMT_1,
1484                                   WM8350_MIC_DET_ENA);
1485         }
1486
1487         return 0;
1488 }
1489 EXPORT_SYMBOL_GPL(wm8350_mic_jack_detect);
1490
1491 static struct snd_soc_codec *wm8350_codec;
1492
1493 static int wm8350_probe(struct platform_device *pdev)
1494 {
1495         struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1496         struct snd_soc_codec *codec;
1497         struct wm8350 *wm8350;
1498         struct wm8350_data *priv;
1499         int ret;
1500         struct wm8350_output *out1;
1501         struct wm8350_output *out2;
1502
1503         BUG_ON(!wm8350_codec);
1504
1505         socdev->card->codec = wm8350_codec;
1506         codec = socdev->card->codec;
1507         wm8350 = codec->control_data;
1508         priv = snd_soc_codec_get_drvdata(codec);
1509
1510         /* Enable the codec */
1511         wm8350_set_bits(wm8350, WM8350_POWER_MGMT_5, WM8350_CODEC_ENA);
1512
1513         /* Enable robust clocking mode in ADC */
1514         wm8350_codec_write(codec, WM8350_SECURITY, 0xa7);
1515         wm8350_codec_write(codec, 0xde, 0x13);
1516         wm8350_codec_write(codec, WM8350_SECURITY, 0);
1517
1518         /* read OUT1 & OUT2 volumes */
1519         out1 = &priv->out1;
1520         out2 = &priv->out2;
1521         out1->left_vol = (wm8350_reg_read(wm8350, WM8350_LOUT1_VOLUME) &
1522                           WM8350_OUT1L_VOL_MASK) >> WM8350_OUT1L_VOL_SHIFT;
1523         out1->right_vol = (wm8350_reg_read(wm8350, WM8350_ROUT1_VOLUME) &
1524                            WM8350_OUT1R_VOL_MASK) >> WM8350_OUT1R_VOL_SHIFT;
1525         out2->left_vol = (wm8350_reg_read(wm8350, WM8350_LOUT2_VOLUME) &
1526                           WM8350_OUT2L_VOL_MASK) >> WM8350_OUT1L_VOL_SHIFT;
1527         out2->right_vol = (wm8350_reg_read(wm8350, WM8350_ROUT2_VOLUME) &
1528                            WM8350_OUT2R_VOL_MASK) >> WM8350_OUT1R_VOL_SHIFT;
1529         wm8350_reg_write(wm8350, WM8350_LOUT1_VOLUME, 0);
1530         wm8350_reg_write(wm8350, WM8350_ROUT1_VOLUME, 0);
1531         wm8350_reg_write(wm8350, WM8350_LOUT2_VOLUME, 0);
1532         wm8350_reg_write(wm8350, WM8350_ROUT2_VOLUME, 0);
1533
1534         /* Latch VU bits & mute */
1535         wm8350_set_bits(wm8350, WM8350_LOUT1_VOLUME,
1536                         WM8350_OUT1_VU | WM8350_OUT1L_MUTE);
1537         wm8350_set_bits(wm8350, WM8350_LOUT2_VOLUME,
1538                         WM8350_OUT2_VU | WM8350_OUT2L_MUTE);
1539         wm8350_set_bits(wm8350, WM8350_ROUT1_VOLUME,
1540                         WM8350_OUT1_VU | WM8350_OUT1R_MUTE);
1541         wm8350_set_bits(wm8350, WM8350_ROUT2_VOLUME,
1542                         WM8350_OUT2_VU | WM8350_OUT2R_MUTE);
1543
1544         /* Make sure jack detect is disabled to start off with */
1545         wm8350_clear_bits(wm8350, WM8350_JACK_DETECT,
1546                           WM8350_JDL_ENA | WM8350_JDR_ENA);
1547
1548         wm8350_register_irq(wm8350, WM8350_IRQ_CODEC_JCK_DET_L,
1549                             wm8350_hp_jack_handler, 0, "Left jack detect",
1550                             priv);
1551         wm8350_register_irq(wm8350, WM8350_IRQ_CODEC_JCK_DET_R,
1552                             wm8350_hp_jack_handler, 0, "Right jack detect",
1553                             priv);
1554         wm8350_register_irq(wm8350, WM8350_IRQ_CODEC_MICSCD,
1555                             wm8350_mic_handler, 0, "Microphone short", priv);
1556         wm8350_register_irq(wm8350, WM8350_IRQ_CODEC_MICD,
1557                             wm8350_mic_handler, 0, "Microphone detect", priv);
1558
1559         ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
1560         if (ret < 0) {
1561                 dev_err(&pdev->dev, "failed to create pcms\n");
1562                 return ret;
1563         }
1564
1565         snd_soc_add_controls(codec, wm8350_snd_controls,
1566                                 ARRAY_SIZE(wm8350_snd_controls));
1567         wm8350_add_widgets(codec);
1568
1569         wm8350_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1570
1571         return 0;
1572 }
1573
1574 static int wm8350_remove(struct platform_device *pdev)
1575 {
1576         struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1577         struct snd_soc_codec *codec = socdev->card->codec;
1578         struct wm8350 *wm8350 = codec->control_data;
1579         struct wm8350_data *priv = snd_soc_codec_get_drvdata(codec);
1580         int ret;
1581
1582         wm8350_clear_bits(wm8350, WM8350_JACK_DETECT,
1583                           WM8350_JDL_ENA | WM8350_JDR_ENA);
1584         wm8350_clear_bits(wm8350, WM8350_POWER_MGMT_4, WM8350_TOCLK_ENA);
1585
1586         wm8350_free_irq(wm8350, WM8350_IRQ_CODEC_MICD, priv);
1587         wm8350_free_irq(wm8350, WM8350_IRQ_CODEC_MICSCD, priv);
1588         wm8350_free_irq(wm8350, WM8350_IRQ_CODEC_JCK_DET_L, priv);
1589         wm8350_free_irq(wm8350, WM8350_IRQ_CODEC_JCK_DET_R, priv);
1590
1591         priv->hpl.jack = NULL;
1592         priv->hpr.jack = NULL;
1593         priv->mic.jack = NULL;
1594
1595         /* cancel any work waiting to be queued. */
1596         ret = cancel_delayed_work(&codec->delayed_work);
1597
1598         /* if there was any work waiting then we run it now and
1599          * wait for its completion */
1600         if (ret) {
1601                 schedule_delayed_work(&codec->delayed_work, 0);
1602                 flush_scheduled_work();
1603         }
1604
1605         wm8350_set_bias_level(codec, SND_SOC_BIAS_OFF);
1606
1607         wm8350_clear_bits(wm8350, WM8350_POWER_MGMT_5, WM8350_CODEC_ENA);
1608
1609         return 0;
1610 }
1611
1612 #define WM8350_RATES (SNDRV_PCM_RATE_8000_96000)
1613
1614 #define WM8350_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
1615                         SNDRV_PCM_FMTBIT_S20_3LE |\
1616                         SNDRV_PCM_FMTBIT_S24_LE)
1617
1618 static struct snd_soc_dai_ops wm8350_dai_ops = {
1619          .hw_params     = wm8350_pcm_hw_params,
1620          .digital_mute  = wm8350_mute,
1621          .trigger       = wm8350_pcm_trigger,
1622          .set_fmt       = wm8350_set_dai_fmt,
1623          .set_sysclk    = wm8350_set_dai_sysclk,
1624          .set_pll       = wm8350_set_fll,
1625          .set_clkdiv    = wm8350_set_clkdiv,
1626 };
1627
1628 struct snd_soc_dai wm8350_dai = {
1629         .name = "WM8350",
1630         .playback = {
1631                 .stream_name = "Playback",
1632                 .channels_min = 1,
1633                 .channels_max = 2,
1634                 .rates = WM8350_RATES,
1635                 .formats = WM8350_FORMATS,
1636         },
1637         .capture = {
1638                  .stream_name = "Capture",
1639                  .channels_min = 1,
1640                  .channels_max = 2,
1641                  .rates = WM8350_RATES,
1642                  .formats = WM8350_FORMATS,
1643          },
1644         .ops = &wm8350_dai_ops,
1645 };
1646 EXPORT_SYMBOL_GPL(wm8350_dai);
1647
1648 struct snd_soc_codec_device soc_codec_dev_wm8350 = {
1649         .probe =        wm8350_probe,
1650         .remove =       wm8350_remove,
1651         .suspend =      wm8350_suspend,
1652         .resume =       wm8350_resume,
1653 };
1654 EXPORT_SYMBOL_GPL(soc_codec_dev_wm8350);
1655
1656 static __devinit int wm8350_codec_probe(struct platform_device *pdev)
1657 {
1658         struct wm8350 *wm8350 = platform_get_drvdata(pdev);
1659         struct wm8350_data *priv;
1660         struct snd_soc_codec *codec;
1661         int ret, i;
1662
1663         if (wm8350->codec.platform_data == NULL) {
1664                 dev_err(&pdev->dev, "No audio platform data supplied\n");
1665                 return -EINVAL;
1666         }
1667
1668         priv = kzalloc(sizeof(struct wm8350_data), GFP_KERNEL);
1669         if (priv == NULL)
1670                 return -ENOMEM;
1671
1672         for (i = 0; i < ARRAY_SIZE(supply_names); i++)
1673                 priv->supplies[i].supply = supply_names[i];
1674
1675         ret = regulator_bulk_get(wm8350->dev, ARRAY_SIZE(priv->supplies),
1676                                  priv->supplies);
1677         if (ret != 0)
1678                 goto err_priv;
1679
1680         codec = &priv->codec;
1681         wm8350->codec.codec = codec;
1682
1683         wm8350_dai.dev = &pdev->dev;
1684
1685         mutex_init(&codec->mutex);
1686         INIT_LIST_HEAD(&codec->dapm_widgets);
1687         INIT_LIST_HEAD(&codec->dapm_paths);
1688         codec->dev = &pdev->dev;
1689         codec->name = "WM8350";
1690         codec->owner = THIS_MODULE;
1691         codec->read = wm8350_codec_read;
1692         codec->write = wm8350_codec_write;
1693         codec->bias_level = SND_SOC_BIAS_OFF;
1694         codec->set_bias_level = wm8350_set_bias_level;
1695         codec->dai = &wm8350_dai;
1696         codec->num_dai = 1;
1697         codec->reg_cache_size = WM8350_MAX_REGISTER;
1698         snd_soc_codec_set_drvdata(codec, priv);
1699         codec->control_data = wm8350;
1700
1701         /* Put the codec into reset if it wasn't already */
1702         wm8350_clear_bits(wm8350, WM8350_POWER_MGMT_5, WM8350_CODEC_ENA);
1703
1704         INIT_DELAYED_WORK(&codec->delayed_work, wm8350_pga_work);
1705         ret = snd_soc_register_codec(codec);
1706         if (ret != 0)
1707                 goto err_supply;
1708
1709         wm8350_codec = codec;
1710
1711         ret = snd_soc_register_dai(&wm8350_dai);
1712         if (ret != 0)
1713                 goto err_codec;
1714         return 0;
1715
1716 err_codec:
1717         snd_soc_unregister_codec(codec);
1718 err_supply:
1719         regulator_bulk_free(ARRAY_SIZE(priv->supplies), priv->supplies);
1720 err_priv:
1721         kfree(priv);
1722         wm8350_codec = NULL;
1723         return ret;
1724 }
1725
1726 static int __devexit wm8350_codec_remove(struct platform_device *pdev)
1727 {
1728         struct wm8350 *wm8350 = platform_get_drvdata(pdev);
1729         struct snd_soc_codec *codec = wm8350->codec.codec;
1730         struct wm8350_data *priv = snd_soc_codec_get_drvdata(codec);
1731
1732         snd_soc_unregister_dai(&wm8350_dai);
1733         snd_soc_unregister_codec(codec);
1734         regulator_bulk_free(ARRAY_SIZE(priv->supplies), priv->supplies);
1735         kfree(priv);
1736         wm8350_codec = NULL;
1737         return 0;
1738 }
1739
1740 static struct platform_driver wm8350_codec_driver = {
1741         .driver = {
1742                    .name = "wm8350-codec",
1743                    .owner = THIS_MODULE,
1744                    },
1745         .probe = wm8350_codec_probe,
1746         .remove = __devexit_p(wm8350_codec_remove),
1747 };
1748
1749 static __init int wm8350_init(void)
1750 {
1751         return platform_driver_register(&wm8350_codec_driver);
1752 }
1753 module_init(wm8350_init);
1754
1755 static __exit void wm8350_exit(void)
1756 {
1757         platform_driver_unregister(&wm8350_codec_driver);
1758 }
1759 module_exit(wm8350_exit);
1760
1761 MODULE_DESCRIPTION("ASoC WM8350 driver");
1762 MODULE_AUTHOR("Liam Girdwood");
1763 MODULE_LICENSE("GPL");
1764 MODULE_ALIAS("platform:wm8350-codec");