2 * ALSA SoC Texas Instruments TLV320DAC33 codec driver
4 * Author: Peter Ujfalusi <peter.ujfalusi@nokia.com>
6 * Copyright: (C) 2009 Nokia Corporation
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
24 #include <linux/module.h>
25 #include <linux/moduleparam.h>
26 #include <linux/init.h>
27 #include <linux/delay.h>
29 #include <linux/i2c.h>
30 #include <linux/platform_device.h>
31 #include <linux/interrupt.h>
32 #include <linux/gpio.h>
33 #include <linux/regulator/consumer.h>
34 #include <sound/core.h>
35 #include <sound/pcm.h>
36 #include <sound/pcm_params.h>
37 #include <sound/soc.h>
38 #include <sound/soc-dapm.h>
39 #include <sound/initval.h>
40 #include <sound/tlv.h>
42 #include <sound/tlv320dac33-plat.h>
43 #include "tlv320dac33.h"
45 #define DAC33_BUFFER_SIZE_BYTES 24576 /* bytes, 12288 16 bit words,
47 #define DAC33_BUFFER_SIZE_SAMPLES 6144
49 #define NSAMPLE_MAX 5700
51 #define LATENCY_TIME_MS 20
54 #define MODE7_UTHR (DAC33_BUFFER_SIZE_SAMPLES - 10)
56 #define BURST_BASEFREQ_HZ 49152000
58 #define SAMPLES_TO_US(rate, samples) \
59 (1000000000 / ((rate * 1000) / samples))
61 #define US_TO_SAMPLES(rate, us) \
62 (rate / (1000000 / us))
64 static void dac33_calculate_times(struct snd_pcm_substream *substream);
65 static int dac33_prepare_chip(struct snd_pcm_substream *substream);
67 static struct snd_soc_codec *tlv320dac33_codec;
76 enum dac33_fifo_modes {
77 DAC33_FIFO_BYPASS = 0,
83 #define DAC33_NUM_SUPPLIES 3
84 static const char *dac33_supply_names[DAC33_NUM_SUPPLIES] = {
90 struct tlv320dac33_priv {
92 struct workqueue_struct *dac33_wq;
93 struct work_struct work;
94 struct snd_soc_codec codec;
95 struct regulator_bulk_data supplies[DAC33_NUM_SUPPLIES];
96 struct snd_pcm_substream *substream;
102 unsigned int alarm_threshold; /* set to be half of LATENCY_TIME_MS */
103 unsigned int nsample_min; /* nsample should not be lower than
105 unsigned int nsample_max; /* nsample should not be higher than
107 enum dac33_fifo_modes fifo_mode;/* FIFO mode selection */
108 unsigned int nsample; /* burst read amount from host */
109 u8 burst_bclkdiv; /* BCLK divider value in burst mode */
110 unsigned int burst_rate; /* Interface speed in Burst modes */
112 int keep_bclk; /* Keep the BCLK continuously running
115 unsigned long long t_stamp1; /* Time stamp for FIFO modes to */
116 unsigned long long t_stamp2; /* calculate the FIFO caused delay */
118 unsigned int mode1_us_burst; /* Time to burst read n number of
120 unsigned int mode7_us_to_lthr; /* Time to reach lthr from uthr */
122 enum dac33_state state;
125 static const u8 dac33_reg[DAC33_CACHEREGNUM] = {
126 0x00, 0x00, 0x00, 0x00, /* 0x00 - 0x03 */
127 0x00, 0x00, 0x00, 0x00, /* 0x04 - 0x07 */
128 0x00, 0x00, 0x00, 0x00, /* 0x08 - 0x0b */
129 0x00, 0x00, 0x00, 0x00, /* 0x0c - 0x0f */
130 0x00, 0x00, 0x00, 0x00, /* 0x10 - 0x13 */
131 0x00, 0x00, 0x00, 0x00, /* 0x14 - 0x17 */
132 0x00, 0x00, 0x00, 0x00, /* 0x18 - 0x1b */
133 0x00, 0x00, 0x00, 0x00, /* 0x1c - 0x1f */
134 0x00, 0x00, 0x00, 0x00, /* 0x20 - 0x23 */
135 0x00, 0x00, 0x00, 0x00, /* 0x24 - 0x27 */
136 0x00, 0x00, 0x00, 0x00, /* 0x28 - 0x2b */
137 0x00, 0x00, 0x00, 0x80, /* 0x2c - 0x2f */
138 0x80, 0x00, 0x00, 0x00, /* 0x30 - 0x33 */
139 0x00, 0x00, 0x00, 0x00, /* 0x34 - 0x37 */
140 0x00, 0x00, /* 0x38 - 0x39 */
141 /* Registers 0x3a - 0x3f are reserved */
142 0x00, 0x00, /* 0x3a - 0x3b */
143 0x00, 0x00, 0x00, 0x00, /* 0x3c - 0x3f */
145 0x00, 0x00, 0x00, 0x00, /* 0x40 - 0x43 */
146 0x00, 0x80, /* 0x44 - 0x45 */
147 /* Registers 0x46 - 0x47 are reserved */
148 0x80, 0x80, /* 0x46 - 0x47 */
150 0x80, 0x00, 0x00, /* 0x48 - 0x4a */
151 /* Registers 0x4b - 0x7c are reserved */
153 0x00, 0x00, 0x00, 0x00, /* 0x4c - 0x4f */
154 0x00, 0x00, 0x00, 0x00, /* 0x50 - 0x53 */
155 0x00, 0x00, 0x00, 0x00, /* 0x54 - 0x57 */
156 0x00, 0x00, 0x00, 0x00, /* 0x58 - 0x5b */
157 0x00, 0x00, 0x00, 0x00, /* 0x5c - 0x5f */
158 0x00, 0x00, 0x00, 0x00, /* 0x60 - 0x63 */
159 0x00, 0x00, 0x00, 0x00, /* 0x64 - 0x67 */
160 0x00, 0x00, 0x00, 0x00, /* 0x68 - 0x6b */
161 0x00, 0x00, 0x00, 0x00, /* 0x6c - 0x6f */
162 0x00, 0x00, 0x00, 0x00, /* 0x70 - 0x73 */
163 0x00, 0x00, 0x00, 0x00, /* 0x74 - 0x77 */
164 0x00, 0x00, 0x00, 0x00, /* 0x78 - 0x7b */
167 0xda, 0x33, 0x03, /* 0x7d - 0x7f */
170 /* Register read and write */
171 static inline unsigned int dac33_read_reg_cache(struct snd_soc_codec *codec,
174 u8 *cache = codec->reg_cache;
175 if (reg >= DAC33_CACHEREGNUM)
181 static inline void dac33_write_reg_cache(struct snd_soc_codec *codec,
184 u8 *cache = codec->reg_cache;
185 if (reg >= DAC33_CACHEREGNUM)
191 static int dac33_read(struct snd_soc_codec *codec, unsigned int reg,
194 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
199 /* If powered off, return the cached value */
200 if (dac33->chip_power) {
201 val = i2c_smbus_read_byte_data(codec->control_data, value[0]);
203 dev_err(codec->dev, "Read failed (%d)\n", val);
204 value[0] = dac33_read_reg_cache(codec, reg);
207 dac33_write_reg_cache(codec, reg, val);
210 value[0] = dac33_read_reg_cache(codec, reg);
216 static int dac33_write(struct snd_soc_codec *codec, unsigned int reg,
219 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
225 * D15..D8 dac33 register offset
226 * D7...D0 register data
228 data[0] = reg & 0xff;
229 data[1] = value & 0xff;
231 dac33_write_reg_cache(codec, data[0], data[1]);
232 if (dac33->chip_power) {
233 ret = codec->hw_write(codec->control_data, data, 2);
235 dev_err(codec->dev, "Write failed (%d)\n", ret);
243 static int dac33_write_locked(struct snd_soc_codec *codec, unsigned int reg,
246 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
249 mutex_lock(&dac33->mutex);
250 ret = dac33_write(codec, reg, value);
251 mutex_unlock(&dac33->mutex);
256 #define DAC33_I2C_ADDR_AUTOINC 0x80
257 static int dac33_write16(struct snd_soc_codec *codec, unsigned int reg,
260 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
266 * D23..D16 dac33 register offset
267 * D15..D8 register data MSB
268 * D7...D0 register data LSB
270 data[0] = reg & 0xff;
271 data[1] = (value >> 8) & 0xff;
272 data[2] = value & 0xff;
274 dac33_write_reg_cache(codec, data[0], data[1]);
275 dac33_write_reg_cache(codec, data[0] + 1, data[2]);
277 if (dac33->chip_power) {
278 /* We need to set autoincrement mode for 16 bit writes */
279 data[0] |= DAC33_I2C_ADDR_AUTOINC;
280 ret = codec->hw_write(codec->control_data, data, 3);
282 dev_err(codec->dev, "Write failed (%d)\n", ret);
290 static void dac33_init_chip(struct snd_soc_codec *codec)
292 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
294 if (unlikely(!dac33->chip_power))
297 /* 44-46: DAC Control Registers */
298 /* A : DAC sample rate Fsref/1.5 */
299 dac33_write(codec, DAC33_DAC_CTRL_A, DAC33_DACRATE(0));
300 /* B : DAC src=normal, not muted */
301 dac33_write(codec, DAC33_DAC_CTRL_B, DAC33_DACSRCR_RIGHT |
304 dac33_write(codec, DAC33_DAC_CTRL_C, 0x00);
306 /* 73 : volume soft stepping control,
307 clock source = internal osc (?) */
308 dac33_write(codec, DAC33_ANA_VOL_SOFT_STEP_CTRL, DAC33_VOLCLKEN);
310 dac33_write(codec, DAC33_PWR_CTRL, DAC33_PDNALLB);
312 /* Restore only selected registers (gains mostly) */
313 dac33_write(codec, DAC33_LDAC_DIG_VOL_CTRL,
314 dac33_read_reg_cache(codec, DAC33_LDAC_DIG_VOL_CTRL));
315 dac33_write(codec, DAC33_RDAC_DIG_VOL_CTRL,
316 dac33_read_reg_cache(codec, DAC33_RDAC_DIG_VOL_CTRL));
318 dac33_write(codec, DAC33_LINEL_TO_LLO_VOL,
319 dac33_read_reg_cache(codec, DAC33_LINEL_TO_LLO_VOL));
320 dac33_write(codec, DAC33_LINER_TO_RLO_VOL,
321 dac33_read_reg_cache(codec, DAC33_LINER_TO_RLO_VOL));
324 static inline void dac33_read_id(struct snd_soc_codec *codec)
328 dac33_read(codec, DAC33_DEVICE_ID_MSB, ®);
329 dac33_read(codec, DAC33_DEVICE_ID_LSB, ®);
330 dac33_read(codec, DAC33_DEVICE_REV_ID, ®);
333 static inline void dac33_soft_power(struct snd_soc_codec *codec, int power)
337 reg = dac33_read_reg_cache(codec, DAC33_PWR_CTRL);
339 reg |= DAC33_PDNALLB;
341 reg &= ~(DAC33_PDNALLB | DAC33_OSCPDNB |
342 DAC33_DACRPDNB | DAC33_DACLPDNB);
343 dac33_write(codec, DAC33_PWR_CTRL, reg);
346 static int dac33_hard_power(struct snd_soc_codec *codec, int power)
348 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
351 mutex_lock(&dac33->mutex);
354 if (unlikely(power == dac33->chip_power)) {
355 dev_warn(codec->dev, "Trying to set the same power state: %s\n",
356 power ? "ON" : "OFF");
361 ret = regulator_bulk_enable(ARRAY_SIZE(dac33->supplies),
365 "Failed to enable supplies: %d\n", ret);
369 if (dac33->power_gpio >= 0)
370 gpio_set_value(dac33->power_gpio, 1);
372 dac33->chip_power = 1;
374 dac33_soft_power(codec, 0);
375 if (dac33->power_gpio >= 0)
376 gpio_set_value(dac33->power_gpio, 0);
378 ret = regulator_bulk_disable(ARRAY_SIZE(dac33->supplies),
382 "Failed to disable supplies: %d\n", ret);
386 dac33->chip_power = 0;
390 mutex_unlock(&dac33->mutex);
394 static int playback_event(struct snd_soc_dapm_widget *w,
395 struct snd_kcontrol *kcontrol, int event)
397 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(w->codec);
400 case SND_SOC_DAPM_PRE_PMU:
401 if (likely(dac33->substream)) {
402 dac33_calculate_times(dac33->substream);
403 dac33_prepare_chip(dac33->substream);
410 static int dac33_get_nsample(struct snd_kcontrol *kcontrol,
411 struct snd_ctl_elem_value *ucontrol)
413 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
414 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
416 ucontrol->value.integer.value[0] = dac33->nsample;
421 static int dac33_set_nsample(struct snd_kcontrol *kcontrol,
422 struct snd_ctl_elem_value *ucontrol)
424 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
425 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
428 if (dac33->nsample == ucontrol->value.integer.value[0])
431 if (ucontrol->value.integer.value[0] < dac33->nsample_min ||
432 ucontrol->value.integer.value[0] > dac33->nsample_max) {
435 dac33->nsample = ucontrol->value.integer.value[0];
436 /* Re calculate the burst time */
437 dac33->mode1_us_burst = SAMPLES_TO_US(dac33->burst_rate,
444 static int dac33_get_fifo_mode(struct snd_kcontrol *kcontrol,
445 struct snd_ctl_elem_value *ucontrol)
447 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
448 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
450 ucontrol->value.integer.value[0] = dac33->fifo_mode;
455 static int dac33_set_fifo_mode(struct snd_kcontrol *kcontrol,
456 struct snd_ctl_elem_value *ucontrol)
458 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
459 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
462 if (dac33->fifo_mode == ucontrol->value.integer.value[0])
464 /* Do not allow changes while stream is running*/
468 if (ucontrol->value.integer.value[0] < 0 ||
469 ucontrol->value.integer.value[0] >= DAC33_FIFO_LAST_MODE)
472 dac33->fifo_mode = ucontrol->value.integer.value[0];
477 /* Codec operation modes */
478 static const char *dac33_fifo_mode_texts[] = {
479 "Bypass", "Mode 1", "Mode 7"
482 static const struct soc_enum dac33_fifo_mode_enum =
483 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(dac33_fifo_mode_texts),
484 dac33_fifo_mode_texts);
487 * DACL/R digital volume control:
488 * from 0 dB to -63.5 in 0.5 dB steps
489 * Need to be inverted later on:
493 static DECLARE_TLV_DB_SCALE(dac_digivol_tlv, -6350, 50, 0);
495 static const struct snd_kcontrol_new dac33_snd_controls[] = {
496 SOC_DOUBLE_R_TLV("DAC Digital Playback Volume",
497 DAC33_LDAC_DIG_VOL_CTRL, DAC33_RDAC_DIG_VOL_CTRL,
498 0, 0x7f, 1, dac_digivol_tlv),
499 SOC_DOUBLE_R("DAC Digital Playback Switch",
500 DAC33_LDAC_DIG_VOL_CTRL, DAC33_RDAC_DIG_VOL_CTRL, 7, 1, 1),
501 SOC_DOUBLE_R("Line to Line Out Volume",
502 DAC33_LINEL_TO_LLO_VOL, DAC33_LINER_TO_RLO_VOL, 0, 127, 1),
505 static const struct snd_kcontrol_new dac33_nsample_snd_controls[] = {
506 SOC_SINGLE_EXT("nSample", 0, 0, 5900, 0,
507 dac33_get_nsample, dac33_set_nsample),
508 SOC_ENUM_EXT("FIFO Mode", dac33_fifo_mode_enum,
509 dac33_get_fifo_mode, dac33_set_fifo_mode),
513 static const struct snd_kcontrol_new dac33_dapm_abypassl_control =
514 SOC_DAPM_SINGLE("Switch", DAC33_LINEL_TO_LLO_VOL, 7, 1, 1);
516 static const struct snd_kcontrol_new dac33_dapm_abypassr_control =
517 SOC_DAPM_SINGLE("Switch", DAC33_LINER_TO_RLO_VOL, 7, 1, 1);
519 static const struct snd_soc_dapm_widget dac33_dapm_widgets[] = {
520 SND_SOC_DAPM_OUTPUT("LEFT_LO"),
521 SND_SOC_DAPM_OUTPUT("RIGHT_LO"),
523 SND_SOC_DAPM_INPUT("LINEL"),
524 SND_SOC_DAPM_INPUT("LINER"),
526 SND_SOC_DAPM_DAC("DACL", "Left Playback", DAC33_LDAC_PWR_CTRL, 2, 0),
527 SND_SOC_DAPM_DAC("DACR", "Right Playback", DAC33_RDAC_PWR_CTRL, 2, 0),
530 SND_SOC_DAPM_SWITCH("Analog Left Bypass", SND_SOC_NOPM, 0, 0,
531 &dac33_dapm_abypassl_control),
532 SND_SOC_DAPM_SWITCH("Analog Right Bypass", SND_SOC_NOPM, 0, 0,
533 &dac33_dapm_abypassr_control),
535 SND_SOC_DAPM_REG(snd_soc_dapm_mixer, "Output Left Amp Power",
536 DAC33_OUT_AMP_PWR_CTRL, 6, 3, 3, 0),
537 SND_SOC_DAPM_REG(snd_soc_dapm_mixer, "Output Right Amp Power",
538 DAC33_OUT_AMP_PWR_CTRL, 4, 3, 3, 0),
540 SND_SOC_DAPM_PRE("Prepare Playback", playback_event),
543 static const struct snd_soc_dapm_route audio_map[] = {
545 {"Analog Left Bypass", "Switch", "LINEL"},
546 {"Analog Right Bypass", "Switch", "LINER"},
548 {"Output Left Amp Power", NULL, "DACL"},
549 {"Output Right Amp Power", NULL, "DACR"},
551 {"Output Left Amp Power", NULL, "Analog Left Bypass"},
552 {"Output Right Amp Power", NULL, "Analog Right Bypass"},
555 {"LEFT_LO", NULL, "Output Left Amp Power"},
556 {"RIGHT_LO", NULL, "Output Right Amp Power"},
559 static int dac33_add_widgets(struct snd_soc_codec *codec)
561 snd_soc_dapm_new_controls(codec, dac33_dapm_widgets,
562 ARRAY_SIZE(dac33_dapm_widgets));
564 /* set up audio path interconnects */
565 snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map));
570 static int dac33_set_bias_level(struct snd_soc_codec *codec,
571 enum snd_soc_bias_level level)
576 case SND_SOC_BIAS_ON:
577 dac33_soft_power(codec, 1);
579 case SND_SOC_BIAS_PREPARE:
581 case SND_SOC_BIAS_STANDBY:
582 if (codec->bias_level == SND_SOC_BIAS_OFF) {
583 /* Coming from OFF, switch on the codec */
584 ret = dac33_hard_power(codec, 1);
588 dac33_init_chip(codec);
591 case SND_SOC_BIAS_OFF:
592 ret = dac33_hard_power(codec, 0);
597 codec->bias_level = level;
602 static inline void dac33_prefill_handler(struct tlv320dac33_priv *dac33)
604 struct snd_soc_codec *codec;
606 codec = &dac33->codec;
608 switch (dac33->fifo_mode) {
609 case DAC33_FIFO_MODE1:
610 dac33_write16(codec, DAC33_NSAMPLE_MSB,
611 DAC33_THRREG(dac33->nsample + dac33->alarm_threshold));
613 /* Take the timestamps */
614 spin_lock_irq(&dac33->lock);
615 dac33->t_stamp2 = ktime_to_us(ktime_get());
616 dac33->t_stamp1 = dac33->t_stamp2;
617 spin_unlock_irq(&dac33->lock);
619 dac33_write16(codec, DAC33_PREFILL_MSB,
620 DAC33_THRREG(dac33->alarm_threshold));
621 /* Enable Alarm Threshold IRQ with a delay */
622 udelay(SAMPLES_TO_US(dac33->burst_rate,
623 dac33->alarm_threshold));
624 dac33_write(codec, DAC33_FIFO_IRQ_MASK, DAC33_MAT);
626 case DAC33_FIFO_MODE7:
627 /* Take the timestamp */
628 spin_lock_irq(&dac33->lock);
629 dac33->t_stamp1 = ktime_to_us(ktime_get());
630 /* Move back the timestamp with drain time */
631 dac33->t_stamp1 -= dac33->mode7_us_to_lthr;
632 spin_unlock_irq(&dac33->lock);
634 dac33_write16(codec, DAC33_PREFILL_MSB,
635 DAC33_THRREG(MODE7_LTHR));
637 /* Enable Upper Threshold IRQ */
638 dac33_write(codec, DAC33_FIFO_IRQ_MASK, DAC33_MUT);
641 dev_warn(codec->dev, "Unhandled FIFO mode: %d\n",
647 static inline void dac33_playback_handler(struct tlv320dac33_priv *dac33)
649 struct snd_soc_codec *codec;
651 codec = &dac33->codec;
653 switch (dac33->fifo_mode) {
654 case DAC33_FIFO_MODE1:
655 /* Take the timestamp */
656 spin_lock_irq(&dac33->lock);
657 dac33->t_stamp2 = ktime_to_us(ktime_get());
658 spin_unlock_irq(&dac33->lock);
660 dac33_write16(codec, DAC33_NSAMPLE_MSB,
661 DAC33_THRREG(dac33->nsample));
663 case DAC33_FIFO_MODE7:
664 /* At the moment we are not using interrupts in mode7 */
667 dev_warn(codec->dev, "Unhandled FIFO mode: %d\n",
673 static void dac33_work(struct work_struct *work)
675 struct snd_soc_codec *codec;
676 struct tlv320dac33_priv *dac33;
679 dac33 = container_of(work, struct tlv320dac33_priv, work);
680 codec = &dac33->codec;
682 mutex_lock(&dac33->mutex);
683 switch (dac33->state) {
685 dac33->state = DAC33_PLAYBACK;
686 dac33_prefill_handler(dac33);
689 dac33_playback_handler(dac33);
694 dac33->state = DAC33_IDLE;
695 /* Mask all interrupts from dac33 */
696 dac33_write(codec, DAC33_FIFO_IRQ_MASK, 0);
699 reg = dac33_read_reg_cache(codec, DAC33_FIFO_CTRL_A);
700 reg |= DAC33_FIFOFLUSH;
701 dac33_write(codec, DAC33_FIFO_CTRL_A, reg);
704 mutex_unlock(&dac33->mutex);
707 static irqreturn_t dac33_interrupt_handler(int irq, void *dev)
709 struct snd_soc_codec *codec = dev;
710 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
712 spin_lock(&dac33->lock);
713 dac33->t_stamp1 = ktime_to_us(ktime_get());
714 spin_unlock(&dac33->lock);
716 /* Do not schedule the workqueue in Mode7 */
717 if (dac33->fifo_mode != DAC33_FIFO_MODE7)
718 queue_work(dac33->dac33_wq, &dac33->work);
723 static void dac33_oscwait(struct snd_soc_codec *codec)
730 dac33_read(codec, DAC33_INT_OSC_STATUS, ®);
731 } while (((reg & 0x03) != DAC33_OSCSTATUS_NORMAL) && timeout--);
732 if ((reg & 0x03) != DAC33_OSCSTATUS_NORMAL)
734 "internal oscillator calibration failed\n");
737 static int dac33_startup(struct snd_pcm_substream *substream,
738 struct snd_soc_dai *dai)
740 struct snd_soc_pcm_runtime *rtd = substream->private_data;
741 struct snd_soc_device *socdev = rtd->socdev;
742 struct snd_soc_codec *codec = socdev->card->codec;
743 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
745 /* Stream started, save the substream pointer */
746 dac33->substream = substream;
751 static void dac33_shutdown(struct snd_pcm_substream *substream,
752 struct snd_soc_dai *dai)
754 struct snd_soc_pcm_runtime *rtd = substream->private_data;
755 struct snd_soc_device *socdev = rtd->socdev;
756 struct snd_soc_codec *codec = socdev->card->codec;
757 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
759 dac33->substream = NULL;
762 static int dac33_hw_params(struct snd_pcm_substream *substream,
763 struct snd_pcm_hw_params *params,
764 struct snd_soc_dai *dai)
766 struct snd_soc_pcm_runtime *rtd = substream->private_data;
767 struct snd_soc_device *socdev = rtd->socdev;
768 struct snd_soc_codec *codec = socdev->card->codec;
770 /* Check parameters for validity */
771 switch (params_rate(params)) {
776 dev_err(codec->dev, "unsupported rate %d\n",
777 params_rate(params));
781 switch (params_format(params)) {
782 case SNDRV_PCM_FORMAT_S16_LE:
785 dev_err(codec->dev, "unsupported format %d\n",
786 params_format(params));
793 #define CALC_OSCSET(rate, refclk) ( \
794 ((((rate * 10000) / refclk) * 4096) + 7000) / 10000)
795 #define CALC_RATIOSET(rate, refclk) ( \
796 ((((refclk * 100000) / rate) * 16384) + 50000) / 100000)
799 * tlv320dac33 is strict on the sequence of the register writes, if the register
800 * writes happens in different order, than dac33 might end up in unknown state.
801 * Use the known, working sequence of register writes to initialize the dac33.
803 static int dac33_prepare_chip(struct snd_pcm_substream *substream)
805 struct snd_soc_pcm_runtime *rtd = substream->private_data;
806 struct snd_soc_device *socdev = rtd->socdev;
807 struct snd_soc_codec *codec = socdev->card->codec;
808 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
809 unsigned int oscset, ratioset, pwr_ctrl, reg_tmp;
810 u8 aictrl_a, aictrl_b, fifoctrl_a;
812 switch (substream->runtime->rate) {
815 oscset = CALC_OSCSET(substream->runtime->rate, dac33->refclk);
816 ratioset = CALC_RATIOSET(substream->runtime->rate,
820 dev_err(codec->dev, "unsupported rate %d\n",
821 substream->runtime->rate);
826 aictrl_a = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_A);
827 aictrl_a &= ~(DAC33_NCYCL_MASK | DAC33_WLEN_MASK);
828 /* Read FIFO control A, and clear FIFO flush bit */
829 fifoctrl_a = dac33_read_reg_cache(codec, DAC33_FIFO_CTRL_A);
830 fifoctrl_a &= ~DAC33_FIFOFLUSH;
832 fifoctrl_a &= ~DAC33_WIDTH;
833 switch (substream->runtime->format) {
834 case SNDRV_PCM_FORMAT_S16_LE:
835 aictrl_a |= (DAC33_NCYCL_16 | DAC33_WLEN_16);
836 fifoctrl_a |= DAC33_WIDTH;
839 dev_err(codec->dev, "unsupported format %d\n",
840 substream->runtime->format);
844 mutex_lock(&dac33->mutex);
846 if (!dac33->chip_power) {
848 * Chip is not powered yet.
849 * Do the init in the dac33_set_bias_level later.
851 mutex_unlock(&dac33->mutex);
855 dac33_soft_power(codec, 0);
856 dac33_soft_power(codec, 1);
858 reg_tmp = dac33_read_reg_cache(codec, DAC33_INT_OSC_CTRL);
859 dac33_write(codec, DAC33_INT_OSC_CTRL, reg_tmp);
861 /* Write registers 0x08 and 0x09 (MSB, LSB) */
862 dac33_write16(codec, DAC33_INT_OSC_FREQ_RAT_A, oscset);
864 /* calib time: 128 is a nice number ;) */
865 dac33_write(codec, DAC33_CALIB_TIME, 128);
867 /* adjustment treshold & step */
868 dac33_write(codec, DAC33_INT_OSC_CTRL_B, DAC33_ADJTHRSHLD(2) |
871 /* div=4 / gain=1 / div */
872 dac33_write(codec, DAC33_INT_OSC_CTRL_C, DAC33_REFDIV(4));
874 pwr_ctrl = dac33_read_reg_cache(codec, DAC33_PWR_CTRL);
875 pwr_ctrl |= DAC33_OSCPDNB | DAC33_DACRPDNB | DAC33_DACLPDNB;
876 dac33_write(codec, DAC33_PWR_CTRL, pwr_ctrl);
878 dac33_oscwait(codec);
880 if (dac33->fifo_mode) {
881 /* Generic for all FIFO modes */
882 /* 50-51 : ASRC Control registers */
883 dac33_write(codec, DAC33_ASRC_CTRL_A, DAC33_SRCLKDIV(1));
884 dac33_write(codec, DAC33_ASRC_CTRL_B, 1); /* ??? */
886 /* Write registers 0x34 and 0x35 (MSB, LSB) */
887 dac33_write16(codec, DAC33_SRC_REF_CLK_RATIO_A, ratioset);
889 /* Set interrupts to high active */
890 dac33_write(codec, DAC33_INTP_CTRL_A, DAC33_INTPM_AHIGH);
892 /* FIFO bypass mode */
893 /* 50-51 : ASRC Control registers */
894 dac33_write(codec, DAC33_ASRC_CTRL_A, DAC33_SRCBYP);
895 dac33_write(codec, DAC33_ASRC_CTRL_B, 0); /* ??? */
898 /* Interrupt behaviour configuration */
899 switch (dac33->fifo_mode) {
900 case DAC33_FIFO_MODE1:
901 dac33_write(codec, DAC33_FIFO_IRQ_MODE_B,
902 DAC33_ATM(DAC33_FIFO_IRQ_MODE_LEVEL));
904 case DAC33_FIFO_MODE7:
905 dac33_write(codec, DAC33_FIFO_IRQ_MODE_A,
906 DAC33_UTM(DAC33_FIFO_IRQ_MODE_LEVEL));
909 /* in FIFO bypass mode, the interrupts are not used */
913 aictrl_b = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_B);
915 switch (dac33->fifo_mode) {
916 case DAC33_FIFO_MODE1:
919 * Disable the FIFO bypass (Enable the use of FIFO)
920 * Select nSample mode
921 * BCLK is only running when data is needed by DAC33
923 fifoctrl_a &= ~DAC33_FBYPAS;
924 fifoctrl_a &= ~DAC33_FAUTO;
925 if (dac33->keep_bclk)
926 aictrl_b |= DAC33_BCLKON;
928 aictrl_b &= ~DAC33_BCLKON;
930 case DAC33_FIFO_MODE7:
933 * Disable the FIFO bypass (Enable the use of FIFO)
934 * Select Threshold mode
935 * BCLK is only running when data is needed by DAC33
937 fifoctrl_a &= ~DAC33_FBYPAS;
938 fifoctrl_a |= DAC33_FAUTO;
939 if (dac33->keep_bclk)
940 aictrl_b |= DAC33_BCLKON;
942 aictrl_b &= ~DAC33_BCLKON;
946 * For FIFO bypass mode:
947 * Enable the FIFO bypass (Disable the FIFO use)
948 * Set the BCLK as continous
950 fifoctrl_a |= DAC33_FBYPAS;
951 aictrl_b |= DAC33_BCLKON;
955 dac33_write(codec, DAC33_FIFO_CTRL_A, fifoctrl_a);
956 dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_A, aictrl_a);
957 dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_B, aictrl_b);
968 if (dac33->fifo_mode)
969 dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_C,
970 dac33->burst_bclkdiv);
972 dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_C, 32);
974 switch (dac33->fifo_mode) {
975 case DAC33_FIFO_MODE1:
976 dac33_write16(codec, DAC33_ATHR_MSB,
977 DAC33_THRREG(dac33->alarm_threshold));
979 case DAC33_FIFO_MODE7:
981 * Configure the threshold levels, and leave 10 sample space
982 * at the bottom, and also at the top of the FIFO
984 dac33_write16(codec, DAC33_UTHR_MSB, DAC33_THRREG(MODE7_UTHR));
985 dac33_write16(codec, DAC33_LTHR_MSB, DAC33_THRREG(MODE7_LTHR));
991 mutex_unlock(&dac33->mutex);
996 static void dac33_calculate_times(struct snd_pcm_substream *substream)
998 struct snd_soc_pcm_runtime *rtd = substream->private_data;
999 struct snd_soc_device *socdev = rtd->socdev;
1000 struct snd_soc_codec *codec = socdev->card->codec;
1001 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
1002 unsigned int nsample_limit;
1004 /* In bypass mode we don't need to calculate */
1005 if (!dac33->fifo_mode)
1008 /* Number of samples (16bit, stereo) in one period */
1009 dac33->nsample_min = snd_pcm_lib_period_bytes(substream) / 4;
1011 /* Number of samples (16bit, stereo) in ALSA buffer */
1012 dac33->nsample_max = snd_pcm_lib_buffer_bytes(substream) / 4;
1013 /* Subtract one period from the total */
1014 dac33->nsample_max -= dac33->nsample_min;
1016 /* Number of samples for LATENCY_TIME_MS / 2 */
1017 dac33->alarm_threshold = substream->runtime->rate /
1018 (1000 / (LATENCY_TIME_MS / 2));
1020 /* Find and fix up the lowest nsmaple limit */
1021 nsample_limit = substream->runtime->rate / (1000 / LATENCY_TIME_MS);
1023 if (dac33->nsample_min < nsample_limit)
1024 dac33->nsample_min = nsample_limit;
1026 if (dac33->nsample < dac33->nsample_min)
1027 dac33->nsample = dac33->nsample_min;
1030 * Find and fix up the highest nsmaple limit
1031 * In order to not overflow the DAC33 buffer substract the
1032 * alarm_threshold value from the size of the DAC33 buffer
1034 nsample_limit = DAC33_BUFFER_SIZE_SAMPLES - dac33->alarm_threshold;
1036 if (dac33->nsample_max > nsample_limit)
1037 dac33->nsample_max = nsample_limit;
1039 if (dac33->nsample > dac33->nsample_max)
1040 dac33->nsample = dac33->nsample_max;
1042 switch (dac33->fifo_mode) {
1043 case DAC33_FIFO_MODE1:
1044 dac33->mode1_us_burst = SAMPLES_TO_US(dac33->burst_rate,
1046 dac33->t_stamp1 = 0;
1047 dac33->t_stamp2 = 0;
1049 case DAC33_FIFO_MODE7:
1050 dac33->mode7_us_to_lthr =
1051 SAMPLES_TO_US(substream->runtime->rate,
1052 MODE7_UTHR - MODE7_LTHR + 1);
1053 dac33->t_stamp1 = 0;
1061 static int dac33_pcm_trigger(struct snd_pcm_substream *substream, int cmd,
1062 struct snd_soc_dai *dai)
1064 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1065 struct snd_soc_device *socdev = rtd->socdev;
1066 struct snd_soc_codec *codec = socdev->card->codec;
1067 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
1071 case SNDRV_PCM_TRIGGER_START:
1072 case SNDRV_PCM_TRIGGER_RESUME:
1073 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1074 if (dac33->fifo_mode) {
1075 dac33->state = DAC33_PREFILL;
1076 queue_work(dac33->dac33_wq, &dac33->work);
1079 case SNDRV_PCM_TRIGGER_STOP:
1080 case SNDRV_PCM_TRIGGER_SUSPEND:
1081 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1082 if (dac33->fifo_mode) {
1083 dac33->state = DAC33_FLUSH;
1084 queue_work(dac33->dac33_wq, &dac33->work);
1094 static snd_pcm_sframes_t dac33_dai_delay(
1095 struct snd_pcm_substream *substream,
1096 struct snd_soc_dai *dai)
1098 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1099 struct snd_soc_device *socdev = rtd->socdev;
1100 struct snd_soc_codec *codec = socdev->card->codec;
1101 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
1102 unsigned long long t0, t1, t_now;
1103 unsigned int time_delta;
1104 int samples_out, samples_in, samples;
1105 snd_pcm_sframes_t delay = 0;
1107 switch (dac33->fifo_mode) {
1108 case DAC33_FIFO_BYPASS:
1110 case DAC33_FIFO_MODE1:
1111 spin_lock(&dac33->lock);
1112 t0 = dac33->t_stamp1;
1113 t1 = dac33->t_stamp2;
1114 spin_unlock(&dac33->lock);
1115 t_now = ktime_to_us(ktime_get());
1117 /* We have not started to fill the FIFO yet, delay is 0 */
1124 * After Alarm threshold, and before nSample write
1126 time_delta = t_now - t0;
1127 samples_out = time_delta ? US_TO_SAMPLES(
1128 substream->runtime->rate,
1131 if (likely(dac33->alarm_threshold > samples_out))
1132 delay = dac33->alarm_threshold - samples_out;
1135 } else if ((t_now - t1) <= dac33->mode1_us_burst) {
1138 * After nSample write (during burst operation)
1140 time_delta = t_now - t0;
1141 samples_out = time_delta ? US_TO_SAMPLES(
1142 substream->runtime->rate,
1145 time_delta = t_now - t1;
1146 samples_in = time_delta ? US_TO_SAMPLES(
1150 samples = dac33->alarm_threshold;
1151 samples += (samples_in - samples_out);
1153 if (likely(samples > 0))
1160 * After burst operation, before next alarm threshold
1162 time_delta = t_now - t0;
1163 samples_out = time_delta ? US_TO_SAMPLES(
1164 substream->runtime->rate,
1167 samples_in = dac33->nsample;
1168 samples = dac33->alarm_threshold;
1169 samples += (samples_in - samples_out);
1171 if (likely(samples > 0))
1172 delay = samples > DAC33_BUFFER_SIZE_SAMPLES ?
1173 DAC33_BUFFER_SIZE_SAMPLES : samples;
1178 case DAC33_FIFO_MODE7:
1179 spin_lock(&dac33->lock);
1180 t0 = dac33->t_stamp1;
1181 spin_unlock(&dac33->lock);
1182 t_now = ktime_to_us(ktime_get());
1184 /* We have not started to fill the FIFO yet, delay is 0 */
1190 * Either the timestamps are messed or equal. Report
1197 time_delta = t_now - t0;
1198 if (time_delta <= dac33->mode7_us_to_lthr) {
1201 * After burst (draining phase)
1203 samples_out = US_TO_SAMPLES(
1204 substream->runtime->rate,
1207 if (likely(MODE7_UTHR > samples_out))
1208 delay = MODE7_UTHR - samples_out;
1214 * During burst operation
1216 time_delta = time_delta - dac33->mode7_us_to_lthr;
1218 samples_out = US_TO_SAMPLES(
1219 substream->runtime->rate,
1221 samples_in = US_TO_SAMPLES(
1224 delay = MODE7_LTHR + samples_in - samples_out;
1226 if (unlikely(delay > MODE7_UTHR))
1231 dev_warn(codec->dev, "Unhandled FIFO mode: %d\n",
1239 static int dac33_set_dai_sysclk(struct snd_soc_dai *codec_dai,
1240 int clk_id, unsigned int freq, int dir)
1242 struct snd_soc_codec *codec = codec_dai->codec;
1243 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
1244 u8 ioc_reg, asrcb_reg;
1246 ioc_reg = dac33_read_reg_cache(codec, DAC33_INT_OSC_CTRL);
1247 asrcb_reg = dac33_read_reg_cache(codec, DAC33_ASRC_CTRL_B);
1249 case TLV320DAC33_MCLK:
1250 ioc_reg |= DAC33_REFSEL;
1251 asrcb_reg |= DAC33_SRCREFSEL;
1253 case TLV320DAC33_SLEEPCLK:
1254 ioc_reg &= ~DAC33_REFSEL;
1255 asrcb_reg &= ~DAC33_SRCREFSEL;
1258 dev_err(codec->dev, "Invalid clock ID (%d)\n", clk_id);
1261 dac33->refclk = freq;
1263 dac33_write_reg_cache(codec, DAC33_INT_OSC_CTRL, ioc_reg);
1264 dac33_write_reg_cache(codec, DAC33_ASRC_CTRL_B, asrcb_reg);
1269 static int dac33_set_dai_fmt(struct snd_soc_dai *codec_dai,
1272 struct snd_soc_codec *codec = codec_dai->codec;
1273 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
1274 u8 aictrl_a, aictrl_b;
1276 aictrl_a = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_A);
1277 aictrl_b = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_B);
1278 /* set master/slave audio interface */
1279 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1280 case SND_SOC_DAIFMT_CBM_CFM:
1282 aictrl_a |= (DAC33_MSBCLK | DAC33_MSWCLK);
1284 case SND_SOC_DAIFMT_CBS_CFS:
1286 if (dac33->fifo_mode) {
1287 dev_err(codec->dev, "FIFO mode requires master mode\n");
1290 aictrl_a &= ~(DAC33_MSBCLK | DAC33_MSWCLK);
1296 aictrl_a &= ~DAC33_AFMT_MASK;
1297 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1298 case SND_SOC_DAIFMT_I2S:
1299 aictrl_a |= DAC33_AFMT_I2S;
1301 case SND_SOC_DAIFMT_DSP_A:
1302 aictrl_a |= DAC33_AFMT_DSP;
1303 aictrl_b &= ~DAC33_DATA_DELAY_MASK;
1304 aictrl_b |= DAC33_DATA_DELAY(0);
1306 case SND_SOC_DAIFMT_RIGHT_J:
1307 aictrl_a |= DAC33_AFMT_RIGHT_J;
1309 case SND_SOC_DAIFMT_LEFT_J:
1310 aictrl_a |= DAC33_AFMT_LEFT_J;
1313 dev_err(codec->dev, "Unsupported format (%u)\n",
1314 fmt & SND_SOC_DAIFMT_FORMAT_MASK);
1318 dac33_write_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_A, aictrl_a);
1319 dac33_write_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_B, aictrl_b);
1324 static int dac33_soc_probe(struct platform_device *pdev)
1326 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1327 struct snd_soc_codec *codec;
1328 struct tlv320dac33_priv *dac33;
1331 BUG_ON(!tlv320dac33_codec);
1333 codec = tlv320dac33_codec;
1334 socdev->card->codec = codec;
1335 dac33 = snd_soc_codec_get_drvdata(codec);
1338 ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
1340 dev_err(codec->dev, "failed to create pcms\n");
1344 snd_soc_add_controls(codec, dac33_snd_controls,
1345 ARRAY_SIZE(dac33_snd_controls));
1346 /* Only add the nSample controls, if we have valid IRQ number */
1347 if (dac33->irq >= 0)
1348 snd_soc_add_controls(codec, dac33_nsample_snd_controls,
1349 ARRAY_SIZE(dac33_nsample_snd_controls));
1351 dac33_add_widgets(codec);
1356 dac33_hard_power(codec, 0);
1360 static int dac33_soc_remove(struct platform_device *pdev)
1362 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1363 struct snd_soc_codec *codec = socdev->card->codec;
1365 dac33_set_bias_level(codec, SND_SOC_BIAS_OFF);
1367 snd_soc_free_pcms(socdev);
1368 snd_soc_dapm_free(socdev);
1373 static int dac33_soc_suspend(struct platform_device *pdev, pm_message_t state)
1375 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1376 struct snd_soc_codec *codec = socdev->card->codec;
1378 dac33_set_bias_level(codec, SND_SOC_BIAS_OFF);
1383 static int dac33_soc_resume(struct platform_device *pdev)
1385 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1386 struct snd_soc_codec *codec = socdev->card->codec;
1388 dac33_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1389 if (codec->suspend_bias_level == SND_SOC_BIAS_ON)
1390 dac33_set_bias_level(codec, SND_SOC_BIAS_PREPARE);
1391 dac33_set_bias_level(codec, codec->suspend_bias_level);
1396 struct snd_soc_codec_device soc_codec_dev_tlv320dac33 = {
1397 .probe = dac33_soc_probe,
1398 .remove = dac33_soc_remove,
1399 .suspend = dac33_soc_suspend,
1400 .resume = dac33_soc_resume,
1402 EXPORT_SYMBOL_GPL(soc_codec_dev_tlv320dac33);
1404 #define DAC33_RATES (SNDRV_PCM_RATE_44100 | \
1405 SNDRV_PCM_RATE_48000)
1406 #define DAC33_FORMATS SNDRV_PCM_FMTBIT_S16_LE
1408 static struct snd_soc_dai_ops dac33_dai_ops = {
1409 .startup = dac33_startup,
1410 .shutdown = dac33_shutdown,
1411 .hw_params = dac33_hw_params,
1412 .trigger = dac33_pcm_trigger,
1413 .delay = dac33_dai_delay,
1414 .set_sysclk = dac33_set_dai_sysclk,
1415 .set_fmt = dac33_set_dai_fmt,
1418 struct snd_soc_dai dac33_dai = {
1419 .name = "tlv320dac33",
1421 .stream_name = "Playback",
1424 .rates = DAC33_RATES,
1425 .formats = DAC33_FORMATS,},
1426 .ops = &dac33_dai_ops,
1428 EXPORT_SYMBOL_GPL(dac33_dai);
1430 static int __devinit dac33_i2c_probe(struct i2c_client *client,
1431 const struct i2c_device_id *id)
1433 struct tlv320dac33_platform_data *pdata;
1434 struct tlv320dac33_priv *dac33;
1435 struct snd_soc_codec *codec;
1438 if (client->dev.platform_data == NULL) {
1439 dev_err(&client->dev, "Platform data not set\n");
1442 pdata = client->dev.platform_data;
1444 dac33 = kzalloc(sizeof(struct tlv320dac33_priv), GFP_KERNEL);
1448 codec = &dac33->codec;
1449 snd_soc_codec_set_drvdata(codec, dac33);
1450 codec->control_data = client;
1452 mutex_init(&codec->mutex);
1453 mutex_init(&dac33->mutex);
1454 spin_lock_init(&dac33->lock);
1455 INIT_LIST_HEAD(&codec->dapm_widgets);
1456 INIT_LIST_HEAD(&codec->dapm_paths);
1458 codec->name = "tlv320dac33";
1459 codec->owner = THIS_MODULE;
1460 codec->read = dac33_read_reg_cache;
1461 codec->write = dac33_write_locked;
1462 codec->hw_write = (hw_write_t) i2c_master_send;
1463 codec->bias_level = SND_SOC_BIAS_OFF;
1464 codec->set_bias_level = dac33_set_bias_level;
1465 codec->idle_bias_off = 1;
1466 codec->dai = &dac33_dai;
1468 codec->reg_cache_size = ARRAY_SIZE(dac33_reg);
1469 codec->reg_cache = kmemdup(dac33_reg, ARRAY_SIZE(dac33_reg),
1471 if (codec->reg_cache == NULL) {
1476 i2c_set_clientdata(client, dac33);
1478 dac33->power_gpio = pdata->power_gpio;
1479 dac33->burst_bclkdiv = pdata->burst_bclkdiv;
1480 /* Pre calculate the burst rate */
1481 dac33->burst_rate = BURST_BASEFREQ_HZ / dac33->burst_bclkdiv / 32;
1482 dac33->keep_bclk = pdata->keep_bclk;
1483 dac33->irq = client->irq;
1484 dac33->nsample = NSAMPLE_MAX;
1485 dac33->nsample_max = NSAMPLE_MAX;
1486 /* Disable FIFO use by default */
1487 dac33->fifo_mode = DAC33_FIFO_BYPASS;
1489 tlv320dac33_codec = codec;
1491 codec->dev = &client->dev;
1492 dac33_dai.dev = codec->dev;
1494 /* Check if the reset GPIO number is valid and request it */
1495 if (dac33->power_gpio >= 0) {
1496 ret = gpio_request(dac33->power_gpio, "tlv320dac33 reset");
1499 "Failed to request reset GPIO (%d)\n",
1501 snd_soc_unregister_dai(&dac33_dai);
1502 snd_soc_unregister_codec(codec);
1505 gpio_direction_output(dac33->power_gpio, 0);
1508 /* Check if the IRQ number is valid and request it */
1509 if (dac33->irq >= 0) {
1510 ret = request_irq(dac33->irq, dac33_interrupt_handler,
1511 IRQF_TRIGGER_RISING | IRQF_DISABLED,
1512 codec->name, codec);
1514 dev_err(codec->dev, "Could not request IRQ%d (%d)\n",
1518 if (dac33->irq != -1) {
1519 /* Setup work queue */
1521 create_singlethread_workqueue("tlv320dac33");
1522 if (dac33->dac33_wq == NULL) {
1523 free_irq(dac33->irq, &dac33->codec);
1528 INIT_WORK(&dac33->work, dac33_work);
1532 for (i = 0; i < ARRAY_SIZE(dac33->supplies); i++)
1533 dac33->supplies[i].supply = dac33_supply_names[i];
1535 ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(dac33->supplies),
1539 dev_err(codec->dev, "Failed to request supplies: %d\n", ret);
1543 /* Read the tlv320dac33 ID registers */
1544 ret = dac33_hard_power(codec, 1);
1546 dev_err(codec->dev, "Failed to power up codec: %d\n", ret);
1549 dac33_read_id(codec);
1550 dac33_hard_power(codec, 0);
1552 ret = snd_soc_register_codec(codec);
1554 dev_err(codec->dev, "Failed to register codec: %d\n", ret);
1558 ret = snd_soc_register_dai(&dac33_dai);
1560 dev_err(codec->dev, "Failed to register DAI: %d\n", ret);
1561 snd_soc_unregister_codec(codec);
1568 regulator_bulk_free(ARRAY_SIZE(dac33->supplies), dac33->supplies);
1570 if (dac33->irq >= 0) {
1571 free_irq(dac33->irq, &dac33->codec);
1572 destroy_workqueue(dac33->dac33_wq);
1575 if (dac33->power_gpio >= 0)
1576 gpio_free(dac33->power_gpio);
1578 kfree(codec->reg_cache);
1580 tlv320dac33_codec = NULL;
1586 static int __devexit dac33_i2c_remove(struct i2c_client *client)
1588 struct tlv320dac33_priv *dac33;
1590 dac33 = i2c_get_clientdata(client);
1592 if (unlikely(dac33->chip_power))
1593 dac33_hard_power(&dac33->codec, 0);
1595 if (dac33->power_gpio >= 0)
1596 gpio_free(dac33->power_gpio);
1597 if (dac33->irq >= 0)
1598 free_irq(dac33->irq, &dac33->codec);
1600 regulator_bulk_free(ARRAY_SIZE(dac33->supplies), dac33->supplies);
1602 destroy_workqueue(dac33->dac33_wq);
1603 snd_soc_unregister_dai(&dac33_dai);
1604 snd_soc_unregister_codec(&dac33->codec);
1605 kfree(dac33->codec.reg_cache);
1607 tlv320dac33_codec = NULL;
1612 static const struct i2c_device_id tlv320dac33_i2c_id[] = {
1614 .name = "tlv320dac33",
1620 static struct i2c_driver tlv320dac33_i2c_driver = {
1622 .name = "tlv320dac33",
1623 .owner = THIS_MODULE,
1625 .probe = dac33_i2c_probe,
1626 .remove = __devexit_p(dac33_i2c_remove),
1627 .id_table = tlv320dac33_i2c_id,
1630 static int __init dac33_module_init(void)
1633 r = i2c_add_driver(&tlv320dac33_i2c_driver);
1635 printk(KERN_ERR "DAC33: driver registration failed\n");
1640 module_init(dac33_module_init);
1642 static void __exit dac33_module_exit(void)
1644 i2c_del_driver(&tlv320dac33_i2c_driver);
1646 module_exit(dac33_module_exit);
1649 MODULE_DESCRIPTION("ASoC TLV320DAC33 codec driver");
1650 MODULE_AUTHOR("Peter Ujfalusi <peter.ujfalusi@nokia.com>");
1651 MODULE_LICENSE("GPL");