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   1 /*
   2  * Driver for ESS Maestro3/Allegro (ES1988) soundcards.
   3  * Copyright (c) 2000 by Zach Brown <zab@zabbo.net>
   4  *                       Takashi Iwai <tiwai@suse.de>
   5  *
   6  * Most of the hardware init stuffs are based on maestro3 driver for
   7  * OSS/Free by Zach Brown.  Many thanks to Zach!
   8  *
   9  *   This program is free software; you can redistribute it and/or modify
  10  *   it under the terms of the GNU General Public License as published by
  11  *   the Free Software Foundation; either version 2 of the License, or
  12  *   (at your option) any later version.
  13  *
  14  *   This program is distributed in the hope that it will be useful,
  15  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *   GNU General Public License for more details.
  18  *
  19  *   You should have received a copy of the GNU General Public License
  20  *   along with this program; if not, write to the Free Software
  21  *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  22  *
  23  *
  24  * ChangeLog:
  25  * Aug. 27, 2001
  26  *     - Fixed deadlock on capture
  27  *     - Added Canyon3D-2 support by Rob Riggs <rob@pangalactic.org>
  28  *
  29  */
  30
  31 #define CARD_NAME "ESS Maestro3/Allegro/Canyon3D-2"
  32 #define DRIVER_NAME "Maestro3"
  33
  34 #include <sound/driver.h>
  35 #include <asm/io.h>
  36 #include <linux/delay.h>
  37 #include <linux/interrupt.h>
  38 #include <linux/init.h>
  39 #include <linux/pci.h>
  40 #include <linux/slab.h>
  41 #include <linux/vmalloc.h>
  42 #include <linux/moduleparam.h>
  43 #include <sound/core.h>
  44 #include <sound/info.h>
  45 #include <sound/control.h>
  46 #include <sound/pcm.h>
  47 #include <sound/mpu401.h>
  48 #include <sound/ac97_codec.h>
  49 #include <sound/initval.h>
  50
  51 MODULE_AUTHOR("Zach Brown <zab@zabbo.net>, Takashi Iwai <tiwai@suse.de>");
  52 MODULE_DESCRIPTION("ESS Maestro3 PCI");
  53 MODULE_LICENSE("GPL");
  54 MODULE_SUPPORTED_DEVICE("{{ESS,Maestro3 PCI},"
  55                 "{ESS,ES1988},"
  56                 "{ESS,Allegro PCI},"
  57                 "{ESS,Allegro-1 PCI},"
  58                 "{ESS,Canyon3D-2/LE PCI}}");
  59
  60 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;      /* Index 0-MAX */
  61 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;       /* ID for this card */
  62 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* all enabled */
  63 static int external_amp[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 1};
  64 static int amp_gpio[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = -1};
  65
  66 module_param_array(index, int, NULL, 0444);
  67 MODULE_PARM_DESC(index, "Index value for " CARD_NAME " soundcard.");
  68 module_param_array(id, charp, NULL, 0444);
  69 MODULE_PARM_DESC(id, "ID string for " CARD_NAME " soundcard.");
  70 module_param_array(enable, bool, NULL, 0444);
  71 MODULE_PARM_DESC(enable, "Enable this soundcard.");
  72 module_param_array(external_amp, bool, NULL, 0444);
  73 MODULE_PARM_DESC(external_amp, "Enable external amp for " CARD_NAME " soundcard.");
  74 module_param_array(amp_gpio, int, NULL, 0444);
  75 MODULE_PARM_DESC(amp_gpio, "GPIO pin number for external amp. (default = -1)");
  76
  77 #define MAX_PLAYBACKS   2
  78 #define MAX_CAPTURES    1
  79 #define NR_DSPS         (MAX_PLAYBACKS + MAX_CAPTURES)
  80
  81
  82 /*
  83  * maestro3 registers
  84  */
  85
  86 /* Allegro PCI configuration registers */
  87 #define PCI_LEGACY_AUDIO_CTRL   0x40
  88 #define SOUND_BLASTER_ENABLE    0x00000001
  89 #define FM_SYNTHESIS_ENABLE     0x00000002
  90 #define GAME_PORT_ENABLE        0x00000004
  91 #define MPU401_IO_ENABLE        0x00000008
  92 #define MPU401_IRQ_ENABLE       0x00000010
  93 #define ALIAS_10BIT_IO          0x00000020
  94 #define SB_DMA_MASK             0x000000C0
  95 #define SB_DMA_0                0x00000040
  96 #define SB_DMA_1                0x00000040
  97 #define SB_DMA_R                0x00000080
  98 #define SB_DMA_3                0x000000C0
  99 #define SB_IRQ_MASK             0x00000700
 100 #define SB_IRQ_5                0x00000000
 101 #define SB_IRQ_7                0x00000100
 102 #define SB_IRQ_9                0x00000200
 103 #define SB_IRQ_10               0x00000300
 104 #define MIDI_IRQ_MASK           0x00003800
 105 #define SERIAL_IRQ_ENABLE       0x00004000
 106 #define DISABLE_LEGACY          0x00008000
 107
 108 #define PCI_ALLEGRO_CONFIG      0x50
 109 #define SB_ADDR_240             0x00000004
 110 #define MPU_ADDR_MASK           0x00000018
 111 #define MPU_ADDR_330            0x00000000
 112 #define MPU_ADDR_300            0x00000008
 113 #define MPU_ADDR_320            0x00000010
 114 #define MPU_ADDR_340            0x00000018
 115 #define USE_PCI_TIMING          0x00000040
 116 #define POSTED_WRITE_ENABLE     0x00000080
 117 #define DMA_POLICY_MASK         0x00000700
 118 #define DMA_DDMA                0x00000000
 119 #define DMA_TDMA                0x00000100
 120 #define DMA_PCPCI               0x00000200
 121 #define DMA_WBDMA16             0x00000400
 122 #define DMA_WBDMA4              0x00000500
 123 #define DMA_WBDMA2              0x00000600
 124 #define DMA_WBDMA1              0x00000700
 125 #define DMA_SAFE_GUARD          0x00000800
 126 #define HI_PERF_GP_ENABLE       0x00001000
 127 #define PIC_SNOOP_MODE_0        0x00002000
 128 #define PIC_SNOOP_MODE_1        0x00004000
 129 #define SOUNDBLASTER_IRQ_MASK   0x00008000
 130 #define RING_IN_ENABLE          0x00010000
 131 #define SPDIF_TEST_MODE         0x00020000
 132 #define CLK_MULT_MODE_SELECT_2  0x00040000
 133 #define EEPROM_WRITE_ENABLE     0x00080000
 134 #define CODEC_DIR_IN            0x00100000
 135 #define HV_BUTTON_FROM_GD       0x00200000
 136 #define REDUCED_DEBOUNCE        0x00400000
 137 #define HV_CTRL_ENABLE          0x00800000
 138 #define SPDIF_ENABLE            0x01000000
 139 #define CLK_DIV_SELECT          0x06000000
 140 #define CLK_DIV_BY_48           0x00000000
 141 #define CLK_DIV_BY_49           0x02000000
 142 #define CLK_DIV_BY_50           0x04000000
 143 #define CLK_DIV_RESERVED        0x06000000
 144 #define PM_CTRL_ENABLE          0x08000000
 145 #define CLK_MULT_MODE_SELECT    0x30000000
 146 #define CLK_MULT_MODE_SHIFT     28
 147 #define CLK_MULT_MODE_0         0x00000000
 148 #define CLK_MULT_MODE_1         0x10000000
 149 #define CLK_MULT_MODE_2         0x20000000
 150 #define CLK_MULT_MODE_3         0x30000000
 151 #define INT_CLK_SELECT          0x40000000
 152 #define INT_CLK_MULT_RESET      0x80000000
 153
 154 /* M3 */
 155 #define INT_CLK_SRC_NOT_PCI     0x00100000
 156 #define INT_CLK_MULT_ENABLE     0x80000000
 157
 158 #define PCI_ACPI_CONTROL        0x54
 159 #define PCI_ACPI_D0             0x00000000
 160 #define PCI_ACPI_D1             0xB4F70000
 161 #define PCI_ACPI_D2             0xB4F7B4F7
 162
 163 #define PCI_USER_CONFIG         0x58
 164 #define EXT_PCI_MASTER_ENABLE   0x00000001
 165 #define SPDIF_OUT_SELECT        0x00000002
 166 #define TEST_PIN_DIR_CTRL       0x00000004
 167 #define AC97_CODEC_TEST         0x00000020
 168 #define TRI_STATE_BUFFER        0x00000080
 169 #define IN_CLK_12MHZ_SELECT     0x00000100
 170 #define MULTI_FUNC_DISABLE      0x00000200
 171 #define EXT_MASTER_PAIR_SEL     0x00000400
 172 #define PCI_MASTER_SUPPORT      0x00000800
 173 #define STOP_CLOCK_ENABLE       0x00001000
 174 #define EAPD_DRIVE_ENABLE       0x00002000
 175 #define REQ_TRI_STATE_ENABLE    0x00004000
 176 #define REQ_LOW_ENABLE          0x00008000
 177 #define MIDI_1_ENABLE           0x00010000
 178 #define MIDI_2_ENABLE           0x00020000
 179 #define SB_AUDIO_SYNC           0x00040000
 180 #define HV_CTRL_TEST            0x00100000
 181 #define SOUNDBLASTER_TEST       0x00400000
 182
 183 #define PCI_USER_CONFIG_C       0x5C
 184
 185 #define PCI_DDMA_CTRL           0x60
 186 #define DDMA_ENABLE             0x00000001
 187
 188
 189 /* Allegro registers */
 190 #define HOST_INT_CTRL           0x18
 191 #define SB_INT_ENABLE           0x0001
 192 #define MPU401_INT_ENABLE       0x0002
 193 #define ASSP_INT_ENABLE         0x0010
 194 #define RING_INT_ENABLE         0x0020
 195 #define HV_INT_ENABLE           0x0040
 196 #define CLKRUN_GEN_ENABLE       0x0100
 197 #define HV_CTRL_TO_PME          0x0400
 198 #define SOFTWARE_RESET_ENABLE   0x8000
 199
 200 /*
 201  * should be using the above defines, probably.
 202  */
 203 #define REGB_ENABLE_RESET               0x01
 204 #define REGB_STOP_CLOCK                 0x10
 205
 206 #define HOST_INT_STATUS         0x1A
 207 #define SB_INT_PENDING          0x01
 208 #define MPU401_INT_PENDING      0x02
 209 #define ASSP_INT_PENDING        0x10
 210 #define RING_INT_PENDING        0x20
 211 #define HV_INT_PENDING          0x40
 212
 213 #define HARDWARE_VOL_CTRL       0x1B
 214 #define SHADOW_MIX_REG_VOICE    0x1C
 215 #define HW_VOL_COUNTER_VOICE    0x1D
 216 #define SHADOW_MIX_REG_MASTER   0x1E
 217 #define HW_VOL_COUNTER_MASTER   0x1F
 218
 219 #define CODEC_COMMAND           0x30
 220 #define CODEC_READ_B            0x80
 221
 222 #define CODEC_STATUS            0x30
 223 #define CODEC_BUSY_B            0x01
 224
 225 #define CODEC_DATA              0x32
 226
 227 #define RING_BUS_CTRL_A         0x36
 228 #define RAC_PME_ENABLE          0x0100
 229 #define RAC_SDFS_ENABLE         0x0200
 230 #define LAC_PME_ENABLE          0x0400
 231 #define LAC_SDFS_ENABLE         0x0800
 232 #define SERIAL_AC_LINK_ENABLE   0x1000
 233 #define IO_SRAM_ENABLE          0x2000
 234 #define IIS_INPUT_ENABLE        0x8000
 235
 236 #define RING_BUS_CTRL_B         0x38
 237 #define SECOND_CODEC_ID_MASK    0x0003
 238 #define SPDIF_FUNC_ENABLE       0x0010
 239 #define SECOND_AC_ENABLE        0x0020
 240 #define SB_MODULE_INTF_ENABLE   0x0040
 241 #define SSPE_ENABLE             0x0040
 242 #define M3I_DOCK_ENABLE         0x0080
 243
 244 #define SDO_OUT_DEST_CTRL       0x3A
 245 #define COMMAND_ADDR_OUT        0x0003
 246 #define PCM_LR_OUT_LOCAL        0x0000
 247 #define PCM_LR_OUT_REMOTE       0x0004
 248 #define PCM_LR_OUT_MUTE         0x0008
 249 #define PCM_LR_OUT_BOTH         0x000C
 250 #define LINE1_DAC_OUT_LOCAL     0x0000
 251 #define LINE1_DAC_OUT_REMOTE    0x0010
 252 #define LINE1_DAC_OUT_MUTE      0x0020
 253 #define LINE1_DAC_OUT_BOTH      0x0030
 254 #define PCM_CLS_OUT_LOCAL       0x0000
 255 #define PCM_CLS_OUT_REMOTE      0x0040
 256 #define PCM_CLS_OUT_MUTE        0x0080
 257 #define PCM_CLS_OUT_BOTH        0x00C0
 258 #define PCM_RLF_OUT_LOCAL       0x0000
 259 #define PCM_RLF_OUT_REMOTE      0x0100
 260 #define PCM_RLF_OUT_MUTE        0x0200
 261 #define PCM_RLF_OUT_BOTH        0x0300
 262 #define LINE2_DAC_OUT_LOCAL     0x0000
 263 #define LINE2_DAC_OUT_REMOTE    0x0400
 264 #define LINE2_DAC_OUT_MUTE      0x0800
 265 #define LINE2_DAC_OUT_BOTH      0x0C00
 266 #define HANDSET_OUT_LOCAL       0x0000
 267 #define HANDSET_OUT_REMOTE      0x1000
 268 #define HANDSET_OUT_MUTE        0x2000
 269 #define HANDSET_OUT_BOTH        0x3000
 270 #define IO_CTRL_OUT_LOCAL       0x0000
 271 #define IO_CTRL_OUT_REMOTE      0x4000
 272 #define IO_CTRL_OUT_MUTE        0x8000
 273 #define IO_CTRL_OUT_BOTH        0xC000
 274
 275 #define SDO_IN_DEST_CTRL        0x3C
 276 #define STATUS_ADDR_IN          0x0003
 277 #define PCM_LR_IN_LOCAL         0x0000
 278 #define PCM_LR_IN_REMOTE        0x0004
 279 #define PCM_LR_RESERVED         0x0008
 280 #define PCM_LR_IN_BOTH          0x000C
 281 #define LINE1_ADC_IN_LOCAL      0x0000
 282 #define LINE1_ADC_IN_REMOTE     0x0010
 283 #define LINE1_ADC_IN_MUTE       0x0020
 284 #define MIC_ADC_IN_LOCAL        0x0000
 285 #define MIC_ADC_IN_REMOTE       0x0040
 286 #define MIC_ADC_IN_MUTE         0x0080
 287 #define LINE2_DAC_IN_LOCAL      0x0000
 288 #define LINE2_DAC_IN_REMOTE     0x0400
 289 #define LINE2_DAC_IN_MUTE       0x0800
 290 #define HANDSET_IN_LOCAL        0x0000
 291 #define HANDSET_IN_REMOTE       0x1000
 292 #define HANDSET_IN_MUTE         0x2000
 293 #define IO_STATUS_IN_LOCAL      0x0000
 294 #define IO_STATUS_IN_REMOTE     0x4000
 295
 296 #define SPDIF_IN_CTRL           0x3E
 297 #define SPDIF_IN_ENABLE         0x0001
 298
 299 #define GPIO_DATA               0x60
 300 #define GPIO_DATA_MASK          0x0FFF
 301 #define GPIO_HV_STATUS          0x3000
 302 #define GPIO_PME_STATUS         0x4000
 303
 304 #define GPIO_MASK               0x64
 305 #define GPIO_DIRECTION          0x68
 306 #define GPO_PRIMARY_AC97        0x0001
 307 #define GPI_LINEOUT_SENSE       0x0004
 308 #define GPO_SECONDARY_AC97      0x0008
 309 #define GPI_VOL_DOWN            0x0010
 310 #define GPI_VOL_UP              0x0020
 311 #define GPI_IIS_CLK             0x0040
 312 #define GPI_IIS_LRCLK           0x0080
 313 #define GPI_IIS_DATA            0x0100
 314 #define GPI_DOCKING_STATUS      0x0100
 315 #define GPI_HEADPHONE_SENSE     0x0200
 316 #define GPO_EXT_AMP_SHUTDOWN    0x1000
 317
 318 #define GPO_EXT_AMP_M3          1       /* default m3 amp */
 319 #define GPO_EXT_AMP_ALLEGRO     8       /* default allegro amp */
 320
 321 /* M3 */
 322 #define GPO_M3_EXT_AMP_SHUTDN   0x0002
 323
 324 #define ASSP_INDEX_PORT         0x80
 325 #define ASSP_MEMORY_PORT        0x82
 326 #define ASSP_DATA_PORT          0x84
 327
 328 #define MPU401_DATA_PORT        0x98
 329 #define MPU401_STATUS_PORT      0x99
 330
 331 #define CLK_MULT_DATA_PORT      0x9C
 332
 333 #define ASSP_CONTROL_A          0xA2
 334 #define ASSP_0_WS_ENABLE        0x01
 335 #define ASSP_CTRL_A_RESERVED1   0x02
 336 #define ASSP_CTRL_A_RESERVED2   0x04
 337 #define ASSP_CLK_49MHZ_SELECT   0x08
 338 #define FAST_PLU_ENABLE         0x10
 339 #define ASSP_CTRL_A_RESERVED3   0x20
 340 #define DSP_CLK_36MHZ_SELECT    0x40
 341
 342 #define ASSP_CONTROL_B          0xA4
 343 #define RESET_ASSP              0x00
 344 #define RUN_ASSP                0x01
 345 #define ENABLE_ASSP_CLOCK       0x00
 346 #define STOP_ASSP_CLOCK         0x10
 347 #define RESET_TOGGLE            0x40
 348
 349 #define ASSP_CONTROL_C          0xA6
 350 #define ASSP_HOST_INT_ENABLE    0x01
 351 #define FM_ADDR_REMAP_DISABLE   0x02
 352 #define HOST_WRITE_PORT_ENABLE  0x08
 353
 354 #define ASSP_HOST_INT_STATUS    0xAC
 355 #define DSP2HOST_REQ_PIORECORD  0x01
 356 #define DSP2HOST_REQ_I2SRATE    0x02
 357 #define DSP2HOST_REQ_TIMER      0x04
 358
 359 /* AC97 registers */
 360 /* XXX fix this crap up */
 361 /*#define AC97_RESET              0x00*/
 362
 363 #define AC97_VOL_MUTE_B         0x8000
 364 #define AC97_VOL_M              0x1F
 365 #define AC97_LEFT_VOL_S         8
 366
 367 #define AC97_MASTER_VOL         0x02
 368 #define AC97_LINE_LEVEL_VOL     0x04
 369 #define AC97_MASTER_MONO_VOL    0x06
 370 #define AC97_PC_BEEP_VOL        0x0A
 371 #define AC97_PC_BEEP_VOL_M      0x0F
 372 #define AC97_SROUND_MASTER_VOL  0x38
 373 #define AC97_PC_BEEP_VOL_S      1
 374
 375 /*#define AC97_PHONE_VOL          0x0C
 376 #define AC97_MIC_VOL            0x0E*/
 377 #define AC97_MIC_20DB_ENABLE    0x40
 378
 379 /*#define AC97_LINEIN_VOL         0x10
 380 #define AC97_CD_VOL             0x12
 381 #define AC97_VIDEO_VOL          0x14
 382 #define AC97_AUX_VOL            0x16*/
 383 #define AC97_PCM_OUT_VOL        0x18
 384 /*#define AC97_RECORD_SELECT      0x1A*/
 385 #define AC97_RECORD_MIC         0x00
 386 #define AC97_RECORD_CD          0x01
 387 #define AC97_RECORD_VIDEO       0x02
 388 #define AC97_RECORD_AUX         0x03
 389 #define AC97_RECORD_MONO_MUX    0x02
 390 #define AC97_RECORD_DIGITAL     0x03
 391 #define AC97_RECORD_LINE        0x04
 392 #define AC97_RECORD_STEREO      0x05
 393 #define AC97_RECORD_MONO        0x06
 394 #define AC97_RECORD_PHONE       0x07
 395
 396 /*#define AC97_RECORD_GAIN        0x1C*/
 397 #define AC97_RECORD_VOL_M       0x0F
 398
 399 /*#define AC97_GENERAL_PURPOSE    0x20*/
 400 #define AC97_POWER_DOWN_CTRL    0x26
 401 #define AC97_ADC_READY          0x0001
 402 #define AC97_DAC_READY          0x0002
 403 #define AC97_ANALOG_READY       0x0004
 404 #define AC97_VREF_ON            0x0008
 405 #define AC97_PR0                0x0100
 406 #define AC97_PR1                0x0200
 407 #define AC97_PR2                0x0400
 408 #define AC97_PR3                0x0800
 409 #define AC97_PR4                0x1000
 410
 411 #define AC97_RESERVED1          0x28
 412
 413 #define AC97_VENDOR_TEST        0x5A
 414
 415 #define AC97_CLOCK_DELAY        0x5C
 416 #define AC97_LINEOUT_MUX_SEL    0x0001
 417 #define AC97_MONO_MUX_SEL       0x0002
 418 #define AC97_CLOCK_DELAY_SEL    0x1F
 419 #define AC97_DAC_CDS_SHIFT      6
 420 #define AC97_ADC_CDS_SHIFT      11
 421
 422 #define AC97_MULTI_CHANNEL_SEL  0x74
 423
 424 /*#define AC97_VENDOR_ID1         0x7C
 425 #define AC97_VENDOR_ID2         0x7E*/
 426
 427 /*
 428  * ASSP control regs
 429  */
 430 #define DSP_PORT_TIMER_COUNT    0x06
 431
 432 #define DSP_PORT_MEMORY_INDEX   0x80
 433
 434 #define DSP_PORT_MEMORY_TYPE    0x82
 435 #define MEMTYPE_INTERNAL_CODE   0x0002
 436 #define MEMTYPE_INTERNAL_DATA   0x0003
 437 #define MEMTYPE_MASK            0x0003
 438
 439 #define DSP_PORT_MEMORY_DATA    0x84
 440
 441 #define DSP_PORT_CONTROL_REG_A  0xA2
 442 #define DSP_PORT_CONTROL_REG_B  0xA4
 443 #define DSP_PORT_CONTROL_REG_C  0xA6
 444
 445 #define REV_A_CODE_MEMORY_BEGIN         0x0000
 446 #define REV_A_CODE_MEMORY_END           0x0FFF
 447 #define REV_A_CODE_MEMORY_UNIT_LENGTH   0x0040
 448 #define REV_A_CODE_MEMORY_LENGTH        (REV_A_CODE_MEMORY_END - REV_A_CODE_MEMORY_BEGIN + 1)
 449
 450 #define REV_B_CODE_MEMORY_BEGIN         0x0000
 451 #define REV_B_CODE_MEMORY_END           0x0BFF
 452 #define REV_B_CODE_MEMORY_UNIT_LENGTH   0x0040
 453 #define REV_B_CODE_MEMORY_LENGTH        (REV_B_CODE_MEMORY_END - REV_B_CODE_MEMORY_BEGIN + 1)
 454
 455 #define REV_A_DATA_MEMORY_BEGIN         0x1000
 456 #define REV_A_DATA_MEMORY_END           0x2FFF
 457 #define REV_A_DATA_MEMORY_UNIT_LENGTH   0x0080
 458 #define REV_A_DATA_MEMORY_LENGTH        (REV_A_DATA_MEMORY_END - REV_A_DATA_MEMORY_BEGIN + 1)
 459
 460 #define REV_B_DATA_MEMORY_BEGIN         0x1000
 461 #define REV_B_DATA_MEMORY_END           0x2BFF
 462 #define REV_B_DATA_MEMORY_UNIT_LENGTH   0x0080
 463 #define REV_B_DATA_MEMORY_LENGTH        (REV_B_DATA_MEMORY_END - REV_B_DATA_MEMORY_BEGIN + 1)
 464
 465
 466 #define NUM_UNITS_KERNEL_CODE          16
 467 #define NUM_UNITS_KERNEL_DATA           2
 468
 469 #define NUM_UNITS_KERNEL_CODE_WITH_HSP 16
 470 #define NUM_UNITS_KERNEL_DATA_WITH_HSP  5
 471
 472 /*
 473  * Kernel data layout
 474  */
 475
 476 #define DP_SHIFT_COUNT                  7
 477
 478 #define KDATA_BASE_ADDR                 0x1000
 479 #define KDATA_BASE_ADDR2                0x1080
 480
 481 #define KDATA_TASK0                     (KDATA_BASE_ADDR + 0x0000)
 482 #define KDATA_TASK1                     (KDATA_BASE_ADDR + 0x0001)
 483 #define KDATA_TASK2                     (KDATA_BASE_ADDR + 0x0002)
 484 #define KDATA_TASK3                     (KDATA_BASE_ADDR + 0x0003)
 485 #define KDATA_TASK4                     (KDATA_BASE_ADDR + 0x0004)
 486 #define KDATA_TASK5                     (KDATA_BASE_ADDR + 0x0005)
 487 #define KDATA_TASK6                     (KDATA_BASE_ADDR + 0x0006)
 488 #define KDATA_TASK7                     (KDATA_BASE_ADDR + 0x0007)
 489 #define KDATA_TASK_ENDMARK              (KDATA_BASE_ADDR + 0x0008)
 490
 491 #define KDATA_CURRENT_TASK              (KDATA_BASE_ADDR + 0x0009)
 492 #define KDATA_TASK_SWITCH               (KDATA_BASE_ADDR + 0x000A)
 493
 494 #define KDATA_INSTANCE0_POS3D           (KDATA_BASE_ADDR + 0x000B)
 495 #define KDATA_INSTANCE1_POS3D           (KDATA_BASE_ADDR + 0x000C)
 496 #define KDATA_INSTANCE2_POS3D           (KDATA_BASE_ADDR + 0x000D)
 497 #define KDATA_INSTANCE3_POS3D           (KDATA_BASE_ADDR + 0x000E)
 498 #define KDATA_INSTANCE4_POS3D           (KDATA_BASE_ADDR + 0x000F)
 499 #define KDATA_INSTANCE5_POS3D           (KDATA_BASE_ADDR + 0x0010)
 500 #define KDATA_INSTANCE6_POS3D           (KDATA_BASE_ADDR + 0x0011)
 501 #define KDATA_INSTANCE7_POS3D           (KDATA_BASE_ADDR + 0x0012)
 502 #define KDATA_INSTANCE8_POS3D           (KDATA_BASE_ADDR + 0x0013)
 503 #define KDATA_INSTANCE_POS3D_ENDMARK    (KDATA_BASE_ADDR + 0x0014)
 504
 505 #define KDATA_INSTANCE0_SPKVIRT         (KDATA_BASE_ADDR + 0x0015)
 506 #define KDATA_INSTANCE_SPKVIRT_ENDMARK  (KDATA_BASE_ADDR + 0x0016)
 507
 508 #define KDATA_INSTANCE0_SPDIF           (KDATA_BASE_ADDR + 0x0017)
 509 #define KDATA_INSTANCE_SPDIF_ENDMARK    (KDATA_BASE_ADDR + 0x0018)
 510
 511 #define KDATA_INSTANCE0_MODEM           (KDATA_BASE_ADDR + 0x0019)
 512 #define KDATA_INSTANCE_MODEM_ENDMARK    (KDATA_BASE_ADDR + 0x001A)
 513
 514 #define KDATA_INSTANCE0_SRC             (KDATA_BASE_ADDR + 0x001B)
 515 #define KDATA_INSTANCE1_SRC             (KDATA_BASE_ADDR + 0x001C)
 516 #define KDATA_INSTANCE_SRC_ENDMARK      (KDATA_BASE_ADDR + 0x001D)
 517
 518 #define KDATA_INSTANCE0_MINISRC         (KDATA_BASE_ADDR + 0x001E)
 519 #define KDATA_INSTANCE1_MINISRC         (KDATA_BASE_ADDR + 0x001F)
 520 #define KDATA_INSTANCE2_MINISRC         (KDATA_BASE_ADDR + 0x0020)
 521 #define KDATA_INSTANCE3_MINISRC         (KDATA_BASE_ADDR + 0x0021)
 522 #define KDATA_INSTANCE_MINISRC_ENDMARK  (KDATA_BASE_ADDR + 0x0022)
 523
 524 #define KDATA_INSTANCE0_CPYTHRU         (KDATA_BASE_ADDR + 0x0023)
 525 #define KDATA_INSTANCE1_CPYTHRU         (KDATA_BASE_ADDR + 0x0024)
 526 #define KDATA_INSTANCE_CPYTHRU_ENDMARK  (KDATA_BASE_ADDR + 0x0025)
 527
 528 #define KDATA_CURRENT_DMA               (KDATA_BASE_ADDR + 0x0026)
 529 #define KDATA_DMA_SWITCH                (KDATA_BASE_ADDR + 0x0027)
 530 #define KDATA_DMA_ACTIVE                (KDATA_BASE_ADDR + 0x0028)
 531
 532 #define KDATA_DMA_XFER0                 (KDATA_BASE_ADDR + 0x0029)
 533 #define KDATA_DMA_XFER1                 (KDATA_BASE_ADDR + 0x002A)
 534 #define KDATA_DMA_XFER2                 (KDATA_BASE_ADDR + 0x002B)
 535 #define KDATA_DMA_XFER3                 (KDATA_BASE_ADDR + 0x002C)
 536 #define KDATA_DMA_XFER4                 (KDATA_BASE_ADDR + 0x002D)
 537 #define KDATA_DMA_XFER5                 (KDATA_BASE_ADDR + 0x002E)
 538 #define KDATA_DMA_XFER6                 (KDATA_BASE_ADDR + 0x002F)
 539 #define KDATA_DMA_XFER7                 (KDATA_BASE_ADDR + 0x0030)
 540 #define KDATA_DMA_XFER8                 (KDATA_BASE_ADDR + 0x0031)
 541 #define KDATA_DMA_XFER_ENDMARK          (KDATA_BASE_ADDR + 0x0032)
 542
 543 #define KDATA_I2S_SAMPLE_COUNT          (KDATA_BASE_ADDR + 0x0033)
 544 #define KDATA_I2S_INT_METER             (KDATA_BASE_ADDR + 0x0034)
 545 #define KDATA_I2S_ACTIVE                (KDATA_BASE_ADDR + 0x0035)
 546
 547 #define KDATA_TIMER_COUNT_RELOAD        (KDATA_BASE_ADDR + 0x0036)
 548 #define KDATA_TIMER_COUNT_CURRENT       (KDATA_BASE_ADDR + 0x0037)
 549
 550 #define KDATA_HALT_SYNCH_CLIENT         (KDATA_BASE_ADDR + 0x0038)
 551 #define KDATA_HALT_SYNCH_DMA            (KDATA_BASE_ADDR + 0x0039)
 552 #define KDATA_HALT_ACKNOWLEDGE          (KDATA_BASE_ADDR + 0x003A)
 553
 554 #define KDATA_ADC1_XFER0                (KDATA_BASE_ADDR + 0x003B)
 555 #define KDATA_ADC1_XFER_ENDMARK         (KDATA_BASE_ADDR + 0x003C)
 556 #define KDATA_ADC1_LEFT_VOLUME                  (KDATA_BASE_ADDR + 0x003D)
 557 #define KDATA_ADC1_RIGHT_VOLUME                 (KDATA_BASE_ADDR + 0x003E)
 558 #define KDATA_ADC1_LEFT_SUR_VOL                 (KDATA_BASE_ADDR + 0x003F)
 559 #define KDATA_ADC1_RIGHT_SUR_VOL                (KDATA_BASE_ADDR + 0x0040)
 560
 561 #define KDATA_ADC2_XFER0                (KDATA_BASE_ADDR + 0x0041)
 562 #define KDATA_ADC2_XFER_ENDMARK         (KDATA_BASE_ADDR + 0x0042)
 563 #define KDATA_ADC2_LEFT_VOLUME                  (KDATA_BASE_ADDR + 0x0043)
 564 #define KDATA_ADC2_RIGHT_VOLUME                 (KDATA_BASE_ADDR + 0x0044)
 565 #define KDATA_ADC2_LEFT_SUR_VOL                 (KDATA_BASE_ADDR + 0x0045)
 566 #define KDATA_ADC2_RIGHT_SUR_VOL                (KDATA_BASE_ADDR + 0x0046)
 567
 568 #define KDATA_CD_XFER0                                  (KDATA_BASE_ADDR + 0x0047)
 569 #define KDATA_CD_XFER_ENDMARK                   (KDATA_BASE_ADDR + 0x0048)
 570 #define KDATA_CD_LEFT_VOLUME                    (KDATA_BASE_ADDR + 0x0049)
 571 #define KDATA_CD_RIGHT_VOLUME                   (KDATA_BASE_ADDR + 0x004A)
 572 #define KDATA_CD_LEFT_SUR_VOL                   (KDATA_BASE_ADDR + 0x004B)
 573 #define KDATA_CD_RIGHT_SUR_VOL                  (KDATA_BASE_ADDR + 0x004C)
 574
 575 #define KDATA_MIC_XFER0                                 (KDATA_BASE_ADDR + 0x004D)
 576 #define KDATA_MIC_XFER_ENDMARK                  (KDATA_BASE_ADDR + 0x004E)
 577 #define KDATA_MIC_VOLUME                                (KDATA_BASE_ADDR + 0x004F)
 578 #define KDATA_MIC_SUR_VOL                               (KDATA_BASE_ADDR + 0x0050)
 579
 580 #define KDATA_I2S_XFER0                 (KDATA_BASE_ADDR + 0x0051)
 581 #define KDATA_I2S_XFER_ENDMARK          (KDATA_BASE_ADDR + 0x0052)
 582
 583 #define KDATA_CHI_XFER0                 (KDATA_BASE_ADDR + 0x0053)
 584 #define KDATA_CHI_XFER_ENDMARK          (KDATA_BASE_ADDR + 0x0054)
 585
 586 #define KDATA_SPDIF_XFER                (KDATA_BASE_ADDR + 0x0055)
 587 #define KDATA_SPDIF_CURRENT_FRAME       (KDATA_BASE_ADDR + 0x0056)
 588 #define KDATA_SPDIF_FRAME0              (KDATA_BASE_ADDR + 0x0057)
 589 #define KDATA_SPDIF_FRAME1              (KDATA_BASE_ADDR + 0x0058)
 590 #define KDATA_SPDIF_FRAME2              (KDATA_BASE_ADDR + 0x0059)
 591
 592 #define KDATA_SPDIF_REQUEST             (KDATA_BASE_ADDR + 0x005A)
 593 #define KDATA_SPDIF_TEMP                (KDATA_BASE_ADDR + 0x005B)
 594
 595 #define KDATA_SPDIFIN_XFER0             (KDATA_BASE_ADDR + 0x005C)
 596 #define KDATA_SPDIFIN_XFER_ENDMARK      (KDATA_BASE_ADDR + 0x005D)
 597 #define KDATA_SPDIFIN_INT_METER         (KDATA_BASE_ADDR + 0x005E)
 598
 599 #define KDATA_DSP_RESET_COUNT           (KDATA_BASE_ADDR + 0x005F)
 600 #define KDATA_DEBUG_OUTPUT              (KDATA_BASE_ADDR + 0x0060)
 601
 602 #define KDATA_KERNEL_ISR_LIST           (KDATA_BASE_ADDR + 0x0061)
 603
 604 #define KDATA_KERNEL_ISR_CBSR1          (KDATA_BASE_ADDR + 0x0062)
 605 #define KDATA_KERNEL_ISR_CBER1          (KDATA_BASE_ADDR + 0x0063)
 606 #define KDATA_KERNEL_ISR_CBCR           (KDATA_BASE_ADDR + 0x0064)
 607 #define KDATA_KERNEL_ISR_AR0            (KDATA_BASE_ADDR + 0x0065)
 608 #define KDATA_KERNEL_ISR_AR1            (KDATA_BASE_ADDR + 0x0066)
 609 #define KDATA_KERNEL_ISR_AR2            (KDATA_BASE_ADDR + 0x0067)
 610 #define KDATA_KERNEL_ISR_AR3            (KDATA_BASE_ADDR + 0x0068)
 611 #define KDATA_KERNEL_ISR_AR4            (KDATA_BASE_ADDR + 0x0069)
 612 #define KDATA_KERNEL_ISR_AR5            (KDATA_BASE_ADDR + 0x006A)
 613 #define KDATA_KERNEL_ISR_BRCR           (KDATA_BASE_ADDR + 0x006B)
 614 #define KDATA_KERNEL_ISR_PASR           (KDATA_BASE_ADDR + 0x006C)
 615 #define KDATA_KERNEL_ISR_PAER           (KDATA_BASE_ADDR + 0x006D)
 616
 617 #define KDATA_CLIENT_SCRATCH0           (KDATA_BASE_ADDR + 0x006E)
 618 #define KDATA_CLIENT_SCRATCH1           (KDATA_BASE_ADDR + 0x006F)
 619 #define KDATA_KERNEL_SCRATCH            (KDATA_BASE_ADDR + 0x0070)
 620 #define KDATA_KERNEL_ISR_SCRATCH        (KDATA_BASE_ADDR + 0x0071)
 621
 622 #define KDATA_OUEUE_LEFT                (KDATA_BASE_ADDR + 0x0072)
 623 #define KDATA_QUEUE_RIGHT               (KDATA_BASE_ADDR + 0x0073)
 624
 625 #define KDATA_ADC1_REQUEST              (KDATA_BASE_ADDR + 0x0074)
 626 #define KDATA_ADC2_REQUEST              (KDATA_BASE_ADDR + 0x0075)
 627 #define KDATA_CD_REQUEST                                (KDATA_BASE_ADDR + 0x0076)
 628 #define KDATA_MIC_REQUEST                               (KDATA_BASE_ADDR + 0x0077)
 629
 630 #define KDATA_ADC1_MIXER_REQUEST        (KDATA_BASE_ADDR + 0x0078)
 631 #define KDATA_ADC2_MIXER_REQUEST        (KDATA_BASE_ADDR + 0x0079)
 632 #define KDATA_CD_MIXER_REQUEST                  (KDATA_BASE_ADDR + 0x007A)
 633 #define KDATA_MIC_MIXER_REQUEST                 (KDATA_BASE_ADDR + 0x007B)
 634 #define KDATA_MIC_SYNC_COUNTER                  (KDATA_BASE_ADDR + 0x007C)
 635
 636 /*
 637  * second 'segment' (?) reserved for mixer
 638  * buffers..
 639  */
 640
 641 #define KDATA_MIXER_WORD0               (KDATA_BASE_ADDR2 + 0x0000)
 642 #define KDATA_MIXER_WORD1               (KDATA_BASE_ADDR2 + 0x0001)
 643 #define KDATA_MIXER_WORD2               (KDATA_BASE_ADDR2 + 0x0002)
 644 #define KDATA_MIXER_WORD3               (KDATA_BASE_ADDR2 + 0x0003)
 645 #define KDATA_MIXER_WORD4               (KDATA_BASE_ADDR2 + 0x0004)
 646 #define KDATA_MIXER_WORD5               (KDATA_BASE_ADDR2 + 0x0005)
 647 #define KDATA_MIXER_WORD6               (KDATA_BASE_ADDR2 + 0x0006)
 648 #define KDATA_MIXER_WORD7               (KDATA_BASE_ADDR2 + 0x0007)
 649 #define KDATA_MIXER_WORD8               (KDATA_BASE_ADDR2 + 0x0008)
 650 #define KDATA_MIXER_WORD9               (KDATA_BASE_ADDR2 + 0x0009)
 651 #define KDATA_MIXER_WORDA               (KDATA_BASE_ADDR2 + 0x000A)
 652 #define KDATA_MIXER_WORDB               (KDATA_BASE_ADDR2 + 0x000B)
 653 #define KDATA_MIXER_WORDC               (KDATA_BASE_ADDR2 + 0x000C)
 654 #define KDATA_MIXER_WORDD               (KDATA_BASE_ADDR2 + 0x000D)
 655 #define KDATA_MIXER_WORDE               (KDATA_BASE_ADDR2 + 0x000E)
 656 #define KDATA_MIXER_WORDF               (KDATA_BASE_ADDR2 + 0x000F)
 657
 658 #define KDATA_MIXER_XFER0               (KDATA_BASE_ADDR2 + 0x0010)
 659 #define KDATA_MIXER_XFER1               (KDATA_BASE_ADDR2 + 0x0011)
 660 #define KDATA_MIXER_XFER2               (KDATA_BASE_ADDR2 + 0x0012)
 661 #define KDATA_MIXER_XFER3               (KDATA_BASE_ADDR2 + 0x0013)
 662 #define KDATA_MIXER_XFER4               (KDATA_BASE_ADDR2 + 0x0014)
 663 #define KDATA_MIXER_XFER5               (KDATA_BASE_ADDR2 + 0x0015)
 664 #define KDATA_MIXER_XFER6               (KDATA_BASE_ADDR2 + 0x0016)
 665 #define KDATA_MIXER_XFER7               (KDATA_BASE_ADDR2 + 0x0017)
 666 #define KDATA_MIXER_XFER8               (KDATA_BASE_ADDR2 + 0x0018)
 667 #define KDATA_MIXER_XFER9               (KDATA_BASE_ADDR2 + 0x0019)
 668 #define KDATA_MIXER_XFER_ENDMARK        (KDATA_BASE_ADDR2 + 0x001A)
 669
 670 #define KDATA_MIXER_TASK_NUMBER         (KDATA_BASE_ADDR2 + 0x001B)
 671 #define KDATA_CURRENT_MIXER             (KDATA_BASE_ADDR2 + 0x001C)
 672 #define KDATA_MIXER_ACTIVE              (KDATA_BASE_ADDR2 + 0x001D)
 673 #define KDATA_MIXER_BANK_STATUS         (KDATA_BASE_ADDR2 + 0x001E)
 674 #define KDATA_DAC_LEFT_VOLUME           (KDATA_BASE_ADDR2 + 0x001F)
 675 #define KDATA_DAC_RIGHT_VOLUME          (KDATA_BASE_ADDR2 + 0x0020)
 676
 677 #define MAX_INSTANCE_MINISRC            (KDATA_INSTANCE_MINISRC_ENDMARK - KDATA_INSTANCE0_MINISRC)
 678 #define MAX_VIRTUAL_DMA_CHANNELS        (KDATA_DMA_XFER_ENDMARK - KDATA_DMA_XFER0)
 679 #define MAX_VIRTUAL_MIXER_CHANNELS      (KDATA_MIXER_XFER_ENDMARK - KDATA_MIXER_XFER0)
 680 #define MAX_VIRTUAL_ADC1_CHANNELS       (KDATA_ADC1_XFER_ENDMARK - KDATA_ADC1_XFER0)
 681
 682 /*
 683  * client data area offsets
 684  */
 685 #define CDATA_INSTANCE_READY            0x00
 686
 687 #define CDATA_HOST_SRC_ADDRL            0x01
 688 #define CDATA_HOST_SRC_ADDRH            0x02
 689 #define CDATA_HOST_SRC_END_PLUS_1L      0x03
 690 #define CDATA_HOST_SRC_END_PLUS_1H      0x04
 691 #define CDATA_HOST_SRC_CURRENTL         0x05
 692 #define CDATA_HOST_SRC_CURRENTH         0x06
 693
 694 #define CDATA_IN_BUF_CONNECT            0x07
 695 #define CDATA_OUT_BUF_CONNECT           0x08
 696
 697 #define CDATA_IN_BUF_BEGIN              0x09
 698 #define CDATA_IN_BUF_END_PLUS_1         0x0A
 699 #define CDATA_IN_BUF_HEAD               0x0B
 700 #define CDATA_IN_BUF_TAIL               0x0C
 701 #define CDATA_OUT_BUF_BEGIN             0x0D
 702 #define CDATA_OUT_BUF_END_PLUS_1        0x0E
 703 #define CDATA_OUT_BUF_HEAD              0x0F
 704 #define CDATA_OUT_BUF_TAIL              0x10
 705
 706 #define CDATA_DMA_CONTROL               0x11
 707 #define CDATA_RESERVED                  0x12
 708
 709 #define CDATA_FREQUENCY                 0x13
 710 #define CDATA_LEFT_VOLUME               0x14
 711 #define CDATA_RIGHT_VOLUME              0x15
 712 #define CDATA_LEFT_SUR_VOL              0x16
 713 #define CDATA_RIGHT_SUR_VOL             0x17
 714
 715 #define CDATA_HEADER_LEN                0x18
 716
 717 #define SRC3_DIRECTION_OFFSET           CDATA_HEADER_LEN
 718 #define SRC3_MODE_OFFSET                (CDATA_HEADER_LEN + 1)
 719 #define SRC3_WORD_LENGTH_OFFSET         (CDATA_HEADER_LEN + 2)
 720 #define SRC3_PARAMETER_OFFSET           (CDATA_HEADER_LEN + 3)
 721 #define SRC3_COEFF_ADDR_OFFSET          (CDATA_HEADER_LEN + 8)
 722 #define SRC3_FILTAP_ADDR_OFFSET         (CDATA_HEADER_LEN + 10)
 723 #define SRC3_TEMP_INBUF_ADDR_OFFSET     (CDATA_HEADER_LEN + 16)
 724 #define SRC3_TEMP_OUTBUF_ADDR_OFFSET    (CDATA_HEADER_LEN + 17)
 725
 726 #define MINISRC_IN_BUFFER_SIZE   ( 0x50 * 2 )
 727 #define MINISRC_OUT_BUFFER_SIZE  ( 0x50 * 2 * 2)
 728 #define MINISRC_OUT_BUFFER_SIZE  ( 0x50 * 2 * 2)
 729 #define MINISRC_TMP_BUFFER_SIZE  ( 112 + ( MINISRC_BIQUAD_STAGE * 3 + 4 ) * 2 * 2 )
 730 #define MINISRC_BIQUAD_STAGE    2
 731 #define MINISRC_COEF_LOC          0x175
 732
 733 #define DMACONTROL_BLOCK_MASK           0x000F
 734 #define  DMAC_BLOCK0_SELECTOR           0x0000
 735 #define  DMAC_BLOCK1_SELECTOR           0x0001
 736 #define  DMAC_BLOCK2_SELECTOR           0x0002
 737 #define  DMAC_BLOCK3_SELECTOR           0x0003
 738 #define  DMAC_BLOCK4_SELECTOR           0x0004
 739 #define  DMAC_BLOCK5_SELECTOR           0x0005
 740 #define  DMAC_BLOCK6_SELECTOR           0x0006
 741 #define  DMAC_BLOCK7_SELECTOR           0x0007
 742 #define  DMAC_BLOCK8_SELECTOR           0x0008
 743 #define  DMAC_BLOCK9_SELECTOR           0x0009
 744 #define  DMAC_BLOCKA_SELECTOR           0x000A
 745 #define  DMAC_BLOCKB_SELECTOR           0x000B
 746 #define  DMAC_BLOCKC_SELECTOR           0x000C
 747 #define  DMAC_BLOCKD_SELECTOR           0x000D
 748 #define  DMAC_BLOCKE_SELECTOR           0x000E
 749 #define  DMAC_BLOCKF_SELECTOR           0x000F
 750 #define DMACONTROL_PAGE_MASK            0x00F0
 751 #define  DMAC_PAGE0_SELECTOR            0x0030
 752 #define  DMAC_PAGE1_SELECTOR            0x0020
 753 #define  DMAC_PAGE2_SELECTOR            0x0010
 754 #define  DMAC_PAGE3_SELECTOR            0x0000
 755 #define DMACONTROL_AUTOREPEAT           0x1000
 756 #define DMACONTROL_STOPPED              0x2000
 757 #define DMACONTROL_DIRECTION            0x0100
 758
 759 /*
 760  * an arbitrary volume we set the internal
 761  * volume settings to so that the ac97 volume
 762  * range is a little less insane.  0x7fff is
 763  * max.
 764  */
 765 #define ARB_VOLUME ( 0x6800 )
 766
 767 /*
 768  */
 769
 770 typedef struct snd_m3_dma m3_dma_t;
 771 typedef struct snd_m3 m3_t;
 772
 773 /* quirk lists */
 774 struct m3_quirk {
 775         const char *name;       /* device name */
 776         u16 vendor, device;     /* subsystem ids */
 777         int amp_gpio;           /* gpio pin #  for external amp, -1 = default */
 778         int irda_workaround;    /* non-zero if avoid to touch 0x10 on GPIO_DIRECTION
 779                                    (e.g. for IrDA on Dell Inspirons) */
 780 };
 781
 782 struct m3_hv_quirk {
 783         u16 vendor, device, subsystem_vendor, subsystem_device;
 784         u32 config;             /* ALLEGRO_CONFIG hardware volume bits */
 785         int is_omnibook;        /* Do HP OmniBook GPIO magic? */
 786 };
 787
 788 struct m3_list {
 789         int curlen;
 790         int mem_addr;
 791         int max;
 792 };
 793
 794 struct snd_m3_dma {
 795
 796         int number;
 797         m3_t *chip;
 798         snd_pcm_substream_t *substream;
 799
 800         struct assp_instance {
 801                 unsigned short code, data;
 802         } inst;
 803
 804         int running;
 805         int opened;
 806
 807         unsigned long buffer_addr;
 808         int dma_size;
 809         int period_size;
 810         unsigned int hwptr;
 811         int count;
 812
 813         int index[3];
 814         struct m3_list *index_list[3];
 815
 816         int in_lists;
 817
 818         struct list_head list;
 819
 820 };
 821
 822 struct snd_m3 {
 823
 824         snd_card_t *card;
 825
 826         unsigned long iobase;
 827
 828         int irq;
 829         unsigned int allegro_flag : 1;
 830
 831         ac97_t *ac97;
 832
 833         snd_pcm_t *pcm;
 834
 835         struct pci_dev *pci;
 836         struct m3_quirk *quirk;
 837         struct m3_hv_quirk *hv_quirk;
 838
 839         int dacs_active;
 840         int timer_users;
 841
 842         struct m3_list  msrc_list;
 843         struct m3_list  mixer_list;
 844         struct m3_list  adc1_list;
 845         struct m3_list  dma_list;
 846
 847         /* for storing reset state..*/
 848         u8 reset_state;
 849
 850         int external_amp;
 851         int amp_gpio;
 852
 853         /* midi */
 854         snd_rawmidi_t *rmidi;
 855
 856         /* pcm streams */
 857         int num_substreams;
 858         m3_dma_t *substreams;
 859
 860         spinlock_t reg_lock;
 861         spinlock_t ac97_lock;
 862
 863         snd_kcontrol_t *master_switch;
 864         snd_kcontrol_t *master_volume;
 865         struct tasklet_struct hwvol_tq;
 866
 867 #ifdef CONFIG_PM
 868         u16 *suspend_mem;
 869 #endif
 870 };
 871
 872 /*
 873  * pci ids
 874  */
 875 static struct pci_device_id snd_m3_ids[] = {
 876         {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_ALLEGRO_1, PCI_ANY_ID, PCI_ANY_ID,
 877          PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
 878         {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_ALLEGRO, PCI_ANY_ID, PCI_ANY_ID,
 879          PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
 880         {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_CANYON3D_2LE, PCI_ANY_ID, PCI_ANY_ID,
 881          PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
 882         {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_CANYON3D_2, PCI_ANY_ID, PCI_ANY_ID,
 883          PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
 884         {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_MAESTRO3, PCI_ANY_ID, PCI_ANY_ID,
 885          PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
 886         {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_MAESTRO3_1, PCI_ANY_ID, PCI_ANY_ID,
 887          PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
 888         {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_MAESTRO3_HW, PCI_ANY_ID, PCI_ANY_ID,
 889          PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
 890         {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_MAESTRO3_2, PCI_ANY_ID, PCI_ANY_ID,
 891          PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
 892         {0,},
 893 };
 894
 895 MODULE_DEVICE_TABLE(pci, snd_m3_ids);
 896
 897 static struct m3_quirk m3_quirk_list[] = {
 898         /* panasonic CF-28 "toughbook" */
 899         {
 900                 .name = "Panasonic CF-28",
 901                 .vendor = 0x10f7,
 902                 .device = 0x833e,
 903                 .amp_gpio = 0x0d,
 904         },
 905         /* panasonic CF-72 "toughbook" */
 906         {
 907                 .name = "Panasonic CF-72",
 908                 .vendor = 0x10f7,
 909                 .device = 0x833d,
 910                 .amp_gpio = 0x0d,
 911         },
 912         /* Dell Inspiron 4000 */
 913         {
 914                 .name = "Dell Inspiron 4000",
 915                 .vendor = 0x1028,
 916                 .device = 0x00b0,
 917                 .amp_gpio = -1,
 918                 .irda_workaround = 1,
 919         },
 920         /* Dell Inspiron 8000 */
 921         {
 922                 .name = "Dell Inspiron 8000",
 923                 .vendor = 0x1028,
 924                 .device = 0x00a4,
 925                 .amp_gpio = -1,
 926                 .irda_workaround = 1,
 927         },
 928         /* Dell Inspiron 8100 */
 929         {
 930                 .name = "Dell Inspiron 8100",
 931                 .vendor = 0x1028,
 932                 .device = 0x00e6,
 933                 .amp_gpio = -1,
 934                 .irda_workaround = 1,
 935         },
 936         /* NEC LM800J/7 */
 937         {
 938                 .name = "NEC LM800J/7",
 939                 .vendor = 0x1033,
 940                 .device = 0x80f1,
 941                 .amp_gpio = 0x03,
 942         },
 943         /* LEGEND ZhaoYang 3100CF */
 944         {
 945                 .name = "LEGEND ZhaoYang 3100CF",
 946                 .vendor = 0x1509,
 947                 .device = 0x1740,
 948                 .amp_gpio = 0x03,
 949         },
 950         /* END */
 951         { NULL }
 952 };
 953
 954 /* These values came from the Windows driver. */
 955 static struct m3_hv_quirk m3_hv_quirk_list[] = {
 956         /* Allegro chips */
 957         { 0x125D, 0x1988, 0x0E11, 0x002E, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD, 0 },
 958         { 0x125D, 0x1988, 0x0E11, 0x0094, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD, 0 },
 959         { 0x125D, 0x1988, 0x0E11, 0xB112, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD, 0 },
 960         { 0x125D, 0x1988, 0x0E11, 0xB114, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD, 0 },
 961         { 0x125D, 0x1988, 0x103C, 0x0012, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD, 0 },
 962         { 0x125D, 0x1988, 0x103C, 0x0018, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD, 0 },
 963         { 0x125D, 0x1988, 0x103C, 0x001C, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD, 0 },
 964         { 0x125D, 0x1988, 0x103C, 0x001D, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD, 0 },
 965         { 0x125D, 0x1988, 0x103C, 0x001E, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD, 0 },
 966         { 0x125D, 0x1988, 0x107B, 0x3350, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD, 0 },
 967         { 0x125D, 0x1988, 0x10F7, 0x8338, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD, 0 },
 968         { 0x125D, 0x1988, 0x10F7, 0x833C, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD, 0 },
 969         { 0x125D, 0x1988, 0x10F7, 0x833D, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD, 0 },
 970         { 0x125D, 0x1988, 0x10F7, 0x833E, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD, 0 },
 971         { 0x125D, 0x1988, 0x10F7, 0x833F, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD, 0 },
 972         { 0x125D, 0x1988, 0x13BD, 0x1018, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD, 0 },
 973         { 0x125D, 0x1988, 0x13BD, 0x1019, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD, 0 },
 974         { 0x125D, 0x1988, 0x13BD, 0x101A, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD, 0 },
 975         { 0x125D, 0x1988, 0x14FF, 0x0F03, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD, 0 },
 976         { 0x125D, 0x1988, 0x14FF, 0x0F04, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD, 0 },
 977         { 0x125D, 0x1988, 0x14FF, 0x0F05, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD, 0 },
 978         { 0x125D, 0x1988, 0x156D, 0xB400, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD, 0 },
 979         { 0x125D, 0x1988, 0x156D, 0xB795, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD, 0 },
 980         { 0x125D, 0x1988, 0x156D, 0xB797, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD, 0 },
 981         { 0x125D, 0x1988, 0x156D, 0xC700, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD, 0 },
 982         { 0x125D, 0x1988, 0x1033, 0x80F1, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE, 0 },
 983         { 0x125D, 0x1988, 0x103C, 0x001A, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE, 0 }, /* HP OmniBook 6100 */
 984         { 0x125D, 0x1988, 0x107B, 0x340A, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE, 0 },
 985         { 0x125D, 0x1988, 0x107B, 0x3450, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE, 0 },
 986         { 0x125D, 0x1988, 0x109F, 0x3134, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE, 0 },
 987         { 0x125D, 0x1988, 0x109F, 0x3161, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE, 0 },
 988         { 0x125D, 0x1988, 0x144D, 0x3280, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE, 0 },
 989         { 0x125D, 0x1988, 0x144D, 0x3281, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE, 0 },
 990         { 0x125D, 0x1988, 0x144D, 0xC002, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE, 0 },
 991         { 0x125D, 0x1988, 0x144D, 0xC003, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE, 0 },
 992         { 0x125D, 0x1988, 0x1509, 0x1740, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE, 0 },
 993         { 0x125D, 0x1988, 0x1610, 0x0010, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE, 0 },
 994         { 0x125D, 0x1988, 0x1042, 0x1042, HV_CTRL_ENABLE, 0 },
 995         { 0x125D, 0x1988, 0x107B, 0x9500, HV_CTRL_ENABLE, 0 },
 996         { 0x125D, 0x1988, 0x14FF, 0x0F06, HV_CTRL_ENABLE, 0 },
 997         { 0x125D, 0x1988, 0x1558, 0x8586, HV_CTRL_ENABLE, 0 },
 998         { 0x125D, 0x1988, 0x161F, 0x2011, HV_CTRL_ENABLE, 0 },
 999         /* Maestro3 chips */
1000         { 0x125D, 0x1998, 0x103C, 0x000E, HV_CTRL_ENABLE, 0 },
1001         { 0x125D, 0x1998, 0x103C, 0x0010, HV_CTRL_ENABLE, 1 }, /* HP OmniBook 6000 */
1002         { 0x125D, 0x1998, 0x103C, 0x0011, HV_CTRL_ENABLE, 1 }, /* HP OmniBook 500 */
1003         { 0x125D, 0x1998, 0x103C, 0x001B, HV_CTRL_ENABLE, 0 },
1004         { 0x125D, 0x1998, 0x104D, 0x80A6, HV_CTRL_ENABLE, 0 },
1005         { 0x125D, 0x1998, 0x104D, 0x80AA, HV_CTRL_ENABLE, 0 },
1006         { 0x125D, 0x1998, 0x107B, 0x5300, HV_CTRL_ENABLE, 0 },
1007         { 0x125D, 0x1998, 0x110A, 0x1998, HV_CTRL_ENABLE, 0 },
1008         { 0x125D, 0x1998, 0x13BD, 0x1015, HV_CTRL_ENABLE, 0 },
1009         { 0x125D, 0x1998, 0x13BD, 0x101C, HV_CTRL_ENABLE, 0 },
1010         { 0x125D, 0x1998, 0x13BD, 0x1802, HV_CTRL_ENABLE, 0 },
1011         { 0x125D, 0x1998, 0x1599, 0x0715, HV_CTRL_ENABLE, 0 },
1012         { 0x125D, 0x1998, 0x5643, 0x5643, HV_CTRL_ENABLE, 0 },
1013         { 0x125D, 0x199A, 0x144D, 0x3260, HV_CTRL_ENABLE | REDUCED_DEBOUNCE, 0 },
1014         { 0x125D, 0x199A, 0x144D, 0x3261, HV_CTRL_ENABLE | REDUCED_DEBOUNCE, 0 },
1015         { 0x125D, 0x199A, 0x144D, 0xC000, HV_CTRL_ENABLE | REDUCED_DEBOUNCE, 0 },
1016         { 0x125D, 0x199A, 0x144D, 0xC001, HV_CTRL_ENABLE | REDUCED_DEBOUNCE, 0 },
1017         { 0 }
1018 };
1019
1020 /*
1021  * lowlevel functions
1022  */
1023
1024 static inline void snd_m3_outw(m3_t *chip, u16 value, unsigned long reg)
1025 {
1026         outw(value, chip->iobase + reg);
1027 }
1028
1029 static inline u16 snd_m3_inw(m3_t *chip, unsigned long reg)
1030 {
1031         return inw(chip->iobase + reg);
1032 }
1033
1034 static inline void snd_m3_outb(m3_t *chip, u8 value, unsigned long reg)
1035 {
1036         outb(value, chip->iobase + reg);
1037 }
1038
1039 static inline u8 snd_m3_inb(m3_t *chip, unsigned long reg)
1040 {
1041         return inb(chip->iobase + reg);
1042 }
1043
1044 /*
1045  * access 16bit words to the code or data regions of the dsp's memory.
1046  * index addresses 16bit words.
1047  */
1048 static u16 snd_m3_assp_read(m3_t *chip, u16 region, u16 index)
1049 {
1050         snd_m3_outw(chip, region & MEMTYPE_MASK, DSP_PORT_MEMORY_TYPE);
1051         snd_m3_outw(chip, index, DSP_PORT_MEMORY_INDEX);
1052         return snd_m3_inw(chip, DSP_PORT_MEMORY_DATA);
1053 }
1054
1055 static void snd_m3_assp_write(m3_t *chip, u16 region, u16 index, u16 data)
1056 {
1057         snd_m3_outw(chip, region & MEMTYPE_MASK, DSP_PORT_MEMORY_TYPE);
1058         snd_m3_outw(chip, index, DSP_PORT_MEMORY_INDEX);
1059         snd_m3_outw(chip, data, DSP_PORT_MEMORY_DATA);
1060 }
1061
1062 static void snd_m3_assp_halt(m3_t *chip)
1063 {
1064         chip->reset_state = snd_m3_inb(chip, DSP_PORT_CONTROL_REG_B) & ~REGB_STOP_CLOCK;
1065         msleep(10);
1066         snd_m3_outb(chip, chip->reset_state & ~REGB_ENABLE_RESET, DSP_PORT_CONTROL_REG_B);
1067 }
1068
1069 static void snd_m3_assp_continue(m3_t *chip)
1070 {
1071         snd_m3_outb(chip, chip->reset_state | REGB_ENABLE_RESET, DSP_PORT_CONTROL_REG_B);
1072 }
1073
1074
1075 /*
1076  * This makes me sad. the maestro3 has lists
1077  * internally that must be packed.. 0 terminates,
1078  * apparently, or maybe all unused entries have
1079  * to be 0, the lists have static lengths set
1080  * by the binary code images.
1081  */
1082
1083 static int snd_m3_add_list(m3_t *chip, struct m3_list *list, u16 val)
1084 {
1085         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1086                           list->mem_addr + list->curlen,
1087                           val);
1088         return list->curlen++;
1089 }
1090
1091 static void snd_m3_remove_list(m3_t *chip, struct m3_list *list, int index)
1092 {
1093         u16  val;
1094         int lastindex = list->curlen - 1;
1095
1096         if (index != lastindex) {
1097                 val = snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA,
1098                                        list->mem_addr + lastindex);
1099                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1100                                   list->mem_addr + index,
1101                                   val);
1102         }
1103
1104         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1105                           list->mem_addr + lastindex,
1106                           0);
1107
1108         list->curlen--;
1109 }
1110
1111 static void snd_m3_inc_timer_users(m3_t *chip)
1112 {
1113         chip->timer_users++;
1114         if (chip->timer_users != 1)
1115                 return;
1116
1117         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1118                           KDATA_TIMER_COUNT_RELOAD,
1119                           240);
1120
1121         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1122                           KDATA_TIMER_COUNT_CURRENT,
1123                           240);
1124
1125         snd_m3_outw(chip,
1126                     snd_m3_inw(chip, HOST_INT_CTRL) | CLKRUN_GEN_ENABLE,
1127                     HOST_INT_CTRL);
1128 }
1129
1130 static void snd_m3_dec_timer_users(m3_t *chip)
1131 {
1132         chip->timer_users--;
1133         if (chip->timer_users > 0)
1134                 return;
1135
1136         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1137                           KDATA_TIMER_COUNT_RELOAD,
1138                           0);
1139
1140         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1141                           KDATA_TIMER_COUNT_CURRENT,
1142                           0);
1143
1144         snd_m3_outw(chip,
1145                     snd_m3_inw(chip, HOST_INT_CTRL) & ~CLKRUN_GEN_ENABLE,
1146                     HOST_INT_CTRL);
1147 }
1148
1149 /*
1150  * start/stop
1151  */
1152
1153 /* spinlock held! */
1154 static int snd_m3_pcm_start(m3_t *chip, m3_dma_t *s, snd_pcm_substream_t *subs)
1155 {
1156         if (! s || ! subs)
1157                 return -EINVAL;
1158
1159         snd_m3_inc_timer_users(chip);
1160         switch (subs->stream) {
1161         case SNDRV_PCM_STREAM_PLAYBACK:
1162                 chip->dacs_active++;
1163                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1164                                   s->inst.data + CDATA_INSTANCE_READY, 1);
1165                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1166                                   KDATA_MIXER_TASK_NUMBER,
1167                                   chip->dacs_active);
1168                 break;
1169         case SNDRV_PCM_STREAM_CAPTURE:
1170                 snd_m3_assp_write(s->chip, MEMTYPE_INTERNAL_DATA,
1171                                   KDATA_ADC1_REQUEST, 1);
1172                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1173                                   s->inst.data + CDATA_INSTANCE_READY, 1);
1174                 break;
1175         }
1176         return 0;
1177 }
1178
1179 /* spinlock held! */
1180 static int snd_m3_pcm_stop(m3_t *chip, m3_dma_t *s, snd_pcm_substream_t *subs)
1181 {
1182         if (! s || ! subs)
1183                 return -EINVAL;
1184
1185         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1186                           s->inst.data + CDATA_INSTANCE_READY, 0);
1187         snd_m3_dec_timer_users(chip);
1188         switch (subs->stream) {
1189         case SNDRV_PCM_STREAM_PLAYBACK:
1190                 chip->dacs_active--;
1191                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1192                                   KDATA_MIXER_TASK_NUMBER,
1193                                   chip->dacs_active);
1194                 break;
1195         case SNDRV_PCM_STREAM_CAPTURE:
1196                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1197                                   KDATA_ADC1_REQUEST, 0);
1198                 break;
1199         }
1200         return 0;
1201 }
1202
1203 static int
1204 snd_m3_pcm_trigger(snd_pcm_substream_t *subs, int cmd)
1205 {
1206         m3_t *chip = snd_pcm_substream_chip(subs);
1207         m3_dma_t *s = (m3_dma_t*)subs->runtime->private_data;
1208         int err = -EINVAL;
1209
1210         snd_assert(s != NULL, return -ENXIO);
1211
1212         spin_lock(&chip->reg_lock);
1213         switch (cmd) {
1214         case SNDRV_PCM_TRIGGER_START:
1215         case SNDRV_PCM_TRIGGER_RESUME:
1216                 if (s->running)
1217                         err = -EBUSY;
1218                 else {
1219                         s->running = 1;
1220                         err = snd_m3_pcm_start(chip, s, subs);
1221                 }
1222                 break;
1223         case SNDRV_PCM_TRIGGER_STOP:
1224         case SNDRV_PCM_TRIGGER_SUSPEND:
1225                 if (! s->running)
1226                         err = 0; /* should return error? */
1227                 else {
1228                         s->running = 0;
1229                         err = snd_m3_pcm_stop(chip, s, subs);
1230                 }
1231                 break;
1232         }
1233         spin_unlock(&chip->reg_lock);
1234         return err;
1235 }
1236
1237 /*
1238  * setup
1239  */
1240 static void
1241 snd_m3_pcm_setup1(m3_t *chip, m3_dma_t *s, snd_pcm_substream_t *subs)
1242 {
1243         int dsp_in_size, dsp_out_size, dsp_in_buffer, dsp_out_buffer;
1244         snd_pcm_runtime_t *runtime = subs->runtime;
1245
1246         if (subs->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1247                 dsp_in_size = MINISRC_IN_BUFFER_SIZE - (0x20 * 2);
1248                 dsp_out_size = MINISRC_OUT_BUFFER_SIZE - (0x20 * 2);
1249         } else {
1250                 dsp_in_size = MINISRC_IN_BUFFER_SIZE - (0x10 * 2);
1251                 dsp_out_size = MINISRC_OUT_BUFFER_SIZE - (0x10 * 2);
1252         }
1253         dsp_in_buffer = s->inst.data + (MINISRC_TMP_BUFFER_SIZE / 2);
1254         dsp_out_buffer = dsp_in_buffer + (dsp_in_size / 2) + 1;
1255
1256         s->dma_size = frames_to_bytes(runtime, runtime->buffer_size);
1257         s->period_size = frames_to_bytes(runtime, runtime->period_size);
1258         s->hwptr = 0;
1259         s->count = 0;
1260
1261 #define LO(x) ((x) & 0xffff)
1262 #define HI(x) LO((x) >> 16)
1263
1264         /* host dma buffer pointers */
1265         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1266                           s->inst.data + CDATA_HOST_SRC_ADDRL,
1267                           LO(s->buffer_addr));
1268
1269         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1270                           s->inst.data + CDATA_HOST_SRC_ADDRH,
1271                           HI(s->buffer_addr));
1272
1273         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1274                           s->inst.data + CDATA_HOST_SRC_END_PLUS_1L,
1275                           LO(s->buffer_addr + s->dma_size));
1276
1277         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1278                           s->inst.data + CDATA_HOST_SRC_END_PLUS_1H,
1279                           HI(s->buffer_addr + s->dma_size));
1280
1281         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1282                           s->inst.data + CDATA_HOST_SRC_CURRENTL,
1283                           LO(s->buffer_addr));
1284
1285         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1286                           s->inst.data + CDATA_HOST_SRC_CURRENTH,
1287                           HI(s->buffer_addr));
1288 #undef LO
1289 #undef HI
1290
1291         /* dsp buffers */
1292
1293         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1294                           s->inst.data + CDATA_IN_BUF_BEGIN,
1295                           dsp_in_buffer);
1296
1297         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1298                           s->inst.data + CDATA_IN_BUF_END_PLUS_1,
1299                           dsp_in_buffer + (dsp_in_size / 2));
1300
1301         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1302                           s->inst.data + CDATA_IN_BUF_HEAD,
1303                           dsp_in_buffer);
1304
1305         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1306                           s->inst.data + CDATA_IN_BUF_TAIL,
1307                           dsp_in_buffer);
1308
1309         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1310                           s->inst.data + CDATA_OUT_BUF_BEGIN,
1311                           dsp_out_buffer);
1312
1313         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1314                           s->inst.data + CDATA_OUT_BUF_END_PLUS_1,
1315                           dsp_out_buffer + (dsp_out_size / 2));
1316
1317         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1318                           s->inst.data + CDATA_OUT_BUF_HEAD,
1319                           dsp_out_buffer);
1320
1321         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1322                           s->inst.data + CDATA_OUT_BUF_TAIL,
1323                           dsp_out_buffer);
1324 }
1325
1326 static void snd_m3_pcm_setup2(m3_t *chip, m3_dma_t *s, snd_pcm_runtime_t *runtime)
1327 {
1328         u32 freq;
1329
1330         /*
1331          * put us in the lists if we're not already there
1332          */
1333         if (! s->in_lists) {
1334                 s->index[0] = snd_m3_add_list(chip, s->index_list[0],
1335                                               s->inst.data >> DP_SHIFT_COUNT);
1336                 s->index[1] = snd_m3_add_list(chip, s->index_list[1],
1337                                               s->inst.data >> DP_SHIFT_COUNT);
1338                 s->index[2] = snd_m3_add_list(chip, s->index_list[2],
1339                                               s->inst.data >> DP_SHIFT_COUNT);
1340                 s->in_lists = 1;
1341         }
1342
1343         /* write to 'mono' word */
1344         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1345                           s->inst.data + SRC3_DIRECTION_OFFSET + 1,
1346                           runtime->channels == 2 ? 0 : 1);
1347         /* write to '8bit' word */
1348         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1349                           s->inst.data + SRC3_DIRECTION_OFFSET + 2,
1350                           snd_pcm_format_width(runtime->format) == 16 ? 0 : 1);
1351
1352         /* set up dac/adc rate */
1353         freq = ((runtime->rate << 15) + 24000 ) / 48000;
1354         if (freq)
1355                 freq--;
1356
1357         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1358                           s->inst.data + CDATA_FREQUENCY,
1359                           freq);
1360 }
1361
1362
1363 static struct play_vals {
1364         u16 addr, val;
1365 } pv[] = {
1366         {CDATA_LEFT_VOLUME, ARB_VOLUME},
1367         {CDATA_RIGHT_VOLUME, ARB_VOLUME},
1368         {SRC3_DIRECTION_OFFSET, 0} ,
1369         /* +1, +2 are stereo/16 bit */
1370         {SRC3_DIRECTION_OFFSET + 3, 0x0000}, /* fraction? */
1371         {SRC3_DIRECTION_OFFSET + 4, 0}, /* first l */
1372         {SRC3_DIRECTION_OFFSET + 5, 0}, /* first r */
1373         {SRC3_DIRECTION_OFFSET + 6, 0}, /* second l */
1374         {SRC3_DIRECTION_OFFSET + 7, 0}, /* second r */
1375         {SRC3_DIRECTION_OFFSET + 8, 0}, /* delta l */
1376         {SRC3_DIRECTION_OFFSET + 9, 0}, /* delta r */
1377         {SRC3_DIRECTION_OFFSET + 10, 0x8000}, /* round */
1378         {SRC3_DIRECTION_OFFSET + 11, 0xFF00}, /* higher bute mark */
1379         {SRC3_DIRECTION_OFFSET + 13, 0}, /* temp0 */
1380         {SRC3_DIRECTION_OFFSET + 14, 0}, /* c fraction */
1381         {SRC3_DIRECTION_OFFSET + 15, 0}, /* counter */
1382         {SRC3_DIRECTION_OFFSET + 16, 8}, /* numin */
1383         {SRC3_DIRECTION_OFFSET + 17, 50*2}, /* numout */
1384         {SRC3_DIRECTION_OFFSET + 18, MINISRC_BIQUAD_STAGE - 1}, /* numstage */
1385         {SRC3_DIRECTION_OFFSET + 20, 0}, /* filtertap */
1386         {SRC3_DIRECTION_OFFSET + 21, 0} /* booster */
1387 };
1388
1389
1390 /* the mode passed should be already shifted and masked */
1391 static void
1392 snd_m3_playback_setup(m3_t *chip, m3_dma_t *s, snd_pcm_substream_t *subs)
1393 {
1394         unsigned int i;
1395
1396         /*
1397          * some per client initializers
1398          */
1399
1400         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1401                           s->inst.data + SRC3_DIRECTION_OFFSET + 12,
1402                           s->inst.data + 40 + 8);
1403
1404         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1405                           s->inst.data + SRC3_DIRECTION_OFFSET + 19,
1406                           s->inst.code + MINISRC_COEF_LOC);
1407
1408         /* enable or disable low pass filter? */
1409         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1410                           s->inst.data + SRC3_DIRECTION_OFFSET + 22,
1411                           subs->runtime->rate > 45000 ? 0xff : 0);
1412
1413         /* tell it which way dma is going? */
1414         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1415                           s->inst.data + CDATA_DMA_CONTROL,
1416                           DMACONTROL_AUTOREPEAT + DMAC_PAGE3_SELECTOR + DMAC_BLOCKF_SELECTOR);
1417
1418         /*
1419          * set an armload of static initializers
1420          */
1421         for (i = 0; i < ARRAY_SIZE(pv); i++)
1422                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1423                                   s->inst.data + pv[i].addr, pv[i].val);
1424 }
1425
1426 /*
1427  *    Native record driver
1428  */
1429 static struct rec_vals {
1430         u16 addr, val;
1431 } rv[] = {
1432         {CDATA_LEFT_VOLUME, ARB_VOLUME},
1433         {CDATA_RIGHT_VOLUME, ARB_VOLUME},
1434         {SRC3_DIRECTION_OFFSET, 1} ,
1435         /* +1, +2 are stereo/16 bit */
1436         {SRC3_DIRECTION_OFFSET + 3, 0x0000}, /* fraction? */
1437         {SRC3_DIRECTION_OFFSET + 4, 0}, /* first l */
1438         {SRC3_DIRECTION_OFFSET + 5, 0}, /* first r */
1439         {SRC3_DIRECTION_OFFSET + 6, 0}, /* second l */
1440         {SRC3_DIRECTION_OFFSET + 7, 0}, /* second r */
1441         {SRC3_DIRECTION_OFFSET + 8, 0}, /* delta l */
1442         {SRC3_DIRECTION_OFFSET + 9, 0}, /* delta r */
1443         {SRC3_DIRECTION_OFFSET + 10, 0x8000}, /* round */
1444         {SRC3_DIRECTION_OFFSET + 11, 0xFF00}, /* higher bute mark */
1445         {SRC3_DIRECTION_OFFSET + 13, 0}, /* temp0 */
1446         {SRC3_DIRECTION_OFFSET + 14, 0}, /* c fraction */
1447         {SRC3_DIRECTION_OFFSET + 15, 0}, /* counter */
1448         {SRC3_DIRECTION_OFFSET + 16, 50},/* numin */
1449         {SRC3_DIRECTION_OFFSET + 17, 8}, /* numout */
1450         {SRC3_DIRECTION_OFFSET + 18, 0}, /* numstage */
1451         {SRC3_DIRECTION_OFFSET + 19, 0}, /* coef */
1452         {SRC3_DIRECTION_OFFSET + 20, 0}, /* filtertap */
1453         {SRC3_DIRECTION_OFFSET + 21, 0}, /* booster */
1454         {SRC3_DIRECTION_OFFSET + 22, 0xff} /* skip lpf */
1455 };
1456
1457 static void
1458 snd_m3_capture_setup(m3_t *chip, m3_dma_t *s, snd_pcm_substream_t *subs)
1459 {
1460         unsigned int i;
1461
1462         /*
1463          * some per client initializers
1464          */
1465
1466         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1467                           s->inst.data + SRC3_DIRECTION_OFFSET + 12,
1468                           s->inst.data + 40 + 8);
1469
1470         /* tell it which way dma is going? */
1471         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1472                           s->inst.data + CDATA_DMA_CONTROL,
1473                           DMACONTROL_DIRECTION + DMACONTROL_AUTOREPEAT +
1474                           DMAC_PAGE3_SELECTOR + DMAC_BLOCKF_SELECTOR);
1475
1476         /*
1477          * set an armload of static initializers
1478          */
1479         for (i = 0; i < ARRAY_SIZE(rv); i++)
1480                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1481                                   s->inst.data + rv[i].addr, rv[i].val);
1482 }
1483
1484 static int snd_m3_pcm_hw_params(snd_pcm_substream_t * substream,
1485                                 snd_pcm_hw_params_t * hw_params)
1486 {
1487         m3_dma_t *s = (m3_dma_t*) substream->runtime->private_data;
1488         int err;
1489
1490         if ((err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params))) < 0)
1491                 return err;
1492         /* set buffer address */
1493         s->buffer_addr = substream->runtime->dma_addr;
1494         if (s->buffer_addr & 0x3) {
1495                 snd_printk(KERN_ERR "oh my, not aligned\n");
1496                 s->buffer_addr = s->buffer_addr & ~0x3;
1497         }
1498         return 0;
1499 }
1500
1501 static int snd_m3_pcm_hw_free(snd_pcm_substream_t * substream)
1502 {
1503         m3_dma_t *s;
1504
1505         if (substream->runtime->private_data == NULL)
1506                 return 0;
1507         s = (m3_dma_t*) substream->runtime->private_data;
1508         snd_pcm_lib_free_pages(substream);
1509         s->buffer_addr = 0;
1510         return 0;
1511 }
1512
1513 static int
1514 snd_m3_pcm_prepare(snd_pcm_substream_t *subs)
1515 {
1516         m3_t *chip = snd_pcm_substream_chip(subs);
1517         snd_pcm_runtime_t *runtime = subs->runtime;
1518         m3_dma_t *s = (m3_dma_t*)runtime->private_data;
1519
1520         snd_assert(s != NULL, return -ENXIO);
1521
1522         if (runtime->format != SNDRV_PCM_FORMAT_U8 &&
1523             runtime->format != SNDRV_PCM_FORMAT_S16_LE)
1524                 return -EINVAL;
1525         if (runtime->rate > 48000 ||
1526             runtime->rate < 8000)
1527                 return -EINVAL;
1528
1529         spin_lock_irq(&chip->reg_lock);
1530
1531         snd_m3_pcm_setup1(chip, s, subs);
1532
1533         if (subs->stream == SNDRV_PCM_STREAM_PLAYBACK)
1534                 snd_m3_playback_setup(chip, s, subs);
1535         else
1536                 snd_m3_capture_setup(chip, s, subs);
1537
1538         snd_m3_pcm_setup2(chip, s, runtime);
1539
1540         spin_unlock_irq(&chip->reg_lock);
1541
1542         return 0;
1543 }
1544
1545 /*
1546  * get current pointer
1547  */
1548 static unsigned int
1549 snd_m3_get_pointer(m3_t *chip, m3_dma_t *s, snd_pcm_substream_t *subs)
1550 {
1551         u16 hi = 0, lo = 0;
1552         int retry = 10;
1553         u32 addr;
1554
1555         /*
1556          * try and get a valid answer
1557          */
1558         while (retry--) {
1559                 hi =  snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA,
1560                                        s->inst.data + CDATA_HOST_SRC_CURRENTH);
1561
1562                 lo = snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA,
1563                                       s->inst.data + CDATA_HOST_SRC_CURRENTL);
1564
1565                 if (hi == snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA,
1566                                            s->inst.data + CDATA_HOST_SRC_CURRENTH))
1567                         break;
1568         }
1569         addr = lo | ((u32)hi<<16);
1570         return (unsigned int)(addr - s->buffer_addr);
1571 }
1572
1573 static snd_pcm_uframes_t
1574 snd_m3_pcm_pointer(snd_pcm_substream_t * subs)
1575 {
1576         m3_t *chip = snd_pcm_substream_chip(subs);
1577         unsigned int ptr;
1578         m3_dma_t *s = (m3_dma_t*)subs->runtime->private_data;
1579         snd_assert(s != NULL, return 0);
1580
1581         spin_lock(&chip->reg_lock);
1582         ptr = snd_m3_get_pointer(chip, s, subs);
1583         spin_unlock(&chip->reg_lock);
1584         return bytes_to_frames(subs->runtime, ptr);
1585 }
1586
1587
1588 /* update pointer */
1589 /* spinlock held! */
1590 static void snd_m3_update_ptr(m3_t *chip, m3_dma_t *s)
1591 {
1592         snd_pcm_substream_t *subs = s->substream;
1593         unsigned int hwptr;
1594         int diff;
1595
1596         if (! s->running)
1597                 return;
1598
1599         hwptr = snd_m3_get_pointer(chip, s, subs) % s->dma_size;
1600         diff = (s->dma_size + hwptr - s->hwptr) % s->dma_size;
1601         s->hwptr = hwptr;
1602         s->count += diff;
1603         if (s->count >= (signed)s->period_size) {
1604                 s->count %= s->period_size;
1605                 spin_unlock(&chip->reg_lock);
1606                 snd_pcm_period_elapsed(subs);
1607                 spin_lock(&chip->reg_lock);
1608         }
1609 }
1610
1611 static void snd_m3_update_hw_volume(unsigned long private_data)
1612 {
1613         m3_t *chip = (m3_t *) private_data;
1614         int x, val;
1615         unsigned long flags;
1616
1617         /* Figure out which volume control button was pushed,
1618            based on differences from the default register
1619            values. */
1620         x = inb(chip->iobase + SHADOW_MIX_REG_VOICE) & 0xee;
1621
1622         /* Reset the volume control registers. */
1623         outb(0x88, chip->iobase + SHADOW_MIX_REG_VOICE);
1624         outb(0x88, chip->iobase + HW_VOL_COUNTER_VOICE);
1625         outb(0x88, chip->iobase + SHADOW_MIX_REG_MASTER);
1626         outb(0x88, chip->iobase + HW_VOL_COUNTER_MASTER);
1627
1628         if (!chip->master_switch || !chip->master_volume)
1629                 return;
1630
1631         /* FIXME: we can't call snd_ac97_* functions since here is in tasklet. */
1632         spin_lock_irqsave(&chip->ac97_lock, flags);
1633
1634         val = chip->ac97->regs[AC97_MASTER_VOL];
1635         switch (x) {
1636         case 0x88:
1637                 /* mute */
1638                 val ^= 0x8000;
1639                 chip->ac97->regs[AC97_MASTER_VOL] = val;
1640                 outw(val, chip->iobase + CODEC_DATA);
1641                 outb(AC97_MASTER_VOL, chip->iobase + CODEC_COMMAND);
1642                 snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE,
1643                                &chip->master_switch->id);
1644                 break;
1645         case 0xaa:
1646                 /* volume up */
1647                 if ((val & 0x7f) > 0)
1648                         val--;
1649                 if ((val & 0x7f00) > 0)
1650                         val -= 0x0100;
1651                 chip->ac97->regs[AC97_MASTER_VOL] = val;
1652                 outw(val, chip->iobase + CODEC_DATA);
1653                 outb(AC97_MASTER_VOL, chip->iobase + CODEC_COMMAND);
1654                 snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE,
1655                                &chip->master_volume->id);
1656                 break;
1657         case 0x66:
1658                 /* volume down */
1659                 if ((val & 0x7f) < 0x1f)
1660                         val++;
1661                 if ((val & 0x7f00) < 0x1f00)
1662                         val += 0x0100;
1663                 chip->ac97->regs[AC97_MASTER_VOL] = val;
1664                 outw(val, chip->iobase + CODEC_DATA);
1665                 outb(AC97_MASTER_VOL, chip->iobase + CODEC_COMMAND);
1666                 snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE,
1667                                &chip->master_volume->id);
1668                 break;
1669         }
1670         spin_unlock_irqrestore(&chip->ac97_lock, flags);
1671 }
1672
1673 static irqreturn_t
1674 snd_m3_interrupt(int irq, void *dev_id, struct pt_regs *regs)
1675 {
1676         m3_t *chip = dev_id;
1677         u8 status;
1678         int i;
1679
1680         status = inb(chip->iobase + HOST_INT_STATUS);
1681
1682         if (status == 0xff)
1683                 return IRQ_NONE;
1684
1685         if (status & HV_INT_PENDING)
1686                 tasklet_hi_schedule(&chip->hwvol_tq);
1687
1688         /*
1689          * ack an assp int if its running
1690          * and has an int pending
1691          */
1692         if (status & ASSP_INT_PENDING) {
1693                 u8 ctl = inb(chip->iobase + ASSP_CONTROL_B);
1694                 if (!(ctl & STOP_ASSP_CLOCK)) {
1695                         ctl = inb(chip->iobase + ASSP_HOST_INT_STATUS);
1696                         if (ctl & DSP2HOST_REQ_TIMER) {
1697                                 outb(DSP2HOST_REQ_TIMER, chip->iobase + ASSP_HOST_INT_STATUS);
1698                                 /* update adc/dac info if it was a timer int */
1699                                 spin_lock(&chip->reg_lock);
1700                                 for (i = 0; i < chip->num_substreams; i++) {
1701                                         m3_dma_t *s = &chip->substreams[i];
1702                                         if (s->running)
1703                                                 snd_m3_update_ptr(chip, s);
1704                                 }
1705                                 spin_unlock(&chip->reg_lock);
1706                         }
1707                 }
1708         }
1709
1710 #if 0 /* TODO: not supported yet */
1711         if ((status & MPU401_INT_PENDING) && chip->rmidi)
1712                 snd_mpu401_uart_interrupt(irq, chip->rmidi->private_data, regs);
1713 #endif
1714
1715         /* ack ints */
1716         outb(status, chip->iobase + HOST_INT_STATUS);
1717
1718         return IRQ_HANDLED;
1719 }
1720
1721
1722 /*
1723  */
1724
1725 static snd_pcm_hardware_t snd_m3_playback =
1726 {
1727         .info =                 (SNDRV_PCM_INFO_MMAP |
1728                                  SNDRV_PCM_INFO_INTERLEAVED |
1729                                  SNDRV_PCM_INFO_MMAP_VALID |
1730                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
1731                                  /*SNDRV_PCM_INFO_PAUSE |*/
1732                                  SNDRV_PCM_INFO_RESUME),
1733         .formats =              SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1734         .rates =                SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1735         .rate_min =             8000,
1736         .rate_max =             48000,
1737         .channels_min =         1,
1738         .channels_max =         2,
1739         .buffer_bytes_max =     (512*1024),
1740         .period_bytes_min =     64,
1741         .period_bytes_max =     (512*1024),
1742         .periods_min =          1,
1743         .periods_max =          1024,
1744 };
1745
1746 static snd_pcm_hardware_t snd_m3_capture =
1747 {
1748         .info =                 (SNDRV_PCM_INFO_MMAP |
1749                                  SNDRV_PCM_INFO_INTERLEAVED |
1750                                  SNDRV_PCM_INFO_MMAP_VALID |
1751                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
1752                                  /*SNDRV_PCM_INFO_PAUSE |*/
1753                                  SNDRV_PCM_INFO_RESUME),
1754         .formats =              SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1755         .rates =                SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1756         .rate_min =             8000,
1757         .rate_max =             48000,
1758         .channels_min =         1,
1759         .channels_max =         2,
1760         .buffer_bytes_max =     (512*1024),
1761         .period_bytes_min =     64,
1762         .period_bytes_max =     (512*1024),
1763         .periods_min =          1,
1764         .periods_max =          1024,
1765 };
1766
1767
1768 /*
1769  */
1770
1771 static int
1772 snd_m3_substream_open(m3_t *chip, snd_pcm_substream_t *subs)
1773 {
1774         int i;
1775         m3_dma_t *s;
1776
1777         spin_lock_irq(&chip->reg_lock);
1778         for (i = 0; i < chip->num_substreams; i++) {
1779                 s = &chip->substreams[i];
1780                 if (! s->opened)
1781                         goto __found;
1782         }
1783         spin_unlock_irq(&chip->reg_lock);
1784         return -ENOMEM;
1785 __found:
1786         s->opened = 1;
1787         s->running = 0;
1788         spin_unlock_irq(&chip->reg_lock);
1789
1790         subs->runtime->private_data = s;
1791         s->substream = subs;
1792
1793         /* set list owners */
1794         if (subs->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1795                 s->index_list[0] = &chip->mixer_list;
1796         } else
1797                 s->index_list[0] = &chip->adc1_list;
1798         s->index_list[1] = &chip->msrc_list;
1799         s->index_list[2] = &chip->dma_list;
1800
1801         return 0;
1802 }
1803
1804 static void
1805 snd_m3_substream_close(m3_t *chip, snd_pcm_substream_t *subs)
1806 {
1807         m3_dma_t *s = (m3_dma_t*) subs->runtime->private_data;
1808
1809         if (s == NULL)
1810                 return; /* not opened properly */
1811
1812         spin_lock_irq(&chip->reg_lock);
1813         if (s->substream && s->running)
1814                 snd_m3_pcm_stop(chip, s, s->substream); /* does this happen? */
1815         if (s->in_lists) {
1816                 snd_m3_remove_list(chip, s->index_list[0], s->index[0]);
1817                 snd_m3_remove_list(chip, s->index_list[1], s->index[1]);
1818                 snd_m3_remove_list(chip, s->index_list[2], s->index[2]);
1819                 s->in_lists = 0;
1820         }
1821         s->running = 0;
1822         s->opened = 0;
1823         spin_unlock_irq(&chip->reg_lock);
1824 }
1825
1826 static int
1827 snd_m3_playback_open(snd_pcm_substream_t *subs)
1828 {
1829         m3_t *chip = snd_pcm_substream_chip(subs);
1830         snd_pcm_runtime_t *runtime = subs->runtime;
1831         int err;
1832
1833         if ((err = snd_m3_substream_open(chip, subs)) < 0)
1834                 return err;
1835
1836         runtime->hw = snd_m3_playback;
1837         snd_pcm_set_sync(subs);
1838
1839         return 0;
1840 }
1841
1842 static int
1843 snd_m3_playback_close(snd_pcm_substream_t *subs)
1844 {
1845         m3_t *chip = snd_pcm_substream_chip(subs);
1846
1847         snd_m3_substream_close(chip, subs);
1848         return 0;
1849 }
1850
1851 static int
1852 snd_m3_capture_open(snd_pcm_substream_t *subs)
1853 {
1854         m3_t *chip = snd_pcm_substream_chip(subs);
1855         snd_pcm_runtime_t *runtime = subs->runtime;
1856         int err;
1857
1858         if ((err = snd_m3_substream_open(chip, subs)) < 0)
1859                 return err;
1860
1861         runtime->hw = snd_m3_capture;
1862         snd_pcm_set_sync(subs);
1863
1864         return 0;
1865 }
1866
1867 static int
1868 snd_m3_capture_close(snd_pcm_substream_t *subs)
1869 {
1870         m3_t *chip = snd_pcm_substream_chip(subs);
1871
1872         snd_m3_substream_close(chip, subs);
1873         return 0;
1874 }
1875
1876 /*
1877  * create pcm instance
1878  */
1879
1880 static snd_pcm_ops_t snd_m3_playback_ops = {
1881         .open =         snd_m3_playback_open,
1882         .close =        snd_m3_playback_close,
1883         .ioctl =        snd_pcm_lib_ioctl,
1884         .hw_params =    snd_m3_pcm_hw_params,
1885         .hw_free =      snd_m3_pcm_hw_free,
1886         .prepare =      snd_m3_pcm_prepare,
1887         .trigger =      snd_m3_pcm_trigger,
1888         .pointer =      snd_m3_pcm_pointer,
1889 };
1890
1891 static snd_pcm_ops_t snd_m3_capture_ops = {
1892         .open =         snd_m3_capture_open,
1893         .close =        snd_m3_capture_close,
1894         .ioctl =        snd_pcm_lib_ioctl,
1895         .hw_params =    snd_m3_pcm_hw_params,
1896         .hw_free =      snd_m3_pcm_hw_free,
1897         .prepare =      snd_m3_pcm_prepare,
1898         .trigger =      snd_m3_pcm_trigger,
1899         .pointer =      snd_m3_pcm_pointer,
1900 };
1901
1902 static int __devinit
1903 snd_m3_pcm(m3_t * chip, int device)
1904 {
1905         snd_pcm_t *pcm;
1906         int err;
1907
1908         err = snd_pcm_new(chip->card, chip->card->driver, device,
1909                           MAX_PLAYBACKS, MAX_CAPTURES, &pcm);
1910         if (err < 0)
1911                 return err;
1912
1913         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_m3_playback_ops);
1914         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_m3_capture_ops);
1915
1916         pcm->private_data = chip;
1917         pcm->info_flags = 0;
1918         strcpy(pcm->name, chip->card->driver);
1919         chip->pcm = pcm;
1920
1921         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1922                                               snd_dma_pci_data(chip->pci), 64*1024, 64*1024);
1923
1924         return 0;
1925 }
1926
1927
1928 /*
1929  * ac97 interface
1930  */
1931
1932 /*
1933  * Wait for the ac97 serial bus to be free.
1934  * return nonzero if the bus is still busy.
1935  */
1936 static int snd_m3_ac97_wait(m3_t *chip)
1937 {
1938         int i = 10000;
1939
1940         do {
1941                 if (! (snd_m3_inb(chip, 0x30) & 1))
1942                         return 0;
1943         } while (i-- > 0);
1944
1945         snd_printk(KERN_ERR "ac97 serial bus busy\n");
1946         return 1;
1947 }
1948
1949 static unsigned short
1950 snd_m3_ac97_read(ac97_t *ac97, unsigned short reg)
1951 {
1952         m3_t *chip = ac97->private_data;
1953         unsigned long flags;
1954         unsigned short data;
1955
1956         if (snd_m3_ac97_wait(chip))
1957                 return 0xffff;
1958         spin_lock_irqsave(&chip->ac97_lock, flags);
1959         snd_m3_outb(chip, 0x80 | (reg & 0x7f), CODEC_COMMAND);
1960         if (snd_m3_ac97_wait(chip))
1961                 return 0xffff;
1962         data = snd_m3_inw(chip, CODEC_DATA);
1963         spin_unlock_irqrestore(&chip->ac97_lock, flags);
1964         return data;
1965 }
1966
1967 static void
1968 snd_m3_ac97_write(ac97_t *ac97, unsigned short reg, unsigned short val)
1969 {
1970         m3_t *chip = ac97->private_data;
1971         unsigned long flags;
1972
1973         if (snd_m3_ac97_wait(chip))
1974                 return;
1975         spin_lock_irqsave(&chip->ac97_lock, flags);
1976         snd_m3_outw(chip, val, CODEC_DATA);
1977         snd_m3_outb(chip, reg & 0x7f, CODEC_COMMAND);
1978         spin_unlock_irqrestore(&chip->ac97_lock, flags);
1979 }
1980
1981
1982 static void snd_m3_remote_codec_config(int io, int isremote)
1983 {
1984         isremote = isremote ? 1 : 0;
1985
1986         outw((inw(io + RING_BUS_CTRL_B) & ~SECOND_CODEC_ID_MASK) | isremote,
1987              io + RING_BUS_CTRL_B);
1988         outw((inw(io + SDO_OUT_DEST_CTRL) & ~COMMAND_ADDR_OUT) | isremote,
1989              io + SDO_OUT_DEST_CTRL);
1990         outw((inw(io + SDO_IN_DEST_CTRL) & ~STATUS_ADDR_IN) | isremote,
1991              io + SDO_IN_DEST_CTRL);
1992 }
1993
1994 /*
1995  * hack, returns non zero on err
1996  */
1997 static int snd_m3_try_read_vendor(m3_t *chip)
1998 {
1999         u16 ret;
2000
2001         if (snd_m3_ac97_wait(chip))
2002                 return 1;
2003
2004         snd_m3_outb(chip, 0x80 | (AC97_VENDOR_ID1 & 0x7f), 0x30);
2005
2006         if (snd_m3_ac97_wait(chip))
2007                 return 1;
2008
2009         ret = snd_m3_inw(chip, 0x32);
2010
2011         return (ret == 0) || (ret == 0xffff);
2012 }
2013
2014 static void snd_m3_ac97_reset(m3_t *chip)
2015 {
2016         u16 dir;
2017         int delay1 = 0, delay2 = 0, i;
2018         int io = chip->iobase;
2019
2020         if (chip->allegro_flag) {
2021                 /*
2022                  * the onboard codec on the allegro seems
2023                  * to want to wait a very long time before
2024                  * coming back to life
2025                  */
2026                 delay1 = 50;
2027                 delay2 = 800;
2028         } else {
2029                 /* maestro3 */
2030                 delay1 = 20;
2031                 delay2 = 500;
2032         }
2033
2034         for (i = 0; i < 5; i++) {
2035                 dir = inw(io + GPIO_DIRECTION);
2036                 if (! chip->quirk || ! chip->quirk->irda_workaround)
2037                         dir |= 0x10; /* assuming pci bus master? */
2038
2039                 snd_m3_remote_codec_config(io, 0);
2040
2041                 outw(IO_SRAM_ENABLE, io + RING_BUS_CTRL_A);
2042                 udelay(20);
2043
2044                 outw(dir & ~GPO_PRIMARY_AC97 , io + GPIO_DIRECTION);
2045                 outw(~GPO_PRIMARY_AC97 , io + GPIO_MASK);
2046                 outw(0, io + GPIO_DATA);
2047                 outw(dir | GPO_PRIMARY_AC97, io + GPIO_DIRECTION);
2048
2049                 schedule_timeout_uninterruptible(msecs_to_jiffies(delay1));
2050
2051                 outw(GPO_PRIMARY_AC97, io + GPIO_DATA);
2052                 udelay(5);
2053                 /* ok, bring back the ac-link */
2054                 outw(IO_SRAM_ENABLE | SERIAL_AC_LINK_ENABLE, io + RING_BUS_CTRL_A);
2055                 outw(~0, io + GPIO_MASK);
2056
2057                 schedule_timeout_uninterruptible(msecs_to_jiffies(delay2));
2058
2059                 if (! snd_m3_try_read_vendor(chip))
2060                         break;
2061
2062                 delay1 += 10;
2063                 delay2 += 100;
2064
2065                 snd_printd("maestro3: retrying codec reset with delays of %d and %d ms\n",
2066                            delay1, delay2);
2067         }
2068
2069 #if 0
2070         /* more gung-ho reset that doesn't
2071          * seem to work anywhere :)
2072          */
2073         tmp = inw(io + RING_BUS_CTRL_A);
2074         outw(RAC_SDFS_ENABLE|LAC_SDFS_ENABLE, io + RING_BUS_CTRL_A);
2075         msleep(20);
2076         outw(tmp, io + RING_BUS_CTRL_A);
2077         msleep(50);
2078 #endif
2079 }
2080
2081 static int __devinit snd_m3_mixer(m3_t *chip)
2082 {
2083         ac97_bus_t *pbus;
2084         ac97_template_t ac97;
2085         snd_ctl_elem_id_t id;
2086         int err;
2087         static ac97_bus_ops_t ops = {
2088                 .write = snd_m3_ac97_write,
2089                 .read = snd_m3_ac97_read,
2090         };
2091
2092         if ((err = snd_ac97_bus(chip->card, 0, &ops, NULL, &pbus)) < 0)
2093                 return err;
2094
2095         memset(&ac97, 0, sizeof(ac97));
2096         ac97.private_data = chip;
2097         if ((err = snd_ac97_mixer(pbus, &ac97, &chip->ac97)) < 0)
2098                 return err;
2099
2100         /* seems ac97 PCM needs initialization.. hack hack.. */
2101         snd_ac97_write(chip->ac97, AC97_PCM, 0x8000 | (15 << 8) | 15);
2102         schedule_timeout_uninterruptible(msecs_to_jiffies(100));
2103         snd_ac97_write(chip->ac97, AC97_PCM, 0);
2104
2105         memset(&id, 0, sizeof(id));
2106         id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
2107         strcpy(id.name, "Master Playback Switch");
2108         chip->master_switch = snd_ctl_find_id(chip->card, &id);
2109         memset(&id, 0, sizeof(id));
2110         id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
2111         strcpy(id.name, "Master Playback Volume");
2112         chip->master_volume = snd_ctl_find_id(chip->card, &id);
2113
2114         return 0;
2115 }
2116
2117
2118 /*
2119  * DSP Code images
2120  */
2121
2122 static u16 assp_kernel_image[] __devinitdata = {
2123     0x7980, 0x0030, 0x7980, 0x03B4, 0x7980, 0x03B4, 0x7980, 0x00FB, 0x7980, 0x00DD, 0x7980, 0x03B4,
2124     0x7980, 0x0332, 0x7980, 0x0287, 0x7980, 0x03B4, 0x7980, 0x03B4, 0x7980, 0x03B4, 0x7980, 0x03B4,
2125     0x7980, 0x031A, 0x7980, 0x03B4, 0x7980, 0x022F, 0x7980, 0x03B4, 0x7980, 0x03B4, 0x7980, 0x03B4,
2126     0x7980, 0x03B4, 0x7980, 0x03B4, 0x7980, 0x0063, 0x7980, 0x006B, 0x7980, 0x03B4, 0x7980, 0x03B4,
2127     0xBF80, 0x2C7C, 0x8806, 0x8804, 0xBE40, 0xBC20, 0xAE09, 0x1000, 0xAE0A, 0x0001, 0x6938, 0xEB08,
2128     0x0053, 0x695A, 0xEB08, 0x00D6, 0x0009, 0x8B88, 0x6980, 0xE388, 0x0036, 0xBE30, 0xBC20, 0x6909,
2129     0xB801, 0x9009, 0xBE41, 0xBE41, 0x6928, 0xEB88, 0x0078, 0xBE41, 0xBE40, 0x7980, 0x0038, 0xBE41,
2130     0xBE41, 0x903A, 0x6938, 0xE308, 0x0056, 0x903A, 0xBE41, 0xBE40, 0xEF00, 0x903A, 0x6939, 0xE308,
2131     0x005E, 0x903A, 0xEF00, 0x690B, 0x660C, 0xEF8C, 0x690A, 0x660C, 0x620B, 0x6609, 0xEF00, 0x6910,
2132     0x660F, 0xEF04, 0xE388, 0x0075, 0x690E, 0x660F, 0x6210, 0x660D, 0xEF00, 0x690E, 0x660D, 0xEF00,
2133     0xAE70, 0x0001, 0xBC20, 0xAE27, 0x0001, 0x6939, 0xEB08, 0x005D, 0x6926, 0xB801, 0x9026, 0x0026,
2134     0x8B88, 0x6980, 0xE388, 0x00CB, 0x9028, 0x0D28, 0x4211, 0xE100, 0x007A, 0x4711, 0xE100, 0x00A0,
2135     0x7A80, 0x0063, 0xB811, 0x660A, 0x6209, 0xE304, 0x007A, 0x0C0B, 0x4005, 0x100A, 0xBA01, 0x9012,
2136     0x0C12, 0x4002, 0x7980, 0x00AF, 0x7A80, 0x006B, 0xBE02, 0x620E, 0x660D, 0xBA10, 0xE344, 0x007A,
2137     0x0C10, 0x4005, 0x100E, 0xBA01, 0x9012, 0x0C12, 0x4002, 0x1003, 0xBA02, 0x9012, 0x0C12, 0x4000,
2138     0x1003, 0xE388, 0x00BA, 0x1004, 0x7980, 0x00BC, 0x1004, 0xBA01, 0x9012, 0x0C12, 0x4001, 0x0C05,
2139     0x4003, 0x0C06, 0x4004, 0x1011, 0xBFB0, 0x01FF, 0x9012, 0x0C12, 0x4006, 0xBC20, 0xEF00, 0xAE26,
2140     0x1028, 0x6970, 0xBFD0, 0x0001, 0x9070, 0xE388, 0x007A, 0xAE28, 0x0000, 0xEF00, 0xAE70, 0x0300,
2141     0x0C70, 0xB00C, 0xAE5A, 0x0000, 0xEF00, 0x7A80, 0x038A, 0x697F, 0xB801, 0x907F, 0x0056, 0x8B88,
2142     0x0CA0, 0xB008, 0xAF71, 0xB000, 0x4E71, 0xE200, 0x00F3, 0xAE56, 0x1057, 0x0056, 0x0CA0, 0xB008,
2143     0x8056, 0x7980, 0x03A1, 0x0810, 0xBFA0, 0x1059, 0xE304, 0x03A1, 0x8056, 0x7980, 0x03A1, 0x7A80,
2144     0x038A, 0xBF01, 0xBE43, 0xBE59, 0x907C, 0x6937, 0xE388, 0x010D, 0xBA01, 0xE308, 0x010C, 0xAE71,
2145     0x0004, 0x0C71, 0x5000, 0x6936, 0x9037, 0xBF0A, 0x109E, 0x8B8A, 0xAF80, 0x8014, 0x4C80, 0xBF0A,
2146     0x0560, 0xF500, 0xBF0A, 0x0520, 0xB900, 0xBB17, 0x90A0, 0x6917, 0xE388, 0x0148, 0x0D17, 0xE100,
2147     0x0127, 0xBF0C, 0x0578, 0xBF0D, 0x057C, 0x7980, 0x012B, 0xBF0C, 0x0538, 0xBF0D, 0x053C, 0x6900,
2148     0xE308, 0x0135, 0x8B8C, 0xBE59, 0xBB07, 0x90A0, 0xBC20, 0x7980, 0x0157, 0x030C, 0x8B8B, 0xB903,
2149     0x8809, 0xBEC6, 0x013E, 0x69AC, 0x90AB, 0x69AD, 0x90AB, 0x0813, 0x660A, 0xE344, 0x0144, 0x0309,
2150     0x830C, 0xBC20, 0x7980, 0x0157, 0x6955, 0xE388, 0x0157, 0x7C38, 0xBF0B, 0x0578, 0xF500, 0xBF0B,
2151     0x0538, 0xB907, 0x8809, 0xBEC6, 0x0156, 0x10AB, 0x90AA, 0x6974, 0xE388, 0x0163, 0xAE72, 0x0540,
2152     0xF500, 0xAE72, 0x0500, 0xAE61, 0x103B, 0x7A80, 0x02F6, 0x6978, 0xE388, 0x0182, 0x8B8C, 0xBF0C,
2153     0x0560, 0xE500, 0x7C40, 0x0814, 0xBA20, 0x8812, 0x733D, 0x7A80, 0x0380, 0x733E, 0x7A80, 0x0380,
2154     0x8B8C, 0xBF0C, 0x056C, 0xE500, 0x7C40, 0x0814, 0xBA2C, 0x8812, 0x733F, 0x7A80, 0x0380, 0x7340,
2155     0x7A80, 0x0380, 0x6975, 0xE388, 0x018E, 0xAE72, 0x0548, 0xF500, 0xAE72, 0x0508, 0xAE61, 0x1041,
2156     0x7A80, 0x02F6, 0x6979, 0xE388, 0x01AD, 0x8B8C, 0xBF0C, 0x0560, 0xE500, 0x7C40, 0x0814, 0xBA18,
2157     0x8812, 0x7343, 0x7A80, 0x0380, 0x7344, 0x7A80, 0x0380, 0x8B8C, 0xBF0C, 0x056C, 0xE500, 0x7C40,
2158     0x0814, 0xBA24, 0x8812, 0x7345, 0x7A80, 0x0380, 0x7346, 0x7A80, 0x0380, 0x6976, 0xE388, 0x01B9,
2159     0xAE72, 0x0558, 0xF500, 0xAE72, 0x0518, 0xAE61, 0x1047, 0x7A80, 0x02F6, 0x697A, 0xE388, 0x01D8,
2160     0x8B8C, 0xBF0C, 0x0560, 0xE500, 0x7C40, 0x0814, 0xBA08, 0x8812, 0x7349, 0x7A80, 0x0380, 0x734A,
2161     0x7A80, 0x0380, 0x8B8C, 0xBF0C, 0x056C, 0xE500, 0x7C40, 0x0814, 0xBA14, 0x8812, 0x734B, 0x7A80,
2162     0x0380, 0x734C, 0x7A80, 0x0380, 0xBC21, 0xAE1C, 0x1090, 0x8B8A, 0xBF0A, 0x0560, 0xE500, 0x7C40,
2163     0x0812, 0xB804, 0x8813, 0x8B8D, 0xBF0D, 0x056C, 0xE500, 0x7C40, 0x0815, 0xB804, 0x8811, 0x7A80,
2164     0x034A, 0x8B8A, 0xBF0A, 0x0560, 0xE500, 0x7C40, 0x731F, 0xB903, 0x8809, 0xBEC6, 0x01F9, 0x548A,
2165     0xBE03, 0x98A0, 0x7320, 0xB903, 0x8809, 0xBEC6, 0x0201, 0x548A, 0xBE03, 0x98A0, 0x1F20, 0x2F1F,
2166     0x9826, 0xBC20, 0x6935, 0xE388, 0x03A1, 0x6933, 0xB801, 0x9033, 0xBFA0, 0x02EE, 0xE308, 0x03A1,
2167     0x9033, 0xBF00, 0x6951, 0xE388, 0x021F, 0x7334, 0xBE80, 0x5760, 0xBE03, 0x9F7E, 0xBE59, 0x9034,
2168     0x697E, 0x0D51, 0x9013, 0xBC20, 0x695C, 0xE388, 0x03A1, 0x735E, 0xBE80, 0x5760, 0xBE03, 0x9F7E,
2169     0xBE59, 0x905E, 0x697E, 0x0D5C, 0x9013, 0x7980, 0x03A1, 0x7A80, 0x038A, 0xBF01, 0xBE43, 0x6977,
2170     0xE388, 0x024E, 0xAE61, 0x104D, 0x0061, 0x8B88, 0x6980, 0xE388, 0x024E, 0x9071, 0x0D71, 0x000B,
2171     0xAFA0, 0x8010, 0xAFA0, 0x8010, 0x0810, 0x660A, 0xE308, 0x0249, 0x0009, 0x0810, 0x660C, 0xE388,
2172     0x024E, 0x800B, 0xBC20, 0x697B, 0xE388, 0x03A1, 0xBF0A, 0x109E, 0x8B8A, 0xAF80, 0x8014, 0x4C80,
2173     0xE100, 0x0266, 0x697C, 0xBF90, 0x0560, 0x9072, 0x0372, 0x697C, 0xBF90, 0x0564, 0x9073, 0x0473,
2174     0x7980, 0x0270, 0x697C, 0xBF90, 0x0520, 0x9072, 0x0372, 0x697C, 0xBF90, 0x0524, 0x9073, 0x0473,
2175     0x697C, 0xB801, 0x907C, 0xBF0A, 0x10FD, 0x8B8A, 0xAF80, 0x8010, 0x734F, 0x548A, 0xBE03, 0x9880,
2176     0xBC21, 0x7326, 0x548B, 0xBE03, 0x618B, 0x988C, 0xBE03, 0x6180, 0x9880, 0x7980, 0x03A1, 0x7A80,
2177     0x038A, 0x0D28, 0x4711, 0xE100, 0x02BE, 0xAF12, 0x4006, 0x6912, 0xBFB0, 0x0C00, 0xE388, 0x02B6,
2178     0xBFA0, 0x0800, 0xE388, 0x02B2, 0x6912, 0xBFB0, 0x0C00, 0xBFA0, 0x0400, 0xE388, 0x02A3, 0x6909,
2179     0x900B, 0x7980, 0x02A5, 0xAF0B, 0x4005, 0x6901, 0x9005, 0x6902, 0x9006, 0x4311, 0xE100, 0x02ED,
2180     0x6911, 0xBFC0, 0x2000, 0x9011, 0x7980, 0x02ED, 0x6909, 0x900B, 0x7980, 0x02B8, 0xAF0B, 0x4005,
2181     0xAF05, 0x4003, 0xAF06, 0x4004, 0x7980, 0x02ED, 0xAF12, 0x4006, 0x6912, 0xBFB0, 0x0C00, 0xE388,
2182     0x02E7, 0xBFA0, 0x0800, 0xE388, 0x02E3, 0x6912, 0xBFB0, 0x0C00, 0xBFA0, 0x0400, 0xE388, 0x02D4,
2183     0x690D, 0x9010, 0x7980, 0x02D6, 0xAF10, 0x4005, 0x6901, 0x9005, 0x6902, 0x9006, 0x4311, 0xE100,
2184     0x02ED, 0x6911, 0xBFC0, 0x2000, 0x9011, 0x7980, 0x02ED, 0x690D, 0x9010, 0x7980, 0x02E9, 0xAF10,
2185     0x4005, 0xAF05, 0x4003, 0xAF06, 0x4004, 0xBC20, 0x6970, 0x9071, 0x7A80, 0x0078, 0x6971, 0x9070,
2186     0x7980, 0x03A1, 0xBC20, 0x0361, 0x8B8B, 0x6980, 0xEF88, 0x0272, 0x0372, 0x7804, 0x9071, 0x0D71,
2187     0x8B8A, 0x000B, 0xB903, 0x8809, 0xBEC6, 0x0309, 0x69A8, 0x90AB, 0x69A8, 0x90AA, 0x0810, 0x660A,
2188     0xE344, 0x030F, 0x0009, 0x0810, 0x660C, 0xE388, 0x0314, 0x800B, 0xBC20, 0x6961, 0xB801, 0x9061,
2189     0x7980, 0x02F7, 0x7A80, 0x038A, 0x5D35, 0x0001, 0x6934, 0xB801, 0x9034, 0xBF0A, 0x109E, 0x8B8A,
2190     0xAF80, 0x8014, 0x4880, 0xAE72, 0x0550, 0xF500, 0xAE72, 0x0510, 0xAE61, 0x1051, 0x7A80, 0x02F6,
2191     0x7980, 0x03A1, 0x7A80, 0x038A, 0x5D35, 0x0002, 0x695E, 0xB801, 0x905E, 0xBF0A, 0x109E, 0x8B8A,
2192     0xAF80, 0x8014, 0x4780, 0xAE72, 0x0558, 0xF500, 0xAE72, 0x0518, 0xAE61, 0x105C, 0x7A80, 0x02F6,
2193     0x7980, 0x03A1, 0x001C, 0x8B88, 0x6980, 0xEF88, 0x901D, 0x0D1D, 0x100F, 0x6610, 0xE38C, 0x0358,
2194     0x690E, 0x6610, 0x620F, 0x660D, 0xBA0F, 0xE301, 0x037A, 0x0410, 0x8B8A, 0xB903, 0x8809, 0xBEC6,
2195     0x036C, 0x6A8C, 0x61AA, 0x98AB, 0x6A8C, 0x61AB, 0x98AD, 0x6A8C, 0x61AD, 0x98A9, 0x6A8C, 0x61A9,
2196     0x98AA, 0x7C04, 0x8B8B, 0x7C04, 0x8B8D, 0x7C04, 0x8B89, 0x7C04, 0x0814, 0x660E, 0xE308, 0x0379,
2197     0x040D, 0x8410, 0xBC21, 0x691C, 0xB801, 0x901C, 0x7980, 0x034A, 0xB903, 0x8809, 0x8B8A, 0xBEC6,
2198     0x0388, 0x54AC, 0xBE03, 0x618C, 0x98AA, 0xEF00, 0xBC20, 0xBE46, 0x0809, 0x906B, 0x080A, 0x906C,
2199     0x080B, 0x906D, 0x081A, 0x9062, 0x081B, 0x9063, 0x081E, 0x9064, 0xBE59, 0x881E, 0x8065, 0x8166,
2200     0x8267, 0x8368, 0x8469, 0x856A, 0xEF00, 0xBC20, 0x696B, 0x8809, 0x696C, 0x880A, 0x696D, 0x880B,
2201     0x6962, 0x881A, 0x6963, 0x881B, 0x6964, 0x881E, 0x0065, 0x0166, 0x0267, 0x0368, 0x0469, 0x056A,
2202     0xBE3A,
2203 };
2204
2205 /*
2206  * Mini sample rate converter code image
2207  * that is to be loaded at 0x400 on the DSP.
2208  */
2209 static u16 assp_minisrc_image[] __devinitdata = {
2210
2211     0xBF80, 0x101E, 0x906E, 0x006E, 0x8B88, 0x6980, 0xEF88, 0x906F, 0x0D6F, 0x6900, 0xEB08, 0x0412,
2212     0xBC20, 0x696E, 0xB801, 0x906E, 0x7980, 0x0403, 0xB90E, 0x8807, 0xBE43, 0xBF01, 0xBE47, 0xBE41,
2213     0x7A80, 0x002A, 0xBE40, 0x3029, 0xEFCC, 0xBE41, 0x7A80, 0x0028, 0xBE40, 0x3028, 0xEFCC, 0x6907,
2214     0xE308, 0x042A, 0x6909, 0x902C, 0x7980, 0x042C, 0x690D, 0x902C, 0x1009, 0x881A, 0x100A, 0xBA01,
2215     0x881B, 0x100D, 0x881C, 0x100E, 0xBA01, 0x881D, 0xBF80, 0x00ED, 0x881E, 0x050C, 0x0124, 0xB904,
2216     0x9027, 0x6918, 0xE308, 0x04B3, 0x902D, 0x6913, 0xBFA0, 0x7598, 0xF704, 0xAE2D, 0x00FF, 0x8B8D,
2217     0x6919, 0xE308, 0x0463, 0x691A, 0xE308, 0x0456, 0xB907, 0x8809, 0xBEC6, 0x0453, 0x10A9, 0x90AD,
2218     0x7980, 0x047C, 0xB903, 0x8809, 0xBEC6, 0x0460, 0x1889, 0x6C22, 0x90AD, 0x10A9, 0x6E23, 0x6C22,
2219     0x90AD, 0x7980, 0x047C, 0x101A, 0xE308, 0x046F, 0xB903, 0x8809, 0xBEC6, 0x046C, 0x10A9, 0x90A0,
2220     0x90AD, 0x7980, 0x047C, 0xB901, 0x8809, 0xBEC6, 0x047B, 0x1889, 0x6C22, 0x90A0, 0x90AD, 0x10A9,
2221     0x6E23, 0x6C22, 0x90A0, 0x90AD, 0x692D, 0xE308, 0x049C, 0x0124, 0xB703, 0xB902, 0x8818, 0x8B89,
2222     0x022C, 0x108A, 0x7C04, 0x90A0, 0x692B, 0x881F, 0x7E80, 0x055B, 0x692A, 0x8809, 0x8B89, 0x99A0,
2223     0x108A, 0x90A0, 0x692B, 0x881F, 0x7E80, 0x055B, 0x692A, 0x8809, 0x8B89, 0x99AF, 0x7B99, 0x0484,
2224     0x0124, 0x060F, 0x101B, 0x2013, 0x901B, 0xBFA0, 0x7FFF, 0xE344, 0x04AC, 0x901B, 0x8B89, 0x7A80,
2225     0x051A, 0x6927, 0xBA01, 0x9027, 0x7A80, 0x0523, 0x6927, 0xE308, 0x049E, 0x7980, 0x050F, 0x0624,
2226     0x1026, 0x2013, 0x9026, 0xBFA0, 0x7FFF, 0xE304, 0x04C0, 0x8B8D, 0x7A80, 0x051A, 0x7980, 0x04B4,
2227     0x9026, 0x1013, 0x3026, 0x901B, 0x8B8D, 0x7A80, 0x051A, 0x7A80, 0x0523, 0x1027, 0xBA01, 0x9027,
2228     0xE308, 0x04B4, 0x0124, 0x060F, 0x8B89, 0x691A, 0xE308, 0x04EA, 0x6919, 0xE388, 0x04E0, 0xB903,
2229     0x8809, 0xBEC6, 0x04DD, 0x1FA0, 0x2FAE, 0x98A9, 0x7980, 0x050F, 0xB901, 0x8818, 0xB907, 0x8809,
2230     0xBEC6, 0x04E7, 0x10EE, 0x90A9, 0x7980, 0x050F, 0x6919, 0xE308, 0x04FE, 0xB903, 0x8809, 0xBE46,
2231     0xBEC6, 0x04FA, 0x17A0, 0xBE1E, 0x1FAE, 0xBFBF, 0xFF00, 0xBE13, 0xBFDF, 0x8080, 0x99A9, 0xBE47,
2232     0x7980, 0x050F, 0xB901, 0x8809, 0xBEC6, 0x050E, 0x16A0, 0x26A0, 0xBFB7, 0xFF00, 0xBE1E, 0x1EA0,
2233     0x2EAE, 0xBFBF, 0xFF00, 0xBE13, 0xBFDF, 0x8080, 0x99A9, 0x850C, 0x860F, 0x6907, 0xE388, 0x0516,
2234     0x0D07, 0x8510, 0xBE59, 0x881E, 0xBE4A, 0xEF00, 0x101E, 0x901C, 0x101F, 0x901D, 0x10A0, 0x901E,
2235     0x10A0, 0x901F, 0xEF00, 0x101E, 0x301C, 0x9020, 0x731B, 0x5420, 0xBE03, 0x9825, 0x1025, 0x201C,
2236     0x9025, 0x7325, 0x5414, 0xBE03, 0x8B8E, 0x9880, 0x692F, 0xE388, 0x0539, 0xBE59, 0xBB07, 0x6180,
2237     0x9880, 0x8BA0, 0x101F, 0x301D, 0x9021, 0x731B, 0x5421, 0xBE03, 0x982E, 0x102E, 0x201D, 0x902E,
2238     0x732E, 0x5415, 0xBE03, 0x9880, 0x692F, 0xE388, 0x054F, 0xBE59, 0xBB07, 0x6180, 0x9880, 0x8BA0,
2239     0x6918, 0xEF08, 0x7325, 0x5416, 0xBE03, 0x98A0, 0x732E, 0x5417, 0xBE03, 0x98A0, 0xEF00, 0x8BA0,
2240     0xBEC6, 0x056B, 0xBE59, 0xBB04, 0xAA90, 0xBE04, 0xBE1E, 0x99E0, 0x8BE0, 0x69A0, 0x90D0, 0x69A0,
2241     0x90D0, 0x081F, 0xB805, 0x881F, 0x8B90, 0x69A0, 0x90D0, 0x69A0, 0x9090, 0x8BD0, 0x8BD8, 0xBE1F,
2242     0xEF00, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
2243     0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
2244 };
2245
2246
2247 /*
2248  * initialize ASSP
2249  */
2250
2251 #define MINISRC_LPF_LEN 10
2252 static u16 minisrc_lpf[MINISRC_LPF_LEN] __devinitdata = {
2253         0X0743, 0X1104, 0X0A4C, 0XF88D, 0X242C,
2254         0X1023, 0X1AA9, 0X0B60, 0XEFDD, 0X186F
2255 };
2256
2257 static void __devinit snd_m3_assp_init(m3_t *chip)
2258 {
2259         unsigned int i;
2260
2261         /* zero kernel data */
2262         for (i = 0; i < (REV_B_DATA_MEMORY_UNIT_LENGTH * NUM_UNITS_KERNEL_DATA) / 2; i++)
2263                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2264                                   KDATA_BASE_ADDR + i, 0);
2265
2266         /* zero mixer data? */
2267         for (i = 0; i < (REV_B_DATA_MEMORY_UNIT_LENGTH * NUM_UNITS_KERNEL_DATA) / 2; i++)
2268                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2269                                   KDATA_BASE_ADDR2 + i, 0);
2270
2271         /* init dma pointer */
2272         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2273                           KDATA_CURRENT_DMA,
2274                           KDATA_DMA_XFER0);
2275
2276         /* write kernel into code memory.. */
2277         for (i = 0 ; i < ARRAY_SIZE(assp_kernel_image); i++) {
2278                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE,
2279                                   REV_B_CODE_MEMORY_BEGIN + i,
2280                                   assp_kernel_image[i]);
2281         }
2282
2283         /*
2284          * We only have this one client and we know that 0x400
2285          * is free in our kernel's mem map, so lets just
2286          * drop it there.  It seems that the minisrc doesn't
2287          * need vectors, so we won't bother with them..
2288          */
2289         for (i = 0; i < ARRAY_SIZE(assp_minisrc_image); i++) {
2290                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE,
2291                                   0x400 + i,
2292                                   assp_minisrc_image[i]);
2293         }
2294
2295         /*
2296          * write the coefficients for the low pass filter?
2297          */
2298         for (i = 0; i < MINISRC_LPF_LEN ; i++) {
2299                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE,
2300                                   0x400 + MINISRC_COEF_LOC + i,
2301                                   minisrc_lpf[i]);
2302         }
2303
2304         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE,
2305                           0x400 + MINISRC_COEF_LOC + MINISRC_LPF_LEN,
2306                           0x8000);
2307
2308         /*
2309          * the minisrc is the only thing on
2310          * our task list..
2311          */
2312         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2313                           KDATA_TASK0,
2314                           0x400);
2315
2316         /*
2317          * init the mixer number..
2318          */
2319
2320         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2321                           KDATA_MIXER_TASK_NUMBER,0);
2322
2323         /*
2324          * EXTREME KERNEL MASTER VOLUME
2325          */
2326         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2327                           KDATA_DAC_LEFT_VOLUME, ARB_VOLUME);
2328         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2329                           KDATA_DAC_RIGHT_VOLUME, ARB_VOLUME);
2330
2331         chip->mixer_list.curlen = 0;
2332         chip->mixer_list.mem_addr = KDATA_MIXER_XFER0;
2333         chip->mixer_list.max = MAX_VIRTUAL_MIXER_CHANNELS;
2334         chip->adc1_list.curlen = 0;
2335         chip->adc1_list.mem_addr = KDATA_ADC1_XFER0;
2336         chip->adc1_list.max = MAX_VIRTUAL_ADC1_CHANNELS;
2337         chip->dma_list.curlen = 0;
2338         chip->dma_list.mem_addr = KDATA_DMA_XFER0;
2339         chip->dma_list.max = MAX_VIRTUAL_DMA_CHANNELS;
2340         chip->msrc_list.curlen = 0;
2341         chip->msrc_list.mem_addr = KDATA_INSTANCE0_MINISRC;
2342         chip->msrc_list.max = MAX_INSTANCE_MINISRC;
2343 }
2344
2345
2346 static int __devinit snd_m3_assp_client_init(m3_t *chip, m3_dma_t *s, int index)
2347 {
2348         int data_bytes = 2 * ( MINISRC_TMP_BUFFER_SIZE / 2 +
2349                                MINISRC_IN_BUFFER_SIZE / 2 +
2350                                1 + MINISRC_OUT_BUFFER_SIZE / 2 + 1 );
2351         int address, i;
2352
2353         /*
2354          * the revb memory map has 0x1100 through 0x1c00
2355          * free.
2356          */
2357
2358         /*
2359          * align instance address to 256 bytes so that it's
2360          * shifted list address is aligned.
2361          * list address = (mem address >> 1) >> 7;
2362          */
2363         data_bytes = (data_bytes + 255) & ~255;
2364         address = 0x1100 + ((data_bytes/2) * index);
2365
2366         if ((address + (data_bytes/2)) >= 0x1c00) {
2367                 snd_printk(KERN_ERR "no memory for %d bytes at ind %d (addr 0x%x)\n",
2368                            data_bytes, index, address);
2369                 return -ENOMEM;
2370         }
2371
2372         s->number = index;
2373         s->inst.code = 0x400;
2374         s->inst.data = address;
2375
2376         for (i = data_bytes / 2; i > 0; address++, i--) {
2377                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2378                                   address, 0);
2379         }
2380
2381         return 0;
2382 }
2383
2384
2385 /*
2386  * this works for the reference board, have to find
2387  * out about others
2388  *
2389  * this needs more magic for 4 speaker, but..
2390  */
2391 static void
2392 snd_m3_amp_enable(m3_t *chip, int enable)
2393 {
2394         int io = chip->iobase;
2395         u16 gpo, polarity;
2396
2397         if (! chip->external_amp)
2398                 return;
2399
2400         polarity = enable ? 0 : 1;
2401         polarity = polarity << chip->amp_gpio;
2402         gpo = 1 << chip->amp_gpio;
2403
2404         outw(~gpo, io + GPIO_MASK);
2405
2406         outw(inw(io + GPIO_DIRECTION) | gpo,
2407              io + GPIO_DIRECTION);
2408
2409         outw((GPO_SECONDARY_AC97 | GPO_PRIMARY_AC97 | polarity),
2410              io + GPIO_DATA);
2411
2412         outw(0xffff, io + GPIO_MASK);
2413 }
2414
2415 static int
2416 snd_m3_chip_init(m3_t *chip)
2417 {
2418         struct pci_dev *pcidev = chip->pci;
2419         unsigned long io = chip->iobase;
2420         u32 n;
2421         u16 w;
2422         u8 t; /* makes as much sense as 'n', no? */
2423
2424         pci_read_config_word(pcidev, PCI_LEGACY_AUDIO_CTRL, &w);
2425         w &= ~(SOUND_BLASTER_ENABLE|FM_SYNTHESIS_ENABLE|
2426                MPU401_IO_ENABLE|MPU401_IRQ_ENABLE|ALIAS_10BIT_IO|
2427                DISABLE_LEGACY);
2428         pci_write_config_word(pcidev, PCI_LEGACY_AUDIO_CTRL, w);
2429
2430         if (chip->hv_quirk && chip->hv_quirk->is_omnibook) {
2431                 /*
2432                  * Volume buttons on some HP OmniBook laptops don't work
2433                  * correctly. This makes them work for the most part.
2434                  *
2435                  * Volume up and down buttons on the laptop side work.
2436                  * Fn+cursor_up (volme up) works.
2437                  * Fn+cursor_down (volume down) doesn't work.
2438                  * Fn+F7 (mute) works acts as volume up.
2439                  */
2440                 outw(~(GPI_VOL_DOWN|GPI_VOL_UP), io + GPIO_MASK);
2441                 outw(inw(io + GPIO_DIRECTION) & ~(GPI_VOL_DOWN|GPI_VOL_UP), io + GPIO_DIRECTION);
2442                 outw((GPI_VOL_DOWN|GPI_VOL_UP), io + GPIO_DATA);
2443                 outw(0xffff, io + GPIO_MASK);
2444         }
2445         pci_read_config_dword(pcidev, PCI_ALLEGRO_CONFIG, &n);
2446         n &= ~(HV_CTRL_ENABLE | REDUCED_DEBOUNCE | HV_BUTTON_FROM_GD);
2447         if (chip->hv_quirk)
2448                 n |= chip->hv_quirk->config;
2449         /* For some reason we must always use reduced debounce. */
2450         n |= REDUCED_DEBOUNCE;
2451         n |= PM_CTRL_ENABLE | CLK_DIV_BY_49 | USE_PCI_TIMING;
2452         pci_write_config_dword(pcidev, PCI_ALLEGRO_CONFIG, n);
2453
2454         outb(RESET_ASSP, chip->iobase + ASSP_CONTROL_B);
2455         pci_read_config_dword(pcidev, PCI_ALLEGRO_CONFIG, &n);
2456         n &= ~INT_CLK_SELECT;
2457         if (!chip->allegro_flag) {
2458                 n &= ~INT_CLK_MULT_ENABLE;
2459                 n |= INT_CLK_SRC_NOT_PCI;
2460         }
2461         n &=  ~( CLK_MULT_MODE_SELECT | CLK_MULT_MODE_SELECT_2 );
2462         pci_write_config_dword(pcidev, PCI_ALLEGRO_CONFIG, n);
2463
2464         if (chip->allegro_flag) {
2465                 pci_read_config_dword(pcidev, PCI_USER_CONFIG, &n);
2466                 n |= IN_CLK_12MHZ_SELECT;
2467                 pci_write_config_dword(pcidev, PCI_USER_CONFIG, n);
2468         }
2469
2470         t = inb(chip->iobase + ASSP_CONTROL_A);
2471         t &= ~( DSP_CLK_36MHZ_SELECT  | ASSP_CLK_49MHZ_SELECT);
2472         t |= ASSP_CLK_49MHZ_SELECT;
2473         t |= ASSP_0_WS_ENABLE;
2474         outb(t, chip->iobase + ASSP_CONTROL_A);
2475
2476         snd_m3_assp_init(chip); /* download DSP code before starting ASSP below */
2477         outb(RUN_ASSP, chip->iobase + ASSP_CONTROL_B);
2478
2479         outb(0x00, io + HARDWARE_VOL_CTRL);
2480         outb(0x88, io + SHADOW_MIX_REG_VOICE);
2481         outb(0x88, io + HW_VOL_COUNTER_VOICE);
2482         outb(0x88, io + SHADOW_MIX_REG_MASTER);
2483         outb(0x88, io + HW_VOL_COUNTER_MASTER);
2484
2485         return 0;
2486 }
2487
2488 static void
2489 snd_m3_enable_ints(m3_t *chip)
2490 {
2491         unsigned long io = chip->iobase;
2492         unsigned short val;
2493
2494         /* TODO: MPU401 not supported yet */
2495         val = ASSP_INT_ENABLE /*| MPU401_INT_ENABLE*/;
2496         if (chip->hv_quirk && (chip->hv_quirk->config & HV_CTRL_ENABLE))
2497                 val |= HV_INT_ENABLE;
2498         outw(val, io + HOST_INT_CTRL);
2499         outb(inb(io + ASSP_CONTROL_C) | ASSP_HOST_INT_ENABLE,
2500              io + ASSP_CONTROL_C);
2501 }
2502
2503
2504 /*
2505  */
2506
2507 static int snd_m3_free(m3_t *chip)
2508 {
2509         m3_dma_t *s;
2510         int i;
2511
2512         if (chip->substreams) {
2513                 spin_lock_irq(&chip->reg_lock);
2514                 for (i = 0; i < chip->num_substreams; i++) {
2515                         s = &chip->substreams[i];
2516                         /* check surviving pcms; this should not happen though.. */
2517                         if (s->substream && s->running)
2518                                 snd_m3_pcm_stop(chip, s, s->substream);
2519                 }
2520                 spin_unlock_irq(&chip->reg_lock);
2521                 kfree(chip->substreams);
2522         }
2523         if (chip->iobase) {
2524                 outw(0, chip->iobase + HOST_INT_CTRL); /* disable ints */
2525         }
2526
2527 #ifdef CONFIG_PM
2528         vfree(chip->suspend_mem);
2529 #endif
2530
2531         if (chip->irq >= 0) {
2532                 synchronize_irq(chip->irq);
2533                 free_irq(chip->irq, (void *)chip);
2534         }
2535
2536         if (chip->iobase)
2537                 pci_release_regions(chip->pci);
2538
2539         pci_disable_device(chip->pci);
2540         kfree(chip);
2541         return 0;
2542 }
2543
2544
2545 /*
2546  * APM support
2547  */
2548 #ifdef CONFIG_PM
2549 static int m3_suspend(snd_card_t *card, pm_message_t state)
2550 {
2551         m3_t *chip = card->pm_private_data;
2552         int i, index;
2553
2554         if (chip->suspend_mem == NULL)
2555                 return 0;
2556
2557         snd_pcm_suspend_all(chip->pcm);
2558         snd_ac97_suspend(chip->ac97);
2559
2560         msleep(10); /* give the assp a chance to idle.. */
2561
2562         snd_m3_assp_halt(chip);
2563
2564         /* save dsp image */
2565         index = 0;
2566         for (i = REV_B_CODE_MEMORY_BEGIN; i <= REV_B_CODE_MEMORY_END; i++)
2567                 chip->suspend_mem[index++] =
2568                         snd_m3_assp_read(chip, MEMTYPE_INTERNAL_CODE, i);
2569         for (i = REV_B_DATA_MEMORY_BEGIN ; i <= REV_B_DATA_MEMORY_END; i++)
2570                 chip->suspend_mem[index++] =
2571                         snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA, i);
2572
2573         /* power down apci registers */
2574         snd_m3_outw(chip, 0xffff, 0x54);
2575         snd_m3_outw(chip, 0xffff, 0x56);
2576
2577         pci_disable_device(chip->pci);
2578         return 0;
2579 }
2580
2581 static int m3_resume(snd_card_t *card)
2582 {
2583         m3_t *chip = card->pm_private_data;
2584         int i, index;
2585
2586         if (chip->suspend_mem == NULL)
2587                 return 0;
2588
2589         pci_enable_device(chip->pci);
2590         pci_set_master(chip->pci);
2591
2592         /* first lets just bring everything back. .*/
2593         snd_m3_outw(chip, 0, 0x54);
2594         snd_m3_outw(chip, 0, 0x56);
2595
2596         snd_m3_chip_init(chip);
2597         snd_m3_assp_halt(chip);
2598         snd_m3_ac97_reset(chip);
2599
2600         /* restore dsp image */
2601         index = 0;
2602         for (i = REV_B_CODE_MEMORY_BEGIN; i <= REV_B_CODE_MEMORY_END; i++)
2603                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE, i,
2604                                   chip->suspend_mem[index++]);
2605         for (i = REV_B_DATA_MEMORY_BEGIN ; i <= REV_B_DATA_MEMORY_END; i++)
2606                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, i,
2607                                   chip->suspend_mem[index++]);
2608
2609         /* tell the dma engine to restart itself */
2610         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2611                           KDATA_DMA_ACTIVE, 0);
2612
2613         /* restore ac97 registers */
2614         snd_ac97_resume(chip->ac97);
2615
2616         snd_m3_assp_continue(chip);
2617         snd_m3_enable_ints(chip);
2618         snd_m3_amp_enable(chip, 1);
2619
2620         return 0;
2621 }
2622 #endif /* CONFIG_PM */
2623
2624
2625 /*
2626  */
2627
2628 static int snd_m3_dev_free(snd_device_t *device)
2629 {
2630         m3_t *chip = device->device_data;
2631         return snd_m3_free(chip);
2632 }
2633
2634 static int __devinit
2635 snd_m3_create(snd_card_t *card, struct pci_dev *pci,
2636               int enable_amp,
2637               int amp_gpio,
2638               m3_t **chip_ret)
2639 {
2640         m3_t *chip;
2641         int i, err;
2642         struct m3_quirk *quirk;
2643         struct m3_hv_quirk *hv_quirk;
2644         static snd_device_ops_t ops = {
2645                 .dev_free =     snd_m3_dev_free,
2646         };
2647
2648         *chip_ret = NULL;
2649
2650         if (pci_enable_device(pci))
2651                 return -EIO;
2652
2653         /* check, if we can restrict PCI DMA transfers to 28 bits */
2654         if (pci_set_dma_mask(pci, 0x0fffffff) < 0 ||
2655             pci_set_consistent_dma_mask(pci, 0x0fffffff) < 0) {
2656                 snd_printk(KERN_ERR "architecture does not support 28bit PCI busmaster DMA\n");
2657                 pci_disable_device(pci);
2658                 return -ENXIO;
2659         }
2660
2661         chip = kzalloc(sizeof(*chip), GFP_KERNEL);
2662         if (chip == NULL) {
2663                 pci_disable_device(pci);
2664                 return -ENOMEM;
2665         }
2666
2667         spin_lock_init(&chip->reg_lock);
2668         spin_lock_init(&chip->ac97_lock);
2669
2670         switch (pci->device) {
2671         case PCI_DEVICE_ID_ESS_ALLEGRO:
2672         case PCI_DEVICE_ID_ESS_ALLEGRO_1:
2673         case PCI_DEVICE_ID_ESS_CANYON3D_2LE:
2674         case PCI_DEVICE_ID_ESS_CANYON3D_2:
2675                 chip->allegro_flag = 1;
2676                 break;
2677         }
2678
2679         chip->card = card;
2680         chip->pci = pci;
2681         chip->irq = -1;
2682
2683         for (quirk = m3_quirk_list; quirk->vendor; quirk++) {
2684                 if (pci->subsystem_vendor == quirk->vendor &&
2685                     pci->subsystem_device == quirk->device) {
2686                         printk(KERN_INFO "maestro3: enabled hack for '%s'\n", quirk->name);
2687                         chip->quirk = quirk;
2688                         break;
2689                 }
2690         }
2691
2692         for (hv_quirk = m3_hv_quirk_list; hv_quirk->vendor; hv_quirk++) {
2693                 if (pci->vendor == hv_quirk->vendor &&
2694                     pci->device == hv_quirk->device &&
2695                     pci->subsystem_vendor == hv_quirk->subsystem_vendor &&
2696                     pci->subsystem_device == hv_quirk->subsystem_device) {
2697                         chip->hv_quirk = hv_quirk;
2698                         break;
2699                 }
2700         }
2701
2702         chip->external_amp = enable_amp;
2703         if (amp_gpio >= 0 && amp_gpio <= 0x0f)
2704                 chip->amp_gpio = amp_gpio;
2705         else if (chip->quirk && chip->quirk->amp_gpio >= 0)
2706                 chip->amp_gpio = chip->quirk->amp_gpio;
2707         else if (chip->allegro_flag)
2708                 chip->amp_gpio = GPO_EXT_AMP_ALLEGRO;
2709         else /* presumably this is for all 'maestro3's.. */
2710                 chip->amp_gpio = GPO_EXT_AMP_M3;
2711
2712         chip->num_substreams = NR_DSPS;
2713         chip->substreams = kmalloc(sizeof(m3_dma_t) * chip->num_substreams, GFP_KERNEL);
2714         if (chip->substreams == NULL) {
2715                 kfree(chip);
2716                 pci_disable_device(pci);
2717                 return -ENOMEM;
2718         }
2719         memset(chip->substreams, 0, sizeof(m3_dma_t) * chip->num_substreams);
2720
2721         if ((err = pci_request_regions(pci, card->driver)) < 0) {
2722                 snd_m3_free(chip);
2723                 return err;
2724         }
2725         chip->iobase = pci_resource_start(pci, 0);
2726
2727         /* just to be sure */
2728         pci_set_master(pci);
2729
2730         snd_m3_chip_init(chip);
2731         snd_m3_assp_halt(chip);
2732
2733         snd_m3_ac97_reset(chip);
2734
2735         snd_m3_amp_enable(chip, 1);
2736
2737         tasklet_init(&chip->hwvol_tq, snd_m3_update_hw_volume, (unsigned long)chip);
2738
2739         if (request_irq(pci->irq, snd_m3_interrupt, SA_INTERRUPT|SA_SHIRQ,
2740                         card->driver, (void *)chip)) {
2741                 snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq);
2742                 snd_m3_free(chip);
2743                 return -ENOMEM;
2744         }
2745         chip->irq = pci->irq;
2746
2747 #ifdef CONFIG_PM
2748         chip->suspend_mem = vmalloc(sizeof(u16) * (REV_B_CODE_MEMORY_LENGTH + REV_B_DATA_MEMORY_LENGTH));
2749         if (chip->suspend_mem == NULL)
2750                 snd_printk(KERN_WARNING "can't allocate apm buffer\n");
2751         else
2752                 snd_card_set_pm_callback(card, m3_suspend, m3_resume, chip);
2753 #endif
2754
2755         if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
2756                 snd_m3_free(chip);
2757                 return err;
2758         }
2759
2760         if ((err = snd_m3_mixer(chip)) < 0)
2761                 return err;
2762
2763         for (i = 0; i < chip->num_substreams; i++) {
2764                 m3_dma_t *s = &chip->substreams[i];
2765                 s->chip = chip;
2766                 if ((err = snd_m3_assp_client_init(chip, s, i)) < 0)
2767                         return err;
2768         }
2769
2770         if ((err = snd_m3_pcm(chip, 0)) < 0)
2771                 return err;
2772
2773         snd_m3_enable_ints(chip);
2774         snd_m3_assp_continue(chip);
2775
2776         snd_card_set_dev(card, &pci->dev);
2777
2778         *chip_ret = chip;
2779
2780         return 0;
2781 }
2782
2783 /*
2784  */
2785 static int __devinit
2786 snd_m3_probe(struct pci_dev *pci, const struct pci_device_id *pci_id)
2787 {
2788         static int dev;
2789         snd_card_t *card;
2790         m3_t *chip;
2791         int err;
2792
2793         /* don't pick up modems */
2794         if (((pci->class >> 8) & 0xffff) != PCI_CLASS_MULTIMEDIA_AUDIO)
2795                 return -ENODEV;
2796
2797         if (dev >= SNDRV_CARDS)
2798                 return -ENODEV;
2799         if (!enable[dev]) {
2800                 dev++;
2801                 return -ENOENT;
2802         }
2803
2804         card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0);
2805         if (card == NULL)
2806                 return -ENOMEM;
2807
2808         switch (pci->device) {
2809         case PCI_DEVICE_ID_ESS_ALLEGRO:
2810         case PCI_DEVICE_ID_ESS_ALLEGRO_1:
2811                 strcpy(card->driver, "Allegro");
2812                 break;
2813         case PCI_DEVICE_ID_ESS_CANYON3D_2LE:
2814         case PCI_DEVICE_ID_ESS_CANYON3D_2:
2815                 strcpy(card->driver, "Canyon3D-2");
2816                 break;
2817         default:
2818                 strcpy(card->driver, "Maestro3");
2819                 break;
2820         }
2821
2822         if ((err = snd_m3_create(card, pci,
2823                                  external_amp[dev],
2824                                  amp_gpio[dev],
2825                                  &chip)) < 0) {
2826                 snd_card_free(card);
2827                 return err;
2828         }
2829
2830         sprintf(card->shortname, "ESS %s PCI", card->driver);
2831         sprintf(card->longname, "%s at 0x%lx, irq %d",
2832                 card->shortname, chip->iobase, chip->irq);
2833
2834         if ((err = snd_card_register(card)) < 0) {
2835                 snd_card_free(card);
2836                 return err;
2837         }
2838
2839 #if 0 /* TODO: not supported yet */
2840         /* TODO enable midi irq and i/o */
2841         err = snd_mpu401_uart_new(chip->card, 0, MPU401_HW_MPU401,
2842                                   chip->iobase + MPU401_DATA_PORT, 1,
2843                                   chip->irq, 0, &chip->rmidi);
2844         if (err < 0)
2845                 printk(KERN_WARNING "maestro3: no midi support.\n");
2846 #endif
2847
2848         pci_set_drvdata(pci, card);
2849         dev++;
2850         return 0;
2851 }
2852
2853 static void __devexit snd_m3_remove(struct pci_dev *pci)
2854 {
2855         snd_card_free(pci_get_drvdata(pci));
2856         pci_set_drvdata(pci, NULL);
2857 }
2858
2859 static struct pci_driver driver = {
2860         .name = "Maestro3",
2861         .id_table = snd_m3_ids,
2862         .probe = snd_m3_probe,
2863         .remove = __devexit_p(snd_m3_remove),
2864         SND_PCI_PM_CALLBACKS
2865 };
2866
2867 static int __init alsa_card_m3_init(void)
2868 {
2869         return pci_register_driver(&driver);
2870 }
2871
2872 static void __exit alsa_card_m3_exit(void)
2873 {
2874         pci_unregister_driver(&driver);
2875 }
2876
2877 module_init(alsa_card_m3_init)
2878 module_exit(alsa_card_m3_exit)