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   1 /*
   2  *   ALSA driver for Intel ICH (i8x0) chipsets
   3  *
   4  *      Copyright (c) 2000 Jaroslav Kysela <perex@suse.cz>
   5  *
   6  *
   7  *   This code also contains alpha support for SiS 735 chipsets provided
   8  *   by Mike Pieper <mptei@users.sourceforge.net>. We have no datasheet
   9  *   for SiS735, so the code is not fully functional.
  10  *
  11  *
  12  *   This program is free software; you can redistribute it and/or modify
  13  *   it under the terms of the GNU General Public License as published by
  14  *   the Free Software Foundation; either version 2 of the License, or
  15  *   (at your option) any later version.
  16  *
  17  *   This program is distributed in the hope that it will be useful,
  18  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20  *   GNU General Public License for more details.
  21  *
  22  *   You should have received a copy of the GNU General Public License
  23  *   along with this program; if not, write to the Free Software
  24  *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  25
  26  *
  27  */
  28
  29 #include <sound/driver.h>
  30 #include <asm/io.h>
  31 #include <linux/delay.h>
  32 #include <linux/interrupt.h>
  33 #include <linux/init.h>
  34 #include <linux/pci.h>
  35 #include <linux/slab.h>
  36 #include <linux/moduleparam.h>
  37 #include <sound/core.h>
  38 #include <sound/pcm.h>
  39 #include <sound/ac97_codec.h>
  40 #include <sound/info.h>
  41 #include <sound/initval.h>
  42 /* for 440MX workaround */
  43 #include <asm/pgtable.h>
  44 #include <asm/cacheflush.h>
  45
  46 MODULE_AUTHOR("Jaroslav Kysela <perex@suse.cz>");
  47 MODULE_DESCRIPTION("Intel 82801AA,82901AB,i810,i820,i830,i840,i845,MX440; SiS 7012; Ali 5455");
  48 MODULE_LICENSE("GPL");
  49 MODULE_SUPPORTED_DEVICE("{{Intel,82801AA-ICH},"
  50                 "{Intel,82901AB-ICH0},"
  51                 "{Intel,82801BA-ICH2},"
  52                 "{Intel,82801CA-ICH3},"
  53                 "{Intel,82801DB-ICH4},"
  54                 "{Intel,ICH5},"
  55                 "{Intel,ICH6},"
  56                 "{Intel,ICH7},"
  57                 "{Intel,6300ESB},"
  58                 "{Intel,ESB2},"
  59                 "{Intel,MX440},"
  60                 "{SiS,SI7012},"
  61                 "{NVidia,nForce Audio},"
  62                 "{NVidia,nForce2 Audio},"
  63                 "{AMD,AMD768},"
  64                 "{AMD,AMD8111},"
  65                 "{ALI,M5455}}");
  66
  67 static int index = SNDRV_DEFAULT_IDX1;  /* Index 0-MAX */
  68 static char *id = SNDRV_DEFAULT_STR1;   /* ID for this card */
  69 static int ac97_clock = 0;
  70 static char *ac97_quirk;
  71 static int buggy_semaphore;
  72 static int buggy_irq = -1; /* auto-check */
  73 static int xbox;
  74
  75 module_param(index, int, 0444);
  76 MODULE_PARM_DESC(index, "Index value for Intel i8x0 soundcard.");
  77 module_param(id, charp, 0444);
  78 MODULE_PARM_DESC(id, "ID string for Intel i8x0 soundcard.");
  79 module_param(ac97_clock, int, 0444);
  80 MODULE_PARM_DESC(ac97_clock, "AC'97 codec clock (0 = auto-detect).");
  81 module_param(ac97_quirk, charp, 0444);
  82 MODULE_PARM_DESC(ac97_quirk, "AC'97 workaround for strange hardware.");
  83 module_param(buggy_semaphore, bool, 0444);
  84 MODULE_PARM_DESC(buggy_semaphore, "Enable workaround for hardwares with problematic codec semaphores.");
  85 module_param(buggy_irq, bool, 0444);
  86 MODULE_PARM_DESC(buggy_irq, "Enable workaround for buggy interrupts on some motherboards.");
  87 module_param(xbox, bool, 0444);
  88 MODULE_PARM_DESC(xbox, "Set to 1 for Xbox, if you have problems with the AC'97 codec detection.");
  89
  90 /* just for backward compatibility */
  91 static int enable;
  92 module_param(enable, bool, 0444);
  93 static int joystick;
  94 module_param(joystick, int, 0444);
  95
  96 /*
  97  *  Direct registers
  98  */
  99 enum { DEVICE_INTEL, DEVICE_INTEL_ICH4, DEVICE_SIS, DEVICE_ALI, DEVICE_NFORCE };
 100
 101 #define ICHREG(x) ICH_REG_##x
 102
 103 #define DEFINE_REGSET(name,base) \
 104 enum { \
 105         ICH_REG_##name##_BDBAR  = base + 0x0,   /* dword - buffer descriptor list base address */ \
 106         ICH_REG_##name##_CIV    = base + 0x04,  /* byte - current index value */ \
 107         ICH_REG_##name##_LVI    = base + 0x05,  /* byte - last valid index */ \
 108         ICH_REG_##name##_SR     = base + 0x06,  /* byte - status register */ \
 109         ICH_REG_##name##_PICB   = base + 0x08,  /* word - position in current buffer */ \
 110         ICH_REG_##name##_PIV    = base + 0x0a,  /* byte - prefetched index value */ \
 111         ICH_REG_##name##_CR     = base + 0x0b,  /* byte - control register */ \
 112 };
 113
 114 /* busmaster blocks */
 115 DEFINE_REGSET(OFF, 0);          /* offset */
 116 DEFINE_REGSET(PI, 0x00);        /* PCM in */
 117 DEFINE_REGSET(PO, 0x10);        /* PCM out */
 118 DEFINE_REGSET(MC, 0x20);        /* Mic in */
 119
 120 /* ICH4 busmaster blocks */
 121 DEFINE_REGSET(MC2, 0x40);       /* Mic in 2 */
 122 DEFINE_REGSET(PI2, 0x50);       /* PCM in 2 */
 123 DEFINE_REGSET(SP, 0x60);        /* SPDIF out */
 124
 125 /* values for each busmaster block */
 126
 127 /* LVI */
 128 #define ICH_REG_LVI_MASK                0x1f
 129
 130 /* SR */
 131 #define ICH_FIFOE                       0x10    /* FIFO error */
 132 #define ICH_BCIS                        0x08    /* buffer completion interrupt status */
 133 #define ICH_LVBCI                       0x04    /* last valid buffer completion interrupt */
 134 #define ICH_CELV                        0x02    /* current equals last valid */
 135 #define ICH_DCH                         0x01    /* DMA controller halted */
 136
 137 /* PIV */
 138 #define ICH_REG_PIV_MASK                0x1f    /* mask */
 139
 140 /* CR */
 141 #define ICH_IOCE                        0x10    /* interrupt on completion enable */
 142 #define ICH_FEIE                        0x08    /* fifo error interrupt enable */
 143 #define ICH_LVBIE                       0x04    /* last valid buffer interrupt enable */
 144 #define ICH_RESETREGS                   0x02    /* reset busmaster registers */
 145 #define ICH_STARTBM                     0x01    /* start busmaster operation */
 146
 147
 148 /* global block */
 149 #define ICH_REG_GLOB_CNT                0x2c    /* dword - global control */
 150 #define   ICH_PCM_SPDIF_MASK    0xc0000000      /* s/pdif pcm slot mask (ICH4) */
 151 #define   ICH_PCM_SPDIF_NONE    0x00000000      /* reserved - undefined */
 152 #define   ICH_PCM_SPDIF_78      0x40000000      /* s/pdif pcm on slots 7&8 */
 153 #define   ICH_PCM_SPDIF_69      0x80000000      /* s/pdif pcm on slots 6&9 */
 154 #define   ICH_PCM_SPDIF_1011    0xc0000000      /* s/pdif pcm on slots 10&11 */
 155 #define   ICH_PCM_20BIT         0x00400000      /* 20-bit samples (ICH4) */
 156 #define   ICH_PCM_246_MASK      0x00300000      /* 6 channels (not all chips) */
 157 #define   ICH_PCM_6             0x00200000      /* 6 channels (not all chips) */
 158 #define   ICH_PCM_4             0x00100000      /* 4 channels (not all chips) */
 159 #define   ICH_PCM_2             0x00000000      /* 2 channels (stereo) */
 160 #define   ICH_SIS_PCM_246_MASK  0x000000c0      /* 6 channels (SIS7012) */
 161 #define   ICH_SIS_PCM_6         0x00000080      /* 6 channels (SIS7012) */
 162 #define   ICH_SIS_PCM_4         0x00000040      /* 4 channels (SIS7012) */
 163 #define   ICH_SIS_PCM_2         0x00000000      /* 2 channels (SIS7012) */
 164 #define   ICH_TRIE              0x00000040      /* tertiary resume interrupt enable */
 165 #define   ICH_SRIE              0x00000020      /* secondary resume interrupt enable */
 166 #define   ICH_PRIE              0x00000010      /* primary resume interrupt enable */
 167 #define   ICH_ACLINK            0x00000008      /* AClink shut off */
 168 #define   ICH_AC97WARM          0x00000004      /* AC'97 warm reset */
 169 #define   ICH_AC97COLD          0x00000002      /* AC'97 cold reset */
 170 #define   ICH_GIE               0x00000001      /* GPI interrupt enable */
 171 #define ICH_REG_GLOB_STA                0x30    /* dword - global status */
 172 #define   ICH_TRI               0x20000000      /* ICH4: tertiary (AC_SDIN2) resume interrupt */
 173 #define   ICH_TCR               0x10000000      /* ICH4: tertiary (AC_SDIN2) codec ready */
 174 #define   ICH_BCS               0x08000000      /* ICH4: bit clock stopped */
 175 #define   ICH_SPINT             0x04000000      /* ICH4: S/PDIF interrupt */
 176 #define   ICH_P2INT             0x02000000      /* ICH4: PCM2-In interrupt */
 177 #define   ICH_M2INT             0x01000000      /* ICH4: Mic2-In interrupt */
 178 #define   ICH_SAMPLE_CAP        0x00c00000      /* ICH4: sample capability bits (RO) */
 179 #define   ICH_SAMPLE_16_20      0x00400000      /* ICH4: 16- and 20-bit samples */
 180 #define   ICH_MULTICHAN_CAP     0x00300000      /* ICH4: multi-channel capability bits (RO) */
 181 #define   ICH_MD3               0x00020000      /* modem power down semaphore */
 182 #define   ICH_AD3               0x00010000      /* audio power down semaphore */
 183 #define   ICH_RCS               0x00008000      /* read completion status */
 184 #define   ICH_BIT3              0x00004000      /* bit 3 slot 12 */
 185 #define   ICH_BIT2              0x00002000      /* bit 2 slot 12 */
 186 #define   ICH_BIT1              0x00001000      /* bit 1 slot 12 */
 187 #define   ICH_SRI               0x00000800      /* secondary (AC_SDIN1) resume interrupt */
 188 #define   ICH_PRI               0x00000400      /* primary (AC_SDIN0) resume interrupt */
 189 #define   ICH_SCR               0x00000200      /* secondary (AC_SDIN1) codec ready */
 190 #define   ICH_PCR               0x00000100      /* primary (AC_SDIN0) codec ready */
 191 #define   ICH_MCINT             0x00000080      /* MIC capture interrupt */
 192 #define   ICH_POINT             0x00000040      /* playback interrupt */
 193 #define   ICH_PIINT             0x00000020      /* capture interrupt */
 194 #define   ICH_NVSPINT           0x00000010      /* nforce spdif interrupt */
 195 #define   ICH_MOINT             0x00000004      /* modem playback interrupt */
 196 #define   ICH_MIINT             0x00000002      /* modem capture interrupt */
 197 #define   ICH_GSCI              0x00000001      /* GPI status change interrupt */
 198 #define ICH_REG_ACC_SEMA                0x34    /* byte - codec write semaphore */
 199 #define   ICH_CAS               0x01            /* codec access semaphore */
 200 #define ICH_REG_SDM             0x80
 201 #define   ICH_DI2L_MASK         0x000000c0      /* PCM In 2, Mic In 2 data in line */
 202 #define   ICH_DI2L_SHIFT        6
 203 #define   ICH_DI1L_MASK         0x00000030      /* PCM In 1, Mic In 1 data in line */
 204 #define   ICH_DI1L_SHIFT        4
 205 #define   ICH_SE                0x00000008      /* steer enable */
 206 #define   ICH_LDI_MASK          0x00000003      /* last codec read data input */
 207
 208 #define ICH_MAX_FRAGS           32              /* max hw frags */
 209
 210
 211 /*
 212  * registers for Ali5455
 213  */
 214
 215 /* ALi 5455 busmaster blocks */
 216 DEFINE_REGSET(AL_PI, 0x40);     /* ALi PCM in */
 217 DEFINE_REGSET(AL_PO, 0x50);     /* Ali PCM out */
 218 DEFINE_REGSET(AL_MC, 0x60);     /* Ali Mic in */
 219 DEFINE_REGSET(AL_CDC_SPO, 0x70);        /* Ali Codec SPDIF out */
 220 DEFINE_REGSET(AL_CENTER, 0x80);         /* Ali center out */
 221 DEFINE_REGSET(AL_LFE, 0x90);            /* Ali center out */
 222 DEFINE_REGSET(AL_CLR_SPI, 0xa0);        /* Ali Controller SPDIF in */
 223 DEFINE_REGSET(AL_CLR_SPO, 0xb0);        /* Ali Controller SPDIF out */
 224 DEFINE_REGSET(AL_I2S, 0xc0);    /* Ali I2S in */
 225 DEFINE_REGSET(AL_PI2, 0xd0);    /* Ali PCM2 in */
 226 DEFINE_REGSET(AL_MC2, 0xe0);    /* Ali Mic2 in */
 227
 228 enum {
 229         ICH_REG_ALI_SCR = 0x00,         /* System Control Register */
 230         ICH_REG_ALI_SSR = 0x04,         /* System Status Register  */
 231         ICH_REG_ALI_DMACR = 0x08,       /* DMA Control Register    */
 232         ICH_REG_ALI_FIFOCR1 = 0x0c,     /* FIFO Control Register 1  */
 233         ICH_REG_ALI_INTERFACECR = 0x10, /* Interface Control Register */
 234         ICH_REG_ALI_INTERRUPTCR = 0x14, /* Interrupt control Register */
 235         ICH_REG_ALI_INTERRUPTSR = 0x18, /* Interrupt  Status Register */
 236         ICH_REG_ALI_FIFOCR2 = 0x1c,     /* FIFO Control Register 2   */
 237         ICH_REG_ALI_CPR = 0x20,         /* Command Port Register     */
 238         ICH_REG_ALI_CPR_ADDR = 0x22,    /* ac97 addr write */
 239         ICH_REG_ALI_SPR = 0x24,         /* Status Port Register      */
 240         ICH_REG_ALI_SPR_ADDR = 0x26,    /* ac97 addr read */
 241         ICH_REG_ALI_FIFOCR3 = 0x2c,     /* FIFO Control Register 3  */
 242         ICH_REG_ALI_TTSR = 0x30,        /* Transmit Tag Slot Register */
 243         ICH_REG_ALI_RTSR = 0x34,        /* Receive Tag Slot  Register */
 244         ICH_REG_ALI_CSPSR = 0x38,       /* Command/Status Port Status Register */
 245         ICH_REG_ALI_CAS = 0x3c,         /* Codec Write Semaphore Register */
 246         ICH_REG_ALI_HWVOL = 0xf0,       /* hardware volume control/status */
 247         ICH_REG_ALI_I2SCR = 0xf4,       /* I2S control/status */
 248         ICH_REG_ALI_SPDIFCSR = 0xf8,    /* spdif channel status register  */
 249         ICH_REG_ALI_SPDIFICS = 0xfc,    /* spdif interface control/status  */
 250 };
 251
 252 #define ALI_CAS_SEM_BUSY        0x80000000
 253 #define ALI_CPR_ADDR_SECONDARY  0x100
 254 #define ALI_CPR_ADDR_READ       0x80
 255 #define ALI_CSPSR_CODEC_READY   0x08
 256 #define ALI_CSPSR_READ_OK       0x02
 257 #define ALI_CSPSR_WRITE_OK      0x01
 258
 259 /* interrupts for the whole chip by interrupt status register finish */
 260
 261 #define ALI_INT_MICIN2          (1<<26)
 262 #define ALI_INT_PCMIN2          (1<<25)
 263 #define ALI_INT_I2SIN           (1<<24)
 264 #define ALI_INT_SPDIFOUT        (1<<23) /* controller spdif out INTERRUPT */
 265 #define ALI_INT_SPDIFIN         (1<<22)
 266 #define ALI_INT_LFEOUT          (1<<21)
 267 #define ALI_INT_CENTEROUT       (1<<20)
 268 #define ALI_INT_CODECSPDIFOUT   (1<<19)
 269 #define ALI_INT_MICIN           (1<<18)
 270 #define ALI_INT_PCMOUT          (1<<17)
 271 #define ALI_INT_PCMIN           (1<<16)
 272 #define ALI_INT_CPRAIS          (1<<7)  /* command port available */
 273 #define ALI_INT_SPRAIS          (1<<5)  /* status port available */
 274 #define ALI_INT_GPIO            (1<<1)
 275 #define ALI_INT_MASK            (ALI_INT_SPDIFOUT|ALI_INT_CODECSPDIFOUT|\
 276                                  ALI_INT_MICIN|ALI_INT_PCMOUT|ALI_INT_PCMIN)
 277
 278 #define ICH_ALI_SC_RESET        (1<<31) /* master reset */
 279 #define ICH_ALI_SC_AC97_DBL     (1<<30)
 280 #define ICH_ALI_SC_CODEC_SPDF   (3<<20) /* 1=7/8, 2=6/9, 3=10/11 */
 281 #define ICH_ALI_SC_IN_BITS      (3<<18)
 282 #define ICH_ALI_SC_OUT_BITS     (3<<16)
 283 #define ICH_ALI_SC_6CH_CFG      (3<<14)
 284 #define ICH_ALI_SC_PCM_4        (1<<8)
 285 #define ICH_ALI_SC_PCM_6        (2<<8)
 286 #define ICH_ALI_SC_PCM_246_MASK (3<<8)
 287
 288 #define ICH_ALI_SS_SEC_ID       (3<<5)
 289 #define ICH_ALI_SS_PRI_ID       (3<<3)
 290
 291 #define ICH_ALI_IF_AC97SP       (1<<21)
 292 #define ICH_ALI_IF_MC           (1<<20)
 293 #define ICH_ALI_IF_PI           (1<<19)
 294 #define ICH_ALI_IF_MC2          (1<<18)
 295 #define ICH_ALI_IF_PI2          (1<<17)
 296 #define ICH_ALI_IF_LINE_SRC     (1<<15) /* 0/1 = slot 3/6 */
 297 #define ICH_ALI_IF_MIC_SRC      (1<<14) /* 0/1 = slot 3/6 */
 298 #define ICH_ALI_IF_SPDF_SRC     (3<<12) /* 00 = PCM, 01 = AC97-in, 10 = spdif-in, 11 = i2s */
 299 #define ICH_ALI_IF_AC97_OUT     (3<<8)  /* 00 = PCM, 10 = spdif-in, 11 = i2s */
 300 #define ICH_ALI_IF_PO_SPDF      (1<<3)
 301 #define ICH_ALI_IF_PO           (1<<1)
 302
 303 /*
 304  *
 305  */
 306
 307 enum {
 308         ICHD_PCMIN,
 309         ICHD_PCMOUT,
 310         ICHD_MIC,
 311         ICHD_MIC2,
 312         ICHD_PCM2IN,
 313         ICHD_SPBAR,
 314         ICHD_LAST = ICHD_SPBAR
 315 };
 316 enum {
 317         NVD_PCMIN,
 318         NVD_PCMOUT,
 319         NVD_MIC,
 320         NVD_SPBAR,
 321         NVD_LAST = NVD_SPBAR
 322 };
 323 enum {
 324         ALID_PCMIN,
 325         ALID_PCMOUT,
 326         ALID_MIC,
 327         ALID_AC97SPDIFOUT,
 328         ALID_SPDIFIN,
 329         ALID_SPDIFOUT,
 330         ALID_LAST = ALID_SPDIFOUT
 331 };
 332
 333 #define get_ichdev(substream) (substream->runtime->private_data)
 334
 335 struct ichdev {
 336         unsigned int ichd;                      /* ich device number */
 337         unsigned long reg_offset;               /* offset to bmaddr */
 338         u32 *bdbar;                             /* CPU address (32bit) */
 339         unsigned int bdbar_addr;                /* PCI bus address (32bit) */
 340         struct snd_pcm_substream *substream;
 341         unsigned int physbuf;                   /* physical address (32bit) */
 342         unsigned int size;
 343         unsigned int fragsize;
 344         unsigned int fragsize1;
 345         unsigned int position;
 346         unsigned int pos_shift;
 347         int frags;
 348         int lvi;
 349         int lvi_frag;
 350         int civ;
 351         int ack;
 352         int ack_reload;
 353         unsigned int ack_bit;
 354         unsigned int roff_sr;
 355         unsigned int roff_picb;
 356         unsigned int int_sta_mask;              /* interrupt status mask */
 357         unsigned int ali_slot;                  /* ALI DMA slot */
 358         struct ac97_pcm *pcm;
 359         int pcm_open_flag;
 360         unsigned int page_attr_changed: 1;
 361         unsigned int suspended: 1;
 362 };
 363
 364 struct intel8x0 {
 365         unsigned int device_type;
 366
 367         int irq;
 368
 369         unsigned int mmio;
 370         unsigned long addr;
 371         void __iomem *remap_addr;
 372         unsigned int bm_mmio;
 373         unsigned long bmaddr;
 374         void __iomem *remap_bmaddr;
 375
 376         struct pci_dev *pci;
 377         struct snd_card *card;
 378
 379         int pcm_devs;
 380         struct snd_pcm *pcm[6];
 381         struct ichdev ichd[6];
 382
 383         unsigned multi4: 1,
 384                  multi6: 1,
 385                  dra: 1,
 386                  smp20bit: 1;
 387         unsigned in_ac97_init: 1,
 388                  in_sdin_init: 1;
 389         unsigned in_measurement: 1;     /* during ac97 clock measurement */
 390         unsigned fix_nocache: 1;        /* workaround for 440MX */
 391         unsigned buggy_irq: 1;          /* workaround for buggy mobos */
 392         unsigned xbox: 1;               /* workaround for Xbox AC'97 detection */
 393         unsigned buggy_semaphore: 1;    /* workaround for buggy codec semaphore */
 394
 395         int spdif_idx;  /* SPDIF BAR index; *_SPBAR or -1 if use PCMOUT */
 396         unsigned int sdm_saved; /* SDM reg value */
 397
 398         struct snd_ac97_bus *ac97_bus;
 399         struct snd_ac97 *ac97[3];
 400         unsigned int ac97_sdin[3];
 401
 402         spinlock_t reg_lock;
 403
 404         u32 bdbars_count;
 405         struct snd_dma_buffer bdbars;
 406         u32 int_sta_reg;                /* interrupt status register */
 407         u32 int_sta_mask;               /* interrupt status mask */
 408 };
 409
 410 static struct pci_device_id snd_intel8x0_ids[] = {
 411         { 0x8086, 0x2415, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 82801AA */
 412         { 0x8086, 0x2425, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 82901AB */
 413         { 0x8086, 0x2445, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 82801BA */
 414         { 0x8086, 0x2485, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* ICH3 */
 415         { 0x8086, 0x24c5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ICH4 */
 416         { 0x8086, 0x24d5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ICH5 */
 417         { 0x8086, 0x25a6, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ESB */
 418         { 0x8086, 0x266e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ICH6 */
 419         { 0x8086, 0x27de, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ICH7 */
 420         { 0x8086, 0x2698, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ESB2 */
 421         { 0x8086, 0x7195, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 440MX */
 422         { 0x1039, 0x7012, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_SIS },   /* SI7012 */
 423         { 0x10de, 0x01b1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE },        /* NFORCE */
 424         { 0x10de, 0x003a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE },        /* MCP04 */
 425         { 0x10de, 0x006a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE },        /* NFORCE2 */
 426         { 0x10de, 0x0059, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE },        /* CK804 */
 427         { 0x10de, 0x008a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE },        /* CK8 */
 428         { 0x10de, 0x00da, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE },        /* NFORCE3 */
 429         { 0x10de, 0x00ea, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE },        /* CK8S */
 430         { 0x10de, 0x026b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE },        /* MCP51 */
 431         { 0x1022, 0x746d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* AMD8111 */
 432         { 0x1022, 0x7445, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* AMD768 */
 433         { 0x10b9, 0x5455, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_ALI },   /* Ali5455 */
 434         { 0, }
 435 };
 436
 437 MODULE_DEVICE_TABLE(pci, snd_intel8x0_ids);
 438
 439 /*
 440  *  Lowlevel I/O - busmaster
 441  */
 442
 443 static u8 igetbyte(struct intel8x0 *chip, u32 offset)
 444 {
 445         if (chip->bm_mmio)
 446                 return readb(chip->remap_bmaddr + offset);
 447         else
 448                 return inb(chip->bmaddr + offset);
 449 }
 450
 451 static u16 igetword(struct intel8x0 *chip, u32 offset)
 452 {
 453         if (chip->bm_mmio)
 454                 return readw(chip->remap_bmaddr + offset);
 455         else
 456                 return inw(chip->bmaddr + offset);
 457 }
 458
 459 static u32 igetdword(struct intel8x0 *chip, u32 offset)
 460 {
 461         if (chip->bm_mmio)
 462                 return readl(chip->remap_bmaddr + offset);
 463         else
 464                 return inl(chip->bmaddr + offset);
 465 }
 466
 467 static void iputbyte(struct intel8x0 *chip, u32 offset, u8 val)
 468 {
 469         if (chip->bm_mmio)
 470                 writeb(val, chip->remap_bmaddr + offset);
 471         else
 472                 outb(val, chip->bmaddr + offset);
 473 }
 474
 475 static void iputword(struct intel8x0 *chip, u32 offset, u16 val)
 476 {
 477         if (chip->bm_mmio)
 478                 writew(val, chip->remap_bmaddr + offset);
 479         else
 480                 outw(val, chip->bmaddr + offset);
 481 }
 482
 483 static void iputdword(struct intel8x0 *chip, u32 offset, u32 val)
 484 {
 485         if (chip->bm_mmio)
 486                 writel(val, chip->remap_bmaddr + offset);
 487         else
 488                 outl(val, chip->bmaddr + offset);
 489 }
 490
 491 /*
 492  *  Lowlevel I/O - AC'97 registers
 493  */
 494
 495 static u16 iagetword(struct intel8x0 *chip, u32 offset)
 496 {
 497         if (chip->mmio)
 498                 return readw(chip->remap_addr + offset);
 499         else
 500                 return inw(chip->addr + offset);
 501 }
 502
 503 static void iaputword(struct intel8x0 *chip, u32 offset, u16 val)
 504 {
 505         if (chip->mmio)
 506                 writew(val, chip->remap_addr + offset);
 507         else
 508                 outw(val, chip->addr + offset);
 509 }
 510
 511 /*
 512  *  Basic I/O
 513  */
 514
 515 /*
 516  * access to AC97 codec via normal i/o (for ICH and SIS7012)
 517  */
 518
 519 /* return the GLOB_STA bit for the corresponding codec */
 520 static unsigned int get_ich_codec_bit(struct intel8x0 *chip, unsigned int codec)
 521 {
 522         static unsigned int codec_bit[3] = {
 523                 ICH_PCR, ICH_SCR, ICH_TCR
 524         };
 525         snd_assert(codec < 3, return ICH_PCR);
 526         if (chip->device_type == DEVICE_INTEL_ICH4)
 527                 codec = chip->ac97_sdin[codec];
 528         return codec_bit[codec];
 529 }
 530
 531 static int snd_intel8x0_codec_semaphore(struct intel8x0 *chip, unsigned int codec)
 532 {
 533         int time;
 534
 535         if (codec > 2)
 536                 return -EIO;
 537         if (chip->in_sdin_init) {
 538                 /* we don't know the ready bit assignment at the moment */
 539                 /* so we check any */
 540                 codec = ICH_PCR | ICH_SCR | ICH_TCR;
 541         } else {
 542                 codec = get_ich_codec_bit(chip, codec);
 543         }
 544
 545         /* codec ready ? */
 546         if ((igetdword(chip, ICHREG(GLOB_STA)) & codec) == 0)
 547                 return -EIO;
 548
 549         if (chip->buggy_semaphore)
 550                 return 0; /* just ignore ... */
 551
 552         /* Anyone holding a semaphore for 1 msec should be shot... */
 553         time = 100;
 554         do {
 555                 if (!(igetbyte(chip, ICHREG(ACC_SEMA)) & ICH_CAS))
 556                         return 0;
 557                 udelay(10);
 558         } while (time--);
 559
 560         /* access to some forbidden (non existant) ac97 registers will not
 561          * reset the semaphore. So even if you don't get the semaphore, still
 562          * continue the access. We don't need the semaphore anyway. */
 563         snd_printk(KERN_ERR "codec_semaphore: semaphore is not ready [0x%x][0x%x]\n",
 564                         igetbyte(chip, ICHREG(ACC_SEMA)), igetdword(chip, ICHREG(GLOB_STA)));
 565         iagetword(chip, 0);     /* clear semaphore flag */
 566         /* I don't care about the semaphore */
 567         return -EBUSY;
 568 }
 569
 570 static void snd_intel8x0_codec_write(struct snd_ac97 *ac97,
 571                                      unsigned short reg,
 572                                      unsigned short val)
 573 {
 574         struct intel8x0 *chip = ac97->private_data;
 575
 576         if (snd_intel8x0_codec_semaphore(chip, ac97->num) < 0) {
 577                 if (! chip->in_ac97_init)
 578                         snd_printk(KERN_ERR "codec_write %d: semaphore is not ready for register 0x%x\n", ac97->num, reg);
 579         }
 580         iaputword(chip, reg + ac97->num * 0x80, val);
 581 }
 582
 583 static unsigned short snd_intel8x0_codec_read(struct snd_ac97 *ac97,
 584                                               unsigned short reg)
 585 {
 586         struct intel8x0 *chip = ac97->private_data;
 587         unsigned short res;
 588         unsigned int tmp;
 589
 590         if (snd_intel8x0_codec_semaphore(chip, ac97->num) < 0) {
 591                 if (! chip->in_ac97_init)
 592                         snd_printk(KERN_ERR "codec_read %d: semaphore is not ready for register 0x%x\n", ac97->num, reg);
 593                 res = 0xffff;
 594         } else {
 595                 res = iagetword(chip, reg + ac97->num * 0x80);
 596                 if ((tmp = igetdword(chip, ICHREG(GLOB_STA))) & ICH_RCS) {
 597                         /* reset RCS and preserve other R/WC bits */
 598                         iputdword(chip, ICHREG(GLOB_STA), tmp &
 599                                   ~(ICH_SRI|ICH_PRI|ICH_TRI|ICH_GSCI));
 600                         if (! chip->in_ac97_init)
 601                                 snd_printk(KERN_ERR "codec_read %d: read timeout for register 0x%x\n", ac97->num, reg);
 602                         res = 0xffff;
 603                 }
 604         }
 605         return res;
 606 }
 607
 608 static void snd_intel8x0_codec_read_test(struct intel8x0 *chip, unsigned int codec)
 609 {
 610         unsigned int tmp;
 611
 612         if (snd_intel8x0_codec_semaphore(chip, codec) >= 0) {
 613                 iagetword(chip, codec * 0x80);
 614                 if ((tmp = igetdword(chip, ICHREG(GLOB_STA))) & ICH_RCS) {
 615                         /* reset RCS and preserve other R/WC bits */
 616                         iputdword(chip, ICHREG(GLOB_STA), tmp &
 617                                   ~(ICH_SRI|ICH_PRI|ICH_TRI|ICH_GSCI));
 618                 }
 619         }
 620 }
 621
 622 /*
 623  * access to AC97 for Ali5455
 624  */
 625 static int snd_intel8x0_ali_codec_ready(struct intel8x0 *chip, int mask)
 626 {
 627         int count = 0;
 628         for (count = 0; count < 0x7f; count++) {
 629                 int val = igetbyte(chip, ICHREG(ALI_CSPSR));
 630                 if (val & mask)
 631                         return 0;
 632         }
 633         if (! chip->in_ac97_init)
 634                 snd_printd(KERN_WARNING "intel8x0: AC97 codec ready timeout.\n");
 635         return -EBUSY;
 636 }
 637
 638 static int snd_intel8x0_ali_codec_semaphore(struct intel8x0 *chip)
 639 {
 640         int time = 100;
 641         if (chip->buggy_semaphore)
 642                 return 0; /* just ignore ... */
 643         while (time-- && (igetdword(chip, ICHREG(ALI_CAS)) & ALI_CAS_SEM_BUSY))
 644                 udelay(1);
 645         if (! time && ! chip->in_ac97_init)
 646                 snd_printk(KERN_WARNING "ali_codec_semaphore timeout\n");
 647         return snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_CODEC_READY);
 648 }
 649
 650 static unsigned short snd_intel8x0_ali_codec_read(struct snd_ac97 *ac97, unsigned short reg)
 651 {
 652         struct intel8x0 *chip = ac97->private_data;
 653         unsigned short data = 0xffff;
 654
 655         if (snd_intel8x0_ali_codec_semaphore(chip))
 656                 goto __err;
 657         reg |= ALI_CPR_ADDR_READ;
 658         if (ac97->num)
 659                 reg |= ALI_CPR_ADDR_SECONDARY;
 660         iputword(chip, ICHREG(ALI_CPR_ADDR), reg);
 661         if (snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_READ_OK))
 662                 goto __err;
 663         data = igetword(chip, ICHREG(ALI_SPR));
 664  __err:
 665         return data;
 666 }
 667
 668 static void snd_intel8x0_ali_codec_write(struct snd_ac97 *ac97, unsigned short reg,
 669                                          unsigned short val)
 670 {
 671         struct intel8x0 *chip = ac97->private_data;
 672
 673         if (snd_intel8x0_ali_codec_semaphore(chip))
 674                 return;
 675         iputword(chip, ICHREG(ALI_CPR), val);
 676         if (ac97->num)
 677                 reg |= ALI_CPR_ADDR_SECONDARY;
 678         iputword(chip, ICHREG(ALI_CPR_ADDR), reg);
 679         snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_WRITE_OK);
 680 }
 681
 682
 683 /*
 684  * DMA I/O
 685  */
 686 static void snd_intel8x0_setup_periods(struct intel8x0 *chip, struct ichdev *ichdev)
 687 {
 688         int idx;
 689         u32 *bdbar = ichdev->bdbar;
 690         unsigned long port = ichdev->reg_offset;
 691
 692         iputdword(chip, port + ICH_REG_OFF_BDBAR, ichdev->bdbar_addr);
 693         if (ichdev->size == ichdev->fragsize) {
 694                 ichdev->ack_reload = ichdev->ack = 2;
 695                 ichdev->fragsize1 = ichdev->fragsize >> 1;
 696                 for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 4) {
 697                         bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf);
 698                         bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */
 699                                                      ichdev->fragsize1 >> ichdev->pos_shift);
 700                         bdbar[idx + 2] = cpu_to_le32(ichdev->physbuf + (ichdev->size >> 1));
 701                         bdbar[idx + 3] = cpu_to_le32(0x80000000 | /* interrupt on completion */
 702                                                      ichdev->fragsize1 >> ichdev->pos_shift);
 703                 }
 704                 ichdev->frags = 2;
 705         } else {
 706                 ichdev->ack_reload = ichdev->ack = 1;
 707                 ichdev->fragsize1 = ichdev->fragsize;
 708                 for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 2) {
 709                         bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf +
 710                                                      (((idx >> 1) * ichdev->fragsize) %
 711                                                       ichdev->size));
 712                         bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */
 713                                                      ichdev->fragsize >> ichdev->pos_shift);
 714 #if 0
 715                         printk("bdbar[%i] = 0x%x [0x%x]\n",
 716                                idx + 0, bdbar[idx + 0], bdbar[idx + 1]);
 717 #endif
 718                 }
 719                 ichdev->frags = ichdev->size / ichdev->fragsize;
 720         }
 721         iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi = ICH_REG_LVI_MASK);
 722         ichdev->civ = 0;
 723         iputbyte(chip, port + ICH_REG_OFF_CIV, 0);
 724         ichdev->lvi_frag = ICH_REG_LVI_MASK % ichdev->frags;
 725         ichdev->position = 0;
 726 #if 0
 727         printk("lvi_frag = %i, frags = %i, period_size = 0x%x, period_size1 = 0x%x\n",
 728                         ichdev->lvi_frag, ichdev->frags, ichdev->fragsize, ichdev->fragsize1);
 729 #endif
 730         /* clear interrupts */
 731         iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI);
 732 }
 733
 734 #ifdef __i386__
 735 /*
 736  * Intel 82443MX running a 100MHz processor system bus has a hardware bug,
 737  * which aborts PCI busmaster for audio transfer.  A workaround is to set
 738  * the pages as non-cached.  For details, see the errata in
 739  *      http://www.intel.com/design/chipsets/specupdt/245051.htm
 740  */
 741 static void fill_nocache(void *buf, int size, int nocache)
 742 {
 743         size = (size + PAGE_SIZE - 1) >> PAGE_SHIFT;
 744         change_page_attr(virt_to_page(buf), size, nocache ? PAGE_KERNEL_NOCACHE : PAGE_KERNEL);
 745         global_flush_tlb();
 746 }
 747 #else
 748 #define fill_nocache(buf,size,nocache)
 749 #endif
 750
 751 /*
 752  *  Interrupt handler
 753  */
 754
 755 static inline void snd_intel8x0_update(struct intel8x0 *chip, struct ichdev *ichdev)
 756 {
 757         unsigned long port = ichdev->reg_offset;
 758         int status, civ, i, step;
 759         int ack = 0;
 760
 761         spin_lock(&chip->reg_lock);
 762         status = igetbyte(chip, port + ichdev->roff_sr);
 763         civ = igetbyte(chip, port + ICH_REG_OFF_CIV);
 764         if (!(status & ICH_BCIS)) {
 765                 step = 0;
 766         } else if (civ == ichdev->civ) {
 767                 // snd_printd("civ same %d\n", civ);
 768                 step = 1;
 769                 ichdev->civ++;
 770                 ichdev->civ &= ICH_REG_LVI_MASK;
 771         } else {
 772                 step = civ - ichdev->civ;
 773                 if (step < 0)
 774                         step += ICH_REG_LVI_MASK + 1;
 775                 // if (step != 1)
 776                 //      snd_printd("step = %d, %d -> %d\n", step, ichdev->civ, civ);
 777                 ichdev->civ = civ;
 778         }
 779
 780         ichdev->position += step * ichdev->fragsize1;
 781         if (! chip->in_measurement)
 782                 ichdev->position %= ichdev->size;
 783         ichdev->lvi += step;
 784         ichdev->lvi &= ICH_REG_LVI_MASK;
 785         iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi);
 786         for (i = 0; i < step; i++) {
 787                 ichdev->lvi_frag++;
 788                 ichdev->lvi_frag %= ichdev->frags;
 789                 ichdev->bdbar[ichdev->lvi * 2] = cpu_to_le32(ichdev->physbuf + ichdev->lvi_frag * ichdev->fragsize1);
 790 #if 0
 791         printk("new: bdbar[%i] = 0x%x [0x%x], prefetch = %i, all = 0x%x, 0x%x\n",
 792                ichdev->lvi * 2, ichdev->bdbar[ichdev->lvi * 2],
 793                ichdev->bdbar[ichdev->lvi * 2 + 1], inb(ICH_REG_OFF_PIV + port),
 794                inl(port + 4), inb(port + ICH_REG_OFF_CR));
 795 #endif
 796                 if (--ichdev->ack == 0) {
 797                         ichdev->ack = ichdev->ack_reload;
 798                         ack = 1;
 799                 }
 800         }
 801         spin_unlock(&chip->reg_lock);
 802         if (ack && ichdev->substream) {
 803                 snd_pcm_period_elapsed(ichdev->substream);
 804         }
 805         iputbyte(chip, port + ichdev->roff_sr,
 806                  status & (ICH_FIFOE | ICH_BCIS | ICH_LVBCI));
 807 }
 808
 809 static irqreturn_t snd_intel8x0_interrupt(int irq, void *dev_id, struct pt_regs *regs)
 810 {
 811         struct intel8x0 *chip = dev_id;
 812         struct ichdev *ichdev;
 813         unsigned int status;
 814         unsigned int i;
 815
 816         status = igetdword(chip, chip->int_sta_reg);
 817         if (status == 0xffffffff)       /* we are not yet resumed */
 818                 return IRQ_NONE;
 819
 820         if ((status & chip->int_sta_mask) == 0) {
 821                 if (status) {
 822                         /* ack */
 823                         iputdword(chip, chip->int_sta_reg, status);
 824                         if (! chip->buggy_irq)
 825                                 status = 0;
 826                 }
 827                 return IRQ_RETVAL(status);
 828         }
 829
 830         for (i = 0; i < chip->bdbars_count; i++) {
 831                 ichdev = &chip->ichd[i];
 832                 if (status & ichdev->int_sta_mask)
 833                         snd_intel8x0_update(chip, ichdev);
 834         }
 835
 836         /* ack them */
 837         iputdword(chip, chip->int_sta_reg, status & chip->int_sta_mask);
 838
 839         return IRQ_HANDLED;
 840 }
 841
 842 /*
 843  *  PCM part
 844  */
 845
 846 static int snd_intel8x0_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
 847 {
 848         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
 849         struct ichdev *ichdev = get_ichdev(substream);
 850         unsigned char val = 0;
 851         unsigned long port = ichdev->reg_offset;
 852
 853         switch (cmd) {
 854         case SNDRV_PCM_TRIGGER_RESUME:
 855                 ichdev->suspended = 0;
 856                 /* fallthru */
 857         case SNDRV_PCM_TRIGGER_START:
 858                 val = ICH_IOCE | ICH_STARTBM;
 859                 break;
 860         case SNDRV_PCM_TRIGGER_SUSPEND:
 861                 ichdev->suspended = 1;
 862                 /* fallthru */
 863         case SNDRV_PCM_TRIGGER_STOP:
 864                 val = 0;
 865                 break;
 866         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 867                 val = ICH_IOCE;
 868                 break;
 869         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 870                 val = ICH_IOCE | ICH_STARTBM;
 871                 break;
 872         default:
 873                 return -EINVAL;
 874         }
 875         iputbyte(chip, port + ICH_REG_OFF_CR, val);
 876         if (cmd == SNDRV_PCM_TRIGGER_STOP) {
 877                 /* wait until DMA stopped */
 878                 while (!(igetbyte(chip, port + ichdev->roff_sr) & ICH_DCH)) ;
 879                 /* reset whole DMA things */
 880                 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
 881         }
 882         return 0;
 883 }
 884
 885 static int snd_intel8x0_ali_trigger(struct snd_pcm_substream *substream, int cmd)
 886 {
 887         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
 888         struct ichdev *ichdev = get_ichdev(substream);
 889         unsigned long port = ichdev->reg_offset;
 890         static int fiforeg[] = {
 891                 ICHREG(ALI_FIFOCR1), ICHREG(ALI_FIFOCR2), ICHREG(ALI_FIFOCR3)
 892         };
 893         unsigned int val, fifo;
 894
 895         val = igetdword(chip, ICHREG(ALI_DMACR));
 896         switch (cmd) {
 897         case SNDRV_PCM_TRIGGER_RESUME:
 898                 ichdev->suspended = 0;
 899                 /* fallthru */
 900         case SNDRV_PCM_TRIGGER_START:
 901         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 902                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
 903                         /* clear FIFO for synchronization of channels */
 904                         fifo = igetdword(chip, fiforeg[ichdev->ali_slot / 4]);
 905                         fifo &= ~(0xff << (ichdev->ali_slot % 4));
 906                         fifo |= 0x83 << (ichdev->ali_slot % 4);
 907                         iputdword(chip, fiforeg[ichdev->ali_slot / 4], fifo);
 908                 }
 909                 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE);
 910                 val &= ~(1 << (ichdev->ali_slot + 16)); /* clear PAUSE flag */
 911                 /* start DMA */
 912                 iputdword(chip, ICHREG(ALI_DMACR), val | (1 << ichdev->ali_slot));
 913                 break;
 914         case SNDRV_PCM_TRIGGER_SUSPEND:
 915                 ichdev->suspended = 1;
 916                 /* fallthru */
 917         case SNDRV_PCM_TRIGGER_STOP:
 918         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 919                 /* pause */
 920                 iputdword(chip, ICHREG(ALI_DMACR), val | (1 << (ichdev->ali_slot + 16)));
 921                 iputbyte(chip, port + ICH_REG_OFF_CR, 0);
 922                 while (igetbyte(chip, port + ICH_REG_OFF_CR))
 923                         ;
 924                 if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH)
 925                         break;
 926                 /* reset whole DMA things */
 927                 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
 928                 /* clear interrupts */
 929                 iputbyte(chip, port + ICH_REG_OFF_SR,
 930                          igetbyte(chip, port + ICH_REG_OFF_SR) | 0x1e);
 931                 iputdword(chip, ICHREG(ALI_INTERRUPTSR),
 932                           igetdword(chip, ICHREG(ALI_INTERRUPTSR)) & ichdev->int_sta_mask);
 933                 break;
 934         default:
 935                 return -EINVAL;
 936         }
 937         return 0;
 938 }
 939
 940 static int snd_intel8x0_hw_params(struct snd_pcm_substream *substream,
 941                                   struct snd_pcm_hw_params *hw_params)
 942 {
 943         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
 944         struct ichdev *ichdev = get_ichdev(substream);
 945         struct snd_pcm_runtime *runtime = substream->runtime;
 946         int dbl = params_rate(hw_params) > 48000;
 947         int err;
 948
 949         if (chip->fix_nocache && ichdev->page_attr_changed) {
 950                 fill_nocache(runtime->dma_area, runtime->dma_bytes, 0); /* clear */
 951                 ichdev->page_attr_changed = 0;
 952         }
 953         err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
 954         if (err < 0)
 955                 return err;
 956         if (chip->fix_nocache) {
 957                 if (runtime->dma_area && ! ichdev->page_attr_changed) {
 958                         fill_nocache(runtime->dma_area, runtime->dma_bytes, 1);
 959                         ichdev->page_attr_changed = 1;
 960                 }
 961         }
 962         if (ichdev->pcm_open_flag) {
 963                 snd_ac97_pcm_close(ichdev->pcm);
 964                 ichdev->pcm_open_flag = 0;
 965         }
 966         err = snd_ac97_pcm_open(ichdev->pcm, params_rate(hw_params),
 967                                 params_channels(hw_params),
 968                                 ichdev->pcm->r[dbl].slots);
 969         if (err >= 0) {
 970                 ichdev->pcm_open_flag = 1;
 971                 /* Force SPDIF setting */
 972                 if (ichdev->ichd == ICHD_PCMOUT && chip->spdif_idx < 0)
 973                         snd_ac97_set_rate(ichdev->pcm->r[0].codec[0], AC97_SPDIF,
 974                                           params_rate(hw_params));
 975         }
 976         return err;
 977 }
 978
 979 static int snd_intel8x0_hw_free(struct snd_pcm_substream *substream)
 980 {
 981         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
 982         struct ichdev *ichdev = get_ichdev(substream);
 983
 984         if (ichdev->pcm_open_flag) {
 985                 snd_ac97_pcm_close(ichdev->pcm);
 986                 ichdev->pcm_open_flag = 0;
 987         }
 988         if (chip->fix_nocache && ichdev->page_attr_changed) {
 989                 fill_nocache(substream->runtime->dma_area, substream->runtime->dma_bytes, 0);
 990                 ichdev->page_attr_changed = 0;
 991         }
 992         return snd_pcm_lib_free_pages(substream);
 993 }
 994
 995 static void snd_intel8x0_setup_pcm_out(struct intel8x0 *chip,
 996                                        struct snd_pcm_runtime *runtime)
 997 {
 998         unsigned int cnt;
 999         int dbl = runtime->rate > 48000;
1000
1001         spin_lock_irq(&chip->reg_lock);
1002         switch (chip->device_type) {
1003         case DEVICE_ALI:
1004                 cnt = igetdword(chip, ICHREG(ALI_SCR));
1005                 cnt &= ~ICH_ALI_SC_PCM_246_MASK;
1006                 if (runtime->channels == 4 || dbl)
1007                         cnt |= ICH_ALI_SC_PCM_4;
1008                 else if (runtime->channels == 6)
1009                         cnt |= ICH_ALI_SC_PCM_6;
1010                 iputdword(chip, ICHREG(ALI_SCR), cnt);
1011                 break;
1012         case DEVICE_SIS:
1013                 cnt = igetdword(chip, ICHREG(GLOB_CNT));
1014                 cnt &= ~ICH_SIS_PCM_246_MASK;
1015                 if (runtime->channels == 4 || dbl)
1016                         cnt |= ICH_SIS_PCM_4;
1017                 else if (runtime->channels == 6)
1018                         cnt |= ICH_SIS_PCM_6;
1019                 iputdword(chip, ICHREG(GLOB_CNT), cnt);
1020                 break;
1021         default:
1022                 cnt = igetdword(chip, ICHREG(GLOB_CNT));
1023                 cnt &= ~(ICH_PCM_246_MASK | ICH_PCM_20BIT);
1024                 if (runtime->channels == 4 || dbl)
1025                         cnt |= ICH_PCM_4;
1026                 else if (runtime->channels == 6)
1027                         cnt |= ICH_PCM_6;
1028                 if (chip->device_type == DEVICE_NFORCE) {
1029                         /* reset to 2ch once to keep the 6 channel data in alignment,
1030                          * to start from Front Left always
1031                          */
1032                         if (cnt & ICH_PCM_246_MASK) {
1033                                 iputdword(chip, ICHREG(GLOB_CNT), cnt & ~ICH_PCM_246_MASK);
1034                                 spin_unlock_irq(&chip->reg_lock);
1035                                 msleep(50); /* grrr... */
1036                                 spin_lock_irq(&chip->reg_lock);
1037                         }
1038                 } else if (chip->device_type == DEVICE_INTEL_ICH4) {
1039                         if (runtime->sample_bits > 16)
1040                                 cnt |= ICH_PCM_20BIT;
1041                 }
1042                 iputdword(chip, ICHREG(GLOB_CNT), cnt);
1043                 break;
1044         }
1045         spin_unlock_irq(&chip->reg_lock);
1046 }
1047
1048 static int snd_intel8x0_pcm_prepare(struct snd_pcm_substream *substream)
1049 {
1050         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1051         struct snd_pcm_runtime *runtime = substream->runtime;
1052         struct ichdev *ichdev = get_ichdev(substream);
1053
1054         ichdev->physbuf = runtime->dma_addr;
1055         ichdev->size = snd_pcm_lib_buffer_bytes(substream);
1056         ichdev->fragsize = snd_pcm_lib_period_bytes(substream);
1057         if (ichdev->ichd == ICHD_PCMOUT) {
1058                 snd_intel8x0_setup_pcm_out(chip, runtime);
1059                 if (chip->device_type == DEVICE_INTEL_ICH4)
1060                         ichdev->pos_shift = (runtime->sample_bits > 16) ? 2 : 1;
1061         }
1062         snd_intel8x0_setup_periods(chip, ichdev);
1063         return 0;
1064 }
1065
1066 static snd_pcm_uframes_t snd_intel8x0_pcm_pointer(struct snd_pcm_substream *substream)
1067 {
1068         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1069         struct ichdev *ichdev = get_ichdev(substream);
1070         size_t ptr1, ptr;
1071         int civ, timeout = 100;
1072         unsigned int position;
1073
1074         spin_lock(&chip->reg_lock);
1075         do {
1076                 civ = igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV);
1077                 ptr1 = igetword(chip, ichdev->reg_offset + ichdev->roff_picb);
1078                 position = ichdev->position;
1079                 if (ptr1 == 0) {
1080                         udelay(10);
1081                         continue;
1082                 }
1083                 if (civ == igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV) &&
1084                     ptr1 == igetword(chip, ichdev->reg_offset + ichdev->roff_picb))
1085                         break;
1086         } while (timeout--);
1087         ptr1 <<= ichdev->pos_shift;
1088         ptr = ichdev->fragsize1 - ptr1;
1089         ptr += position;
1090         spin_unlock(&chip->reg_lock);
1091         if (ptr >= ichdev->size)
1092                 return 0;
1093         return bytes_to_frames(substream->runtime, ptr);
1094 }
1095
1096 static struct snd_pcm_hardware snd_intel8x0_stream =
1097 {
1098         .info =                 (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1099                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
1100                                  SNDRV_PCM_INFO_MMAP_VALID |
1101                                  SNDRV_PCM_INFO_PAUSE |
1102                                  SNDRV_PCM_INFO_RESUME),
1103         .formats =              SNDRV_PCM_FMTBIT_S16_LE,
1104         .rates =                SNDRV_PCM_RATE_48000,
1105         .rate_min =             48000,
1106         .rate_max =             48000,
1107         .channels_min =         2,
1108         .channels_max =         2,
1109         .buffer_bytes_max =     128 * 1024,
1110         .period_bytes_min =     32,
1111         .period_bytes_max =     128 * 1024,
1112         .periods_min =          1,
1113         .periods_max =          1024,
1114         .fifo_size =            0,
1115 };
1116
1117 static unsigned int channels4[] = {
1118         2, 4,
1119 };
1120
1121 static struct snd_pcm_hw_constraint_list hw_constraints_channels4 = {
1122         .count = ARRAY_SIZE(channels4),
1123         .list = channels4,
1124         .mask = 0,
1125 };
1126
1127 static unsigned int channels6[] = {
1128         2, 4, 6,
1129 };
1130
1131 static struct snd_pcm_hw_constraint_list hw_constraints_channels6 = {
1132         .count = ARRAY_SIZE(channels6),
1133         .list = channels6,
1134         .mask = 0,
1135 };
1136
1137 static int snd_intel8x0_pcm_open(struct snd_pcm_substream *substream, struct ichdev *ichdev)
1138 {
1139         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1140         struct snd_pcm_runtime *runtime = substream->runtime;
1141         int err;
1142
1143         ichdev->substream = substream;
1144         runtime->hw = snd_intel8x0_stream;
1145         runtime->hw.rates = ichdev->pcm->rates;
1146         snd_pcm_limit_hw_rates(runtime);
1147         if (chip->device_type == DEVICE_SIS) {
1148                 runtime->hw.buffer_bytes_max = 64*1024;
1149                 runtime->hw.period_bytes_max = 64*1024;
1150         }
1151         if ((err = snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS)) < 0)
1152                 return err;
1153         runtime->private_data = ichdev;
1154         return 0;
1155 }
1156
1157 static int snd_intel8x0_playback_open(struct snd_pcm_substream *substream)
1158 {
1159         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1160         struct snd_pcm_runtime *runtime = substream->runtime;
1161         int err;
1162
1163         err = snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCMOUT]);
1164         if (err < 0)
1165                 return err;
1166
1167         if (chip->multi6) {
1168                 runtime->hw.channels_max = 6;
1169                 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
1170                                            &hw_constraints_channels6);
1171         } else if (chip->multi4) {
1172                 runtime->hw.channels_max = 4;
1173                 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
1174                                            &hw_constraints_channels4);
1175         }
1176         if (chip->dra) {
1177                 snd_ac97_pcm_double_rate_rules(runtime);
1178         }
1179         if (chip->smp20bit) {
1180                 runtime->hw.formats |= SNDRV_PCM_FMTBIT_S32_LE;
1181                 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 20);
1182         }
1183         return 0;
1184 }
1185
1186 static int snd_intel8x0_playback_close(struct snd_pcm_substream *substream)
1187 {
1188         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1189
1190         chip->ichd[ICHD_PCMOUT].substream = NULL;
1191         return 0;
1192 }
1193
1194 static int snd_intel8x0_capture_open(struct snd_pcm_substream *substream)
1195 {
1196         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1197
1198         return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCMIN]);
1199 }
1200
1201 static int snd_intel8x0_capture_close(struct snd_pcm_substream *substream)
1202 {
1203         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1204
1205         chip->ichd[ICHD_PCMIN].substream = NULL;
1206         return 0;
1207 }
1208
1209 static int snd_intel8x0_mic_open(struct snd_pcm_substream *substream)
1210 {
1211         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1212
1213         return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_MIC]);
1214 }
1215
1216 static int snd_intel8x0_mic_close(struct snd_pcm_substream *substream)
1217 {
1218         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1219
1220         chip->ichd[ICHD_MIC].substream = NULL;
1221         return 0;
1222 }
1223
1224 static int snd_intel8x0_mic2_open(struct snd_pcm_substream *substream)
1225 {
1226         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1227
1228         return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_MIC2]);
1229 }
1230
1231 static int snd_intel8x0_mic2_close(struct snd_pcm_substream *substream)
1232 {
1233         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1234
1235         chip->ichd[ICHD_MIC2].substream = NULL;
1236         return 0;
1237 }
1238
1239 static int snd_intel8x0_capture2_open(struct snd_pcm_substream *substream)
1240 {
1241         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1242
1243         return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCM2IN]);
1244 }
1245
1246 static int snd_intel8x0_capture2_close(struct snd_pcm_substream *substream)
1247 {
1248         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1249
1250         chip->ichd[ICHD_PCM2IN].substream = NULL;
1251         return 0;
1252 }
1253
1254 static int snd_intel8x0_spdif_open(struct snd_pcm_substream *substream)
1255 {
1256         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1257         int idx = chip->device_type == DEVICE_NFORCE ? NVD_SPBAR : ICHD_SPBAR;
1258
1259         return snd_intel8x0_pcm_open(substream, &chip->ichd[idx]);
1260 }
1261
1262 static int snd_intel8x0_spdif_close(struct snd_pcm_substream *substream)
1263 {
1264         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1265         int idx = chip->device_type == DEVICE_NFORCE ? NVD_SPBAR : ICHD_SPBAR;
1266
1267         chip->ichd[idx].substream = NULL;
1268         return 0;
1269 }
1270
1271 static int snd_intel8x0_ali_ac97spdifout_open(struct snd_pcm_substream *substream)
1272 {
1273         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1274         unsigned int val;
1275
1276         spin_lock_irq(&chip->reg_lock);
1277         val = igetdword(chip, ICHREG(ALI_INTERFACECR));
1278         val |= ICH_ALI_IF_AC97SP;
1279         iputdword(chip, ICHREG(ALI_INTERFACECR), val);
1280         /* also needs to set ALI_SC_CODEC_SPDF correctly */
1281         spin_unlock_irq(&chip->reg_lock);
1282
1283         return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_AC97SPDIFOUT]);
1284 }
1285
1286 static int snd_intel8x0_ali_ac97spdifout_close(struct snd_pcm_substream *substream)
1287 {
1288         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1289         unsigned int val;
1290
1291         chip->ichd[ALID_AC97SPDIFOUT].substream = NULL;
1292         spin_lock_irq(&chip->reg_lock);
1293         val = igetdword(chip, ICHREG(ALI_INTERFACECR));
1294         val &= ~ICH_ALI_IF_AC97SP;
1295         iputdword(chip, ICHREG(ALI_INTERFACECR), val);
1296         spin_unlock_irq(&chip->reg_lock);
1297
1298         return 0;
1299 }
1300
1301 static int snd_intel8x0_ali_spdifin_open(struct snd_pcm_substream *substream)
1302 {
1303         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1304
1305         return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_SPDIFIN]);
1306 }
1307
1308 static int snd_intel8x0_ali_spdifin_close(struct snd_pcm_substream *substream)
1309 {
1310         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1311
1312         chip->ichd[ALID_SPDIFIN].substream = NULL;
1313         return 0;
1314 }
1315
1316 #if 0 // NYI
1317 static int snd_intel8x0_ali_spdifout_open(struct snd_pcm_substream *substream)
1318 {
1319         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1320
1321         return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_SPDIFOUT]);
1322 }
1323
1324 static int snd_intel8x0_ali_spdifout_close(struct snd_pcm_substream *substream)
1325 {
1326         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1327
1328         chip->ichd[ALID_SPDIFOUT].substream = NULL;
1329         return 0;
1330 }
1331 #endif
1332
1333 static struct snd_pcm_ops snd_intel8x0_playback_ops = {
1334         .open =         snd_intel8x0_playback_open,
1335         .close =        snd_intel8x0_playback_close,
1336         .ioctl =        snd_pcm_lib_ioctl,
1337         .hw_params =    snd_intel8x0_hw_params,
1338         .hw_free =      snd_intel8x0_hw_free,
1339         .prepare =      snd_intel8x0_pcm_prepare,
1340         .trigger =      snd_intel8x0_pcm_trigger,
1341         .pointer =      snd_intel8x0_pcm_pointer,
1342 };
1343
1344 static struct snd_pcm_ops snd_intel8x0_capture_ops = {
1345         .open =         snd_intel8x0_capture_open,
1346         .close =        snd_intel8x0_capture_close,
1347         .ioctl =        snd_pcm_lib_ioctl,
1348         .hw_params =    snd_intel8x0_hw_params,
1349         .hw_free =      snd_intel8x0_hw_free,
1350         .prepare =      snd_intel8x0_pcm_prepare,
1351         .trigger =      snd_intel8x0_pcm_trigger,
1352         .pointer =      snd_intel8x0_pcm_pointer,
1353 };
1354
1355 static struct snd_pcm_ops snd_intel8x0_capture_mic_ops = {
1356         .open =         snd_intel8x0_mic_open,
1357         .close =        snd_intel8x0_mic_close,
1358         .ioctl =        snd_pcm_lib_ioctl,
1359         .hw_params =    snd_intel8x0_hw_params,
1360         .hw_free =      snd_intel8x0_hw_free,
1361         .prepare =      snd_intel8x0_pcm_prepare,
1362         .trigger =      snd_intel8x0_pcm_trigger,
1363         .pointer =      snd_intel8x0_pcm_pointer,
1364 };
1365
1366 static struct snd_pcm_ops snd_intel8x0_capture_mic2_ops = {
1367         .open =         snd_intel8x0_mic2_open,
1368         .close =        snd_intel8x0_mic2_close,
1369         .ioctl =        snd_pcm_lib_ioctl,
1370         .hw_params =    snd_intel8x0_hw_params,
1371         .hw_free =      snd_intel8x0_hw_free,
1372         .prepare =      snd_intel8x0_pcm_prepare,
1373         .trigger =      snd_intel8x0_pcm_trigger,
1374         .pointer =      snd_intel8x0_pcm_pointer,
1375 };
1376
1377 static struct snd_pcm_ops snd_intel8x0_capture2_ops = {
1378         .open =         snd_intel8x0_capture2_open,
1379         .close =        snd_intel8x0_capture2_close,
1380         .ioctl =        snd_pcm_lib_ioctl,
1381         .hw_params =    snd_intel8x0_hw_params,
1382         .hw_free =      snd_intel8x0_hw_free,
1383         .prepare =      snd_intel8x0_pcm_prepare,
1384         .trigger =      snd_intel8x0_pcm_trigger,
1385         .pointer =      snd_intel8x0_pcm_pointer,
1386 };
1387
1388 static struct snd_pcm_ops snd_intel8x0_spdif_ops = {
1389         .open =         snd_intel8x0_spdif_open,
1390         .close =        snd_intel8x0_spdif_close,
1391         .ioctl =        snd_pcm_lib_ioctl,
1392         .hw_params =    snd_intel8x0_hw_params,
1393         .hw_free =      snd_intel8x0_hw_free,
1394         .prepare =      snd_intel8x0_pcm_prepare,
1395         .trigger =      snd_intel8x0_pcm_trigger,
1396         .pointer =      snd_intel8x0_pcm_pointer,
1397 };
1398
1399 static struct snd_pcm_ops snd_intel8x0_ali_playback_ops = {
1400         .open =         snd_intel8x0_playback_open,
1401         .close =        snd_intel8x0_playback_close,
1402         .ioctl =        snd_pcm_lib_ioctl,
1403         .hw_params =    snd_intel8x0_hw_params,
1404         .hw_free =      snd_intel8x0_hw_free,
1405         .prepare =      snd_intel8x0_pcm_prepare,
1406         .trigger =      snd_intel8x0_ali_trigger,
1407         .pointer =      snd_intel8x0_pcm_pointer,
1408 };
1409
1410 static struct snd_pcm_ops snd_intel8x0_ali_capture_ops = {
1411         .open =         snd_intel8x0_capture_open,
1412         .close =        snd_intel8x0_capture_close,
1413         .ioctl =        snd_pcm_lib_ioctl,
1414         .hw_params =    snd_intel8x0_hw_params,
1415         .hw_free =      snd_intel8x0_hw_free,
1416         .prepare =      snd_intel8x0_pcm_prepare,
1417         .trigger =      snd_intel8x0_ali_trigger,
1418         .pointer =      snd_intel8x0_pcm_pointer,
1419 };
1420
1421 static struct snd_pcm_ops snd_intel8x0_ali_capture_mic_ops = {
1422         .open =         snd_intel8x0_mic_open,
1423         .close =        snd_intel8x0_mic_close,
1424         .ioctl =        snd_pcm_lib_ioctl,
1425         .hw_params =    snd_intel8x0_hw_params,
1426         .hw_free =      snd_intel8x0_hw_free,
1427         .prepare =      snd_intel8x0_pcm_prepare,
1428         .trigger =      snd_intel8x0_ali_trigger,
1429         .pointer =      snd_intel8x0_pcm_pointer,
1430 };
1431
1432 static struct snd_pcm_ops snd_intel8x0_ali_ac97spdifout_ops = {
1433         .open =         snd_intel8x0_ali_ac97spdifout_open,
1434         .close =        snd_intel8x0_ali_ac97spdifout_close,
1435         .ioctl =        snd_pcm_lib_ioctl,
1436         .hw_params =    snd_intel8x0_hw_params,
1437         .hw_free =      snd_intel8x0_hw_free,
1438         .prepare =      snd_intel8x0_pcm_prepare,
1439         .trigger =      snd_intel8x0_ali_trigger,
1440         .pointer =      snd_intel8x0_pcm_pointer,
1441 };
1442
1443 static struct snd_pcm_ops snd_intel8x0_ali_spdifin_ops = {
1444         .open =         snd_intel8x0_ali_spdifin_open,
1445         .close =        snd_intel8x0_ali_spdifin_close,
1446         .ioctl =        snd_pcm_lib_ioctl,
1447         .hw_params =    snd_intel8x0_hw_params,
1448         .hw_free =      snd_intel8x0_hw_free,
1449         .prepare =      snd_intel8x0_pcm_prepare,
1450         .trigger =      snd_intel8x0_pcm_trigger,
1451         .pointer =      snd_intel8x0_pcm_pointer,
1452 };
1453
1454 #if 0 // NYI
1455 static struct snd_pcm_ops snd_intel8x0_ali_spdifout_ops = {
1456         .open =         snd_intel8x0_ali_spdifout_open,
1457         .close =        snd_intel8x0_ali_spdifout_close,
1458         .ioctl =        snd_pcm_lib_ioctl,
1459         .hw_params =    snd_intel8x0_hw_params,
1460         .hw_free =      snd_intel8x0_hw_free,
1461         .prepare =      snd_intel8x0_pcm_prepare,
1462         .trigger =      snd_intel8x0_pcm_trigger,
1463         .pointer =      snd_intel8x0_pcm_pointer,
1464 };
1465 #endif // NYI
1466
1467 struct ich_pcm_table {
1468         char *suffix;
1469         struct snd_pcm_ops *playback_ops;
1470         struct snd_pcm_ops *capture_ops;
1471         size_t prealloc_size;
1472         size_t prealloc_max_size;
1473         int ac97_idx;
1474 };
1475
1476 static int __devinit snd_intel8x0_pcm1(struct intel8x0 *chip, int device,
1477                                        struct ich_pcm_table *rec)
1478 {
1479         struct snd_pcm *pcm;
1480         int err;
1481         char name[32];
1482
1483         if (rec->suffix)
1484                 sprintf(name, "Intel ICH - %s", rec->suffix);
1485         else
1486                 strcpy(name, "Intel ICH");
1487         err = snd_pcm_new(chip->card, name, device,
1488                           rec->playback_ops ? 1 : 0,
1489                           rec->capture_ops ? 1 : 0, &pcm);
1490         if (err < 0)
1491                 return err;
1492
1493         if (rec->playback_ops)
1494                 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, rec->playback_ops);
1495         if (rec->capture_ops)
1496                 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, rec->capture_ops);
1497
1498         pcm->private_data = chip;
1499         pcm->info_flags = 0;
1500         if (rec->suffix)
1501                 sprintf(pcm->name, "%s - %s", chip->card->shortname, rec->suffix);
1502         else
1503                 strcpy(pcm->name, chip->card->shortname);
1504         chip->pcm[device] = pcm;
1505
1506         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1507                                               snd_dma_pci_data(chip->pci),
1508                                               rec->prealloc_size, rec->prealloc_max_size);
1509
1510         return 0;
1511 }
1512
1513 static struct ich_pcm_table intel_pcms[] __devinitdata = {
1514         {
1515                 .playback_ops = &snd_intel8x0_playback_ops,
1516                 .capture_ops = &snd_intel8x0_capture_ops,
1517                 .prealloc_size = 64 * 1024,
1518                 .prealloc_max_size = 128 * 1024,
1519         },
1520         {
1521                 .suffix = "MIC ADC",
1522                 .capture_ops = &snd_intel8x0_capture_mic_ops,
1523                 .prealloc_size = 0,
1524                 .prealloc_max_size = 128 * 1024,
1525                 .ac97_idx = ICHD_MIC,
1526         },
1527         {
1528                 .suffix = "MIC2 ADC",
1529                 .capture_ops = &snd_intel8x0_capture_mic2_ops,
1530                 .prealloc_size = 0,
1531                 .prealloc_max_size = 128 * 1024,
1532                 .ac97_idx = ICHD_MIC2,
1533         },
1534         {
1535                 .suffix = "ADC2",
1536                 .capture_ops = &snd_intel8x0_capture2_ops,
1537                 .prealloc_size = 0,
1538                 .prealloc_max_size = 128 * 1024,
1539                 .ac97_idx = ICHD_PCM2IN,
1540         },
1541         {
1542                 .suffix = "IEC958",
1543                 .playback_ops = &snd_intel8x0_spdif_ops,
1544                 .prealloc_size = 64 * 1024,
1545                 .prealloc_max_size = 128 * 1024,
1546                 .ac97_idx = ICHD_SPBAR,
1547         },
1548 };
1549
1550 static struct ich_pcm_table nforce_pcms[] __devinitdata = {
1551         {
1552                 .playback_ops = &snd_intel8x0_playback_ops,
1553                 .capture_ops = &snd_intel8x0_capture_ops,
1554                 .prealloc_size = 64 * 1024,
1555                 .prealloc_max_size = 128 * 1024,
1556         },
1557         {
1558                 .suffix = "MIC ADC",
1559                 .capture_ops = &snd_intel8x0_capture_mic_ops,
1560                 .prealloc_size = 0,
1561                 .prealloc_max_size = 128 * 1024,
1562                 .ac97_idx = NVD_MIC,
1563         },
1564         {
1565                 .suffix = "IEC958",
1566                 .playback_ops = &snd_intel8x0_spdif_ops,
1567                 .prealloc_size = 64 * 1024,
1568                 .prealloc_max_size = 128 * 1024,
1569                 .ac97_idx = NVD_SPBAR,
1570         },
1571 };
1572
1573 static struct ich_pcm_table ali_pcms[] __devinitdata = {
1574         {
1575                 .playback_ops = &snd_intel8x0_ali_playback_ops,
1576                 .capture_ops = &snd_intel8x0_ali_capture_ops,
1577                 .prealloc_size = 64 * 1024,
1578                 .prealloc_max_size = 128 * 1024,
1579         },
1580         {
1581                 .suffix = "MIC ADC",
1582                 .capture_ops = &snd_intel8x0_ali_capture_mic_ops,
1583                 .prealloc_size = 0,
1584                 .prealloc_max_size = 128 * 1024,
1585                 .ac97_idx = ALID_MIC,
1586         },
1587         {
1588                 .suffix = "IEC958",
1589                 .playback_ops = &snd_intel8x0_ali_ac97spdifout_ops,
1590                 .capture_ops = &snd_intel8x0_ali_spdifin_ops,
1591                 .prealloc_size = 64 * 1024,
1592                 .prealloc_max_size = 128 * 1024,
1593                 .ac97_idx = ALID_AC97SPDIFOUT,
1594         },
1595 #if 0 // NYI
1596         {
1597                 .suffix = "HW IEC958",
1598                 .playback_ops = &snd_intel8x0_ali_spdifout_ops,
1599                 .prealloc_size = 64 * 1024,
1600                 .prealloc_max_size = 128 * 1024,
1601         },
1602 #endif
1603 };
1604
1605 static int __devinit snd_intel8x0_pcm(struct intel8x0 *chip)
1606 {
1607         int i, tblsize, device, err;
1608         struct ich_pcm_table *tbl, *rec;
1609
1610         switch (chip->device_type) {
1611         case DEVICE_INTEL_ICH4:
1612                 tbl = intel_pcms;
1613                 tblsize = ARRAY_SIZE(intel_pcms);
1614                 break;
1615         case DEVICE_NFORCE:
1616                 tbl = nforce_pcms;
1617                 tblsize = ARRAY_SIZE(nforce_pcms);
1618                 break;
1619         case DEVICE_ALI:
1620                 tbl = ali_pcms;
1621                 tblsize = ARRAY_SIZE(ali_pcms);
1622                 break;
1623         default:
1624                 tbl = intel_pcms;
1625                 tblsize = 2;
1626                 break;
1627         }
1628
1629         device = 0;
1630         for (i = 0; i < tblsize; i++) {
1631                 rec = tbl + i;
1632                 if (i > 0 && rec->ac97_idx) {
1633                         /* activate PCM only when associated AC'97 codec */
1634                         if (! chip->ichd[rec->ac97_idx].pcm)
1635                                 continue;
1636                 }
1637                 err = snd_intel8x0_pcm1(chip, device, rec);
1638                 if (err < 0)
1639                         return err;
1640                 device++;
1641         }
1642
1643         chip->pcm_devs = device;
1644         return 0;
1645 }
1646
1647
1648 /*
1649  *  Mixer part
1650  */
1651
1652 static void snd_intel8x0_mixer_free_ac97_bus(struct snd_ac97_bus *bus)
1653 {
1654         struct intel8x0 *chip = bus->private_data;
1655         chip->ac97_bus = NULL;
1656 }
1657
1658 static void snd_intel8x0_mixer_free_ac97(struct snd_ac97 *ac97)
1659 {
1660         struct intel8x0 *chip = ac97->private_data;
1661         chip->ac97[ac97->num] = NULL;
1662 }
1663
1664 static struct ac97_pcm ac97_pcm_defs[] __devinitdata = {
1665         /* front PCM */
1666         {
1667                 .exclusive = 1,
1668                 .r = {  {
1669                                 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1670                                          (1 << AC97_SLOT_PCM_RIGHT) |
1671                                          (1 << AC97_SLOT_PCM_CENTER) |
1672                                          (1 << AC97_SLOT_PCM_SLEFT) |
1673                                          (1 << AC97_SLOT_PCM_SRIGHT) |
1674                                          (1 << AC97_SLOT_LFE)
1675                         },
1676                         {
1677                                 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1678                                          (1 << AC97_SLOT_PCM_RIGHT) |
1679                                          (1 << AC97_SLOT_PCM_LEFT_0) |
1680                                          (1 << AC97_SLOT_PCM_RIGHT_0)
1681                         }
1682                 }
1683         },
1684         /* PCM IN #1 */
1685         {
1686                 .stream = 1,
1687                 .exclusive = 1,
1688                 .r = {  {
1689                                 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1690                                          (1 << AC97_SLOT_PCM_RIGHT)
1691                         }
1692                 }
1693         },
1694         /* MIC IN #1 */
1695         {
1696                 .stream = 1,
1697                 .exclusive = 1,
1698                 .r = {  {
1699                                 .slots = (1 << AC97_SLOT_MIC)
1700                         }
1701                 }
1702         },
1703         /* S/PDIF PCM */
1704         {
1705                 .exclusive = 1,
1706                 .spdif = 1,
1707                 .r = {  {
1708                                 .slots = (1 << AC97_SLOT_SPDIF_LEFT2) |
1709                                          (1 << AC97_SLOT_SPDIF_RIGHT2)
1710                         }
1711                 }
1712         },
1713         /* PCM IN #2 */
1714         {
1715                 .stream = 1,
1716                 .exclusive = 1,
1717                 .r = {  {
1718                                 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1719                                          (1 << AC97_SLOT_PCM_RIGHT)
1720                         }
1721                 }
1722         },
1723         /* MIC IN #2 */
1724         {
1725                 .stream = 1,
1726                 .exclusive = 1,
1727                 .r = {  {
1728                                 .slots = (1 << AC97_SLOT_MIC)
1729                         }
1730                 }
1731         },
1732 };
1733
1734 static struct ac97_quirk ac97_quirks[] __devinitdata = {
1735         {
1736                 .subvendor = 0x0e11,
1737                 .subdevice = 0x008a,
1738                 .name = "Compaq Evo W4000",     /* AD1885 */
1739                 .type = AC97_TUNE_HP_ONLY
1740         },
1741         {
1742                 .subvendor = 0x0e11,
1743                 .subdevice = 0x00b8,
1744                 .name = "Compaq Evo D510C",
1745                 .type = AC97_TUNE_HP_ONLY
1746         },
1747         {
1748                 .subvendor = 0x0e11,
1749                 .subdevice = 0x0860,
1750                 .name = "HP/Compaq nx7010",
1751                 .type = AC97_TUNE_MUTE_LED
1752         },
1753         {
1754                 .subvendor = 0x1014,
1755                 .subdevice = 0x1f00,
1756                 .name = "MS-9128",
1757                 .type = AC97_TUNE_ALC_JACK
1758         },
1759         {
1760                 .subvendor = 0x1014,
1761                 .subdevice = 0x0267,
1762                 .name = "IBM NetVista A30p",    /* AD1981B */
1763                 .type = AC97_TUNE_HP_ONLY
1764         },
1765         {
1766                 .subvendor = 0x1025,
1767                 .subdevice = 0x0083,
1768                 .name = "Acer Aspire 3003LCi",
1769                 .type = AC97_TUNE_HP_ONLY
1770         },
1771         {
1772                 .subvendor = 0x1028,
1773                 .subdevice = 0x00d8,
1774                 .name = "Dell Precision 530",   /* AD1885 */
1775                 .type = AC97_TUNE_HP_ONLY
1776         },
1777         {
1778                 .subvendor = 0x1028,
1779                 .subdevice = 0x010d,
1780                 .name = "Dell", /* which model?  AD1885 */
1781                 .type = AC97_TUNE_HP_ONLY
1782         },
1783         {
1784                 .subvendor = 0x1028,
1785                 .subdevice = 0x0126,
1786                 .name = "Dell Optiplex GX260",  /* AD1981A */
1787                 .type = AC97_TUNE_HP_ONLY
1788         },
1789         {
1790                 .subvendor = 0x1028,
1791                 .subdevice = 0x012c,
1792                 .name = "Dell Precision 650",   /* AD1981A */
1793                 .type = AC97_TUNE_HP_ONLY
1794         },
1795         {
1796                 .subvendor = 0x1028,
1797                 .subdevice = 0x012d,
1798                 .name = "Dell Precision 450",   /* AD1981B*/
1799                 .type = AC97_TUNE_HP_ONLY
1800         },
1801         {
1802                 .subvendor = 0x1028,
1803                 .subdevice = 0x0147,
1804                 .name = "Dell", /* which model?  AD1981B*/
1805                 .type = AC97_TUNE_HP_ONLY
1806         },
1807         {
1808                 .subvendor = 0x1028,
1809                 .subdevice = 0x0151,
1810                 .name = "Dell Optiplex GX270",  /* AD1981B */
1811                 .type = AC97_TUNE_HP_ONLY
1812         },
1813         {
1814                 .subvendor = 0x1028,
1815                 .subdevice = 0x0163,
1816                 .name = "Dell Unknown", /* STAC9750/51 */
1817                 .type = AC97_TUNE_HP_ONLY
1818         },
1819         {
1820                 .subvendor = 0x1028,
1821                 .subdevice = 0x0191,
1822                 .name = "Dell Inspiron 8600",
1823                 .type = AC97_TUNE_HP_ONLY
1824         },
1825         {
1826                 .subvendor = 0x103c,
1827                 .subdevice = 0x006d,
1828                 .name = "HP zv5000",
1829                 .type = AC97_TUNE_MUTE_LED      /*AD1981B*/
1830         },
1831         {       /* FIXME: which codec? */
1832                 .subvendor = 0x103c,
1833                 .subdevice = 0x00c3,
1834                 .name = "HP xw6000",
1835                 .type = AC97_TUNE_HP_ONLY
1836         },
1837         {
1838                 .subvendor = 0x103c,
1839                 .subdevice = 0x088c,
1840                 .name = "HP nc8000",
1841                 .type = AC97_TUNE_MUTE_LED
1842         },
1843         {
1844                 .subvendor = 0x103c,
1845                 .subdevice = 0x0890,
1846                 .name = "HP nc6000",
1847                 .type = AC97_TUNE_MUTE_LED
1848         },
1849         {
1850                 .subvendor = 0x103c,
1851                 .subdevice = 0x0934,
1852                 .name = "HP nx8220",
1853                 .type = AC97_TUNE_MUTE_LED
1854         },
1855         {
1856                 .subvendor = 0x103c,
1857                 .subdevice = 0x129d,
1858                 .name = "HP xw8000",
1859                 .type = AC97_TUNE_HP_ONLY
1860         },
1861         {
1862                 .subvendor = 0x103c,
1863                 .subdevice = 0x0938,
1864                 .name = "HP nc4200",
1865                 .type = AC97_TUNE_HP_MUTE_LED
1866         },
1867         {
1868                 .subvendor = 0x103c,
1869                 .subdevice = 0x099c,
1870                 .name = "HP nx6110/nc6120",
1871                 .type = AC97_TUNE_HP_MUTE_LED
1872         },
1873         {
1874                 .subvendor = 0x103c,
1875                 .subdevice = 0x0944,
1876                 .name = "HP nc6220",
1877                 .type = AC97_TUNE_HP_MUTE_LED
1878         },
1879         {
1880                 .subvendor = 0x103c,
1881                 .subdevice = 0x0934,
1882                 .name = "HP nc8220",
1883                 .type = AC97_TUNE_HP_MUTE_LED
1884         },
1885         {
1886                 .subvendor = 0x103c,
1887                 .subdevice = 0x12f1,
1888                 .name = "HP xw8200",    /* AD1981B*/
1889                 .type = AC97_TUNE_HP_ONLY
1890         },
1891         {
1892                 .subvendor = 0x103c,
1893                 .subdevice = 0x12f2,
1894                 .name = "HP xw6200",
1895                 .type = AC97_TUNE_HP_ONLY
1896         },
1897         {
1898                 .subvendor = 0x103c,
1899                 .subdevice = 0x3008,
1900                 .name = "HP xw4200",    /* AD1981B*/
1901                 .type = AC97_TUNE_HP_ONLY
1902         },
1903         {
1904                 .subvendor = 0x104d,
1905                 .subdevice = 0x8197,
1906                 .name = "Sony S1XP",
1907                 .type = AC97_TUNE_INV_EAPD
1908         },
1909         {
1910                 .subvendor = 0x1043,
1911                 .subdevice = 0x80f3,
1912                 .name = "ASUS ICH5/AD1985",
1913                 .type = AC97_TUNE_AD_SHARING
1914         },
1915         {
1916                 .subvendor = 0x10cf,
1917                 .subdevice = 0x11c3,
1918                 .name = "Fujitsu-Siemens E4010",
1919                 .type = AC97_TUNE_HP_ONLY
1920         },
1921         {
1922                 .subvendor = 0x10cf,
1923                 .subdevice = 0x1225,
1924                 .name = "Fujitsu-Siemens T3010",
1925                 .type = AC97_TUNE_HP_ONLY
1926         },
1927         {
1928                 .subvendor = 0x10cf,
1929                 .subdevice = 0x1253,
1930                 .name = "Fujitsu S6210",        /* STAC9750/51 */
1931                 .type = AC97_TUNE_HP_ONLY
1932         },
1933         {
1934                 .subvendor = 0x10cf,
1935                 .subdevice = 0x12ec,
1936                 .name = "Fujitsu-Siemens 4010",
1937                 .type = AC97_TUNE_HP_ONLY
1938         },
1939         {
1940                 .subvendor = 0x10cf,
1941                 .subdevice = 0x12f2,
1942                 .name = "Fujitsu-Siemens Celsius H320",
1943                 .type = AC97_TUNE_SWAP_HP
1944         },
1945         {
1946                 .subvendor = 0x10f1,
1947                 .subdevice = 0x2665,
1948                 .name = "Fujitsu-Siemens Celsius",      /* AD1981? */
1949                 .type = AC97_TUNE_HP_ONLY
1950         },
1951         {
1952                 .subvendor = 0x10f1,
1953                 .subdevice = 0x2885,
1954                 .name = "AMD64 Mobo",   /* ALC650 */
1955                 .type = AC97_TUNE_HP_ONLY
1956         },
1957         {
1958                 .subvendor = 0x110a,
1959                 .subdevice = 0x0056,
1960                 .name = "Fujitsu-Siemens Scenic",       /* AD1981? */
1961                 .type = AC97_TUNE_HP_ONLY
1962         },
1963         {
1964                 .subvendor = 0x11d4,
1965                 .subdevice = 0x5375,
1966                 .name = "ADI AD1985 (discrete)",
1967                 .type = AC97_TUNE_HP_ONLY
1968         },
1969         {
1970                 .subvendor = 0x1462,
1971                 .subdevice = 0x5470,
1972                 .name = "MSI P4 ATX 645 Ultra",
1973                 .type = AC97_TUNE_HP_ONLY
1974         },
1975         {
1976                 .subvendor = 0x1734,
1977                 .subdevice = 0x0088,
1978                 .name = "Fujitsu-Siemens D1522",        /* AD1981 */
1979                 .type = AC97_TUNE_HP_ONLY
1980         },
1981         {
1982                 .subvendor = 0x8086,
1983                 .subdevice = 0x2000,
1984                 .mask = 0xfff0,
1985                 .name = "Intel ICH5/AD1985",
1986                 .type = AC97_TUNE_AD_SHARING
1987         },
1988         {
1989                 .subvendor = 0x8086,
1990                 .subdevice = 0x4000,
1991                 .mask = 0xfff0,
1992                 .name = "Intel ICH5/AD1985",
1993                 .type = AC97_TUNE_AD_SHARING
1994         },
1995         {
1996                 .subvendor = 0x8086,
1997                 .subdevice = 0x4856,
1998                 .name = "Intel D845WN (82801BA)",
1999                 .type = AC97_TUNE_SWAP_HP
2000         },
2001         {
2002                 .subvendor = 0x8086,
2003                 .subdevice = 0x4d44,
2004                 .name = "Intel D850EMV2",       /* AD1885 */
2005                 .type = AC97_TUNE_HP_ONLY
2006         },
2007         {
2008                 .subvendor = 0x8086,
2009                 .subdevice = 0x4d56,
2010                 .name = "Intel ICH/AD1885",
2011                 .type = AC97_TUNE_HP_ONLY
2012         },
2013         {
2014                 .subvendor = 0x8086,
2015                 .subdevice = 0x6000,
2016                 .mask = 0xfff0,
2017                 .name = "Intel ICH5/AD1985",
2018                 .type = AC97_TUNE_AD_SHARING
2019         },
2020         {
2021                 .subvendor = 0x8086,
2022                 .subdevice = 0xe000,
2023                 .mask = 0xfff0,
2024                 .name = "Intel ICH5/AD1985",
2025                 .type = AC97_TUNE_AD_SHARING
2026         },
2027 #if 0 /* FIXME: this seems wrong on most boards */
2028         {
2029                 .subvendor = 0x8086,
2030                 .subdevice = 0xa000,
2031                 .mask = 0xfff0,
2032                 .name = "Intel ICH5/AD1985",
2033                 .type = AC97_TUNE_HP_ONLY
2034         },
2035 #endif
2036         { } /* terminator */
2037 };
2038
2039 static int __devinit snd_intel8x0_mixer(struct intel8x0 *chip, int ac97_clock,
2040                                         const char *quirk_override)
2041 {
2042         struct snd_ac97_bus *pbus;
2043         struct snd_ac97_template ac97;
2044         int err;
2045         unsigned int i, codecs;
2046         unsigned int glob_sta = 0;
2047         struct snd_ac97_bus_ops *ops;
2048         static struct snd_ac97_bus_ops standard_bus_ops = {
2049                 .write = snd_intel8x0_codec_write,
2050                 .read = snd_intel8x0_codec_read,
2051         };
2052         static struct snd_ac97_bus_ops ali_bus_ops = {
2053                 .write = snd_intel8x0_ali_codec_write,
2054                 .read = snd_intel8x0_ali_codec_read,
2055         };
2056
2057         chip->spdif_idx = -1; /* use PCMOUT (or disabled) */
2058         switch (chip->device_type) {
2059         case DEVICE_NFORCE:
2060                 chip->spdif_idx = NVD_SPBAR;
2061                 break;
2062         case DEVICE_ALI:
2063                 chip->spdif_idx = ALID_AC97SPDIFOUT;
2064                 break;
2065         case DEVICE_INTEL_ICH4:
2066                 chip->spdif_idx = ICHD_SPBAR;
2067                 break;
2068         };
2069
2070         chip->in_ac97_init = 1;
2071
2072         memset(&ac97, 0, sizeof(ac97));
2073         ac97.private_data = chip;
2074         ac97.private_free = snd_intel8x0_mixer_free_ac97;
2075         ac97.scaps = AC97_SCAP_SKIP_MODEM;
2076         if (chip->xbox)
2077                 ac97.scaps |= AC97_SCAP_DETECT_BY_VENDOR;
2078         if (chip->device_type != DEVICE_ALI) {
2079                 glob_sta = igetdword(chip, ICHREG(GLOB_STA));
2080                 ops = &standard_bus_ops;
2081                 if (chip->device_type == DEVICE_INTEL_ICH4) {
2082                         codecs = 0;
2083                         if (glob_sta & ICH_PCR)
2084                                 codecs++;
2085                         if (glob_sta & ICH_SCR)
2086                                 codecs++;
2087                         if (glob_sta & ICH_TCR)
2088                                 codecs++;
2089                         chip->in_sdin_init = 1;
2090                         for (i = 0; i < codecs; i++) {
2091                                 snd_intel8x0_codec_read_test(chip, i);
2092                                 chip->ac97_sdin[i] = igetbyte(chip, ICHREG(SDM)) & ICH_LDI_MASK;
2093                         }
2094                         chip->in_sdin_init = 0;
2095                 } else {
2096                         codecs = glob_sta & ICH_SCR ? 2 : 1;
2097                 }
2098         } else {
2099                 ops = &ali_bus_ops;
2100                 codecs = 1;
2101                 /* detect the secondary codec */
2102                 for (i = 0; i < 100; i++) {
2103                         unsigned int reg = igetdword(chip, ICHREG(ALI_RTSR));
2104                         if (reg & 0x40) {
2105                                 codecs = 2;
2106                                 break;
2107                         }
2108                         iputdword(chip, ICHREG(ALI_RTSR), reg | 0x40);
2109                         udelay(1);
2110                 }
2111         }
2112         if ((err = snd_ac97_bus(chip->card, 0, ops, chip, &pbus)) < 0)
2113                 goto __err;
2114         pbus->private_free = snd_intel8x0_mixer_free_ac97_bus;
2115         if (ac97_clock >= 8000 && ac97_clock <= 48000)
2116                 pbus->clock = ac97_clock;
2117         /* FIXME: my test board doesn't work well with VRA... */
2118         if (chip->device_type == DEVICE_ALI)
2119                 pbus->no_vra = 1;
2120         else
2121                 pbus->dra = 1;
2122         chip->ac97_bus = pbus;
2123
2124         ac97.pci = chip->pci;
2125         for (i = 0; i < codecs; i++) {
2126                 ac97.num = i;
2127                 if ((err = snd_ac97_mixer(pbus, &ac97, &chip->ac97[i])) < 0) {
2128                         if (err != -EACCES)
2129                                 snd_printk(KERN_ERR "Unable to initialize codec #%d\n", i);
2130                         if (i == 0)
2131                                 goto __err;
2132                         continue;
2133                 }
2134         }
2135         /* tune up the primary codec */
2136         snd_ac97_tune_hardware(chip->ac97[0], ac97_quirks, quirk_override);
2137         /* enable separate SDINs for ICH4 */
2138         if (chip->device_type == DEVICE_INTEL_ICH4)
2139                 pbus->isdin = 1;
2140         /* find the available PCM streams */
2141         i = ARRAY_SIZE(ac97_pcm_defs);
2142         if (chip->device_type != DEVICE_INTEL_ICH4)
2143                 i -= 2;         /* do not allocate PCM2IN and MIC2 */
2144         if (chip->spdif_idx < 0)
2145                 i--;            /* do not allocate S/PDIF */
2146         err = snd_ac97_pcm_assign(pbus, i, ac97_pcm_defs);
2147         if (err < 0)
2148                 goto __err;
2149         chip->ichd[ICHD_PCMOUT].pcm = &pbus->pcms[0];
2150         chip->ichd[ICHD_PCMIN].pcm = &pbus->pcms[1];
2151         chip->ichd[ICHD_MIC].pcm = &pbus->pcms[2];
2152         if (chip->spdif_idx >= 0)
2153                 chip->ichd[chip->spdif_idx].pcm = &pbus->pcms[3];
2154         if (chip->device_type == DEVICE_INTEL_ICH4) {
2155                 chip->ichd[ICHD_PCM2IN].pcm = &pbus->pcms[4];
2156                 chip->ichd[ICHD_MIC2].pcm = &pbus->pcms[5];
2157         }
2158         /* enable separate SDINs for ICH4 */
2159         if (chip->device_type == DEVICE_INTEL_ICH4) {
2160                 struct ac97_pcm *pcm = chip->ichd[ICHD_PCM2IN].pcm;
2161                 u8 tmp = igetbyte(chip, ICHREG(SDM));
2162                 tmp &= ~(ICH_DI2L_MASK|ICH_DI1L_MASK);
2163                 if (pcm) {
2164                         tmp |= ICH_SE;  /* steer enable for multiple SDINs */
2165                         tmp |= chip->ac97_sdin[0] << ICH_DI1L_SHIFT;
2166                         for (i = 1; i < 4; i++) {
2167                                 if (pcm->r[0].codec[i]) {
2168                                         tmp |= chip->ac97_sdin[pcm->r[0].codec[1]->num] << ICH_DI2L_SHIFT;
2169                                         break;
2170                                 }
2171                         }
2172                 } else {
2173                         tmp &= ~ICH_SE; /* steer disable */
2174                 }
2175                 iputbyte(chip, ICHREG(SDM), tmp);
2176         }
2177         if (pbus->pcms[0].r[0].slots & (1 << AC97_SLOT_PCM_SLEFT)) {
2178                 chip->multi4 = 1;
2179                 if (pbus->pcms[0].r[0].slots & (1 << AC97_SLOT_LFE))
2180                         chip->multi6 = 1;
2181         }
2182         if (pbus->pcms[0].r[1].rslots[0]) {
2183                 chip->dra = 1;
2184         }
2185         if (chip->device_type == DEVICE_INTEL_ICH4) {
2186                 if ((igetdword(chip, ICHREG(GLOB_STA)) & ICH_SAMPLE_CAP) == ICH_SAMPLE_16_20)
2187                         chip->smp20bit = 1;
2188         }
2189         if (chip->device_type == DEVICE_NFORCE) {
2190                 /* 48kHz only */
2191                 chip->ichd[chip->spdif_idx].pcm->rates = SNDRV_PCM_RATE_48000;
2192         }
2193         if (chip->device_type == DEVICE_INTEL_ICH4) {
2194                 /* use slot 10/11 for SPDIF */
2195                 u32 val;
2196                 val = igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_PCM_SPDIF_MASK;
2197                 val |= ICH_PCM_SPDIF_1011;
2198                 iputdword(chip, ICHREG(GLOB_CNT), val);
2199                 snd_ac97_update_bits(chip->ac97[0], AC97_EXTENDED_STATUS, 0x03 << 4, 0x03 << 4);
2200         }
2201         chip->in_ac97_init = 0;
2202         return 0;
2203
2204  __err:
2205         /* clear the cold-reset bit for the next chance */
2206         if (chip->device_type != DEVICE_ALI)
2207                 iputdword(chip, ICHREG(GLOB_CNT),
2208                           igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_AC97COLD);
2209         return err;
2210 }
2211
2212
2213 /*
2214  *
2215  */
2216
2217 static void do_ali_reset(struct intel8x0 *chip)
2218 {
2219         iputdword(chip, ICHREG(ALI_SCR), ICH_ALI_SC_RESET);
2220         iputdword(chip, ICHREG(ALI_FIFOCR1), 0x83838383);
2221         iputdword(chip, ICHREG(ALI_FIFOCR2), 0x83838383);
2222         iputdword(chip, ICHREG(ALI_FIFOCR3), 0x83838383);
2223         iputdword(chip, ICHREG(ALI_INTERFACECR),
2224                   ICH_ALI_IF_PI|ICH_ALI_IF_PO);
2225         iputdword(chip, ICHREG(ALI_INTERRUPTCR), 0x00000000);
2226         iputdword(chip, ICHREG(ALI_INTERRUPTSR), 0x00000000);
2227 }
2228
2229 static int snd_intel8x0_ich_chip_init(struct intel8x0 *chip, int probing)
2230 {
2231         unsigned long end_time;
2232         unsigned int cnt, status, nstatus;
2233
2234         /* put logic to right state */
2235         /* first clear status bits */
2236         status = ICH_RCS | ICH_MCINT | ICH_POINT | ICH_PIINT;
2237         if (chip->device_type == DEVICE_NFORCE)
2238                 status |= ICH_NVSPINT;
2239         cnt = igetdword(chip, ICHREG(GLOB_STA));
2240         iputdword(chip, ICHREG(GLOB_STA), cnt & status);
2241
2242         /* ACLink on, 2 channels */
2243         cnt = igetdword(chip, ICHREG(GLOB_CNT));
2244         cnt &= ~(ICH_ACLINK | ICH_PCM_246_MASK);
2245         /* finish cold or do warm reset */
2246         cnt |= (cnt & ICH_AC97COLD) == 0 ? ICH_AC97COLD : ICH_AC97WARM;
2247         iputdword(chip, ICHREG(GLOB_CNT), cnt);
2248         end_time = (jiffies + (HZ / 4)) + 1;
2249         do {
2250                 if ((igetdword(chip, ICHREG(GLOB_CNT)) & ICH_AC97WARM) == 0)
2251                         goto __ok;
2252                 schedule_timeout_uninterruptible(1);
2253         } while (time_after_eq(end_time, jiffies));
2254         snd_printk(KERN_ERR "AC'97 warm reset still in progress? [0x%x]\n",
2255                    igetdword(chip, ICHREG(GLOB_CNT)));
2256         return -EIO;
2257
2258       __ok:
2259         if (probing) {
2260                 /* wait for any codec ready status.
2261                  * Once it becomes ready it should remain ready
2262                  * as long as we do not disable the ac97 link.
2263                  */
2264                 end_time = jiffies + HZ;
2265                 do {
2266                         status = igetdword(chip, ICHREG(GLOB_STA)) &
2267                                 (ICH_PCR | ICH_SCR | ICH_TCR);
2268                         if (status)
2269                                 break;
2270                         schedule_timeout_uninterruptible(1);
2271                 } while (time_after_eq(end_time, jiffies));
2272                 if (! status) {
2273                         /* no codec is found */
2274                         snd_printk(KERN_ERR "codec_ready: codec is not ready [0x%x]\n",
2275                                    igetdword(chip, ICHREG(GLOB_STA)));
2276                         return -EIO;
2277                 }
2278
2279                 if (chip->device_type == DEVICE_INTEL_ICH4)
2280                         /* ICH4 can have three codecs */
2281                         nstatus = ICH_PCR | ICH_SCR | ICH_TCR;
2282                 else
2283                         /* others up to two codecs */
2284                         nstatus = ICH_PCR | ICH_SCR;
2285
2286                 /* wait for other codecs ready status. */
2287                 end_time = jiffies + HZ / 4;
2288                 while (status != nstatus && time_after_eq(end_time, jiffies)) {
2289                         schedule_timeout_uninterruptible(1);
2290                         status |= igetdword(chip, ICHREG(GLOB_STA)) & nstatus;
2291                 }
2292
2293         } else {
2294                 /* resume phase */
2295                 int i;
2296                 status = 0;
2297                 for (i = 0; i < 3; i++)
2298                         if (chip->ac97[i])
2299                                 status |= get_ich_codec_bit(chip, i);
2300                 /* wait until all the probed codecs are ready */
2301                 end_time = jiffies + HZ;
2302                 do {
2303                         nstatus = igetdword(chip, ICHREG(GLOB_STA)) &
2304                                 (ICH_PCR | ICH_SCR | ICH_TCR);
2305                         if (status == nstatus)
2306                                 break;
2307                         schedule_timeout_uninterruptible(1);
2308                 } while (time_after_eq(end_time, jiffies));
2309         }
2310
2311         if (chip->device_type == DEVICE_SIS) {
2312                 /* unmute the output on SIS7012 */
2313                 iputword(chip, 0x4c, igetword(chip, 0x4c) | 1);
2314         }
2315         if (chip->device_type == DEVICE_NFORCE) {
2316                 /* enable SPDIF interrupt */
2317                 unsigned int val;
2318                 pci_read_config_dword(chip->pci, 0x4c, &val);
2319                 val |= 0x1000000;
2320                 pci_write_config_dword(chip->pci, 0x4c, val);
2321         }
2322         return 0;
2323 }
2324
2325 static int snd_intel8x0_ali_chip_init(struct intel8x0 *chip, int probing)
2326 {
2327         u32 reg;
2328         int i = 0;
2329
2330         reg = igetdword(chip, ICHREG(ALI_SCR));
2331         if ((reg & 2) == 0)     /* Cold required */
2332                 reg |= 2;
2333         else
2334                 reg |= 1;       /* Warm */
2335         reg &= ~0x80000000;     /* ACLink on */
2336         iputdword(chip, ICHREG(ALI_SCR), reg);
2337
2338         for (i = 0; i < HZ / 2; i++) {
2339                 if (! (igetdword(chip, ICHREG(ALI_INTERRUPTSR)) & ALI_INT_GPIO))
2340                         goto __ok;
2341                 schedule_timeout_uninterruptible(1);
2342         }
2343         snd_printk(KERN_ERR "AC'97 reset failed.\n");
2344         if (probing)
2345                 return -EIO;
2346
2347  __ok:
2348         for (i = 0; i < HZ / 2; i++) {
2349                 reg = igetdword(chip, ICHREG(ALI_RTSR));
2350                 if (reg & 0x80) /* primary codec */
2351                         break;
2352                 iputdword(chip, ICHREG(ALI_RTSR), reg | 0x80);
2353                 schedule_timeout_uninterruptible(1);
2354         }
2355
2356         do_ali_reset(chip);
2357         return 0;
2358 }
2359
2360 static int snd_intel8x0_chip_init(struct intel8x0 *chip, int probing)
2361 {
2362         unsigned int i;
2363         int err;
2364
2365         if (chip->device_type != DEVICE_ALI) {
2366                 if ((err = snd_intel8x0_ich_chip_init(chip, probing)) < 0)
2367                         return err;
2368                 iagetword(chip, 0);     /* clear semaphore flag */
2369         } else {
2370                 if ((err = snd_intel8x0_ali_chip_init(chip, probing)) < 0)
2371                         return err;
2372         }
2373
2374         /* disable interrupts */
2375         for (i = 0; i < chip->bdbars_count; i++)
2376                 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00);
2377         /* reset channels */
2378         for (i = 0; i < chip->bdbars_count; i++)
2379                 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS);
2380         /* initialize Buffer Descriptor Lists */
2381         for (i = 0; i < chip->bdbars_count; i++)
2382                 iputdword(chip, ICH_REG_OFF_BDBAR + chip->ichd[i].reg_offset,
2383                           chip->ichd[i].bdbar_addr);
2384         return 0;
2385 }
2386
2387 static int snd_intel8x0_free(struct intel8x0 *chip)
2388 {
2389         unsigned int i;
2390
2391         if (chip->irq < 0)
2392                 goto __hw_end;
2393         /* disable interrupts */
2394         for (i = 0; i < chip->bdbars_count; i++)
2395                 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00);
2396         /* reset channels */
2397         for (i = 0; i < chip->bdbars_count; i++)
2398                 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS);
2399         if (chip->device_type == DEVICE_NFORCE) {
2400                 /* stop the spdif interrupt */
2401                 unsigned int val;
2402                 pci_read_config_dword(chip->pci, 0x4c, &val);
2403                 val &= ~0x1000000;
2404                 pci_write_config_dword(chip->pci, 0x4c, val);
2405         }
2406         /* --- */
2407         synchronize_irq(chip->irq);
2408       __hw_end:
2409         if (chip->irq >= 0)
2410                 free_irq(chip->irq, chip);
2411         if (chip->bdbars.area) {
2412                 if (chip->fix_nocache)
2413                         fill_nocache(chip->bdbars.area, chip->bdbars.bytes, 0);
2414                 snd_dma_free_pages(&chip->bdbars);
2415         }
2416         if (chip->remap_addr)
2417                 iounmap(chip->remap_addr);
2418         if (chip->remap_bmaddr)
2419                 iounmap(chip->remap_bmaddr);
2420         pci_release_regions(chip->pci);
2421         pci_disable_device(chip->pci);
2422         kfree(chip);
2423         return 0;
2424 }
2425
2426 #ifdef CONFIG_PM
2427 /*
2428  * power management
2429  */
2430 static int intel8x0_suspend(struct pci_dev *pci, pm_message_t state)
2431 {
2432         struct snd_card *card = pci_get_drvdata(pci);
2433         struct intel8x0 *chip = card->private_data;
2434         int i;
2435
2436         snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2437         for (i = 0; i < chip->pcm_devs; i++)
2438                 snd_pcm_suspend_all(chip->pcm[i]);
2439         /* clear nocache */
2440         if (chip->fix_nocache) {
2441                 for (i = 0; i < chip->bdbars_count; i++) {
2442                         struct ichdev *ichdev = &chip->ichd[i];
2443                         if (ichdev->substream && ichdev->page_attr_changed) {
2444                                 struct snd_pcm_runtime *runtime = ichdev->substream->runtime;
2445                                 if (runtime->dma_area)
2446                                         fill_nocache(runtime->dma_area, runtime->dma_bytes, 0);
2447                         }
2448                 }
2449         }
2450         for (i = 0; i < 3; i++)
2451                 snd_ac97_suspend(chip->ac97[i]);
2452         if (chip->device_type == DEVICE_INTEL_ICH4)
2453                 chip->sdm_saved = igetbyte(chip, ICHREG(SDM));
2454
2455         if (chip->irq >= 0)
2456                 free_irq(chip->irq, chip);
2457         pci_disable_device(pci);
2458         pci_save_state(pci);
2459         return 0;
2460 }
2461
2462 static int intel8x0_resume(struct pci_dev *pci)
2463 {
2464         struct snd_card *card = pci_get_drvdata(pci);
2465         struct intel8x0 *chip = card->private_data;
2466         int i;
2467
2468         pci_restore_state(pci);
2469         pci_enable_device(pci);
2470         pci_set_master(pci);
2471         request_irq(pci->irq, snd_intel8x0_interrupt, SA_INTERRUPT|SA_SHIRQ,
2472                     card->shortname, chip);
2473         chip->irq = pci->irq;
2474         synchronize_irq(chip->irq);
2475         snd_intel8x0_chip_init(chip, 1);
2476
2477         /* re-initialize mixer stuff */
2478         if (chip->device_type == DEVICE_INTEL_ICH4) {
2479                 /* enable separate SDINs for ICH4 */
2480                 iputbyte(chip, ICHREG(SDM), chip->sdm_saved);
2481                 /* use slot 10/11 for SPDIF */
2482                 iputdword(chip, ICHREG(GLOB_CNT),
2483                           (igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_PCM_SPDIF_MASK) |
2484                           ICH_PCM_SPDIF_1011);
2485         }
2486
2487         /* refill nocache */
2488         if (chip->fix_nocache)
2489                 fill_nocache(chip->bdbars.area, chip->bdbars.bytes, 1);
2490
2491         for (i = 0; i < 3; i++)
2492                 snd_ac97_resume(chip->ac97[i]);
2493
2494         /* refill nocache */
2495         if (chip->fix_nocache) {
2496                 for (i = 0; i < chip->bdbars_count; i++) {
2497                         struct ichdev *ichdev = &chip->ichd[i];
2498                         if (ichdev->substream && ichdev->page_attr_changed) {
2499                                 struct snd_pcm_runtime *runtime = ichdev->substream->runtime;
2500                                 if (runtime->dma_area)
2501                                         fill_nocache(runtime->dma_area, runtime->dma_bytes, 1);
2502                         }
2503                 }
2504         }
2505
2506         /* resume status */
2507         for (i = 0; i < chip->bdbars_count; i++) {
2508                 struct ichdev *ichdev = &chip->ichd[i];
2509                 unsigned long port = ichdev->reg_offset;
2510                 if (! ichdev->substream || ! ichdev->suspended)
2511                         continue;
2512                 if (ichdev->ichd == ICHD_PCMOUT)
2513                         snd_intel8x0_setup_pcm_out(chip, ichdev->substream->runtime);
2514                 iputdword(chip, port + ICH_REG_OFF_BDBAR, ichdev->bdbar_addr);
2515                 iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi);
2516                 iputbyte(chip, port + ICH_REG_OFF_CIV, ichdev->civ);
2517                 iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI);
2518         }
2519
2520         snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2521         return 0;
2522 }
2523 #endif /* CONFIG_PM */
2524
2525 #define INTEL8X0_TESTBUF_SIZE   32768   /* enough large for one shot */
2526
2527 static void __devinit intel8x0_measure_ac97_clock(struct intel8x0 *chip)
2528 {
2529         struct snd_pcm_substream *subs;
2530         struct ichdev *ichdev;
2531         unsigned long port;
2532         unsigned long pos, t;
2533         struct timeval start_time, stop_time;
2534
2535         if (chip->ac97_bus->clock != 48000)
2536                 return; /* specified in module option */
2537
2538         subs = chip->pcm[0]->streams[0].substream;
2539         if (! subs || subs->dma_buffer.bytes < INTEL8X0_TESTBUF_SIZE) {
2540                 snd_printk(KERN_WARNING "no playback buffer allocated - aborting measure ac97 clock\n");
2541                 return;
2542         }
2543         ichdev = &chip->ichd[ICHD_PCMOUT];
2544         ichdev->physbuf = subs->dma_buffer.addr;
2545         ichdev->size = chip->ichd[ICHD_PCMOUT].fragsize = INTEL8X0_TESTBUF_SIZE;
2546         ichdev->substream = NULL; /* don't process interrupts */
2547
2548         /* set rate */
2549         if (snd_ac97_set_rate(chip->ac97[0], AC97_PCM_FRONT_DAC_RATE, 48000) < 0) {
2550                 snd_printk(KERN_ERR "cannot set ac97 rate: clock = %d\n", chip->ac97_bus->clock);
2551                 return;
2552         }
2553         snd_intel8x0_setup_periods(chip, ichdev);
2554         port = ichdev->reg_offset;
2555         spin_lock_irq(&chip->reg_lock);
2556         chip->in_measurement = 1;
2557         /* trigger */
2558         if (chip->device_type != DEVICE_ALI)
2559                 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE | ICH_STARTBM);
2560         else {
2561                 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE);
2562                 iputdword(chip, ICHREG(ALI_DMACR), 1 << ichdev->ali_slot);
2563         }
2564         do_gettimeofday(&start_time);
2565         spin_unlock_irq(&chip->reg_lock);
2566         msleep(50);
2567         spin_lock_irq(&chip->reg_lock);
2568         /* check the position */
2569         pos = ichdev->fragsize1;
2570         pos -= igetword(chip, ichdev->reg_offset + ichdev->roff_picb) << ichdev->pos_shift;
2571         pos += ichdev->position;
2572         chip->in_measurement = 0;
2573         do_gettimeofday(&stop_time);
2574         /* stop */
2575         if (chip->device_type == DEVICE_ALI) {
2576                 iputdword(chip, ICHREG(ALI_DMACR), 1 << (ichdev->ali_slot + 16));
2577                 iputbyte(chip, port + ICH_REG_OFF_CR, 0);
2578                 while (igetbyte(chip, port + ICH_REG_OFF_CR))
2579                         ;
2580         } else {
2581                 iputbyte(chip, port + ICH_REG_OFF_CR, 0);
2582                 while (!(igetbyte(chip, port + ichdev->roff_sr) & ICH_DCH))
2583                         ;
2584         }
2585         iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
2586         spin_unlock_irq(&chip->reg_lock);
2587
2588         t = stop_time.tv_sec - start_time.tv_sec;
2589         t *= 1000000;
2590         t += stop_time.tv_usec - start_time.tv_usec;
2591         printk(KERN_INFO "%s: measured %lu usecs\n", __FUNCTION__, t);
2592         if (t == 0) {
2593                 snd_printk(KERN_ERR "?? calculation error..\n");
2594                 return;
2595         }
2596         pos = (pos / 4) * 1000;
2597         pos = (pos / t) * 1000 + ((pos % t) * 1000) / t;
2598         if (pos < 40000 || pos >= 60000)
2599                 /* abnormal value. hw problem? */
2600                 printk(KERN_INFO "intel8x0: measured clock %ld rejected\n", pos);
2601         else if (pos < 47500 || pos > 48500)
2602                 /* not 48000Hz, tuning the clock.. */
2603                 chip->ac97_bus->clock = (chip->ac97_bus->clock * 48000) / pos;
2604         printk(KERN_INFO "intel8x0: clocking to %d\n", chip->ac97_bus->clock);
2605 }
2606
2607 #ifdef CONFIG_PROC_FS
2608 static void snd_intel8x0_proc_read(struct snd_info_entry * entry,
2609                                    struct snd_info_buffer *buffer)
2610 {
2611         struct intel8x0 *chip = entry->private_data;
2612         unsigned int tmp;
2613
2614         snd_iprintf(buffer, "Intel8x0\n\n");
2615         if (chip->device_type == DEVICE_ALI)
2616                 return;
2617         tmp = igetdword(chip, ICHREG(GLOB_STA));
2618         snd_iprintf(buffer, "Global control        : 0x%08x\n", igetdword(chip, ICHREG(GLOB_CNT)));
2619         snd_iprintf(buffer, "Global status         : 0x%08x\n", tmp);
2620         if (chip->device_type == DEVICE_INTEL_ICH4)
2621                 snd_iprintf(buffer, "SDM                   : 0x%08x\n", igetdword(chip, ICHREG(SDM)));
2622         snd_iprintf(buffer, "AC'97 codecs ready    :%s%s%s%s\n",
2623                         tmp & ICH_PCR ? " primary" : "",
2624                         tmp & ICH_SCR ? " secondary" : "",
2625                         tmp & ICH_TCR ? " tertiary" : "",
2626                         (tmp & (ICH_PCR | ICH_SCR | ICH_TCR)) == 0 ? " none" : "");
2627         if (chip->device_type == DEVICE_INTEL_ICH4)
2628                 snd_iprintf(buffer, "AC'97 codecs SDIN     : %i %i %i\n",
2629                         chip->ac97_sdin[0],
2630                         chip->ac97_sdin[1],
2631                         chip->ac97_sdin[2]);
2632 }
2633
2634 static void __devinit snd_intel8x0_proc_init(struct intel8x0 * chip)
2635 {
2636         struct snd_info_entry *entry;
2637
2638         if (! snd_card_proc_new(chip->card, "intel8x0", &entry))
2639                 snd_info_set_text_ops(entry, chip, 1024, snd_intel8x0_proc_read);
2640 }
2641 #else
2642 #define snd_intel8x0_proc_init(x)
2643 #endif
2644
2645 static int snd_intel8x0_dev_free(struct snd_device *device)
2646 {
2647         struct intel8x0 *chip = device->device_data;
2648         return snd_intel8x0_free(chip);
2649 }
2650
2651 struct ich_reg_info {
2652         unsigned int int_sta_mask;
2653         unsigned int offset;
2654 };
2655
2656 static int __devinit snd_intel8x0_create(struct snd_card *card,
2657                                          struct pci_dev *pci,
2658                                          unsigned long device_type,
2659                                          struct intel8x0 ** r_intel8x0)
2660 {
2661         struct intel8x0 *chip;
2662         int err;
2663         unsigned int i;
2664         unsigned int int_sta_masks;
2665         struct ichdev *ichdev;
2666         static struct snd_device_ops ops = {
2667                 .dev_free =     snd_intel8x0_dev_free,
2668         };
2669
2670         static unsigned int bdbars[] = {
2671                 3, /* DEVICE_INTEL */
2672                 6, /* DEVICE_INTEL_ICH4 */
2673                 3, /* DEVICE_SIS */
2674                 6, /* DEVICE_ALI */
2675                 4, /* DEVICE_NFORCE */
2676         };
2677         static struct ich_reg_info intel_regs[6] = {
2678                 { ICH_PIINT, 0 },
2679                 { ICH_POINT, 0x10 },
2680                 { ICH_MCINT, 0x20 },
2681                 { ICH_M2INT, 0x40 },
2682                 { ICH_P2INT, 0x50 },
2683                 { ICH_SPINT, 0x60 },
2684         };
2685         static struct ich_reg_info nforce_regs[4] = {
2686                 { ICH_PIINT, 0 },
2687                 { ICH_POINT, 0x10 },
2688                 { ICH_MCINT, 0x20 },
2689                 { ICH_NVSPINT, 0x70 },
2690         };
2691         static struct ich_reg_info ali_regs[6] = {
2692                 { ALI_INT_PCMIN, 0x40 },
2693                 { ALI_INT_PCMOUT, 0x50 },
2694                 { ALI_INT_MICIN, 0x60 },
2695                 { ALI_INT_CODECSPDIFOUT, 0x70 },
2696                 { ALI_INT_SPDIFIN, 0xa0 },
2697                 { ALI_INT_SPDIFOUT, 0xb0 },
2698         };
2699         struct ich_reg_info *tbl;
2700
2701         *r_intel8x0 = NULL;
2702
2703         if ((err = pci_enable_device(pci)) < 0)
2704                 return err;
2705
2706         chip = kzalloc(sizeof(*chip), GFP_KERNEL);
2707         if (chip == NULL) {
2708                 pci_disable_device(pci);
2709                 return -ENOMEM;
2710         }
2711         spin_lock_init(&chip->reg_lock);
2712         chip->device_type = device_type;
2713         chip->card = card;
2714         chip->pci = pci;
2715         chip->irq = -1;
2716
2717         /* module parameters */
2718         chip->buggy_irq = buggy_irq;
2719         chip->buggy_semaphore = buggy_semaphore;
2720         if (xbox)
2721                 chip->xbox = 1;
2722
2723         if (pci->vendor == PCI_VENDOR_ID_INTEL &&
2724             pci->device == PCI_DEVICE_ID_INTEL_440MX)
2725                 chip->fix_nocache = 1; /* enable workaround */
2726
2727         if ((err = pci_request_regions(pci, card->shortname)) < 0) {
2728                 kfree(chip);
2729                 pci_disable_device(pci);
2730                 return err;
2731         }
2732
2733         if (device_type == DEVICE_ALI) {
2734                 /* ALI5455 has no ac97 region */
2735                 chip->bmaddr = pci_resource_start(pci, 0);
2736                 goto port_inited;
2737         }
2738
2739         if (pci_resource_flags(pci, 2) & IORESOURCE_MEM) {      /* ICH4 and Nforce */
2740                 chip->mmio = 1;
2741                 chip->addr = pci_resource_start(pci, 2);
2742                 chip->remap_addr = ioremap_nocache(chip->addr,
2743                                                    pci_resource_len(pci, 2));
2744                 if (chip->remap_addr == NULL) {
2745                         snd_printk(KERN_ERR "AC'97 space ioremap problem\n");
2746                         snd_intel8x0_free(chip);
2747                         return -EIO;
2748                 }
2749         } else {
2750                 chip->addr = pci_resource_start(pci, 0);
2751         }
2752         if (pci_resource_flags(pci, 3) & IORESOURCE_MEM) {      /* ICH4 */
2753                 chip->bm_mmio = 1;
2754                 chip->bmaddr = pci_resource_start(pci, 3);
2755                 chip->remap_bmaddr = ioremap_nocache(chip->bmaddr,
2756                                                      pci_resource_len(pci, 3));
2757                 if (chip->remap_bmaddr == NULL) {
2758                         snd_printk(KERN_ERR "Controller space ioremap problem\n");
2759                         snd_intel8x0_free(chip);
2760                         return -EIO;
2761                 }
2762         } else {
2763                 chip->bmaddr = pci_resource_start(pci, 1);
2764         }
2765
2766  port_inited:
2767         chip->bdbars_count = bdbars[device_type];
2768
2769         /* initialize offsets */
2770         switch (device_type) {
2771         case DEVICE_NFORCE:
2772                 tbl = nforce_regs;
2773                 break;
2774         case DEVICE_ALI:
2775                 tbl = ali_regs;
2776                 break;
2777         default:
2778                 tbl = intel_regs;
2779                 break;
2780         }
2781         for (i = 0; i < chip->bdbars_count; i++) {
2782                 ichdev = &chip->ichd[i];
2783                 ichdev->ichd = i;
2784                 ichdev->reg_offset = tbl[i].offset;
2785                 ichdev->int_sta_mask = tbl[i].int_sta_mask;
2786                 if (device_type == DEVICE_SIS) {
2787                         /* SiS 7012 swaps the registers */
2788                         ichdev->roff_sr = ICH_REG_OFF_PICB;
2789                         ichdev->roff_picb = ICH_REG_OFF_SR;
2790                 } else {
2791                         ichdev->roff_sr = ICH_REG_OFF_SR;
2792                         ichdev->roff_picb = ICH_REG_OFF_PICB;
2793                 }
2794                 if (device_type == DEVICE_ALI)
2795                         ichdev->ali_slot = (ichdev->reg_offset - 0x40) / 0x10;
2796                 /* SIS7012 handles the pcm data in bytes, others are in samples */
2797                 ichdev->pos_shift = (device_type == DEVICE_SIS) ? 0 : 1;
2798         }
2799
2800         /* allocate buffer descriptor lists */
2801         /* the start of each lists must be aligned to 8 bytes */
2802         if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(pci),
2803                                 chip->bdbars_count * sizeof(u32) * ICH_MAX_FRAGS * 2,
2804                                 &chip->bdbars) < 0) {
2805                 snd_intel8x0_free(chip);
2806                 snd_printk(KERN_ERR "intel8x0: cannot allocate buffer descriptors\n");
2807                 return -ENOMEM;
2808         }
2809         /* tables must be aligned to 8 bytes here, but the kernel pages
2810            are much bigger, so we don't care (on i386) */
2811         /* workaround for 440MX */
2812         if (chip->fix_nocache)
2813                 fill_nocache(chip->bdbars.area, chip->bdbars.bytes, 1);
2814         int_sta_masks = 0;
2815         for (i = 0; i < chip->bdbars_count; i++) {
2816                 ichdev = &chip->ichd[i];
2817                 ichdev->bdbar = ((u32 *)chip->bdbars.area) +
2818                         (i * ICH_MAX_FRAGS * 2);
2819                 ichdev->bdbar_addr = chip->bdbars.addr +
2820                         (i * sizeof(u32) * ICH_MAX_FRAGS * 2);
2821                 int_sta_masks |= ichdev->int_sta_mask;
2822         }
2823         chip->int_sta_reg = device_type == DEVICE_ALI ?
2824                 ICH_REG_ALI_INTERRUPTSR : ICH_REG_GLOB_STA;
2825         chip->int_sta_mask = int_sta_masks;
2826
2827         /* request irq after initializaing int_sta_mask, etc */
2828         if (request_irq(pci->irq, snd_intel8x0_interrupt,
2829                         SA_INTERRUPT|SA_SHIRQ, card->shortname, chip)) {
2830                 snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq);
2831                 snd_intel8x0_free(chip);
2832                 return -EBUSY;
2833         }
2834         chip->irq = pci->irq;
2835         pci_set_master(pci);
2836         synchronize_irq(chip->irq);
2837
2838         if ((err = snd_intel8x0_chip_init(chip, 1)) < 0) {
2839                 snd_intel8x0_free(chip);
2840                 return err;
2841         }
2842
2843         if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
2844                 snd_intel8x0_free(chip);
2845                 return err;
2846         }
2847
2848         snd_card_set_dev(card, &pci->dev);
2849
2850         *r_intel8x0 = chip;
2851         return 0;
2852 }
2853
2854 static struct shortname_table {
2855         unsigned int id;
2856         const char *s;
2857 } shortnames[] __devinitdata = {
2858         { PCI_DEVICE_ID_INTEL_82801AA_5, "Intel 82801AA-ICH" },
2859         { PCI_DEVICE_ID_INTEL_82801AB_5, "Intel 82901AB-ICH0" },
2860         { PCI_DEVICE_ID_INTEL_82801BA_4, "Intel 82801BA-ICH2" },
2861         { PCI_DEVICE_ID_INTEL_440MX, "Intel 440MX" },
2862         { PCI_DEVICE_ID_INTEL_82801CA_5, "Intel 82801CA-ICH3" },
2863         { PCI_DEVICE_ID_INTEL_82801DB_5, "Intel 82801DB-ICH4" },
2864         { PCI_DEVICE_ID_INTEL_82801EB_5, "Intel ICH5" },
2865         { PCI_DEVICE_ID_INTEL_ESB_5, "Intel 6300ESB" },
2866         { PCI_DEVICE_ID_INTEL_ICH6_18, "Intel ICH6" },
2867         { PCI_DEVICE_ID_INTEL_ICH7_20, "Intel ICH7" },
2868         { PCI_DEVICE_ID_INTEL_ESB2_14, "Intel ESB2" },
2869         { PCI_DEVICE_ID_SI_7012, "SiS SI7012" },
2870         { PCI_DEVICE_ID_NVIDIA_MCP1_AUDIO, "NVidia nForce" },
2871         { PCI_DEVICE_ID_NVIDIA_MCP2_AUDIO, "NVidia nForce2" },
2872         { PCI_DEVICE_ID_NVIDIA_MCP3_AUDIO, "NVidia nForce3" },
2873         { PCI_DEVICE_ID_NVIDIA_CK8S_AUDIO, "NVidia CK8S" },
2874         { PCI_DEVICE_ID_NVIDIA_CK804_AUDIO, "NVidia CK804" },
2875         { PCI_DEVICE_ID_NVIDIA_CK8_AUDIO, "NVidia CK8" },
2876         { 0x003a, "NVidia MCP04" },
2877         { 0x746d, "AMD AMD8111" },
2878         { 0x7445, "AMD AMD768" },
2879         { 0x5455, "ALi M5455" },
2880         { 0, NULL },
2881 };
2882
2883 static int __devinit snd_intel8x0_probe(struct pci_dev *pci,
2884                                         const struct pci_device_id *pci_id)
2885 {
2886         struct snd_card *card;
2887         struct intel8x0 *chip;
2888         int err;
2889         struct shortname_table *name;
2890
2891         card = snd_card_new(index, id, THIS_MODULE, 0);
2892         if (card == NULL)
2893                 return -ENOMEM;
2894
2895         switch (pci_id->driver_data) {
2896         case DEVICE_NFORCE:
2897                 strcpy(card->driver, "NFORCE");
2898                 break;
2899         case DEVICE_INTEL_ICH4:
2900                 strcpy(card->driver, "ICH4");
2901                 break;
2902         default:
2903                 strcpy(card->driver, "ICH");
2904                 break;
2905         }
2906
2907         strcpy(card->shortname, "Intel ICH");
2908         for (name = shortnames; name->id; name++) {
2909                 if (pci->device == name->id) {
2910                         strcpy(card->shortname, name->s);
2911                         break;
2912                 }
2913         }
2914
2915         if (buggy_irq < 0) {
2916                 /* some Nforce[2] and ICH boards have problems with IRQ handling.
2917                  * Needs to return IRQ_HANDLED for unknown irqs.
2918                  */
2919                 if (pci_id->driver_data == DEVICE_NFORCE)
2920                         buggy_irq = 1;
2921                 else
2922                         buggy_irq = 0;
2923         }
2924
2925         if ((err = snd_intel8x0_create(card, pci, pci_id->driver_data,
2926                                        &chip)) < 0) {
2927                 snd_card_free(card);
2928                 return err;
2929         }
2930         card->private_data = chip;
2931
2932         if ((err = snd_intel8x0_mixer(chip, ac97_clock, ac97_quirk)) < 0) {
2933                 snd_card_free(card);
2934                 return err;
2935         }
2936         if ((err = snd_intel8x0_pcm(chip)) < 0) {
2937                 snd_card_free(card);
2938                 return err;
2939         }
2940
2941         snd_intel8x0_proc_init(chip);
2942
2943         snprintf(card->longname, sizeof(card->longname),
2944                  "%s with %s at %#lx, irq %i", card->shortname,
2945                  snd_ac97_get_short_name(chip->ac97[0]), chip->addr, chip->irq);
2946
2947         if (! ac97_clock)
2948                 intel8x0_measure_ac97_clock(chip);
2949
2950         if ((err = snd_card_register(card)) < 0) {
2951                 snd_card_free(card);
2952                 return err;
2953         }
2954         pci_set_drvdata(pci, card);
2955         return 0;
2956 }
2957
2958 static void __devexit snd_intel8x0_remove(struct pci_dev *pci)
2959 {
2960         snd_card_free(pci_get_drvdata(pci));
2961         pci_set_drvdata(pci, NULL);
2962 }
2963
2964 static struct pci_driver driver = {
2965         .name = "Intel ICH",
2966         .id_table = snd_intel8x0_ids,
2967         .probe = snd_intel8x0_probe,
2968         .remove = __devexit_p(snd_intel8x0_remove),
2969 #ifdef CONFIG_PM
2970         .suspend = intel8x0_suspend,
2971         .resume = intel8x0_resume,
2972 #endif
2973 };
2974
2975
2976 static int __init alsa_card_intel8x0_init(void)
2977 {
2978         return pci_register_driver(&driver);
2979 }
2980
2981 static void __exit alsa_card_intel8x0_exit(void)
2982 {
2983         pci_unregister_driver(&driver);
2984 }
2985
2986 module_init(alsa_card_intel8x0_init)
2987 module_exit(alsa_card_intel8x0_exit)