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   1 /*
   2  *   ALSA driver for Intel ICH (i8x0) chipsets
   3  *
   4  *      Copyright (c) 2000 Jaroslav Kysela <perex@suse.cz>
   5  *
   6  *
   7  *   This code also contains alpha support for SiS 735 chipsets provided
   8  *   by Mike Pieper <mptei@users.sourceforge.net>. We have no datasheet
   9  *   for SiS735, so the code is not fully functional.
  10  *
  11  *
  12  *   This program is free software; you can redistribute it and/or modify
  13  *   it under the terms of the GNU General Public License as published by
  14  *   the Free Software Foundation; either version 2 of the License, or
  15  *   (at your option) any later version.
  16  *
  17  *   This program is distributed in the hope that it will be useful,
  18  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20  *   GNU General Public License for more details.
  21  *
  22  *   You should have received a copy of the GNU General Public License
  23  *   along with this program; if not, write to the Free Software
  24  *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  25
  26  *
  27  */
  28
  29 #include <sound/driver.h>
  30 #include <asm/io.h>
  31 #include <linux/delay.h>
  32 #include <linux/interrupt.h>
  33 #include <linux/init.h>
  34 #include <linux/pci.h>
  35 #include <linux/slab.h>
  36 #include <linux/moduleparam.h>
  37 #include <sound/core.h>
  38 #include <sound/pcm.h>
  39 #include <sound/ac97_codec.h>
  40 #include <sound/info.h>
  41 #include <sound/initval.h>
  42 /* for 440MX workaround */
  43 #include <asm/pgtable.h>
  44 #include <asm/cacheflush.h>
  45
  46 MODULE_AUTHOR("Jaroslav Kysela <perex@suse.cz>");
  47 MODULE_DESCRIPTION("Intel 82801AA,82901AB,i810,i820,i830,i840,i845,MX440; SiS 7012; Ali 5455");
  48 MODULE_LICENSE("GPL");
  49 MODULE_SUPPORTED_DEVICE("{{Intel,82801AA-ICH},"
  50                 "{Intel,82901AB-ICH0},"
  51                 "{Intel,82801BA-ICH2},"
  52                 "{Intel,82801CA-ICH3},"
  53                 "{Intel,82801DB-ICH4},"
  54                 "{Intel,ICH5},"
  55                 "{Intel,ICH6},"
  56                 "{Intel,ICH7},"
  57                 "{Intel,6300ESB},"
  58                 "{Intel,ESB2},"
  59                 "{Intel,MX440},"
  60                 "{SiS,SI7012},"
  61                 "{NVidia,nForce Audio},"
  62                 "{NVidia,nForce2 Audio},"
  63                 "{AMD,AMD768},"
  64                 "{AMD,AMD8111},"
  65                 "{ALI,M5455}}");
  66
  67 static int index = SNDRV_DEFAULT_IDX1;  /* Index 0-MAX */
  68 static char *id = SNDRV_DEFAULT_STR1;   /* ID for this card */
  69 static int ac97_clock = 0;
  70 static char *ac97_quirk;
  71 static int buggy_semaphore;
  72 static int buggy_irq;
  73 static int xbox;
  74
  75 module_param(index, int, 0444);
  76 MODULE_PARM_DESC(index, "Index value for Intel i8x0 soundcard.");
  77 module_param(id, charp, 0444);
  78 MODULE_PARM_DESC(id, "ID string for Intel i8x0 soundcard.");
  79 module_param(ac97_clock, int, 0444);
  80 MODULE_PARM_DESC(ac97_clock, "AC'97 codec clock (0 = auto-detect).");
  81 module_param(ac97_quirk, charp, 0444);
  82 MODULE_PARM_DESC(ac97_quirk, "AC'97 workaround for strange hardware.");
  83 module_param(buggy_semaphore, bool, 0444);
  84 MODULE_PARM_DESC(buggy_semaphore, "Enable workaround for hardwares with problematic codec semaphores.");
  85 module_param(buggy_irq, bool, 0444);
  86 MODULE_PARM_DESC(buggy_irq, "Enable workaround for buggy interrupts on some motherboards.");
  87 module_param(xbox, bool, 0444);
  88 MODULE_PARM_DESC(xbox, "Set to 1 for Xbox, if you have problems with the AC'97 codec detection.");
  89
  90 /*
  91  *  Direct registers
  92  */
  93 enum { DEVICE_INTEL, DEVICE_INTEL_ICH4, DEVICE_SIS, DEVICE_ALI, DEVICE_NFORCE };
  94
  95 #define ICHREG(x) ICH_REG_##x
  96
  97 #define DEFINE_REGSET(name,base) \
  98 enum { \
  99         ICH_REG_##name##_BDBAR  = base + 0x0,   /* dword - buffer descriptor list base address */ \
 100         ICH_REG_##name##_CIV    = base + 0x04,  /* byte - current index value */ \
 101         ICH_REG_##name##_LVI    = base + 0x05,  /* byte - last valid index */ \
 102         ICH_REG_##name##_SR     = base + 0x06,  /* byte - status register */ \
 103         ICH_REG_##name##_PICB   = base + 0x08,  /* word - position in current buffer */ \
 104         ICH_REG_##name##_PIV    = base + 0x0a,  /* byte - prefetched index value */ \
 105         ICH_REG_##name##_CR     = base + 0x0b,  /* byte - control register */ \
 106 };
 107
 108 /* busmaster blocks */
 109 DEFINE_REGSET(OFF, 0);          /* offset */
 110 DEFINE_REGSET(PI, 0x00);        /* PCM in */
 111 DEFINE_REGSET(PO, 0x10);        /* PCM out */
 112 DEFINE_REGSET(MC, 0x20);        /* Mic in */
 113
 114 /* ICH4 busmaster blocks */
 115 DEFINE_REGSET(MC2, 0x40);       /* Mic in 2 */
 116 DEFINE_REGSET(PI2, 0x50);       /* PCM in 2 */
 117 DEFINE_REGSET(SP, 0x60);        /* SPDIF out */
 118
 119 /* values for each busmaster block */
 120
 121 /* LVI */
 122 #define ICH_REG_LVI_MASK                0x1f
 123
 124 /* SR */
 125 #define ICH_FIFOE                       0x10    /* FIFO error */
 126 #define ICH_BCIS                        0x08    /* buffer completion interrupt status */
 127 #define ICH_LVBCI                       0x04    /* last valid buffer completion interrupt */
 128 #define ICH_CELV                        0x02    /* current equals last valid */
 129 #define ICH_DCH                         0x01    /* DMA controller halted */
 130
 131 /* PIV */
 132 #define ICH_REG_PIV_MASK                0x1f    /* mask */
 133
 134 /* CR */
 135 #define ICH_IOCE                        0x10    /* interrupt on completion enable */
 136 #define ICH_FEIE                        0x08    /* fifo error interrupt enable */
 137 #define ICH_LVBIE                       0x04    /* last valid buffer interrupt enable */
 138 #define ICH_RESETREGS                   0x02    /* reset busmaster registers */
 139 #define ICH_STARTBM                     0x01    /* start busmaster operation */
 140
 141
 142 /* global block */
 143 #define ICH_REG_GLOB_CNT                0x2c    /* dword - global control */
 144 #define   ICH_PCM_SPDIF_MASK    0xc0000000      /* s/pdif pcm slot mask (ICH4) */
 145 #define   ICH_PCM_SPDIF_NONE    0x00000000      /* reserved - undefined */
 146 #define   ICH_PCM_SPDIF_78      0x40000000      /* s/pdif pcm on slots 7&8 */
 147 #define   ICH_PCM_SPDIF_69      0x80000000      /* s/pdif pcm on slots 6&9 */
 148 #define   ICH_PCM_SPDIF_1011    0xc0000000      /* s/pdif pcm on slots 10&11 */
 149 #define   ICH_PCM_20BIT         0x00400000      /* 20-bit samples (ICH4) */
 150 #define   ICH_PCM_246_MASK      0x00300000      /* 6 channels (not all chips) */
 151 #define   ICH_PCM_6             0x00200000      /* 6 channels (not all chips) */
 152 #define   ICH_PCM_4             0x00100000      /* 4 channels (not all chips) */
 153 #define   ICH_PCM_2             0x00000000      /* 2 channels (stereo) */
 154 #define   ICH_SIS_PCM_246_MASK  0x000000c0      /* 6 channels (SIS7012) */
 155 #define   ICH_SIS_PCM_6         0x00000080      /* 6 channels (SIS7012) */
 156 #define   ICH_SIS_PCM_4         0x00000040      /* 4 channels (SIS7012) */
 157 #define   ICH_SIS_PCM_2         0x00000000      /* 2 channels (SIS7012) */
 158 #define   ICH_TRIE              0x00000040      /* tertiary resume interrupt enable */
 159 #define   ICH_SRIE              0x00000020      /* secondary resume interrupt enable */
 160 #define   ICH_PRIE              0x00000010      /* primary resume interrupt enable */
 161 #define   ICH_ACLINK            0x00000008      /* AClink shut off */
 162 #define   ICH_AC97WARM          0x00000004      /* AC'97 warm reset */
 163 #define   ICH_AC97COLD          0x00000002      /* AC'97 cold reset */
 164 #define   ICH_GIE               0x00000001      /* GPI interrupt enable */
 165 #define ICH_REG_GLOB_STA                0x30    /* dword - global status */
 166 #define   ICH_TRI               0x20000000      /* ICH4: tertiary (AC_SDIN2) resume interrupt */
 167 #define   ICH_TCR               0x10000000      /* ICH4: tertiary (AC_SDIN2) codec ready */
 168 #define   ICH_BCS               0x08000000      /* ICH4: bit clock stopped */
 169 #define   ICH_SPINT             0x04000000      /* ICH4: S/PDIF interrupt */
 170 #define   ICH_P2INT             0x02000000      /* ICH4: PCM2-In interrupt */
 171 #define   ICH_M2INT             0x01000000      /* ICH4: Mic2-In interrupt */
 172 #define   ICH_SAMPLE_CAP        0x00c00000      /* ICH4: sample capability bits (RO) */
 173 #define   ICH_SAMPLE_16_20      0x00400000      /* ICH4: 16- and 20-bit samples */
 174 #define   ICH_MULTICHAN_CAP     0x00300000      /* ICH4: multi-channel capability bits (RO) */
 175 #define   ICH_MD3               0x00020000      /* modem power down semaphore */
 176 #define   ICH_AD3               0x00010000      /* audio power down semaphore */
 177 #define   ICH_RCS               0x00008000      /* read completion status */
 178 #define   ICH_BIT3              0x00004000      /* bit 3 slot 12 */
 179 #define   ICH_BIT2              0x00002000      /* bit 2 slot 12 */
 180 #define   ICH_BIT1              0x00001000      /* bit 1 slot 12 */
 181 #define   ICH_SRI               0x00000800      /* secondary (AC_SDIN1) resume interrupt */
 182 #define   ICH_PRI               0x00000400      /* primary (AC_SDIN0) resume interrupt */
 183 #define   ICH_SCR               0x00000200      /* secondary (AC_SDIN1) codec ready */
 184 #define   ICH_PCR               0x00000100      /* primary (AC_SDIN0) codec ready */
 185 #define   ICH_MCINT             0x00000080      /* MIC capture interrupt */
 186 #define   ICH_POINT             0x00000040      /* playback interrupt */
 187 #define   ICH_PIINT             0x00000020      /* capture interrupt */
 188 #define   ICH_NVSPINT           0x00000010      /* nforce spdif interrupt */
 189 #define   ICH_MOINT             0x00000004      /* modem playback interrupt */
 190 #define   ICH_MIINT             0x00000002      /* modem capture interrupt */
 191 #define   ICH_GSCI              0x00000001      /* GPI status change interrupt */
 192 #define ICH_REG_ACC_SEMA                0x34    /* byte - codec write semaphore */
 193 #define   ICH_CAS               0x01            /* codec access semaphore */
 194 #define ICH_REG_SDM             0x80
 195 #define   ICH_DI2L_MASK         0x000000c0      /* PCM In 2, Mic In 2 data in line */
 196 #define   ICH_DI2L_SHIFT        6
 197 #define   ICH_DI1L_MASK         0x00000030      /* PCM In 1, Mic In 1 data in line */
 198 #define   ICH_DI1L_SHIFT        4
 199 #define   ICH_SE                0x00000008      /* steer enable */
 200 #define   ICH_LDI_MASK          0x00000003      /* last codec read data input */
 201
 202 #define ICH_MAX_FRAGS           32              /* max hw frags */
 203
 204
 205 /*
 206  * registers for Ali5455
 207  */
 208
 209 /* ALi 5455 busmaster blocks */
 210 DEFINE_REGSET(AL_PI, 0x40);     /* ALi PCM in */
 211 DEFINE_REGSET(AL_PO, 0x50);     /* Ali PCM out */
 212 DEFINE_REGSET(AL_MC, 0x60);     /* Ali Mic in */
 213 DEFINE_REGSET(AL_CDC_SPO, 0x70);        /* Ali Codec SPDIF out */
 214 DEFINE_REGSET(AL_CENTER, 0x80);         /* Ali center out */
 215 DEFINE_REGSET(AL_LFE, 0x90);            /* Ali center out */
 216 DEFINE_REGSET(AL_CLR_SPI, 0xa0);        /* Ali Controller SPDIF in */
 217 DEFINE_REGSET(AL_CLR_SPO, 0xb0);        /* Ali Controller SPDIF out */
 218 DEFINE_REGSET(AL_I2S, 0xc0);    /* Ali I2S in */
 219 DEFINE_REGSET(AL_PI2, 0xd0);    /* Ali PCM2 in */
 220 DEFINE_REGSET(AL_MC2, 0xe0);    /* Ali Mic2 in */
 221
 222 enum {
 223         ICH_REG_ALI_SCR = 0x00,         /* System Control Register */
 224         ICH_REG_ALI_SSR = 0x04,         /* System Status Register  */
 225         ICH_REG_ALI_DMACR = 0x08,       /* DMA Control Register    */
 226         ICH_REG_ALI_FIFOCR1 = 0x0c,     /* FIFO Control Register 1  */
 227         ICH_REG_ALI_INTERFACECR = 0x10, /* Interface Control Register */
 228         ICH_REG_ALI_INTERRUPTCR = 0x14, /* Interrupt control Register */
 229         ICH_REG_ALI_INTERRUPTSR = 0x18, /* Interrupt  Status Register */
 230         ICH_REG_ALI_FIFOCR2 = 0x1c,     /* FIFO Control Register 2   */
 231         ICH_REG_ALI_CPR = 0x20,         /* Command Port Register     */
 232         ICH_REG_ALI_CPR_ADDR = 0x22,    /* ac97 addr write */
 233         ICH_REG_ALI_SPR = 0x24,         /* Status Port Register      */
 234         ICH_REG_ALI_SPR_ADDR = 0x26,    /* ac97 addr read */
 235         ICH_REG_ALI_FIFOCR3 = 0x2c,     /* FIFO Control Register 3  */
 236         ICH_REG_ALI_TTSR = 0x30,        /* Transmit Tag Slot Register */
 237         ICH_REG_ALI_RTSR = 0x34,        /* Receive Tag Slot  Register */
 238         ICH_REG_ALI_CSPSR = 0x38,       /* Command/Status Port Status Register */
 239         ICH_REG_ALI_CAS = 0x3c,         /* Codec Write Semaphore Register */
 240         ICH_REG_ALI_HWVOL = 0xf0,       /* hardware volume control/status */
 241         ICH_REG_ALI_I2SCR = 0xf4,       /* I2S control/status */
 242         ICH_REG_ALI_SPDIFCSR = 0xf8,    /* spdif channel status register  */
 243         ICH_REG_ALI_SPDIFICS = 0xfc,    /* spdif interface control/status  */
 244 };
 245
 246 #define ALI_CAS_SEM_BUSY        0x80000000
 247 #define ALI_CPR_ADDR_SECONDARY  0x100
 248 #define ALI_CPR_ADDR_READ       0x80
 249 #define ALI_CSPSR_CODEC_READY   0x08
 250 #define ALI_CSPSR_READ_OK       0x02
 251 #define ALI_CSPSR_WRITE_OK      0x01
 252
 253 /* interrupts for the whole chip by interrupt status register finish */
 254
 255 #define ALI_INT_MICIN2          (1<<26)
 256 #define ALI_INT_PCMIN2          (1<<25)
 257 #define ALI_INT_I2SIN           (1<<24)
 258 #define ALI_INT_SPDIFOUT        (1<<23) /* controller spdif out INTERRUPT */
 259 #define ALI_INT_SPDIFIN         (1<<22)
 260 #define ALI_INT_LFEOUT          (1<<21)
 261 #define ALI_INT_CENTEROUT       (1<<20)
 262 #define ALI_INT_CODECSPDIFOUT   (1<<19)
 263 #define ALI_INT_MICIN           (1<<18)
 264 #define ALI_INT_PCMOUT          (1<<17)
 265 #define ALI_INT_PCMIN           (1<<16)
 266 #define ALI_INT_CPRAIS          (1<<7)  /* command port available */
 267 #define ALI_INT_SPRAIS          (1<<5)  /* status port available */
 268 #define ALI_INT_GPIO            (1<<1)
 269 #define ALI_INT_MASK            (ALI_INT_SPDIFOUT|ALI_INT_CODECSPDIFOUT|ALI_INT_MICIN|ALI_INT_PCMOUT|ALI_INT_PCMIN)
 270
 271 #define ICH_ALI_SC_RESET        (1<<31) /* master reset */
 272 #define ICH_ALI_SC_AC97_DBL     (1<<30)
 273 #define ICH_ALI_SC_CODEC_SPDF   (3<<20) /* 1=7/8, 2=6/9, 3=10/11 */
 274 #define ICH_ALI_SC_IN_BITS      (3<<18)
 275 #define ICH_ALI_SC_OUT_BITS     (3<<16)
 276 #define ICH_ALI_SC_6CH_CFG      (3<<14)
 277 #define ICH_ALI_SC_PCM_4        (1<<8)
 278 #define ICH_ALI_SC_PCM_6        (2<<8)
 279 #define ICH_ALI_SC_PCM_246_MASK (3<<8)
 280
 281 #define ICH_ALI_SS_SEC_ID       (3<<5)
 282 #define ICH_ALI_SS_PRI_ID       (3<<3)
 283
 284 #define ICH_ALI_IF_AC97SP       (1<<21)
 285 #define ICH_ALI_IF_MC           (1<<20)
 286 #define ICH_ALI_IF_PI           (1<<19)
 287 #define ICH_ALI_IF_MC2          (1<<18)
 288 #define ICH_ALI_IF_PI2          (1<<17)
 289 #define ICH_ALI_IF_LINE_SRC     (1<<15) /* 0/1 = slot 3/6 */
 290 #define ICH_ALI_IF_MIC_SRC      (1<<14) /* 0/1 = slot 3/6 */
 291 #define ICH_ALI_IF_SPDF_SRC     (3<<12) /* 00 = PCM, 01 = AC97-in, 10 = spdif-in, 11 = i2s */
 292 #define ICH_ALI_IF_AC97_OUT     (3<<8)  /* 00 = PCM, 10 = spdif-in, 11 = i2s */
 293 #define ICH_ALI_IF_PO_SPDF      (1<<3)
 294 #define ICH_ALI_IF_PO           (1<<1)
 295
 296 /*
 297  *
 298  */
 299
 300 enum { ICHD_PCMIN, ICHD_PCMOUT, ICHD_MIC, ICHD_MIC2, ICHD_PCM2IN, ICHD_SPBAR, ICHD_LAST = ICHD_SPBAR };
 301 enum { NVD_PCMIN, NVD_PCMOUT, NVD_MIC, NVD_SPBAR, NVD_LAST = NVD_SPBAR };
 302 enum { ALID_PCMIN, ALID_PCMOUT, ALID_MIC, ALID_AC97SPDIFOUT, ALID_SPDIFIN, ALID_SPDIFOUT, ALID_LAST = ALID_SPDIFOUT };
 303
 304 #define get_ichdev(substream) (ichdev_t *)(substream->runtime->private_data)
 305
 306 typedef struct {
 307         unsigned int ichd;                      /* ich device number */
 308         unsigned long reg_offset;               /* offset to bmaddr */
 309         u32 *bdbar;                             /* CPU address (32bit) */
 310         unsigned int bdbar_addr;                /* PCI bus address (32bit) */
 311         snd_pcm_substream_t *substream;
 312         unsigned int physbuf;                   /* physical address (32bit) */
 313         unsigned int size;
 314         unsigned int fragsize;
 315         unsigned int fragsize1;
 316         unsigned int position;
 317         unsigned int pos_shift;
 318         int frags;
 319         int lvi;
 320         int lvi_frag;
 321         int civ;
 322         int ack;
 323         int ack_reload;
 324         unsigned int ack_bit;
 325         unsigned int roff_sr;
 326         unsigned int roff_picb;
 327         unsigned int int_sta_mask;              /* interrupt status mask */
 328         unsigned int ali_slot;                  /* ALI DMA slot */
 329         struct ac97_pcm *pcm;
 330         int pcm_open_flag;
 331         unsigned int page_attr_changed: 1;
 332         unsigned int suspended: 1;
 333 } ichdev_t;
 334
 335 typedef struct _snd_intel8x0 intel8x0_t;
 336
 337 struct _snd_intel8x0 {
 338         unsigned int device_type;
 339
 340         int irq;
 341
 342         unsigned int mmio;
 343         unsigned long addr;
 344         void __iomem *remap_addr;
 345         unsigned int bm_mmio;
 346         unsigned long bmaddr;
 347         void __iomem *remap_bmaddr;
 348
 349         struct pci_dev *pci;
 350         snd_card_t *card;
 351
 352         int pcm_devs;
 353         snd_pcm_t *pcm[6];
 354         ichdev_t ichd[6];
 355
 356         unsigned multi4: 1,
 357                  multi6: 1,
 358                  dra: 1,
 359                  smp20bit: 1;
 360         unsigned in_ac97_init: 1,
 361                  in_sdin_init: 1;
 362         unsigned in_measurement: 1;     /* during ac97 clock measurement */
 363         unsigned fix_nocache: 1;        /* workaround for 440MX */
 364         unsigned buggy_irq: 1;          /* workaround for buggy mobos */
 365         unsigned xbox: 1;               /* workaround for Xbox AC'97 detection */
 366         unsigned buggy_semaphore: 1;    /* workaround for buggy codec semaphore */
 367
 368         int spdif_idx;  /* SPDIF BAR index; *_SPBAR or -1 if use PCMOUT */
 369         unsigned int sdm_saved; /* SDM reg value */
 370
 371         ac97_bus_t *ac97_bus;
 372         ac97_t *ac97[3];
 373         unsigned int ac97_sdin[3];
 374
 375         spinlock_t reg_lock;
 376
 377         u32 bdbars_count;
 378         struct snd_dma_buffer bdbars;
 379         u32 int_sta_reg;                /* interrupt status register */
 380         u32 int_sta_mask;               /* interrupt status mask */
 381 };
 382
 383 static struct pci_device_id snd_intel8x0_ids[] = {
 384         { 0x8086, 0x2415, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 82801AA */
 385         { 0x8086, 0x2425, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 82901AB */
 386         { 0x8086, 0x2445, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 82801BA */
 387         { 0x8086, 0x2485, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* ICH3 */
 388         { 0x8086, 0x24c5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ICH4 */
 389         { 0x8086, 0x24d5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ICH5 */
 390         { 0x8086, 0x25a6, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ESB */
 391         { 0x8086, 0x266e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ICH6 */
 392         { 0x8086, 0x27de, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ICH7 */
 393         { 0x8086, 0x2698, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ESB2 */
 394         { 0x8086, 0x7195, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 440MX */
 395         { 0x1039, 0x7012, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_SIS },   /* SI7012 */
 396         { 0x10de, 0x01b1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE },        /* NFORCE */
 397         { 0x10de, 0x003a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE },        /* MCP04 */
 398         { 0x10de, 0x006a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE },        /* NFORCE2 */
 399         { 0x10de, 0x0059, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE },        /* CK804 */
 400         { 0x10de, 0x008a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE },        /* CK8 */
 401         { 0x10de, 0x00da, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE },        /* NFORCE3 */
 402         { 0x10de, 0x00ea, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE },        /* CK8S */
 403         { 0x1022, 0x746d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* AMD8111 */
 404         { 0x1022, 0x7445, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* AMD768 */
 405         { 0x10b9, 0x5455, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_ALI },   /* Ali5455 */
 406         { 0, }
 407 };
 408
 409 MODULE_DEVICE_TABLE(pci, snd_intel8x0_ids);
 410
 411 /*
 412  *  Lowlevel I/O - busmaster
 413  */
 414
 415 static u8 igetbyte(intel8x0_t *chip, u32 offset)
 416 {
 417         if (chip->bm_mmio)
 418                 return readb(chip->remap_bmaddr + offset);
 419         else
 420                 return inb(chip->bmaddr + offset);
 421 }
 422
 423 static u16 igetword(intel8x0_t *chip, u32 offset)
 424 {
 425         if (chip->bm_mmio)
 426                 return readw(chip->remap_bmaddr + offset);
 427         else
 428                 return inw(chip->bmaddr + offset);
 429 }
 430
 431 static u32 igetdword(intel8x0_t *chip, u32 offset)
 432 {
 433         if (chip->bm_mmio)
 434                 return readl(chip->remap_bmaddr + offset);
 435         else
 436                 return inl(chip->bmaddr + offset);
 437 }
 438
 439 static void iputbyte(intel8x0_t *chip, u32 offset, u8 val)
 440 {
 441         if (chip->bm_mmio)
 442                 writeb(val, chip->remap_bmaddr + offset);
 443         else
 444                 outb(val, chip->bmaddr + offset);
 445 }
 446
 447 static void iputword(intel8x0_t *chip, u32 offset, u16 val)
 448 {
 449         if (chip->bm_mmio)
 450                 writew(val, chip->remap_bmaddr + offset);
 451         else
 452                 outw(val, chip->bmaddr + offset);
 453 }
 454
 455 static void iputdword(intel8x0_t *chip, u32 offset, u32 val)
 456 {
 457         if (chip->bm_mmio)
 458                 writel(val, chip->remap_bmaddr + offset);
 459         else
 460                 outl(val, chip->bmaddr + offset);
 461 }
 462
 463 /*
 464  *  Lowlevel I/O - AC'97 registers
 465  */
 466
 467 static u16 iagetword(intel8x0_t *chip, u32 offset)
 468 {
 469         if (chip->mmio)
 470                 return readw(chip->remap_addr + offset);
 471         else
 472                 return inw(chip->addr + offset);
 473 }
 474
 475 static void iaputword(intel8x0_t *chip, u32 offset, u16 val)
 476 {
 477         if (chip->mmio)
 478                 writew(val, chip->remap_addr + offset);
 479         else
 480                 outw(val, chip->addr + offset);
 481 }
 482
 483 /*
 484  *  Basic I/O
 485  */
 486
 487 /*
 488  * access to AC97 codec via normal i/o (for ICH and SIS7012)
 489  */
 490
 491 /* return the GLOB_STA bit for the corresponding codec */
 492 static unsigned int get_ich_codec_bit(intel8x0_t *chip, unsigned int codec)
 493 {
 494         static unsigned int codec_bit[3] = {
 495                 ICH_PCR, ICH_SCR, ICH_TCR
 496         };
 497         snd_assert(codec < 3, return ICH_PCR);
 498         if (chip->device_type == DEVICE_INTEL_ICH4)
 499                 codec = chip->ac97_sdin[codec];
 500         return codec_bit[codec];
 501 }
 502
 503 static int snd_intel8x0_codec_semaphore(intel8x0_t *chip, unsigned int codec)
 504 {
 505         int time;
 506
 507         if (codec > 2)
 508                 return -EIO;
 509         if (chip->in_sdin_init) {
 510                 /* we don't know the ready bit assignment at the moment */
 511                 /* so we check any */
 512                 codec = ICH_PCR | ICH_SCR | ICH_TCR;
 513         } else {
 514                 codec = get_ich_codec_bit(chip, codec);
 515         }
 516
 517         /* codec ready ? */
 518         if ((igetdword(chip, ICHREG(GLOB_STA)) & codec) == 0)
 519                 return -EIO;
 520
 521         if (chip->buggy_semaphore)
 522                 return 0; /* just ignore ... */
 523
 524         /* Anyone holding a semaphore for 1 msec should be shot... */
 525         time = 100;
 526         do {
 527                 if (!(igetbyte(chip, ICHREG(ACC_SEMA)) & ICH_CAS))
 528                         return 0;
 529                 udelay(10);
 530         } while (time--);
 531
 532         /* access to some forbidden (non existant) ac97 registers will not
 533          * reset the semaphore. So even if you don't get the semaphore, still
 534          * continue the access. We don't need the semaphore anyway. */
 535         snd_printk("codec_semaphore: semaphore is not ready [0x%x][0x%x]\n",
 536                         igetbyte(chip, ICHREG(ACC_SEMA)), igetdword(chip, ICHREG(GLOB_STA)));
 537         iagetword(chip, 0);     /* clear semaphore flag */
 538         /* I don't care about the semaphore */
 539         return -EBUSY;
 540 }
 541
 542 static void snd_intel8x0_codec_write(ac97_t *ac97,
 543                                      unsigned short reg,
 544                                      unsigned short val)
 545 {
 546         intel8x0_t *chip = ac97->private_data;
 547
 548         if (snd_intel8x0_codec_semaphore(chip, ac97->num) < 0) {
 549                 if (! chip->in_ac97_init)
 550                         snd_printk("codec_write %d: semaphore is not ready for register 0x%x\n", ac97->num, reg);
 551         }
 552         iaputword(chip, reg + ac97->num * 0x80, val);
 553 }
 554
 555 static unsigned short snd_intel8x0_codec_read(ac97_t *ac97,
 556                                               unsigned short reg)
 557 {
 558         intel8x0_t *chip = ac97->private_data;
 559         unsigned short res;
 560         unsigned int tmp;
 561
 562         if (snd_intel8x0_codec_semaphore(chip, ac97->num) < 0) {
 563                 if (! chip->in_ac97_init)
 564                         snd_printk("codec_read %d: semaphore is not ready for register 0x%x\n", ac97->num, reg);
 565                 res = 0xffff;
 566         } else {
 567                 res = iagetword(chip, reg + ac97->num * 0x80);
 568                 if ((tmp = igetdword(chip, ICHREG(GLOB_STA))) & ICH_RCS) {
 569                         /* reset RCS and preserve other R/WC bits */
 570                         iputdword(chip, ICHREG(GLOB_STA), tmp & ~(ICH_SRI|ICH_PRI|ICH_TRI|ICH_GSCI));
 571                         if (! chip->in_ac97_init)
 572                                 snd_printk("codec_read %d: read timeout for register 0x%x\n", ac97->num, reg);
 573                         res = 0xffff;
 574                 }
 575         }
 576         return res;
 577 }
 578
 579 static void snd_intel8x0_codec_read_test(intel8x0_t *chip, unsigned int codec)
 580 {
 581         unsigned int tmp;
 582
 583         if (snd_intel8x0_codec_semaphore(chip, codec) >= 0) {
 584                 iagetword(chip, codec * 0x80);
 585                 if ((tmp = igetdword(chip, ICHREG(GLOB_STA))) & ICH_RCS) {
 586                         /* reset RCS and preserve other R/WC bits */
 587                         iputdword(chip, ICHREG(GLOB_STA), tmp & ~(ICH_SRI|ICH_PRI|ICH_TRI|ICH_GSCI));
 588                 }
 589         }
 590 }
 591
 592 /*
 593  * access to AC97 for Ali5455
 594  */
 595 static int snd_intel8x0_ali_codec_ready(intel8x0_t *chip, int mask)
 596 {
 597         int count = 0;
 598         for (count = 0; count < 0x7f; count++) {
 599                 int val = igetbyte(chip, ICHREG(ALI_CSPSR));
 600                 if (val & mask)
 601                         return 0;
 602         }
 603         if (! chip->in_ac97_init)
 604                 snd_printd(KERN_WARNING "intel8x0: AC97 codec ready timeout.\n");
 605         return -EBUSY;
 606 }
 607
 608 static int snd_intel8x0_ali_codec_semaphore(intel8x0_t *chip)
 609 {
 610         int time = 100;
 611         if (chip->buggy_semaphore)
 612                 return 0; /* just ignore ... */
 613         while (time-- && (igetdword(chip, ICHREG(ALI_CAS)) & ALI_CAS_SEM_BUSY))
 614                 udelay(1);
 615         if (! time && ! chip->in_ac97_init)
 616                 snd_printk(KERN_WARNING "ali_codec_semaphore timeout\n");
 617         return snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_CODEC_READY);
 618 }
 619
 620 static unsigned short snd_intel8x0_ali_codec_read(ac97_t *ac97, unsigned short reg)
 621 {
 622         intel8x0_t *chip = ac97->private_data;
 623         unsigned short data = 0xffff;
 624
 625         if (snd_intel8x0_ali_codec_semaphore(chip))
 626                 goto __err;
 627         reg |= ALI_CPR_ADDR_READ;
 628         if (ac97->num)
 629                 reg |= ALI_CPR_ADDR_SECONDARY;
 630         iputword(chip, ICHREG(ALI_CPR_ADDR), reg);
 631         if (snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_READ_OK))
 632                 goto __err;
 633         data = igetword(chip, ICHREG(ALI_SPR));
 634  __err:
 635         return data;
 636 }
 637
 638 static void snd_intel8x0_ali_codec_write(ac97_t *ac97, unsigned short reg, unsigned short val)
 639 {
 640         intel8x0_t *chip = ac97->private_data;
 641
 642         if (snd_intel8x0_ali_codec_semaphore(chip))
 643                 return;
 644         iputword(chip, ICHREG(ALI_CPR), val);
 645         if (ac97->num)
 646                 reg |= ALI_CPR_ADDR_SECONDARY;
 647         iputword(chip, ICHREG(ALI_CPR_ADDR), reg);
 648         snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_WRITE_OK);
 649 }
 650
 651
 652 /*
 653  * DMA I/O
 654  */
 655 static void snd_intel8x0_setup_periods(intel8x0_t *chip, ichdev_t *ichdev)
 656 {
 657         int idx;
 658         u32 *bdbar = ichdev->bdbar;
 659         unsigned long port = ichdev->reg_offset;
 660
 661         iputdword(chip, port + ICH_REG_OFF_BDBAR, ichdev->bdbar_addr);
 662         if (ichdev->size == ichdev->fragsize) {
 663                 ichdev->ack_reload = ichdev->ack = 2;
 664                 ichdev->fragsize1 = ichdev->fragsize >> 1;
 665                 for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 4) {
 666                         bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf);
 667                         bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */
 668                                                      ichdev->fragsize1 >> ichdev->pos_shift);
 669                         bdbar[idx + 2] = cpu_to_le32(ichdev->physbuf + (ichdev->size >> 1));
 670                         bdbar[idx + 3] = cpu_to_le32(0x80000000 | /* interrupt on completion */
 671                                                      ichdev->fragsize1 >> ichdev->pos_shift);
 672                 }
 673                 ichdev->frags = 2;
 674         } else {
 675                 ichdev->ack_reload = ichdev->ack = 1;
 676                 ichdev->fragsize1 = ichdev->fragsize;
 677                 for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 2) {
 678                         bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf + (((idx >> 1) * ichdev->fragsize) % ichdev->size));
 679                         bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */
 680                                                      ichdev->fragsize >> ichdev->pos_shift);
 681                         // printk("bdbar[%i] = 0x%x [0x%x]\n", idx + 0, bdbar[idx + 0], bdbar[idx + 1]);
 682                 }
 683                 ichdev->frags = ichdev->size / ichdev->fragsize;
 684         }
 685         iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi = ICH_REG_LVI_MASK);
 686         ichdev->civ = 0;
 687         iputbyte(chip, port + ICH_REG_OFF_CIV, 0);
 688         ichdev->lvi_frag = ICH_REG_LVI_MASK % ichdev->frags;
 689         ichdev->position = 0;
 690 #if 0
 691         printk("lvi_frag = %i, frags = %i, period_size = 0x%x, period_size1 = 0x%x\n",
 692                         ichdev->lvi_frag, ichdev->frags, ichdev->fragsize, ichdev->fragsize1);
 693 #endif
 694         /* clear interrupts */
 695         iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI);
 696 }
 697
 698 #ifdef __i386__
 699 /*
 700  * Intel 82443MX running a 100MHz processor system bus has a hardware bug,
 701  * which aborts PCI busmaster for audio transfer.  A workaround is to set
 702  * the pages as non-cached.  For details, see the errata in
 703  *      http://www.intel.com/design/chipsets/specupdt/245051.htm
 704  */
 705 static void fill_nocache(void *buf, int size, int nocache)
 706 {
 707         size = (size + PAGE_SIZE - 1) >> PAGE_SHIFT;
 708         change_page_attr(virt_to_page(buf), size, nocache ? PAGE_KERNEL_NOCACHE : PAGE_KERNEL);
 709         global_flush_tlb();
 710 }
 711 #else
 712 #define fill_nocache(buf,size,nocache)
 713 #endif
 714
 715 /*
 716  *  Interrupt handler
 717  */
 718
 719 static inline void snd_intel8x0_update(intel8x0_t *chip, ichdev_t *ichdev)
 720 {
 721         unsigned long port = ichdev->reg_offset;
 722         int status, civ, i, step;
 723         int ack = 0;
 724
 725         spin_lock(&chip->reg_lock);
 726         status = igetbyte(chip, port + ichdev->roff_sr);
 727         civ = igetbyte(chip, port + ICH_REG_OFF_CIV);
 728         if (!(status & ICH_BCIS)) {
 729                 step = 0;
 730         } else if (civ == ichdev->civ) {
 731                 // snd_printd("civ same %d\n", civ);
 732                 step = 1;
 733                 ichdev->civ++;
 734                 ichdev->civ &= ICH_REG_LVI_MASK;
 735         } else {
 736                 step = civ - ichdev->civ;
 737                 if (step < 0)
 738                         step += ICH_REG_LVI_MASK + 1;
 739                 // if (step != 1)
 740                 //      snd_printd("step = %d, %d -> %d\n", step, ichdev->civ, civ);
 741                 ichdev->civ = civ;
 742         }
 743
 744         ichdev->position += step * ichdev->fragsize1;
 745         if (! chip->in_measurement)
 746                 ichdev->position %= ichdev->size;
 747         ichdev->lvi += step;
 748         ichdev->lvi &= ICH_REG_LVI_MASK;
 749         iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi);
 750         for (i = 0; i < step; i++) {
 751                 ichdev->lvi_frag++;
 752                 ichdev->lvi_frag %= ichdev->frags;
 753                 ichdev->bdbar[ichdev->lvi * 2] = cpu_to_le32(ichdev->physbuf + ichdev->lvi_frag * ichdev->fragsize1);
 754         // printk("new: bdbar[%i] = 0x%x [0x%x], prefetch = %i, all = 0x%x, 0x%x\n", ichdev->lvi * 2, ichdev->bdbar[ichdev->lvi * 2], ichdev->bdbar[ichdev->lvi * 2 + 1], inb(ICH_REG_OFF_PIV + port), inl(port + 4), inb(port + ICH_REG_OFF_CR));
 755                 if (--ichdev->ack == 0) {
 756                         ichdev->ack = ichdev->ack_reload;
 757                         ack = 1;
 758                 }
 759         }
 760         spin_unlock(&chip->reg_lock);
 761         if (ack && ichdev->substream) {
 762                 snd_pcm_period_elapsed(ichdev->substream);
 763         }
 764         iputbyte(chip, port + ichdev->roff_sr,
 765                  status & (ICH_FIFOE | ICH_BCIS | ICH_LVBCI));
 766 }
 767
 768 static irqreturn_t snd_intel8x0_interrupt(int irq, void *dev_id, struct pt_regs *regs)
 769 {
 770         intel8x0_t *chip = dev_id;
 771         ichdev_t *ichdev;
 772         unsigned int status;
 773         unsigned int i;
 774
 775         status = igetdword(chip, chip->int_sta_reg);
 776         if (status == 0xffffffff)       /* we are not yet resumed */
 777                 return IRQ_NONE;
 778
 779         if ((status & chip->int_sta_mask) == 0) {
 780                 if (status) {
 781                         /* ack */
 782                         iputdword(chip, chip->int_sta_reg, status);
 783                         if (! chip->buggy_irq)
 784                                 status = 0;
 785                 }
 786                 return IRQ_RETVAL(status);
 787         }
 788
 789         for (i = 0; i < chip->bdbars_count; i++) {
 790                 ichdev = &chip->ichd[i];
 791                 if (status & ichdev->int_sta_mask)
 792                         snd_intel8x0_update(chip, ichdev);
 793         }
 794
 795         /* ack them */
 796         iputdword(chip, chip->int_sta_reg, status & chip->int_sta_mask);
 797
 798         return IRQ_HANDLED;
 799 }
 800
 801 /*
 802  *  PCM part
 803  */
 804
 805 static int snd_intel8x0_pcm_trigger(snd_pcm_substream_t *substream, int cmd)
 806 {
 807         intel8x0_t *chip = snd_pcm_substream_chip(substream);
 808         ichdev_t *ichdev = get_ichdev(substream);
 809         unsigned char val = 0;
 810         unsigned long port = ichdev->reg_offset;
 811
 812         switch (cmd) {
 813         case SNDRV_PCM_TRIGGER_RESUME:
 814                 ichdev->suspended = 0;
 815                 /* fallthru */
 816         case SNDRV_PCM_TRIGGER_START:
 817                 val = ICH_IOCE | ICH_STARTBM;
 818                 break;
 819         case SNDRV_PCM_TRIGGER_SUSPEND:
 820                 ichdev->suspended = 1;
 821                 /* fallthru */
 822         case SNDRV_PCM_TRIGGER_STOP:
 823                 val = 0;
 824                 break;
 825         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 826                 val = ICH_IOCE;
 827                 break;
 828         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 829                 val = ICH_IOCE | ICH_STARTBM;
 830                 break;
 831         default:
 832                 return -EINVAL;
 833         }
 834         iputbyte(chip, port + ICH_REG_OFF_CR, val);
 835         if (cmd == SNDRV_PCM_TRIGGER_STOP) {
 836                 /* wait until DMA stopped */
 837                 while (!(igetbyte(chip, port + ichdev->roff_sr) & ICH_DCH)) ;
 838                 /* reset whole DMA things */
 839                 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
 840         }
 841         return 0;
 842 }
 843
 844 static int snd_intel8x0_ali_trigger(snd_pcm_substream_t *substream, int cmd)
 845 {
 846         intel8x0_t *chip = snd_pcm_substream_chip(substream);
 847         ichdev_t *ichdev = get_ichdev(substream);
 848         unsigned long port = ichdev->reg_offset;
 849         static int fiforeg[] = { ICHREG(ALI_FIFOCR1), ICHREG(ALI_FIFOCR2), ICHREG(ALI_FIFOCR3) };
 850         unsigned int val, fifo;
 851
 852         val = igetdword(chip, ICHREG(ALI_DMACR));
 853         switch (cmd) {
 854         case SNDRV_PCM_TRIGGER_RESUME:
 855                 ichdev->suspended = 0;
 856                 /* fallthru */
 857         case SNDRV_PCM_TRIGGER_START:
 858         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 859                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
 860                         /* clear FIFO for synchronization of channels */
 861                         fifo = igetdword(chip, fiforeg[ichdev->ali_slot / 4]);
 862                         fifo &= ~(0xff << (ichdev->ali_slot % 4));
 863                         fifo |= 0x83 << (ichdev->ali_slot % 4);
 864                         iputdword(chip, fiforeg[ichdev->ali_slot / 4], fifo);
 865                 }
 866                 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE);
 867                 val &= ~(1 << (ichdev->ali_slot + 16)); /* clear PAUSE flag */
 868                 iputdword(chip, ICHREG(ALI_DMACR), val | (1 << ichdev->ali_slot)); /* start DMA */
 869                 break;
 870         case SNDRV_PCM_TRIGGER_SUSPEND:
 871                 ichdev->suspended = 1;
 872                 /* fallthru */
 873         case SNDRV_PCM_TRIGGER_STOP:
 874         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 875                 iputdword(chip, ICHREG(ALI_DMACR), val | (1 << (ichdev->ali_slot + 16))); /* pause */
 876                 iputbyte(chip, port + ICH_REG_OFF_CR, 0);
 877                 while (igetbyte(chip, port + ICH_REG_OFF_CR))
 878                         ;
 879                 if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH)
 880                         break;
 881                 /* reset whole DMA things */
 882                 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
 883                 /* clear interrupts */
 884                 iputbyte(chip, port + ICH_REG_OFF_SR, igetbyte(chip, port + ICH_REG_OFF_SR) | 0x1e);
 885                 iputdword(chip, ICHREG(ALI_INTERRUPTSR),
 886                           igetdword(chip, ICHREG(ALI_INTERRUPTSR)) & ichdev->int_sta_mask);
 887                 break;
 888         default:
 889                 return -EINVAL;
 890         }
 891         return 0;
 892 }
 893
 894 static int snd_intel8x0_hw_params(snd_pcm_substream_t * substream,
 895                                   snd_pcm_hw_params_t * hw_params)
 896 {
 897         intel8x0_t *chip = snd_pcm_substream_chip(substream);
 898         ichdev_t *ichdev = get_ichdev(substream);
 899         snd_pcm_runtime_t *runtime = substream->runtime;
 900         int dbl = params_rate(hw_params) > 48000;
 901         int err;
 902
 903         if (chip->fix_nocache && ichdev->page_attr_changed) {
 904                 fill_nocache(runtime->dma_area, runtime->dma_bytes, 0); /* clear */
 905                 ichdev->page_attr_changed = 0;
 906         }
 907         err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
 908         if (err < 0)
 909                 return err;
 910         if (chip->fix_nocache) {
 911                 if (runtime->dma_area && ! ichdev->page_attr_changed) {
 912                         fill_nocache(runtime->dma_area, runtime->dma_bytes, 1);
 913                         ichdev->page_attr_changed = 1;
 914                 }
 915         }
 916         if (ichdev->pcm_open_flag) {
 917                 snd_ac97_pcm_close(ichdev->pcm);
 918                 ichdev->pcm_open_flag = 0;
 919         }
 920         err = snd_ac97_pcm_open(ichdev->pcm, params_rate(hw_params),
 921                                 params_channels(hw_params),
 922                                 ichdev->pcm->r[dbl].slots);
 923         if (err >= 0) {
 924                 ichdev->pcm_open_flag = 1;
 925                 /* Force SPDIF setting */
 926                 if (ichdev->ichd == ICHD_PCMOUT && chip->spdif_idx < 0)
 927                         snd_ac97_set_rate(ichdev->pcm->r[0].codec[0], AC97_SPDIF, params_rate(hw_params));
 928         }
 929         return err;
 930 }
 931
 932 static int snd_intel8x0_hw_free(snd_pcm_substream_t * substream)
 933 {
 934         intel8x0_t *chip = snd_pcm_substream_chip(substream);
 935         ichdev_t *ichdev = get_ichdev(substream);
 936
 937         if (ichdev->pcm_open_flag) {
 938                 snd_ac97_pcm_close(ichdev->pcm);
 939                 ichdev->pcm_open_flag = 0;
 940         }
 941         if (chip->fix_nocache && ichdev->page_attr_changed) {
 942                 fill_nocache(substream->runtime->dma_area, substream->runtime->dma_bytes, 0);
 943                 ichdev->page_attr_changed = 0;
 944         }
 945         return snd_pcm_lib_free_pages(substream);
 946 }
 947
 948 static void snd_intel8x0_setup_pcm_out(intel8x0_t *chip,
 949                                        snd_pcm_runtime_t *runtime)
 950 {
 951         unsigned int cnt;
 952         int dbl = runtime->rate > 48000;
 953
 954         spin_lock_irq(&chip->reg_lock);
 955         switch (chip->device_type) {
 956         case DEVICE_ALI:
 957                 cnt = igetdword(chip, ICHREG(ALI_SCR));
 958                 cnt &= ~ICH_ALI_SC_PCM_246_MASK;
 959                 if (runtime->channels == 4 || dbl)
 960                         cnt |= ICH_ALI_SC_PCM_4;
 961                 else if (runtime->channels == 6)
 962                         cnt |= ICH_ALI_SC_PCM_6;
 963                 iputdword(chip, ICHREG(ALI_SCR), cnt);
 964                 break;
 965         case DEVICE_SIS:
 966                 cnt = igetdword(chip, ICHREG(GLOB_CNT));
 967                 cnt &= ~ICH_SIS_PCM_246_MASK;
 968                 if (runtime->channels == 4 || dbl)
 969                         cnt |= ICH_SIS_PCM_4;
 970                 else if (runtime->channels == 6)
 971                         cnt |= ICH_SIS_PCM_6;
 972                 iputdword(chip, ICHREG(GLOB_CNT), cnt);
 973                 break;
 974         default:
 975                 cnt = igetdword(chip, ICHREG(GLOB_CNT));
 976                 cnt &= ~(ICH_PCM_246_MASK | ICH_PCM_20BIT);
 977                 if (runtime->channels == 4 || dbl)
 978                         cnt |= ICH_PCM_4;
 979                 else if (runtime->channels == 6)
 980                         cnt |= ICH_PCM_6;
 981                 if (chip->device_type == DEVICE_NFORCE) {
 982                         /* reset to 2ch once to keep the 6 channel data in alignment,
 983                          * to start from Front Left always
 984                          */
 985                         if (cnt & ICH_PCM_246_MASK) {
 986                                 iputdword(chip, ICHREG(GLOB_CNT), cnt & ~ICH_PCM_246_MASK);
 987                                 spin_unlock_irq(&chip->reg_lock);
 988                                 msleep(50); /* grrr... */
 989                                 spin_lock_irq(&chip->reg_lock);
 990                         }
 991                 } else if (chip->device_type == DEVICE_INTEL_ICH4) {
 992                         if (runtime->sample_bits > 16)
 993                                 cnt |= ICH_PCM_20BIT;
 994                 }
 995                 iputdword(chip, ICHREG(GLOB_CNT), cnt);
 996                 break;
 997         }
 998         spin_unlock_irq(&chip->reg_lock);
 999 }
1000
1001 static int snd_intel8x0_pcm_prepare(snd_pcm_substream_t * substream)
1002 {
1003         intel8x0_t *chip = snd_pcm_substream_chip(substream);
1004         snd_pcm_runtime_t *runtime = substream->runtime;
1005         ichdev_t *ichdev = get_ichdev(substream);
1006
1007         ichdev->physbuf = runtime->dma_addr;
1008         ichdev->size = snd_pcm_lib_buffer_bytes(substream);
1009         ichdev->fragsize = snd_pcm_lib_period_bytes(substream);
1010         if (ichdev->ichd == ICHD_PCMOUT) {
1011                 snd_intel8x0_setup_pcm_out(chip, runtime);
1012                 if (chip->device_type == DEVICE_INTEL_ICH4)
1013                         ichdev->pos_shift = (runtime->sample_bits > 16) ? 2 : 1;
1014         }
1015         snd_intel8x0_setup_periods(chip, ichdev);
1016         return 0;
1017 }
1018
1019 static snd_pcm_uframes_t snd_intel8x0_pcm_pointer(snd_pcm_substream_t * substream)
1020 {
1021         intel8x0_t *chip = snd_pcm_substream_chip(substream);
1022         ichdev_t *ichdev = get_ichdev(substream);
1023         size_t ptr1, ptr;
1024         int civ, timeout = 100;
1025         unsigned int position;
1026
1027         spin_lock(&chip->reg_lock);
1028         do {
1029                 civ = igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV);
1030                 ptr1 = igetword(chip, ichdev->reg_offset + ichdev->roff_picb);
1031                 position = ichdev->position;
1032                 if (ptr1 == 0) {
1033                         udelay(10);
1034                         continue;
1035                 }
1036                 if (civ == igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV) &&
1037                     ptr1 == igetword(chip, ichdev->reg_offset + ichdev->roff_picb))
1038                         break;
1039         } while (timeout--);
1040         ptr1 <<= ichdev->pos_shift;
1041         ptr = ichdev->fragsize1 - ptr1;
1042         ptr += position;
1043         spin_unlock(&chip->reg_lock);
1044         if (ptr >= ichdev->size)
1045                 return 0;
1046         return bytes_to_frames(substream->runtime, ptr);
1047 }
1048
1049 static snd_pcm_hardware_t snd_intel8x0_stream =
1050 {
1051         .info =                 (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1052                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
1053                                  SNDRV_PCM_INFO_MMAP_VALID |
1054                                  SNDRV_PCM_INFO_PAUSE |
1055                                  SNDRV_PCM_INFO_RESUME),
1056         .formats =              SNDRV_PCM_FMTBIT_S16_LE,
1057         .rates =                SNDRV_PCM_RATE_48000,
1058         .rate_min =             48000,
1059         .rate_max =             48000,
1060         .channels_min =         2,
1061         .channels_max =         2,
1062         .buffer_bytes_max =     128 * 1024,
1063         .period_bytes_min =     32,
1064         .period_bytes_max =     128 * 1024,
1065         .periods_min =          1,
1066         .periods_max =          1024,
1067         .fifo_size =            0,
1068 };
1069
1070 static unsigned int channels4[] = {
1071         2, 4,
1072 };
1073
1074 static snd_pcm_hw_constraint_list_t hw_constraints_channels4 = {
1075         .count = ARRAY_SIZE(channels4),
1076         .list = channels4,
1077         .mask = 0,
1078 };
1079
1080 static unsigned int channels6[] = {
1081         2, 4, 6,
1082 };
1083
1084 static snd_pcm_hw_constraint_list_t hw_constraints_channels6 = {
1085         .count = ARRAY_SIZE(channels6),
1086         .list = channels6,
1087         .mask = 0,
1088 };
1089
1090 static int snd_intel8x0_pcm_open(snd_pcm_substream_t * substream, ichdev_t *ichdev)
1091 {
1092         intel8x0_t *chip = snd_pcm_substream_chip(substream);
1093         snd_pcm_runtime_t *runtime = substream->runtime;
1094         int err;
1095
1096         ichdev->substream = substream;
1097         runtime->hw = snd_intel8x0_stream;
1098         runtime->hw.rates = ichdev->pcm->rates;
1099         snd_pcm_limit_hw_rates(runtime);
1100         if (chip->device_type == DEVICE_SIS) {
1101                 runtime->hw.buffer_bytes_max = 64*1024;
1102                 runtime->hw.period_bytes_max = 64*1024;
1103         }
1104         if ((err = snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS)) < 0)
1105                 return err;
1106         runtime->private_data = ichdev;
1107         return 0;
1108 }
1109
1110 static int snd_intel8x0_playback_open(snd_pcm_substream_t * substream)
1111 {
1112         intel8x0_t *chip = snd_pcm_substream_chip(substream);
1113         snd_pcm_runtime_t *runtime = substream->runtime;
1114         int err;
1115
1116         err = snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCMOUT]);
1117         if (err < 0)
1118                 return err;
1119
1120         if (chip->multi6) {
1121                 runtime->hw.channels_max = 6;
1122                 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels6);
1123         } else if (chip->multi4) {
1124                 runtime->hw.channels_max = 4;
1125                 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels4);
1126         }
1127         if (chip->dra) {
1128                 snd_ac97_pcm_double_rate_rules(runtime);
1129         }
1130         if (chip->smp20bit) {
1131                 runtime->hw.formats |= SNDRV_PCM_FMTBIT_S32_LE;
1132                 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 20);
1133         }
1134         return 0;
1135 }
1136
1137 static int snd_intel8x0_playback_close(snd_pcm_substream_t * substream)
1138 {
1139         intel8x0_t *chip = snd_pcm_substream_chip(substream);
1140
1141         chip->ichd[ICHD_PCMOUT].substream = NULL;
1142         return 0;
1143 }
1144
1145 static int snd_intel8x0_capture_open(snd_pcm_substream_t * substream)
1146 {
1147         intel8x0_t *chip = snd_pcm_substream_chip(substream);
1148
1149         return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCMIN]);
1150 }
1151
1152 static int snd_intel8x0_capture_close(snd_pcm_substream_t * substream)
1153 {
1154         intel8x0_t *chip = snd_pcm_substream_chip(substream);
1155
1156         chip->ichd[ICHD_PCMIN].substream = NULL;
1157         return 0;
1158 }
1159
1160 static int snd_intel8x0_mic_open(snd_pcm_substream_t * substream)
1161 {
1162         intel8x0_t *chip = snd_pcm_substream_chip(substream);
1163
1164         return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_MIC]);
1165 }
1166
1167 static int snd_intel8x0_mic_close(snd_pcm_substream_t * substream)
1168 {
1169         intel8x0_t *chip = snd_pcm_substream_chip(substream);
1170
1171         chip->ichd[ICHD_MIC].substream = NULL;
1172         return 0;
1173 }
1174
1175 static int snd_intel8x0_mic2_open(snd_pcm_substream_t * substream)
1176 {
1177         intel8x0_t *chip = snd_pcm_substream_chip(substream);
1178
1179         return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_MIC2]);
1180 }
1181
1182 static int snd_intel8x0_mic2_close(snd_pcm_substream_t * substream)
1183 {
1184         intel8x0_t *chip = snd_pcm_substream_chip(substream);
1185
1186         chip->ichd[ICHD_MIC2].substream = NULL;
1187         return 0;
1188 }
1189
1190 static int snd_intel8x0_capture2_open(snd_pcm_substream_t * substream)
1191 {
1192         intel8x0_t *chip = snd_pcm_substream_chip(substream);
1193
1194         return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCM2IN]);
1195 }
1196
1197 static int snd_intel8x0_capture2_close(snd_pcm_substream_t * substream)
1198 {
1199         intel8x0_t *chip = snd_pcm_substream_chip(substream);
1200
1201         chip->ichd[ICHD_PCM2IN].substream = NULL;
1202         return 0;
1203 }
1204
1205 static int snd_intel8x0_spdif_open(snd_pcm_substream_t * substream)
1206 {
1207         intel8x0_t *chip = snd_pcm_substream_chip(substream);
1208         int idx = chip->device_type == DEVICE_NFORCE ? NVD_SPBAR : ICHD_SPBAR;
1209
1210         return snd_intel8x0_pcm_open(substream, &chip->ichd[idx]);
1211 }
1212
1213 static int snd_intel8x0_spdif_close(snd_pcm_substream_t * substream)
1214 {
1215         intel8x0_t *chip = snd_pcm_substream_chip(substream);
1216         int idx = chip->device_type == DEVICE_NFORCE ? NVD_SPBAR : ICHD_SPBAR;
1217
1218         chip->ichd[idx].substream = NULL;
1219         return 0;
1220 }
1221
1222 static int snd_intel8x0_ali_ac97spdifout_open(snd_pcm_substream_t * substream)
1223 {
1224         intel8x0_t *chip = snd_pcm_substream_chip(substream);
1225         unsigned int val;
1226
1227         spin_lock_irq(&chip->reg_lock);
1228         val = igetdword(chip, ICHREG(ALI_INTERFACECR));
1229         val |= ICH_ALI_IF_AC97SP;
1230         iputdword(chip, ICHREG(ALI_INTERFACECR), val);
1231         /* also needs to set ALI_SC_CODEC_SPDF correctly */
1232         spin_unlock_irq(&chip->reg_lock);
1233
1234         return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_AC97SPDIFOUT]);
1235 }
1236
1237 static int snd_intel8x0_ali_ac97spdifout_close(snd_pcm_substream_t * substream)
1238 {
1239         intel8x0_t *chip = snd_pcm_substream_chip(substream);
1240         unsigned int val;
1241
1242         chip->ichd[ALID_AC97SPDIFOUT].substream = NULL;
1243         spin_lock_irq(&chip->reg_lock);
1244         val = igetdword(chip, ICHREG(ALI_INTERFACECR));
1245         val &= ~ICH_ALI_IF_AC97SP;
1246         iputdword(chip, ICHREG(ALI_INTERFACECR), val);
1247         spin_unlock_irq(&chip->reg_lock);
1248
1249         return 0;
1250 }
1251
1252 static int snd_intel8x0_ali_spdifin_open(snd_pcm_substream_t * substream)
1253 {
1254         intel8x0_t *chip = snd_pcm_substream_chip(substream);
1255
1256         return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_SPDIFIN]);
1257 }
1258
1259 static int snd_intel8x0_ali_spdifin_close(snd_pcm_substream_t * substream)
1260 {
1261         intel8x0_t *chip = snd_pcm_substream_chip(substream);
1262
1263         chip->ichd[ALID_SPDIFIN].substream = NULL;
1264         return 0;
1265 }
1266
1267 #if 0 // NYI
1268 static int snd_intel8x0_ali_spdifout_open(snd_pcm_substream_t * substream)
1269 {
1270         intel8x0_t *chip = snd_pcm_substream_chip(substream);
1271
1272         return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_SPDIFOUT]);
1273 }
1274
1275 static int snd_intel8x0_ali_spdifout_close(snd_pcm_substream_t * substream)
1276 {
1277         intel8x0_t *chip = snd_pcm_substream_chip(substream);
1278
1279         chip->ichd[ALID_SPDIFOUT].substream = NULL;
1280         return 0;
1281 }
1282 #endif
1283
1284 static snd_pcm_ops_t snd_intel8x0_playback_ops = {
1285         .open =         snd_intel8x0_playback_open,
1286         .close =        snd_intel8x0_playback_close,
1287         .ioctl =        snd_pcm_lib_ioctl,
1288         .hw_params =    snd_intel8x0_hw_params,
1289         .hw_free =      snd_intel8x0_hw_free,
1290         .prepare =      snd_intel8x0_pcm_prepare,
1291         .trigger =      snd_intel8x0_pcm_trigger,
1292         .pointer =      snd_intel8x0_pcm_pointer,
1293 };
1294
1295 static snd_pcm_ops_t snd_intel8x0_capture_ops = {
1296         .open =         snd_intel8x0_capture_open,
1297         .close =        snd_intel8x0_capture_close,
1298         .ioctl =        snd_pcm_lib_ioctl,
1299         .hw_params =    snd_intel8x0_hw_params,
1300         .hw_free =      snd_intel8x0_hw_free,
1301         .prepare =      snd_intel8x0_pcm_prepare,
1302         .trigger =      snd_intel8x0_pcm_trigger,
1303         .pointer =      snd_intel8x0_pcm_pointer,
1304 };
1305
1306 static snd_pcm_ops_t snd_intel8x0_capture_mic_ops = {
1307         .open =         snd_intel8x0_mic_open,
1308         .close =        snd_intel8x0_mic_close,
1309         .ioctl =        snd_pcm_lib_ioctl,
1310         .hw_params =    snd_intel8x0_hw_params,
1311         .hw_free =      snd_intel8x0_hw_free,
1312         .prepare =      snd_intel8x0_pcm_prepare,
1313         .trigger =      snd_intel8x0_pcm_trigger,
1314         .pointer =      snd_intel8x0_pcm_pointer,
1315 };
1316
1317 static snd_pcm_ops_t snd_intel8x0_capture_mic2_ops = {
1318         .open =         snd_intel8x0_mic2_open,
1319         .close =        snd_intel8x0_mic2_close,
1320         .ioctl =        snd_pcm_lib_ioctl,
1321         .hw_params =    snd_intel8x0_hw_params,
1322         .hw_free =      snd_intel8x0_hw_free,
1323         .prepare =      snd_intel8x0_pcm_prepare,
1324         .trigger =      snd_intel8x0_pcm_trigger,
1325         .pointer =      snd_intel8x0_pcm_pointer,
1326 };
1327
1328 static snd_pcm_ops_t snd_intel8x0_capture2_ops = {
1329         .open =         snd_intel8x0_capture2_open,
1330         .close =        snd_intel8x0_capture2_close,
1331         .ioctl =        snd_pcm_lib_ioctl,
1332         .hw_params =    snd_intel8x0_hw_params,
1333         .hw_free =      snd_intel8x0_hw_free,
1334         .prepare =      snd_intel8x0_pcm_prepare,
1335         .trigger =      snd_intel8x0_pcm_trigger,
1336         .pointer =      snd_intel8x0_pcm_pointer,
1337 };
1338
1339 static snd_pcm_ops_t snd_intel8x0_spdif_ops = {
1340         .open =         snd_intel8x0_spdif_open,
1341         .close =        snd_intel8x0_spdif_close,
1342         .ioctl =        snd_pcm_lib_ioctl,
1343         .hw_params =    snd_intel8x0_hw_params,
1344         .hw_free =      snd_intel8x0_hw_free,
1345         .prepare =      snd_intel8x0_pcm_prepare,
1346         .trigger =      snd_intel8x0_pcm_trigger,
1347         .pointer =      snd_intel8x0_pcm_pointer,
1348 };
1349
1350 static snd_pcm_ops_t snd_intel8x0_ali_playback_ops = {
1351         .open =         snd_intel8x0_playback_open,
1352         .close =        snd_intel8x0_playback_close,
1353         .ioctl =        snd_pcm_lib_ioctl,
1354         .hw_params =    snd_intel8x0_hw_params,
1355         .hw_free =      snd_intel8x0_hw_free,
1356         .prepare =      snd_intel8x0_pcm_prepare,
1357         .trigger =      snd_intel8x0_ali_trigger,
1358         .pointer =      snd_intel8x0_pcm_pointer,
1359 };
1360
1361 static snd_pcm_ops_t snd_intel8x0_ali_capture_ops = {
1362         .open =         snd_intel8x0_capture_open,
1363         .close =        snd_intel8x0_capture_close,
1364         .ioctl =        snd_pcm_lib_ioctl,
1365         .hw_params =    snd_intel8x0_hw_params,
1366         .hw_free =      snd_intel8x0_hw_free,
1367         .prepare =      snd_intel8x0_pcm_prepare,
1368         .trigger =      snd_intel8x0_ali_trigger,
1369         .pointer =      snd_intel8x0_pcm_pointer,
1370 };
1371
1372 static snd_pcm_ops_t snd_intel8x0_ali_capture_mic_ops = {
1373         .open =         snd_intel8x0_mic_open,
1374         .close =        snd_intel8x0_mic_close,
1375         .ioctl =        snd_pcm_lib_ioctl,
1376         .hw_params =    snd_intel8x0_hw_params,
1377         .hw_free =      snd_intel8x0_hw_free,
1378         .prepare =      snd_intel8x0_pcm_prepare,
1379         .trigger =      snd_intel8x0_ali_trigger,
1380         .pointer =      snd_intel8x0_pcm_pointer,
1381 };
1382
1383 static snd_pcm_ops_t snd_intel8x0_ali_ac97spdifout_ops = {
1384         .open =         snd_intel8x0_ali_ac97spdifout_open,
1385         .close =        snd_intel8x0_ali_ac97spdifout_close,
1386         .ioctl =        snd_pcm_lib_ioctl,
1387         .hw_params =    snd_intel8x0_hw_params,
1388         .hw_free =      snd_intel8x0_hw_free,
1389         .prepare =      snd_intel8x0_pcm_prepare,
1390         .trigger =      snd_intel8x0_ali_trigger,
1391         .pointer =      snd_intel8x0_pcm_pointer,
1392 };
1393
1394 static snd_pcm_ops_t snd_intel8x0_ali_spdifin_ops = {
1395         .open =         snd_intel8x0_ali_spdifin_open,
1396         .close =        snd_intel8x0_ali_spdifin_close,
1397         .ioctl =        snd_pcm_lib_ioctl,
1398         .hw_params =    snd_intel8x0_hw_params,
1399         .hw_free =      snd_intel8x0_hw_free,
1400         .prepare =      snd_intel8x0_pcm_prepare,
1401         .trigger =      snd_intel8x0_pcm_trigger,
1402         .pointer =      snd_intel8x0_pcm_pointer,
1403 };
1404
1405 #if 0 // NYI
1406 static snd_pcm_ops_t snd_intel8x0_ali_spdifout_ops = {
1407         .open =         snd_intel8x0_ali_spdifout_open,
1408         .close =        snd_intel8x0_ali_spdifout_close,
1409         .ioctl =        snd_pcm_lib_ioctl,
1410         .hw_params =    snd_intel8x0_hw_params,
1411         .hw_free =      snd_intel8x0_hw_free,
1412         .prepare =      snd_intel8x0_pcm_prepare,
1413         .trigger =      snd_intel8x0_pcm_trigger,
1414         .pointer =      snd_intel8x0_pcm_pointer,
1415 };
1416 #endif // NYI
1417
1418 struct ich_pcm_table {
1419         char *suffix;
1420         snd_pcm_ops_t *playback_ops;
1421         snd_pcm_ops_t *capture_ops;
1422         size_t prealloc_size;
1423         size_t prealloc_max_size;
1424         int ac97_idx;
1425 };
1426
1427 static int __devinit snd_intel8x0_pcm1(intel8x0_t *chip, int device, struct ich_pcm_table *rec)
1428 {
1429         snd_pcm_t *pcm;
1430         int err;
1431         char name[32];
1432
1433         if (rec->suffix)
1434                 sprintf(name, "Intel ICH - %s", rec->suffix);
1435         else
1436                 strcpy(name, "Intel ICH");
1437         err = snd_pcm_new(chip->card, name, device,
1438                           rec->playback_ops ? 1 : 0,
1439                           rec->capture_ops ? 1 : 0, &pcm);
1440         if (err < 0)
1441                 return err;
1442
1443         if (rec->playback_ops)
1444                 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, rec->playback_ops);
1445         if (rec->capture_ops)
1446                 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, rec->capture_ops);
1447
1448         pcm->private_data = chip;
1449         pcm->info_flags = 0;
1450         if (rec->suffix)
1451                 sprintf(pcm->name, "%s - %s", chip->card->shortname, rec->suffix);
1452         else
1453                 strcpy(pcm->name, chip->card->shortname);
1454         chip->pcm[device] = pcm;
1455
1456         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(chip->pci),
1457                                               rec->prealloc_size, rec->prealloc_max_size);
1458
1459         return 0;
1460 }
1461
1462 static struct ich_pcm_table intel_pcms[] __devinitdata = {
1463         {
1464                 .playback_ops = &snd_intel8x0_playback_ops,
1465                 .capture_ops = &snd_intel8x0_capture_ops,
1466                 .prealloc_size = 64 * 1024,
1467                 .prealloc_max_size = 128 * 1024,
1468         },
1469         {
1470                 .suffix = "MIC ADC",
1471                 .capture_ops = &snd_intel8x0_capture_mic_ops,
1472                 .prealloc_size = 0,
1473                 .prealloc_max_size = 128 * 1024,
1474                 .ac97_idx = ICHD_MIC,
1475         },
1476         {
1477                 .suffix = "MIC2 ADC",
1478                 .capture_ops = &snd_intel8x0_capture_mic2_ops,
1479                 .prealloc_size = 0,
1480                 .prealloc_max_size = 128 * 1024,
1481                 .ac97_idx = ICHD_MIC2,
1482         },
1483         {
1484                 .suffix = "ADC2",
1485                 .capture_ops = &snd_intel8x0_capture2_ops,
1486                 .prealloc_size = 0,
1487                 .prealloc_max_size = 128 * 1024,
1488                 .ac97_idx = ICHD_PCM2IN,
1489         },
1490         {
1491                 .suffix = "IEC958",
1492                 .playback_ops = &snd_intel8x0_spdif_ops,
1493                 .prealloc_size = 64 * 1024,
1494                 .prealloc_max_size = 128 * 1024,
1495                 .ac97_idx = ICHD_SPBAR,
1496         },
1497 };
1498
1499 static struct ich_pcm_table nforce_pcms[] __devinitdata = {
1500         {
1501                 .playback_ops = &snd_intel8x0_playback_ops,
1502                 .capture_ops = &snd_intel8x0_capture_ops,
1503                 .prealloc_size = 64 * 1024,
1504                 .prealloc_max_size = 128 * 1024,
1505         },
1506         {
1507                 .suffix = "MIC ADC",
1508                 .capture_ops = &snd_intel8x0_capture_mic_ops,
1509                 .prealloc_size = 0,
1510                 .prealloc_max_size = 128 * 1024,
1511                 .ac97_idx = NVD_MIC,
1512         },
1513         {
1514                 .suffix = "IEC958",
1515                 .playback_ops = &snd_intel8x0_spdif_ops,
1516                 .prealloc_size = 64 * 1024,
1517                 .prealloc_max_size = 128 * 1024,
1518                 .ac97_idx = NVD_SPBAR,
1519         },
1520 };
1521
1522 static struct ich_pcm_table ali_pcms[] __devinitdata = {
1523         {
1524                 .playback_ops = &snd_intel8x0_ali_playback_ops,
1525                 .capture_ops = &snd_intel8x0_ali_capture_ops,
1526                 .prealloc_size = 64 * 1024,
1527                 .prealloc_max_size = 128 * 1024,
1528         },
1529         {
1530                 .suffix = "MIC ADC",
1531                 .capture_ops = &snd_intel8x0_ali_capture_mic_ops,
1532                 .prealloc_size = 0,
1533                 .prealloc_max_size = 128 * 1024,
1534                 .ac97_idx = ALID_MIC,
1535         },
1536         {
1537                 .suffix = "IEC958",
1538                 .playback_ops = &snd_intel8x0_ali_ac97spdifout_ops,
1539                 .capture_ops = &snd_intel8x0_ali_spdifin_ops,
1540                 .prealloc_size = 64 * 1024,
1541                 .prealloc_max_size = 128 * 1024,
1542                 .ac97_idx = ALID_AC97SPDIFOUT,
1543         },
1544 #if 0 // NYI
1545         {
1546                 .suffix = "HW IEC958",
1547                 .playback_ops = &snd_intel8x0_ali_spdifout_ops,
1548                 .prealloc_size = 64 * 1024,
1549                 .prealloc_max_size = 128 * 1024,
1550         },
1551 #endif
1552 };
1553
1554 static int __devinit snd_intel8x0_pcm(intel8x0_t *chip)
1555 {
1556         int i, tblsize, device, err;
1557         struct ich_pcm_table *tbl, *rec;
1558
1559         switch (chip->device_type) {
1560         case DEVICE_INTEL_ICH4:
1561                 tbl = intel_pcms;
1562                 tblsize = ARRAY_SIZE(intel_pcms);
1563                 break;
1564         case DEVICE_NFORCE:
1565                 tbl = nforce_pcms;
1566                 tblsize = ARRAY_SIZE(nforce_pcms);
1567                 break;
1568         case DEVICE_ALI:
1569                 tbl = ali_pcms;
1570                 tblsize = ARRAY_SIZE(ali_pcms);
1571                 break;
1572         default:
1573                 tbl = intel_pcms;
1574                 tblsize = 2;
1575                 break;
1576         }
1577
1578         device = 0;
1579         for (i = 0; i < tblsize; i++) {
1580                 rec = tbl + i;
1581                 if (i > 0 && rec->ac97_idx) {
1582                         /* activate PCM only when associated AC'97 codec */
1583                         if (! chip->ichd[rec->ac97_idx].pcm)
1584                                 continue;
1585                 }
1586                 err = snd_intel8x0_pcm1(chip, device, rec);
1587                 if (err < 0)
1588                         return err;
1589                 device++;
1590         }
1591
1592         chip->pcm_devs = device;
1593         return 0;
1594 }
1595
1596
1597 /*
1598  *  Mixer part
1599  */
1600
1601 static void snd_intel8x0_mixer_free_ac97_bus(ac97_bus_t *bus)
1602 {
1603         intel8x0_t *chip = bus->private_data;
1604         chip->ac97_bus = NULL;
1605 }
1606
1607 static void snd_intel8x0_mixer_free_ac97(ac97_t *ac97)
1608 {
1609         intel8x0_t *chip = ac97->private_data;
1610         chip->ac97[ac97->num] = NULL;
1611 }
1612
1613 static struct ac97_pcm ac97_pcm_defs[] __devinitdata = {
1614         /* front PCM */
1615         {
1616                 .exclusive = 1,
1617                 .r = {  {
1618                                 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1619                                          (1 << AC97_SLOT_PCM_RIGHT) |
1620                                          (1 << AC97_SLOT_PCM_CENTER) |
1621                                          (1 << AC97_SLOT_PCM_SLEFT) |
1622                                          (1 << AC97_SLOT_PCM_SRIGHT) |
1623                                          (1 << AC97_SLOT_LFE)
1624                         },
1625                         {
1626                                 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1627                                          (1 << AC97_SLOT_PCM_RIGHT) |
1628                                          (1 << AC97_SLOT_PCM_LEFT_0) |
1629                                          (1 << AC97_SLOT_PCM_RIGHT_0)
1630                         }
1631                 }
1632         },
1633         /* PCM IN #1 */
1634         {
1635                 .stream = 1,
1636                 .exclusive = 1,
1637                 .r = {  {
1638                                 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1639                                          (1 << AC97_SLOT_PCM_RIGHT)
1640                         }
1641                 }
1642         },
1643         /* MIC IN #1 */
1644         {
1645                 .stream = 1,
1646                 .exclusive = 1,
1647                 .r = {  {
1648                                 .slots = (1 << AC97_SLOT_MIC)
1649                         }
1650                 }
1651         },
1652         /* S/PDIF PCM */
1653         {
1654                 .exclusive = 1,
1655                 .spdif = 1,
1656                 .r = {  {
1657                                 .slots = (1 << AC97_SLOT_SPDIF_LEFT2) |
1658                                          (1 << AC97_SLOT_SPDIF_RIGHT2)
1659                         }
1660                 }
1661         },
1662         /* PCM IN #2 */
1663         {
1664                 .stream = 1,
1665                 .exclusive = 1,
1666                 .r = {  {
1667                                 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1668                                          (1 << AC97_SLOT_PCM_RIGHT)
1669                         }
1670                 }
1671         },
1672         /* MIC IN #2 */
1673         {
1674                 .stream = 1,
1675                 .exclusive = 1,
1676                 .r = {  {
1677                                 .slots = (1 << AC97_SLOT_MIC)
1678                         }
1679                 }
1680         },
1681 };
1682
1683 static struct ac97_quirk ac97_quirks[] __devinitdata = {
1684         {
1685                 .subvendor = 0x0e11,
1686                 .subdevice = 0x008a,
1687                 .name = "Compaq Evo W4000",     /* AD1885 */
1688                 .type = AC97_TUNE_HP_ONLY
1689         },
1690         {
1691                 .subvendor = 0x0e11,
1692                 .subdevice = 0x00b8,
1693                 .name = "Compaq Evo D510C",
1694                 .type = AC97_TUNE_HP_ONLY
1695         },
1696         {
1697                 .subvendor = 0x0e11,
1698                 .subdevice = 0x0860,
1699                 .name = "HP/Compaq nx7010",
1700                 .type = AC97_TUNE_MUTE_LED
1701         },
1702         {
1703                 .subvendor = 0x1014,
1704                 .subdevice = 0x1f00,
1705                 .name = "MS-9128",
1706                 .type = AC97_TUNE_ALC_JACK
1707         },
1708         {
1709                 .subvendor = 0x1014,
1710                 .subdevice = 0x0267,
1711                 .name = "IBM NetVista A30p",    /* AD1981B */
1712                 .type = AC97_TUNE_HP_ONLY
1713         },
1714         {
1715                 .subvendor = 0x1028,
1716                 .subdevice = 0x00d8,
1717                 .name = "Dell Precision 530",   /* AD1885 */
1718                 .type = AC97_TUNE_HP_ONLY
1719         },
1720         {
1721                 .subvendor = 0x1028,
1722                 .subdevice = 0x010d,
1723                 .name = "Dell", /* which model?  AD1885 */
1724                 .type = AC97_TUNE_HP_ONLY
1725         },
1726         {
1727                 .subvendor = 0x1028,
1728                 .subdevice = 0x0126,
1729                 .name = "Dell Optiplex GX260",  /* AD1981A */
1730                 .type = AC97_TUNE_HP_ONLY
1731         },
1732         {
1733                 .subvendor = 0x1028,
1734                 .subdevice = 0x012c,
1735                 .name = "Dell Precision 650",   /* AD1981A */
1736                 .type = AC97_TUNE_HP_ONLY
1737         },
1738         {
1739                 .subvendor = 0x1028,
1740                 .subdevice = 0x012d,
1741                 .name = "Dell Precision 450",   /* AD1981B*/
1742                 .type = AC97_TUNE_HP_ONLY
1743         },
1744         {
1745                 .subvendor = 0x1028,
1746                 .subdevice = 0x0147,
1747                 .name = "Dell", /* which model?  AD1981B*/
1748                 .type = AC97_TUNE_HP_ONLY
1749         },
1750         {
1751                 .subvendor = 0x1028,
1752                 .subdevice = 0x0163,
1753                 .name = "Dell Unknown", /* STAC9750/51 */
1754                 .type = AC97_TUNE_HP_ONLY
1755         },
1756         {
1757                 .subvendor = 0x103c,
1758                 .subdevice = 0x006d,
1759                 .name = "HP zv5000",
1760                 .type = AC97_TUNE_MUTE_LED      /*AD1981B*/
1761         },
1762         {       /* FIXME: which codec? */
1763                 .subvendor = 0x103c,
1764                 .subdevice = 0x00c3,
1765                 .name = "HP xw6000",
1766                 .type = AC97_TUNE_HP_ONLY
1767         },
1768         {
1769                 .subvendor = 0x103c,
1770                 .subdevice = 0x088c,
1771                 .name = "HP nc8000",
1772                 .type = AC97_TUNE_MUTE_LED
1773         },
1774         {
1775                 .subvendor = 0x103c,
1776                 .subdevice = 0x0890,
1777                 .name = "HP nc6000",
1778                 .type = AC97_TUNE_MUTE_LED
1779         },
1780         {
1781                 .subvendor = 0x103c,
1782                 .subdevice = 0x0934,
1783                 .name = "HP nx8220",
1784                 .type = AC97_TUNE_MUTE_LED
1785         },
1786         {
1787                 .subvendor = 0x103c,
1788                 .subdevice = 0x099c,
1789                 .name = "HP nx6110",    /* AD1981B */
1790                 .type = AC97_TUNE_HP_ONLY
1791         },
1792         {
1793                 .subvendor = 0x103c,
1794                 .subdevice = 0x129d,
1795                 .name = "HP xw8000",
1796                 .type = AC97_TUNE_HP_ONLY
1797         },
1798         {
1799                 .subvendor = 0x103c,
1800                 .subdevice = 0x12f1,
1801                 .name = "HP xw8200",    /* AD1981B*/
1802                 .type = AC97_TUNE_HP_ONLY
1803         },
1804         {
1805                 .subvendor = 0x103c,
1806                 .subdevice = 0x12f2,
1807                 .name = "HP xw6200",
1808                 .type = AC97_TUNE_HP_ONLY
1809         },
1810         {
1811                 .subvendor = 0x103c,
1812                 .subdevice = 0x3008,
1813                 .name = "HP xw4200",    /* AD1981B*/
1814                 .type = AC97_TUNE_HP_ONLY
1815         },
1816         {
1817                 .subvendor = 0x104d,
1818                 .subdevice = 0x8197,
1819                 .name = "Sony S1XP",
1820                 .type = AC97_TUNE_INV_EAPD
1821         },
1822         {
1823                 .subvendor = 0x1043,
1824                 .subdevice = 0x80f3,
1825                 .name = "ASUS ICH5/AD1985",
1826                 .type = AC97_TUNE_AD_SHARING
1827         },
1828         {
1829                 .subvendor = 0x10cf,
1830                 .subdevice = 0x11c3,
1831                 .name = "Fujitsu-Siemens E4010",
1832                 .type = AC97_TUNE_HP_ONLY
1833         },
1834         {
1835                 .subvendor = 0x10cf,
1836                 .subdevice = 0x1225,
1837                 .name = "Fujitsu-Siemens T3010",
1838                 .type = AC97_TUNE_HP_ONLY
1839         },
1840         {
1841                 .subvendor = 0x10cf,
1842                 .subdevice = 0x1253,
1843                 .name = "Fujitsu S6210",        /* STAC9750/51 */
1844                 .type = AC97_TUNE_HP_ONLY
1845         },
1846         {
1847                 .subvendor = 0x10cf,
1848                 .subdevice = 0x12ec,
1849                 .name = "Fujitsu-Siemens 4010",
1850                 .type = AC97_TUNE_HP_ONLY
1851         },
1852         {
1853                 .subvendor = 0x10f1,
1854                 .subdevice = 0x2665,
1855                 .name = "Fujitsu-Siemens Celsius",      /* AD1981? */
1856                 .type = AC97_TUNE_HP_ONLY
1857         },
1858         {
1859                 .subvendor = 0x10f1,
1860                 .subdevice = 0x2885,
1861                 .name = "AMD64 Mobo",   /* ALC650 */
1862                 .type = AC97_TUNE_HP_ONLY
1863         },
1864         {
1865                 .subvendor = 0x110a,
1866                 .subdevice = 0x0056,
1867                 .name = "Fujitsu-Siemens Scenic",       /* AD1981? */
1868                 .type = AC97_TUNE_HP_ONLY
1869         },
1870         {
1871                 .subvendor = 0x11d4,
1872                 .subdevice = 0x5375,
1873                 .name = "ADI AD1985 (discrete)",
1874                 .type = AC97_TUNE_HP_ONLY
1875         },
1876         {
1877                 .subvendor = 0x1462,
1878                 .subdevice = 0x5470,
1879                 .name = "MSI P4 ATX 645 Ultra",
1880                 .type = AC97_TUNE_HP_ONLY
1881         },
1882         {
1883                 .subvendor = 0x1734,
1884                 .subdevice = 0x0088,
1885                 .name = "Fujitsu-Siemens D1522",        /* AD1981 */
1886                 .type = AC97_TUNE_HP_ONLY
1887         },
1888         {
1889                 .subvendor = 0x8086,
1890                 .subdevice = 0x2000,
1891                 .mask = 0xfff0,
1892                 .name = "Intel ICH5/AD1985",
1893                 .type = AC97_TUNE_AD_SHARING
1894         },
1895         {
1896                 .subvendor = 0x8086,
1897                 .subdevice = 0x4000,
1898                 .mask = 0xfff0,
1899                 .name = "Intel ICH5/AD1985",
1900                 .type = AC97_TUNE_AD_SHARING
1901         },
1902         {
1903                 .subvendor = 0x8086,
1904                 .subdevice = 0x4856,
1905                 .name = "Intel D845WN (82801BA)",
1906                 .type = AC97_TUNE_SWAP_HP
1907         },
1908         {
1909                 .subvendor = 0x8086,
1910                 .subdevice = 0x4d44,
1911                 .name = "Intel D850EMV2",       /* AD1885 */
1912                 .type = AC97_TUNE_HP_ONLY
1913         },
1914         {
1915                 .subvendor = 0x8086,
1916                 .subdevice = 0x4d56,
1917                 .name = "Intel ICH/AD1885",
1918                 .type = AC97_TUNE_HP_ONLY
1919         },
1920         {
1921                 .subvendor = 0x8086,
1922                 .subdevice = 0x6000,
1923                 .mask = 0xfff0,
1924                 .name = "Intel ICH5/AD1985",
1925                 .type = AC97_TUNE_AD_SHARING
1926         },
1927         {
1928                 .subvendor = 0x8086,
1929                 .subdevice = 0xe000,
1930                 .mask = 0xfff0,
1931                 .name = "Intel ICH5/AD1985",
1932                 .type = AC97_TUNE_AD_SHARING
1933         },
1934 #if 0 /* FIXME: this seems wrong on most boards */
1935         {
1936                 .subvendor = 0x8086,
1937                 .subdevice = 0xa000,
1938                 .mask = 0xfff0,
1939                 .name = "Intel ICH5/AD1985",
1940                 .type = AC97_TUNE_HP_ONLY
1941         },
1942 #endif
1943         { } /* terminator */
1944 };
1945
1946 static int __devinit snd_intel8x0_mixer(intel8x0_t *chip, int ac97_clock, const char *quirk_override)
1947 {
1948         ac97_bus_t *pbus;
1949         ac97_template_t ac97;
1950         int err;
1951         unsigned int i, codecs;
1952         unsigned int glob_sta = 0;
1953         ac97_bus_ops_t *ops;
1954         static ac97_bus_ops_t standard_bus_ops = {
1955                 .write = snd_intel8x0_codec_write,
1956                 .read = snd_intel8x0_codec_read,
1957         };
1958         static ac97_bus_ops_t ali_bus_ops = {
1959                 .write = snd_intel8x0_ali_codec_write,
1960                 .read = snd_intel8x0_ali_codec_read,
1961         };
1962
1963         chip->spdif_idx = -1; /* use PCMOUT (or disabled) */
1964         switch (chip->device_type) {
1965         case DEVICE_NFORCE:
1966                 chip->spdif_idx = NVD_SPBAR;
1967                 break;
1968         case DEVICE_ALI:
1969                 chip->spdif_idx = ALID_AC97SPDIFOUT;
1970                 break;
1971         case DEVICE_INTEL_ICH4:
1972                 chip->spdif_idx = ICHD_SPBAR;
1973                 break;
1974         };
1975
1976         chip->in_ac97_init = 1;
1977
1978         memset(&ac97, 0, sizeof(ac97));
1979         ac97.private_data = chip;
1980         ac97.private_free = snd_intel8x0_mixer_free_ac97;
1981         ac97.scaps = AC97_SCAP_SKIP_MODEM;
1982         if (chip->xbox)
1983                 ac97.scaps |= AC97_SCAP_DETECT_BY_VENDOR;
1984         if (chip->device_type != DEVICE_ALI) {
1985                 glob_sta = igetdword(chip, ICHREG(GLOB_STA));
1986                 ops = &standard_bus_ops;
1987                 if (chip->device_type == DEVICE_INTEL_ICH4) {
1988                         codecs = 0;
1989                         if (glob_sta & ICH_PCR)
1990                                 codecs++;
1991                         if (glob_sta & ICH_SCR)
1992                                 codecs++;
1993                         if (glob_sta & ICH_TCR)
1994                                 codecs++;
1995                         chip->in_sdin_init = 1;
1996                         for (i = 0; i < codecs; i++) {
1997                                 snd_intel8x0_codec_read_test(chip, i);
1998                                 chip->ac97_sdin[i] = igetbyte(chip, ICHREG(SDM)) & ICH_LDI_MASK;
1999                         }
2000                         chip->in_sdin_init = 0;
2001                 } else {
2002                         codecs = glob_sta & ICH_SCR ? 2 : 1;
2003                 }
2004         } else {
2005                 ops = &ali_bus_ops;
2006                 codecs = 1;
2007                 /* detect the secondary codec */
2008                 for (i = 0; i < 100; i++) {
2009                         unsigned int reg = igetdword(chip, ICHREG(ALI_RTSR));
2010                         if (reg & 0x40) {
2011                                 codecs = 2;
2012                                 break;
2013                         }
2014                         iputdword(chip, ICHREG(ALI_RTSR), reg | 0x40);
2015                         udelay(1);
2016                 }
2017         }
2018         if ((err = snd_ac97_bus(chip->card, 0, ops, chip, &pbus)) < 0)
2019                 goto __err;
2020         pbus->private_free = snd_intel8x0_mixer_free_ac97_bus;
2021         if (ac97_clock >= 8000 && ac97_clock <= 48000)
2022                 pbus->clock = ac97_clock;
2023         /* FIXME: my test board doesn't work well with VRA... */
2024         if (chip->device_type == DEVICE_ALI)
2025                 pbus->no_vra = 1;
2026         else
2027                 pbus->dra = 1;
2028         chip->ac97_bus = pbus;
2029
2030         ac97.pci = chip->pci;
2031         for (i = 0; i < codecs; i++) {
2032                 ac97.num = i;
2033                 if ((err = snd_ac97_mixer(pbus, &ac97, &chip->ac97[i])) < 0) {
2034                         if (err != -EACCES)
2035                                 snd_printk(KERN_ERR "Unable to initialize codec #%d\n", i);
2036                         if (i == 0)
2037                                 goto __err;
2038                         continue;
2039                 }
2040         }
2041         /* tune up the primary codec */
2042         snd_ac97_tune_hardware(chip->ac97[0], ac97_quirks, quirk_override);
2043         /* enable separate SDINs for ICH4 */
2044         if (chip->device_type == DEVICE_INTEL_ICH4)
2045                 pbus->isdin = 1;
2046         /* find the available PCM streams */
2047         i = ARRAY_SIZE(ac97_pcm_defs);
2048         if (chip->device_type != DEVICE_INTEL_ICH4)
2049                 i -= 2;         /* do not allocate PCM2IN and MIC2 */
2050         if (chip->spdif_idx < 0)
2051                 i--;            /* do not allocate S/PDIF */
2052         err = snd_ac97_pcm_assign(pbus, i, ac97_pcm_defs);
2053         if (err < 0)
2054                 goto __err;
2055         chip->ichd[ICHD_PCMOUT].pcm = &pbus->pcms[0];
2056         chip->ichd[ICHD_PCMIN].pcm = &pbus->pcms[1];
2057         chip->ichd[ICHD_MIC].pcm = &pbus->pcms[2];
2058         if (chip->spdif_idx >= 0)
2059                 chip->ichd[chip->spdif_idx].pcm = &pbus->pcms[3];
2060         if (chip->device_type == DEVICE_INTEL_ICH4) {
2061                 chip->ichd[ICHD_PCM2IN].pcm = &pbus->pcms[4];
2062                 chip->ichd[ICHD_MIC2].pcm = &pbus->pcms[5];
2063         }
2064         /* enable separate SDINs for ICH4 */
2065         if (chip->device_type == DEVICE_INTEL_ICH4) {
2066                 struct ac97_pcm *pcm = chip->ichd[ICHD_PCM2IN].pcm;
2067                 u8 tmp = igetbyte(chip, ICHREG(SDM));
2068                 tmp &= ~(ICH_DI2L_MASK|ICH_DI1L_MASK);
2069                 if (pcm) {
2070                         tmp |= ICH_SE;  /* steer enable for multiple SDINs */
2071                         tmp |= chip->ac97_sdin[0] << ICH_DI1L_SHIFT;
2072                         for (i = 1; i < 4; i++) {
2073                                 if (pcm->r[0].codec[i]) {
2074                                         tmp |= chip->ac97_sdin[pcm->r[0].codec[1]->num] << ICH_DI2L_SHIFT;
2075                                         break;
2076                                 }
2077                         }
2078                 } else {
2079                         tmp &= ~ICH_SE; /* steer disable */
2080                 }
2081                 iputbyte(chip, ICHREG(SDM), tmp);
2082         }
2083         if (pbus->pcms[0].r[0].slots & (1 << AC97_SLOT_PCM_SLEFT)) {
2084                 chip->multi4 = 1;
2085                 if (pbus->pcms[0].r[0].slots & (1 << AC97_SLOT_LFE))
2086                         chip->multi6 = 1;
2087         }
2088         if (pbus->pcms[0].r[1].rslots[0]) {
2089                 chip->dra = 1;
2090         }
2091         if (chip->device_type == DEVICE_INTEL_ICH4) {
2092                 if ((igetdword(chip, ICHREG(GLOB_STA)) & ICH_SAMPLE_CAP) == ICH_SAMPLE_16_20)
2093                         chip->smp20bit = 1;
2094         }
2095         if (chip->device_type == DEVICE_NFORCE) {
2096                 /* 48kHz only */
2097                 chip->ichd[chip->spdif_idx].pcm->rates = SNDRV_PCM_RATE_48000;
2098         }
2099         if (chip->device_type == DEVICE_INTEL_ICH4) {
2100                 /* use slot 10/11 for SPDIF */
2101                 u32 val;
2102                 val = igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_PCM_SPDIF_MASK;
2103                 val |= ICH_PCM_SPDIF_1011;
2104                 iputdword(chip, ICHREG(GLOB_CNT), val);
2105                 snd_ac97_update_bits(chip->ac97[0], AC97_EXTENDED_STATUS, 0x03 << 4, 0x03 << 4);
2106         }
2107         chip->in_ac97_init = 0;
2108         return 0;
2109
2110  __err:
2111         /* clear the cold-reset bit for the next chance */
2112         if (chip->device_type != DEVICE_ALI)
2113                 iputdword(chip, ICHREG(GLOB_CNT), igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_AC97COLD);
2114         return err;
2115 }
2116
2117
2118 /*
2119  *
2120  */
2121
2122 static void do_ali_reset(intel8x0_t *chip)
2123 {
2124         iputdword(chip, ICHREG(ALI_SCR), ICH_ALI_SC_RESET);
2125         iputdword(chip, ICHREG(ALI_FIFOCR1), 0x83838383);
2126         iputdword(chip, ICHREG(ALI_FIFOCR2), 0x83838383);
2127         iputdword(chip, ICHREG(ALI_FIFOCR3), 0x83838383);
2128         iputdword(chip, ICHREG(ALI_INTERFACECR),
2129                   ICH_ALI_IF_MC|ICH_ALI_IF_PI|ICH_ALI_IF_PO);
2130         iputdword(chip, ICHREG(ALI_INTERRUPTCR), 0x00000000);
2131         iputdword(chip, ICHREG(ALI_INTERRUPTSR), 0x00000000);
2132 }
2133
2134 #define do_delay(chip) do {\
2135         set_current_state(TASK_UNINTERRUPTIBLE);\
2136         schedule_timeout(1);\
2137 } while (0)
2138
2139 static int snd_intel8x0_ich_chip_init(intel8x0_t *chip, int probing)
2140 {
2141         unsigned long end_time;
2142         unsigned int cnt, status, nstatus;
2143
2144         /* put logic to right state */
2145         /* first clear status bits */
2146         status = ICH_RCS | ICH_MCINT | ICH_POINT | ICH_PIINT;
2147         if (chip->device_type == DEVICE_NFORCE)
2148                 status |= ICH_NVSPINT;
2149         cnt = igetdword(chip, ICHREG(GLOB_STA));
2150         iputdword(chip, ICHREG(GLOB_STA), cnt & status);
2151
2152         /* ACLink on, 2 channels */
2153         cnt = igetdword(chip, ICHREG(GLOB_CNT));
2154         cnt &= ~(ICH_ACLINK | ICH_PCM_246_MASK);
2155         /* finish cold or do warm reset */
2156         cnt |= (cnt & ICH_AC97COLD) == 0 ? ICH_AC97COLD : ICH_AC97WARM;
2157         iputdword(chip, ICHREG(GLOB_CNT), cnt);
2158         end_time = (jiffies + (HZ / 4)) + 1;
2159         do {
2160                 if ((igetdword(chip, ICHREG(GLOB_CNT)) & ICH_AC97WARM) == 0)
2161                         goto __ok;
2162                 do_delay(chip);
2163         } while (time_after_eq(end_time, jiffies));
2164         snd_printk("AC'97 warm reset still in progress? [0x%x]\n", igetdword(chip, ICHREG(GLOB_CNT)));
2165         return -EIO;
2166
2167       __ok:
2168         if (probing) {
2169                 /* wait for any codec ready status.
2170                  * Once it becomes ready it should remain ready
2171                  * as long as we do not disable the ac97 link.
2172                  */
2173                 end_time = jiffies + HZ;
2174                 do {
2175                         status = igetdword(chip, ICHREG(GLOB_STA)) & (ICH_PCR | ICH_SCR | ICH_TCR);
2176                         if (status)
2177                                 break;
2178                         do_delay(chip);
2179                 } while (time_after_eq(end_time, jiffies));
2180                 if (! status) {
2181                         /* no codec is found */
2182                         snd_printk(KERN_ERR "codec_ready: codec is not ready [0x%x]\n", igetdword(chip, ICHREG(GLOB_STA)));
2183                         return -EIO;
2184                 }
2185
2186                 if (chip->device_type == DEVICE_INTEL_ICH4)
2187                         /* ICH4 can have three codecs */
2188                         nstatus = ICH_PCR | ICH_SCR | ICH_TCR;
2189                 else
2190                         /* others up to two codecs */
2191                         nstatus = ICH_PCR | ICH_SCR;
2192
2193                 /* wait for other codecs ready status. */
2194                 end_time = jiffies + HZ / 4;
2195                 while (status != nstatus && time_after_eq(end_time, jiffies)) {
2196                         do_delay(chip);
2197                         status |= igetdword(chip, ICHREG(GLOB_STA)) & nstatus;
2198                 }
2199
2200         } else {
2201                 /* resume phase */
2202                 int i;
2203                 status = 0;
2204                 for (i = 0; i < 3; i++)
2205                         if (chip->ac97[i])
2206                                 status |= get_ich_codec_bit(chip, i);
2207                 /* wait until all the probed codecs are ready */
2208                 end_time = jiffies + HZ;
2209                 do {
2210                         nstatus = igetdword(chip, ICHREG(GLOB_STA)) & (ICH_PCR | ICH_SCR | ICH_TCR);
2211                         if (status == nstatus)
2212                                 break;
2213                         do_delay(chip);
2214                 } while (time_after_eq(end_time, jiffies));
2215         }
2216
2217         if (chip->device_type == DEVICE_SIS) {
2218                 /* unmute the output on SIS7012 */
2219                 iputword(chip, 0x4c, igetword(chip, 0x4c) | 1);
2220         }
2221         if (chip->device_type == DEVICE_NFORCE) {
2222                 /* enable SPDIF interrupt */
2223                 unsigned int val;
2224                 pci_read_config_dword(chip->pci, 0x4c, &val);
2225                 val |= 0x1000000;
2226                 pci_write_config_dword(chip->pci, 0x4c, val);
2227         }
2228         return 0;
2229 }
2230
2231 static int snd_intel8x0_ali_chip_init(intel8x0_t *chip, int probing)
2232 {
2233         u32 reg;
2234         int i = 0;
2235
2236         reg = igetdword(chip, ICHREG(ALI_SCR));
2237         if ((reg & 2) == 0)     /* Cold required */
2238                 reg |= 2;
2239         else
2240                 reg |= 1;       /* Warm */
2241         reg &= ~0x80000000;     /* ACLink on */
2242         iputdword(chip, ICHREG(ALI_SCR), reg);
2243
2244         for (i = 0; i < HZ / 2; i++) {
2245                 if (! (igetdword(chip, ICHREG(ALI_INTERRUPTSR)) & ALI_INT_GPIO))
2246                         goto __ok;
2247                 do_delay(chip);
2248         }
2249         snd_printk(KERN_ERR "AC'97 reset failed.\n");
2250         if (probing)
2251                 return -EIO;
2252
2253  __ok:
2254         for (i = 0; i < HZ / 2; i++) {
2255                 reg = igetdword(chip, ICHREG(ALI_RTSR));
2256                 if (reg & 0x80) /* primary codec */
2257                         break;
2258                 iputdword(chip, ICHREG(ALI_RTSR), reg | 0x80);
2259                 do_delay(chip);
2260         }
2261
2262         do_ali_reset(chip);
2263         return 0;
2264 }
2265
2266 static int snd_intel8x0_chip_init(intel8x0_t *chip, int probing)
2267 {
2268         unsigned int i;
2269         int err;
2270
2271         if (chip->device_type != DEVICE_ALI) {
2272                 if ((err = snd_intel8x0_ich_chip_init(chip, probing)) < 0)
2273                         return err;
2274                 iagetword(chip, 0);     /* clear semaphore flag */
2275         } else {
2276                 if ((err = snd_intel8x0_ali_chip_init(chip, probing)) < 0)
2277                         return err;
2278         }
2279
2280         /* disable interrupts */
2281         for (i = 0; i < chip->bdbars_count; i++)
2282                 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00);
2283         /* reset channels */
2284         for (i = 0; i < chip->bdbars_count; i++)
2285                 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS);
2286         /* initialize Buffer Descriptor Lists */
2287         for (i = 0; i < chip->bdbars_count; i++)
2288                 iputdword(chip, ICH_REG_OFF_BDBAR + chip->ichd[i].reg_offset, chip->ichd[i].bdbar_addr);
2289         return 0;
2290 }
2291
2292 static int snd_intel8x0_free(intel8x0_t *chip)
2293 {
2294         unsigned int i;
2295
2296         if (chip->irq < 0)
2297                 goto __hw_end;
2298         /* disable interrupts */
2299         for (i = 0; i < chip->bdbars_count; i++)
2300                 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00);
2301         /* reset channels */
2302         for (i = 0; i < chip->bdbars_count; i++)
2303                 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS);
2304         if (chip->device_type == DEVICE_NFORCE) {
2305                 /* stop the spdif interrupt */
2306                 unsigned int val;
2307                 pci_read_config_dword(chip->pci, 0x4c, &val);
2308                 val &= ~0x1000000;
2309                 pci_write_config_dword(chip->pci, 0x4c, val);
2310         }
2311         /* --- */
2312         synchronize_irq(chip->irq);
2313       __hw_end:
2314         if (chip->irq >= 0)
2315                 free_irq(chip->irq, (void *)chip);
2316         if (chip->bdbars.area) {
2317                 if (chip->fix_nocache)
2318                         fill_nocache(chip->bdbars.area, chip->bdbars.bytes, 0);
2319                 snd_dma_free_pages(&chip->bdbars);
2320         }
2321         if (chip->remap_addr)
2322                 iounmap(chip->remap_addr);
2323         if (chip->remap_bmaddr)
2324                 iounmap(chip->remap_bmaddr);
2325         pci_release_regions(chip->pci);
2326         pci_disable_device(chip->pci);
2327         kfree(chip);
2328         return 0;
2329 }
2330
2331 #ifdef CONFIG_PM
2332 /*
2333  * power management
2334  */
2335 static int intel8x0_suspend(snd_card_t *card, pm_message_t state)
2336 {
2337         intel8x0_t *chip = card->pm_private_data;
2338         int i;
2339
2340         for (i = 0; i < chip->pcm_devs; i++)
2341                 snd_pcm_suspend_all(chip->pcm[i]);
2342         /* clear nocache */
2343         if (chip->fix_nocache) {
2344                 for (i = 0; i < chip->bdbars_count; i++) {
2345                         ichdev_t *ichdev = &chip->ichd[i];
2346                         if (ichdev->substream && ichdev->page_attr_changed) {
2347                                 snd_pcm_runtime_t *runtime = ichdev->substream->runtime;
2348                                 if (runtime->dma_area)
2349                                         fill_nocache(runtime->dma_area, runtime->dma_bytes, 0);
2350                         }
2351                 }
2352         }
2353         for (i = 0; i < 3; i++)
2354                 if (chip->ac97[i])
2355                         snd_ac97_suspend(chip->ac97[i]);
2356         if (chip->device_type == DEVICE_INTEL_ICH4)
2357                 chip->sdm_saved = igetbyte(chip, ICHREG(SDM));
2358
2359         if (chip->irq >= 0)
2360                 free_irq(chip->irq, (void *)chip);
2361         pci_disable_device(chip->pci);
2362         return 0;
2363 }
2364
2365 static int intel8x0_resume(snd_card_t *card)
2366 {
2367         intel8x0_t *chip = card->pm_private_data;
2368         int i;
2369
2370         pci_enable_device(chip->pci);
2371         pci_set_master(chip->pci);
2372         request_irq(chip->irq, snd_intel8x0_interrupt, SA_INTERRUPT|SA_SHIRQ, card->shortname, (void *)chip);
2373         synchronize_irq(chip->irq);
2374         snd_intel8x0_chip_init(chip, 1);
2375
2376         /* re-initialize mixer stuff */
2377         if (chip->device_type == DEVICE_INTEL_ICH4) {
2378                 /* enable separate SDINs for ICH4 */
2379                 iputbyte(chip, ICHREG(SDM), chip->sdm_saved);
2380                 /* use slot 10/11 for SPDIF */
2381                 iputdword(chip, ICHREG(GLOB_CNT),
2382                           (igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_PCM_SPDIF_MASK) |
2383                           ICH_PCM_SPDIF_1011);
2384         }
2385
2386         /* refill nocache */
2387         if (chip->fix_nocache)
2388                 fill_nocache(chip->bdbars.area, chip->bdbars.bytes, 1);
2389
2390         for (i = 0; i < 3; i++)
2391                 if (chip->ac97[i])
2392                         snd_ac97_resume(chip->ac97[i]);
2393
2394         /* refill nocache */
2395         if (chip->fix_nocache) {
2396                 for (i = 0; i < chip->bdbars_count; i++) {
2397                         ichdev_t *ichdev = &chip->ichd[i];
2398                         if (ichdev->substream && ichdev->page_attr_changed) {
2399                                 snd_pcm_runtime_t *runtime = ichdev->substream->runtime;
2400                                 if (runtime->dma_area)
2401                                         fill_nocache(runtime->dma_area, runtime->dma_bytes, 1);
2402                         }
2403                 }
2404         }
2405
2406         /* resume status */
2407         for (i = 0; i < chip->bdbars_count; i++) {
2408                 ichdev_t *ichdev = &chip->ichd[i];
2409                 unsigned long port = ichdev->reg_offset;
2410                 if (! ichdev->substream || ! ichdev->suspended)
2411                         continue;
2412                 if (ichdev->ichd == ICHD_PCMOUT)
2413                         snd_intel8x0_setup_pcm_out(chip, ichdev->substream->runtime);
2414                 iputdword(chip, port + ICH_REG_OFF_BDBAR, ichdev->bdbar_addr);
2415                 iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi);
2416                 iputbyte(chip, port + ICH_REG_OFF_CIV, ichdev->civ);
2417                 iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI);
2418         }
2419
2420         return 0;
2421 }
2422 #endif /* CONFIG_PM */
2423
2424 #define INTEL8X0_TESTBUF_SIZE   32768   /* enough large for one shot */
2425
2426 static void __devinit intel8x0_measure_ac97_clock(intel8x0_t *chip)
2427 {
2428         snd_pcm_substream_t *subs;
2429         ichdev_t *ichdev;
2430         unsigned long port;
2431         unsigned long pos, t;
2432         struct timeval start_time, stop_time;
2433
2434         if (chip->ac97_bus->clock != 48000)
2435                 return; /* specified in module option */
2436
2437         subs = chip->pcm[0]->streams[0].substream;
2438         if (! subs || subs->dma_buffer.bytes < INTEL8X0_TESTBUF_SIZE) {
2439                 snd_printk("no playback buffer allocated - aborting measure ac97 clock\n");
2440                 return;
2441         }
2442         ichdev = &chip->ichd[ICHD_PCMOUT];
2443         ichdev->physbuf = subs->dma_buffer.addr;
2444         ichdev->size = chip->ichd[ICHD_PCMOUT].fragsize = INTEL8X0_TESTBUF_SIZE;
2445         ichdev->substream = NULL; /* don't process interrupts */
2446
2447         /* set rate */
2448         if (snd_ac97_set_rate(chip->ac97[0], AC97_PCM_FRONT_DAC_RATE, 48000) < 0) {
2449                 snd_printk(KERN_ERR "cannot set ac97 rate: clock = %d\n", chip->ac97_bus->clock);
2450                 return;
2451         }
2452         snd_intel8x0_setup_periods(chip, ichdev);
2453         port = ichdev->reg_offset;
2454         spin_lock_irq(&chip->reg_lock);
2455         chip->in_measurement = 1;
2456         /* trigger */
2457         if (chip->device_type != DEVICE_ALI)
2458                 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE | ICH_STARTBM);
2459         else {
2460                 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE);
2461                 iputdword(chip, ICHREG(ALI_DMACR), 1 << ichdev->ali_slot);
2462         }
2463         do_gettimeofday(&start_time);
2464         spin_unlock_irq(&chip->reg_lock);
2465         msleep(50);
2466         spin_lock_irq(&chip->reg_lock);
2467         /* check the position */
2468         pos = ichdev->fragsize1;
2469         pos -= igetword(chip, ichdev->reg_offset + ichdev->roff_picb) << ichdev->pos_shift;
2470         pos += ichdev->position;
2471         chip->in_measurement = 0;
2472         do_gettimeofday(&stop_time);
2473         /* stop */
2474         if (chip->device_type == DEVICE_ALI) {
2475                 iputdword(chip, ICHREG(ALI_DMACR), 1 << (ichdev->ali_slot + 8));
2476                 iputbyte(chip, port + ICH_REG_OFF_CR, 0);
2477                 while (igetbyte(chip, port + ICH_REG_OFF_CR))
2478                         ;
2479         } else {
2480                 iputbyte(chip, port + ICH_REG_OFF_CR, 0);
2481                 while (!(igetbyte(chip, port + ichdev->roff_sr) & ICH_DCH))
2482                         ;
2483         }
2484         iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
2485         spin_unlock_irq(&chip->reg_lock);
2486
2487         t = stop_time.tv_sec - start_time.tv_sec;
2488         t *= 1000000;
2489         t += stop_time.tv_usec - start_time.tv_usec;
2490         printk(KERN_INFO "%s: measured %lu usecs\n", __FUNCTION__, t);
2491         if (t == 0) {
2492                 snd_printk(KERN_ERR "?? calculation error..\n");
2493                 return;
2494         }
2495         pos = (pos / 4) * 1000;
2496         pos = (pos / t) * 1000 + ((pos % t) * 1000) / t;
2497         if (pos < 40000 || pos >= 60000)
2498                 /* abnormal value. hw problem? */
2499                 printk(KERN_INFO "intel8x0: measured clock %ld rejected\n", pos);
2500         else if (pos < 47500 || pos > 48500)
2501                 /* not 48000Hz, tuning the clock.. */
2502                 chip->ac97_bus->clock = (chip->ac97_bus->clock * 48000) / pos;
2503         printk(KERN_INFO "intel8x0: clocking to %d\n", chip->ac97_bus->clock);
2504 }
2505
2506 static void snd_intel8x0_proc_read(snd_info_entry_t * entry,
2507                                    snd_info_buffer_t * buffer)
2508 {
2509         intel8x0_t *chip = entry->private_data;
2510         unsigned int tmp;
2511
2512         snd_iprintf(buffer, "Intel8x0\n\n");
2513         if (chip->device_type == DEVICE_ALI)
2514                 return;
2515         tmp = igetdword(chip, ICHREG(GLOB_STA));
2516         snd_iprintf(buffer, "Global control        : 0x%08x\n", igetdword(chip, ICHREG(GLOB_CNT)));
2517         snd_iprintf(buffer, "Global status         : 0x%08x\n", tmp);
2518         if (chip->device_type == DEVICE_INTEL_ICH4)
2519                 snd_iprintf(buffer, "SDM                   : 0x%08x\n", igetdword(chip, ICHREG(SDM)));
2520         snd_iprintf(buffer, "AC'97 codecs ready    :%s%s%s%s\n",
2521                         tmp & ICH_PCR ? " primary" : "",
2522                         tmp & ICH_SCR ? " secondary" : "",
2523                         tmp & ICH_TCR ? " tertiary" : "",
2524                         (tmp & (ICH_PCR | ICH_SCR | ICH_TCR)) == 0 ? " none" : "");
2525         if (chip->device_type == DEVICE_INTEL_ICH4)
2526                 snd_iprintf(buffer, "AC'97 codecs SDIN     : %i %i %i\n",
2527                         chip->ac97_sdin[0],
2528                         chip->ac97_sdin[1],
2529                         chip->ac97_sdin[2]);
2530 }
2531
2532 static void __devinit snd_intel8x0_proc_init(intel8x0_t * chip)
2533 {
2534         snd_info_entry_t *entry;
2535
2536         if (! snd_card_proc_new(chip->card, "intel8x0", &entry))
2537                 snd_info_set_text_ops(entry, chip, 1024, snd_intel8x0_proc_read);
2538 }
2539
2540 static int snd_intel8x0_dev_free(snd_device_t *device)
2541 {
2542         intel8x0_t *chip = device->device_data;
2543         return snd_intel8x0_free(chip);
2544 }
2545
2546 struct ich_reg_info {
2547         unsigned int int_sta_mask;
2548         unsigned int offset;
2549 };
2550
2551 static int __devinit snd_intel8x0_create(snd_card_t * card,
2552                                          struct pci_dev *pci,
2553                                          unsigned long device_type,
2554                                          int buggy_sem,
2555                                          intel8x0_t ** r_intel8x0)
2556 {
2557         intel8x0_t *chip;
2558         int err;
2559         unsigned int i;
2560         unsigned int int_sta_masks;
2561         ichdev_t *ichdev;
2562         static snd_device_ops_t ops = {
2563                 .dev_free =     snd_intel8x0_dev_free,
2564         };
2565
2566         static unsigned int bdbars[] = {
2567                 3, /* DEVICE_INTEL */
2568                 6, /* DEVICE_INTEL_ICH4 */
2569                 3, /* DEVICE_SIS */
2570                 6, /* DEVICE_ALI */
2571                 4, /* DEVICE_NFORCE */
2572         };
2573         static struct ich_reg_info intel_regs[6] = {
2574                 { ICH_PIINT, 0 },
2575                 { ICH_POINT, 0x10 },
2576                 { ICH_MCINT, 0x20 },
2577                 { ICH_M2INT, 0x40 },
2578                 { ICH_P2INT, 0x50 },
2579                 { ICH_SPINT, 0x60 },
2580         };
2581         static struct ich_reg_info nforce_regs[4] = {
2582                 { ICH_PIINT, 0 },
2583                 { ICH_POINT, 0x10 },
2584                 { ICH_MCINT, 0x20 },
2585                 { ICH_NVSPINT, 0x70 },
2586         };
2587         static struct ich_reg_info ali_regs[6] = {
2588                 { ALI_INT_PCMIN, 0x40 },
2589                 { ALI_INT_PCMOUT, 0x50 },
2590                 { ALI_INT_MICIN, 0x60 },
2591                 { ALI_INT_CODECSPDIFOUT, 0x70 },
2592                 { ALI_INT_SPDIFIN, 0xa0 },
2593                 { ALI_INT_SPDIFOUT, 0xb0 },
2594         };
2595         struct ich_reg_info *tbl;
2596
2597         *r_intel8x0 = NULL;
2598
2599         if ((err = pci_enable_device(pci)) < 0)
2600                 return err;
2601
2602         chip = kzalloc(sizeof(*chip), GFP_KERNEL);
2603         if (chip == NULL) {
2604                 pci_disable_device(pci);
2605                 return -ENOMEM;
2606         }
2607         spin_lock_init(&chip->reg_lock);
2608         chip->device_type = device_type;
2609         chip->card = card;
2610         chip->pci = pci;
2611         chip->irq = -1;
2612         chip->buggy_semaphore = buggy_sem;
2613
2614         if (pci->vendor == PCI_VENDOR_ID_INTEL &&
2615             pci->device == PCI_DEVICE_ID_INTEL_440MX)
2616                 chip->fix_nocache = 1; /* enable workaround */
2617
2618         /* some Nforce[2] and ICH boards have problems with IRQ handling.
2619          * Needs to return IRQ_HANDLED for unknown irqs.
2620          */
2621         if (device_type == DEVICE_NFORCE)
2622                 chip->buggy_irq = 1;
2623
2624         if ((err = pci_request_regions(pci, card->shortname)) < 0) {
2625                 kfree(chip);
2626                 pci_disable_device(pci);
2627                 return err;
2628         }
2629
2630         if (device_type == DEVICE_ALI) {
2631                 /* ALI5455 has no ac97 region */
2632                 chip->bmaddr = pci_resource_start(pci, 0);
2633                 goto port_inited;
2634         }
2635
2636         if (pci_resource_flags(pci, 2) & IORESOURCE_MEM) {      /* ICH4 and Nforce */
2637                 chip->mmio = 1;
2638                 chip->addr = pci_resource_start(pci, 2);
2639                 chip->remap_addr = ioremap_nocache(chip->addr,
2640                                                    pci_resource_len(pci, 2));
2641                 if (chip->remap_addr == NULL) {
2642                         snd_printk("AC'97 space ioremap problem\n");
2643                         snd_intel8x0_free(chip);
2644                         return -EIO;
2645                 }
2646         } else {
2647                 chip->addr = pci_resource_start(pci, 0);
2648         }
2649         if (pci_resource_flags(pci, 3) & IORESOURCE_MEM) {      /* ICH4 */
2650                 chip->bm_mmio = 1;
2651                 chip->bmaddr = pci_resource_start(pci, 3);
2652                 chip->remap_bmaddr = ioremap_nocache(chip->bmaddr,
2653                                                      pci_resource_len(pci, 3));
2654                 if (chip->remap_bmaddr == NULL) {
2655                         snd_printk("Controller space ioremap problem\n");
2656                         snd_intel8x0_free(chip);
2657                         return -EIO;
2658                 }
2659         } else {
2660                 chip->bmaddr = pci_resource_start(pci, 1);
2661         }
2662
2663  port_inited:
2664         if (request_irq(pci->irq, snd_intel8x0_interrupt, SA_INTERRUPT|SA_SHIRQ, card->shortname, (void *)chip)) {
2665                 snd_printk("unable to grab IRQ %d\n", pci->irq);
2666                 snd_intel8x0_free(chip);
2667                 return -EBUSY;
2668         }
2669         chip->irq = pci->irq;
2670         pci_set_master(pci);
2671         synchronize_irq(chip->irq);
2672
2673         chip->bdbars_count = bdbars[device_type];
2674
2675         /* initialize offsets */
2676         switch (device_type) {
2677         case DEVICE_NFORCE:
2678                 tbl = nforce_regs;
2679                 break;
2680         case DEVICE_ALI:
2681                 tbl = ali_regs;
2682                 break;
2683         default:
2684                 tbl = intel_regs;
2685                 break;
2686         }
2687         for (i = 0; i < chip->bdbars_count; i++) {
2688                 ichdev = &chip->ichd[i];
2689                 ichdev->ichd = i;
2690                 ichdev->reg_offset = tbl[i].offset;
2691                 ichdev->int_sta_mask = tbl[i].int_sta_mask;
2692                 if (device_type == DEVICE_SIS) {
2693                         /* SiS 7012 swaps the registers */
2694                         ichdev->roff_sr = ICH_REG_OFF_PICB;
2695                         ichdev->roff_picb = ICH_REG_OFF_SR;
2696                 } else {
2697                         ichdev->roff_sr = ICH_REG_OFF_SR;
2698                         ichdev->roff_picb = ICH_REG_OFF_PICB;
2699                 }
2700                 if (device_type == DEVICE_ALI)
2701                         ichdev->ali_slot = (ichdev->reg_offset - 0x40) / 0x10;
2702                 /* SIS7012 handles the pcm data in bytes, others are in samples */
2703                 ichdev->pos_shift = (device_type == DEVICE_SIS) ? 0 : 1;
2704         }
2705
2706         /* allocate buffer descriptor lists */
2707         /* the start of each lists must be aligned to 8 bytes */
2708         if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(pci),
2709                                 chip->bdbars_count * sizeof(u32) * ICH_MAX_FRAGS * 2,
2710                                 &chip->bdbars) < 0) {
2711                 snd_intel8x0_free(chip);
2712                 snd_printk(KERN_ERR "intel8x0: cannot allocate buffer descriptors\n");
2713                 return -ENOMEM;
2714         }
2715         /* tables must be aligned to 8 bytes here, but the kernel pages
2716            are much bigger, so we don't care (on i386) */
2717         /* workaround for 440MX */
2718         if (chip->fix_nocache)
2719                 fill_nocache(chip->bdbars.area, chip->bdbars.bytes, 1);
2720         int_sta_masks = 0;
2721         for (i = 0; i < chip->bdbars_count; i++) {
2722                 ichdev = &chip->ichd[i];
2723                 ichdev->bdbar = ((u32 *)chip->bdbars.area) + (i * ICH_MAX_FRAGS * 2);
2724                 ichdev->bdbar_addr = chip->bdbars.addr + (i * sizeof(u32) * ICH_MAX_FRAGS * 2);
2725                 int_sta_masks |= ichdev->int_sta_mask;
2726         }
2727         chip->int_sta_reg = device_type == DEVICE_ALI ? ICH_REG_ALI_INTERRUPTSR : ICH_REG_GLOB_STA;
2728         chip->int_sta_mask = int_sta_masks;
2729
2730         if ((err = snd_intel8x0_chip_init(chip, 1)) < 0) {
2731                 snd_intel8x0_free(chip);
2732                 return err;
2733         }
2734
2735         snd_card_set_pm_callback(card, intel8x0_suspend, intel8x0_resume, chip);
2736
2737         if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
2738                 snd_intel8x0_free(chip);
2739                 return err;
2740         }
2741
2742         snd_card_set_dev(card, &pci->dev);
2743
2744         *r_intel8x0 = chip;
2745         return 0;
2746 }
2747
2748 static struct shortname_table {
2749         unsigned int id;
2750         const char *s;
2751 } shortnames[] __devinitdata = {
2752         { PCI_DEVICE_ID_INTEL_82801AA_5, "Intel 82801AA-ICH" },
2753         { PCI_DEVICE_ID_INTEL_82801AB_5, "Intel 82901AB-ICH0" },
2754         { PCI_DEVICE_ID_INTEL_82801BA_4, "Intel 82801BA-ICH2" },
2755         { PCI_DEVICE_ID_INTEL_440MX, "Intel 440MX" },
2756         { PCI_DEVICE_ID_INTEL_82801CA_5, "Intel 82801CA-ICH3" },
2757         { PCI_DEVICE_ID_INTEL_82801DB_5, "Intel 82801DB-ICH4" },
2758         { PCI_DEVICE_ID_INTEL_82801EB_5, "Intel ICH5" },
2759         { PCI_DEVICE_ID_INTEL_ESB_5, "Intel 6300ESB" },
2760         { PCI_DEVICE_ID_INTEL_ICH6_18, "Intel ICH6" },
2761         { PCI_DEVICE_ID_INTEL_ICH7_20, "Intel ICH7" },
2762         { PCI_DEVICE_ID_INTEL_ESB2_14, "Intel ESB2" },
2763         { PCI_DEVICE_ID_SI_7012, "SiS SI7012" },
2764         { PCI_DEVICE_ID_NVIDIA_MCP1_AUDIO, "NVidia nForce" },
2765         { PCI_DEVICE_ID_NVIDIA_MCP2_AUDIO, "NVidia nForce2" },
2766         { PCI_DEVICE_ID_NVIDIA_MCP3_AUDIO, "NVidia nForce3" },
2767         { PCI_DEVICE_ID_NVIDIA_CK8S_AUDIO, "NVidia CK8S" },
2768         { PCI_DEVICE_ID_NVIDIA_CK804_AUDIO, "NVidia CK804" },
2769         { PCI_DEVICE_ID_NVIDIA_CK8_AUDIO, "NVidia CK8" },
2770         { 0x003a, "NVidia MCP04" },
2771         { 0x746d, "AMD AMD8111" },
2772         { 0x7445, "AMD AMD768" },
2773         { 0x5455, "ALi M5455" },
2774         { 0, NULL },
2775 };
2776
2777 static int __devinit snd_intel8x0_probe(struct pci_dev *pci,
2778                                         const struct pci_device_id *pci_id)
2779 {
2780         snd_card_t *card;
2781         intel8x0_t *chip;
2782         int err;
2783         struct shortname_table *name;
2784
2785         card = snd_card_new(index, id, THIS_MODULE, 0);
2786         if (card == NULL)
2787                 return -ENOMEM;
2788
2789         switch (pci_id->driver_data) {
2790         case DEVICE_NFORCE:
2791                 strcpy(card->driver, "NFORCE");
2792                 break;
2793         case DEVICE_INTEL_ICH4:
2794                 strcpy(card->driver, "ICH4");
2795                 break;
2796         default:
2797                 strcpy(card->driver, "ICH");
2798                 break;
2799         }
2800
2801         strcpy(card->shortname, "Intel ICH");
2802         for (name = shortnames; name->id; name++) {
2803                 if (pci->device == name->id) {
2804                         strcpy(card->shortname, name->s);
2805                         break;
2806                 }
2807         }
2808
2809         if ((err = snd_intel8x0_create(card, pci, pci_id->driver_data,
2810                                        buggy_semaphore, &chip)) < 0) {
2811                 snd_card_free(card);
2812                 return err;
2813         }
2814         if (buggy_irq)
2815                 chip->buggy_irq = 1;
2816         if (xbox)
2817                 chip->xbox = 1;
2818
2819         if ((err = snd_intel8x0_mixer(chip, ac97_clock, ac97_quirk)) < 0) {
2820                 snd_card_free(card);
2821                 return err;
2822         }
2823         if ((err = snd_intel8x0_pcm(chip)) < 0) {
2824                 snd_card_free(card);
2825                 return err;
2826         }
2827
2828         snd_intel8x0_proc_init(chip);
2829
2830         snprintf(card->longname, sizeof(card->longname),
2831                  "%s with %s at %#lx, irq %i", card->shortname,
2832                  snd_ac97_get_short_name(chip->ac97[0]), chip->addr, chip->irq);
2833
2834         if (! ac97_clock)
2835                 intel8x0_measure_ac97_clock(chip);
2836
2837         if ((err = snd_card_register(card)) < 0) {
2838                 snd_card_free(card);
2839                 return err;
2840         }
2841         pci_set_drvdata(pci, card);
2842         return 0;
2843 }
2844
2845 static void __devexit snd_intel8x0_remove(struct pci_dev *pci)
2846 {
2847         snd_card_free(pci_get_drvdata(pci));
2848         pci_set_drvdata(pci, NULL);
2849 }
2850
2851 static struct pci_driver driver = {
2852         .name = "Intel ICH",
2853         .owner = THIS_MODULE,
2854         .id_table = snd_intel8x0_ids,
2855         .probe = snd_intel8x0_probe,
2856         .remove = __devexit_p(snd_intel8x0_remove),
2857         SND_PCI_PM_CALLBACKS
2858 };
2859
2860
2861 static int __init alsa_card_intel8x0_init(void)
2862 {
2863         return pci_register_driver(&driver);
2864 }
2865
2866 static void __exit alsa_card_intel8x0_exit(void)
2867 {
2868         pci_unregister_driver(&driver);
2869 }
2870
2871 module_init(alsa_card_intel8x0_init)
2872 module_exit(alsa_card_intel8x0_exit)