SAFE public projects git trees. - safe/jmp/linux-2.6/blob - sound/pci/hda/hda_intel.c

   1 /*
   2  *
   3  *  hda_intel.c - Implementation of primary alsa driver code base
   4  *                for Intel HD Audio.
   5  *
   6  *  Copyright(c) 2004 Intel Corporation. All rights reserved.
   7  *
   8  *  Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
   9  *                     PeiSen Hou <pshou@realtek.com.tw>
  10  *
  11  *  This program is free software; you can redistribute it and/or modify it
  12  *  under the terms of the GNU General Public License as published by the Free
  13  *  Software Foundation; either version 2 of the License, or (at your option)
  14  *  any later version.
  15  *
  16  *  This program is distributed in the hope that it will be useful, but WITHOUT
  17  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  18  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  19  *  more details.
  20  *
  21  *  You should have received a copy of the GNU General Public License along with
  22  *  this program; if not, write to the Free Software Foundation, Inc., 59
  23  *  Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  24  *
  25  *  CONTACTS:
  26  *
  27  *  Matt Jared          matt.jared@intel.com
  28  *  Andy Kopp           andy.kopp@intel.com
  29  *  Dan Kogan           dan.d.kogan@intel.com
  30  *
  31  *  CHANGES:
  32  *
  33  *  2004.12.01  Major rewrite by tiwai, merged the work of pshou
  34  *
  35  */
  36
  37 #include <asm/io.h>
  38 #include <linux/delay.h>
  39 #include <linux/interrupt.h>
  40 #include <linux/kernel.h>
  41 #include <linux/module.h>
  42 #include <linux/dma-mapping.h>
  43 #include <linux/moduleparam.h>
  44 #include <linux/init.h>
  45 #include <linux/slab.h>
  46 #include <linux/pci.h>
  47 #include <linux/mutex.h>
  48 #include <linux/reboot.h>
  49 #include <sound/core.h>
  50 #include <sound/initval.h>
  51 #include "hda_codec.h"
  52
  53
  54 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
  55 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
  56 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
  57 static char *model[SNDRV_CARDS];
  58 static int position_fix[SNDRV_CARDS];
  59 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
  60 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
  61 static int probe_only[SNDRV_CARDS];
  62 static int single_cmd;
  63 static int enable_msi;
  64
  65 module_param_array(index, int, NULL, 0444);
  66 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
  67 module_param_array(id, charp, NULL, 0444);
  68 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
  69 module_param_array(enable, bool, NULL, 0444);
  70 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
  71 module_param_array(model, charp, NULL, 0444);
  72 MODULE_PARM_DESC(model, "Use the given board model.");
  73 module_param_array(position_fix, int, NULL, 0444);
  74 MODULE_PARM_DESC(position_fix, "Fix DMA pointer "
  75                  "(0 = auto, 1 = none, 2 = POSBUF).");
  76 module_param_array(bdl_pos_adj, int, NULL, 0644);
  77 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
  78 module_param_array(probe_mask, int, NULL, 0444);
  79 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
  80 module_param_array(probe_only, bool, NULL, 0444);
  81 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
  82 module_param(single_cmd, bool, 0444);
  83 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
  84                  "(for debugging only).");
  85 module_param(enable_msi, int, 0444);
  86 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
  87
  88 #ifdef CONFIG_SND_HDA_POWER_SAVE
  89 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
  90 module_param(power_save, int, 0644);
  91 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
  92                  "(in second, 0 = disable).");
  93
  94 /* reset the HD-audio controller in power save mode.
  95  * this may give more power-saving, but will take longer time to
  96  * wake up.
  97  */
  98 static int power_save_controller = 1;
  99 module_param(power_save_controller, bool, 0644);
 100 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
 101 #endif
 102
 103 MODULE_LICENSE("GPL");
 104 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
 105                          "{Intel, ICH6M},"
 106                          "{Intel, ICH7},"
 107                          "{Intel, ESB2},"
 108                          "{Intel, ICH8},"
 109                          "{Intel, ICH9},"
 110                          "{Intel, ICH10},"
 111                          "{Intel, PCH},"
 112                          "{Intel, SCH},"
 113                          "{ATI, SB450},"
 114                          "{ATI, SB600},"
 115                          "{ATI, RS600},"
 116                          "{ATI, RS690},"
 117                          "{ATI, RS780},"
 118                          "{ATI, R600},"
 119                          "{ATI, RV630},"
 120                          "{ATI, RV610},"
 121                          "{ATI, RV670},"
 122                          "{ATI, RV635},"
 123                          "{ATI, RV620},"
 124                          "{ATI, RV770},"
 125                          "{VIA, VT8251},"
 126                          "{VIA, VT8237A},"
 127                          "{SiS, SIS966},"
 128                          "{ULI, M5461}}");
 129 MODULE_DESCRIPTION("Intel HDA driver");
 130
 131 #ifdef CONFIG_SND_VERBOSE_PRINTK
 132 #define SFX     /* nop */
 133 #else
 134 #define SFX     "hda-intel: "
 135 #endif
 136
 137 /*
 138  * registers
 139  */
 140 #define ICH6_REG_GCAP                   0x00
 141 #define ICH6_REG_VMIN                   0x02
 142 #define ICH6_REG_VMAJ                   0x03
 143 #define ICH6_REG_OUTPAY                 0x04
 144 #define ICH6_REG_INPAY                  0x06
 145 #define ICH6_REG_GCTL                   0x08
 146 #define ICH6_REG_WAKEEN                 0x0c
 147 #define ICH6_REG_STATESTS               0x0e
 148 #define ICH6_REG_GSTS                   0x10
 149 #define ICH6_REG_INTCTL                 0x20
 150 #define ICH6_REG_INTSTS                 0x24
 151 #define ICH6_REG_WALCLK                 0x30
 152 #define ICH6_REG_SYNC                   0x34
 153 #define ICH6_REG_CORBLBASE              0x40
 154 #define ICH6_REG_CORBUBASE              0x44
 155 #define ICH6_REG_CORBWP                 0x48
 156 #define ICH6_REG_CORBRP                 0x4A
 157 #define ICH6_REG_CORBCTL                0x4c
 158 #define ICH6_REG_CORBSTS                0x4d
 159 #define ICH6_REG_CORBSIZE               0x4e
 160
 161 #define ICH6_REG_RIRBLBASE              0x50
 162 #define ICH6_REG_RIRBUBASE              0x54
 163 #define ICH6_REG_RIRBWP                 0x58
 164 #define ICH6_REG_RINTCNT                0x5a
 165 #define ICH6_REG_RIRBCTL                0x5c
 166 #define ICH6_REG_RIRBSTS                0x5d
 167 #define ICH6_REG_RIRBSIZE               0x5e
 168
 169 #define ICH6_REG_IC                     0x60
 170 #define ICH6_REG_IR                     0x64
 171 #define ICH6_REG_IRS                    0x68
 172 #define   ICH6_IRS_VALID        (1<<1)
 173 #define   ICH6_IRS_BUSY         (1<<0)
 174
 175 #define ICH6_REG_DPLBASE                0x70
 176 #define ICH6_REG_DPUBASE                0x74
 177 #define   ICH6_DPLBASE_ENABLE   0x1     /* Enable position buffer */
 178
 179 /* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
 180 enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
 181
 182 /* stream register offsets from stream base */
 183 #define ICH6_REG_SD_CTL                 0x00
 184 #define ICH6_REG_SD_STS                 0x03
 185 #define ICH6_REG_SD_LPIB                0x04
 186 #define ICH6_REG_SD_CBL                 0x08
 187 #define ICH6_REG_SD_LVI                 0x0c
 188 #define ICH6_REG_SD_FIFOW               0x0e
 189 #define ICH6_REG_SD_FIFOSIZE            0x10
 190 #define ICH6_REG_SD_FORMAT              0x12
 191 #define ICH6_REG_SD_BDLPL               0x18
 192 #define ICH6_REG_SD_BDLPU               0x1c
 193
 194 /* PCI space */
 195 #define ICH6_PCIREG_TCSEL       0x44
 196
 197 /*
 198  * other constants
 199  */
 200
 201 /* max number of SDs */
 202 /* ICH, ATI and VIA have 4 playback and 4 capture */
 203 #define ICH6_NUM_CAPTURE        4
 204 #define ICH6_NUM_PLAYBACK       4
 205
 206 /* ULI has 6 playback and 5 capture */
 207 #define ULI_NUM_CAPTURE         5
 208 #define ULI_NUM_PLAYBACK        6
 209
 210 /* ATI HDMI has 1 playback and 0 capture */
 211 #define ATIHDMI_NUM_CAPTURE     0
 212 #define ATIHDMI_NUM_PLAYBACK    1
 213
 214 /* TERA has 4 playback and 3 capture */
 215 #define TERA_NUM_CAPTURE        3
 216 #define TERA_NUM_PLAYBACK       4
 217
 218 /* this number is statically defined for simplicity */
 219 #define MAX_AZX_DEV             16
 220
 221 /* max number of fragments - we may use more if allocating more pages for BDL */
 222 #define BDL_SIZE                4096
 223 #define AZX_MAX_BDL_ENTRIES     (BDL_SIZE / 16)
 224 #define AZX_MAX_FRAG            32
 225 /* max buffer size - no h/w limit, you can increase as you like */
 226 #define AZX_MAX_BUF_SIZE        (1024*1024*1024)
 227 /* max number of PCM devics per card */
 228 #define AZX_MAX_PCMS            8
 229
 230 /* RIRB int mask: overrun[2], response[0] */
 231 #define RIRB_INT_RESPONSE       0x01
 232 #define RIRB_INT_OVERRUN        0x04
 233 #define RIRB_INT_MASK           0x05
 234
 235 /* STATESTS int mask: S3,SD2,SD1,SD0 */
 236 #define AZX_MAX_CODECS          4
 237 #define STATESTS_INT_MASK       0x0f
 238
 239 /* SD_CTL bits */
 240 #define SD_CTL_STREAM_RESET     0x01    /* stream reset bit */
 241 #define SD_CTL_DMA_START        0x02    /* stream DMA start bit */
 242 #define SD_CTL_STRIPE           (3 << 16)       /* stripe control */
 243 #define SD_CTL_TRAFFIC_PRIO     (1 << 18)       /* traffic priority */
 244 #define SD_CTL_DIR              (1 << 19)       /* bi-directional stream */
 245 #define SD_CTL_STREAM_TAG_MASK  (0xf << 20)
 246 #define SD_CTL_STREAM_TAG_SHIFT 20
 247
 248 /* SD_CTL and SD_STS */
 249 #define SD_INT_DESC_ERR         0x10    /* descriptor error interrupt */
 250 #define SD_INT_FIFO_ERR         0x08    /* FIFO error interrupt */
 251 #define SD_INT_COMPLETE         0x04    /* completion interrupt */
 252 #define SD_INT_MASK             (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\
 253                                  SD_INT_COMPLETE)
 254
 255 /* SD_STS */
 256 #define SD_STS_FIFO_READY       0x20    /* FIFO ready */
 257
 258 /* INTCTL and INTSTS */
 259 #define ICH6_INT_ALL_STREAM     0xff       /* all stream interrupts */
 260 #define ICH6_INT_CTRL_EN        0x40000000 /* controller interrupt enable bit */
 261 #define ICH6_INT_GLOBAL_EN      0x80000000 /* global interrupt enable bit */
 262
 263 /* GCTL unsolicited response enable bit */
 264 #define ICH6_GCTL_UREN          (1<<8)
 265
 266 /* GCTL reset bit */
 267 #define ICH6_GCTL_RESET         (1<<0)
 268
 269 /* CORB/RIRB control, read/write pointer */
 270 #define ICH6_RBCTL_DMA_EN       0x02    /* enable DMA */
 271 #define ICH6_RBCTL_IRQ_EN       0x01    /* enable IRQ */
 272 #define ICH6_RBRWP_CLR          0x8000  /* read/write pointer clear */
 273 /* below are so far hardcoded - should read registers in future */
 274 #define ICH6_MAX_CORB_ENTRIES   256
 275 #define ICH6_MAX_RIRB_ENTRIES   256
 276
 277 /* position fix mode */
 278 enum {
 279         POS_FIX_AUTO,
 280         POS_FIX_LPIB,
 281         POS_FIX_POSBUF,
 282 };
 283
 284 /* Defines for ATI HD Audio support in SB450 south bridge */
 285 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR   0x42
 286 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP      0x02
 287
 288 /* Defines for Nvidia HDA support */
 289 #define NVIDIA_HDA_TRANSREG_ADDR      0x4e
 290 #define NVIDIA_HDA_ENABLE_COHBITS     0x0f
 291 #define NVIDIA_HDA_ISTRM_COH          0x4d
 292 #define NVIDIA_HDA_OSTRM_COH          0x4c
 293 #define NVIDIA_HDA_ENABLE_COHBIT      0x01
 294
 295 /* Defines for Intel SCH HDA snoop control */
 296 #define INTEL_SCH_HDA_DEVC      0x78
 297 #define INTEL_SCH_HDA_DEVC_NOSNOOP       (0x1<<11)
 298
 299 /* Define IN stream 0 FIFO size offset in VIA controller */
 300 #define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
 301 /* Define VIA HD Audio Device ID*/
 302 #define VIA_HDAC_DEVICE_ID              0x3288
 303
 304 /* HD Audio class code */
 305 #define PCI_CLASS_MULTIMEDIA_HD_AUDIO   0x0403
 306
 307 /*
 308  */
 309
 310 struct azx_dev {
 311         struct snd_dma_buffer bdl; /* BDL buffer */
 312         u32 *posbuf;            /* position buffer pointer */
 313
 314         unsigned int bufsize;   /* size of the play buffer in bytes */
 315         unsigned int period_bytes; /* size of the period in bytes */
 316         unsigned int frags;     /* number for period in the play buffer */
 317         unsigned int fifo_size; /* FIFO size */
 318         unsigned long start_jiffies;    /* start + minimum jiffies */
 319         unsigned long min_jiffies;      /* minimum jiffies before position is valid */
 320
 321         void __iomem *sd_addr;  /* stream descriptor pointer */
 322
 323         u32 sd_int_sta_mask;    /* stream int status mask */
 324
 325         /* pcm support */
 326         struct snd_pcm_substream *substream;    /* assigned substream,
 327                                                  * set in PCM open
 328                                                  */
 329         unsigned int format_val;        /* format value to be set in the
 330                                          * controller and the codec
 331                                          */
 332         unsigned char stream_tag;       /* assigned stream */
 333         unsigned char index;            /* stream index */
 334
 335         unsigned int opened :1;
 336         unsigned int running :1;
 337         unsigned int irq_pending :1;
 338         unsigned int start_flag: 1;     /* stream full start flag */
 339         /*
 340          * For VIA:
 341          *  A flag to ensure DMA position is 0
 342          *  when link position is not greater than FIFO size
 343          */
 344         unsigned int insufficient :1;
 345 };
 346
 347 /* CORB/RIRB */
 348 struct azx_rb {
 349         u32 *buf;               /* CORB/RIRB buffer
 350                                  * Each CORB entry is 4byte, RIRB is 8byte
 351                                  */
 352         dma_addr_t addr;        /* physical address of CORB/RIRB buffer */
 353         /* for RIRB */
 354         unsigned short rp, wp;  /* read/write pointers */
 355         int cmds;               /* number of pending requests */
 356         u32 res;                /* last read value */
 357 };
 358
 359 struct azx {
 360         struct snd_card *card;
 361         struct pci_dev *pci;
 362         int dev_index;
 363
 364         /* chip type specific */
 365         int driver_type;
 366         int playback_streams;
 367         int playback_index_offset;
 368         int capture_streams;
 369         int capture_index_offset;
 370         int num_streams;
 371
 372         /* pci resources */
 373         unsigned long addr;
 374         void __iomem *remap_addr;
 375         int irq;
 376
 377         /* locks */
 378         spinlock_t reg_lock;
 379         struct mutex open_mutex;
 380
 381         /* streams (x num_streams) */
 382         struct azx_dev *azx_dev;
 383
 384         /* PCM */
 385         struct snd_pcm *pcm[AZX_MAX_PCMS];
 386
 387         /* HD codec */
 388         unsigned short codec_mask;
 389         int  codec_probe_mask; /* copied from probe_mask option */
 390         struct hda_bus *bus;
 391
 392         /* CORB/RIRB */
 393         struct azx_rb corb;
 394         struct azx_rb rirb;
 395
 396         /* CORB/RIRB and position buffers */
 397         struct snd_dma_buffer rb;
 398         struct snd_dma_buffer posbuf;
 399
 400         /* flags */
 401         int position_fix;
 402         unsigned int running :1;
 403         unsigned int initialized :1;
 404         unsigned int single_cmd :1;
 405         unsigned int polling_mode :1;
 406         unsigned int msi :1;
 407         unsigned int irq_pending_warned :1;
 408         unsigned int via_dmapos_patch :1; /* enable DMA-position fix for VIA */
 409         unsigned int probing :1; /* codec probing phase */
 410
 411         /* for debugging */
 412         unsigned int last_cmd;  /* last issued command (to sync) */
 413
 414         /* for pending irqs */
 415         struct work_struct irq_pending_work;
 416
 417         /* reboot notifier (for mysterious hangup problem at power-down) */
 418         struct notifier_block reboot_notifier;
 419 };
 420
 421 /* driver types */
 422 enum {
 423         AZX_DRIVER_ICH,
 424         AZX_DRIVER_SCH,
 425         AZX_DRIVER_ATI,
 426         AZX_DRIVER_ATIHDMI,
 427         AZX_DRIVER_VIA,
 428         AZX_DRIVER_SIS,
 429         AZX_DRIVER_ULI,
 430         AZX_DRIVER_NVIDIA,
 431         AZX_DRIVER_TERA,
 432         AZX_DRIVER_GENERIC,
 433         AZX_NUM_DRIVERS, /* keep this as last entry */
 434 };
 435
 436 static char *driver_short_names[] __devinitdata = {
 437         [AZX_DRIVER_ICH] = "HDA Intel",
 438         [AZX_DRIVER_SCH] = "HDA Intel MID",
 439         [AZX_DRIVER_ATI] = "HDA ATI SB",
 440         [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
 441         [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
 442         [AZX_DRIVER_SIS] = "HDA SIS966",
 443         [AZX_DRIVER_ULI] = "HDA ULI M5461",
 444         [AZX_DRIVER_NVIDIA] = "HDA NVidia",
 445         [AZX_DRIVER_TERA] = "HDA Teradici",
 446         [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
 447 };
 448
 449 /*
 450  * macros for easy use
 451  */
 452 #define azx_writel(chip,reg,value) \
 453         writel(value, (chip)->remap_addr + ICH6_REG_##reg)
 454 #define azx_readl(chip,reg) \
 455         readl((chip)->remap_addr + ICH6_REG_##reg)
 456 #define azx_writew(chip,reg,value) \
 457         writew(value, (chip)->remap_addr + ICH6_REG_##reg)
 458 #define azx_readw(chip,reg) \
 459         readw((chip)->remap_addr + ICH6_REG_##reg)
 460 #define azx_writeb(chip,reg,value) \
 461         writeb(value, (chip)->remap_addr + ICH6_REG_##reg)
 462 #define azx_readb(chip,reg) \
 463         readb((chip)->remap_addr + ICH6_REG_##reg)
 464
 465 #define azx_sd_writel(dev,reg,value) \
 466         writel(value, (dev)->sd_addr + ICH6_REG_##reg)
 467 #define azx_sd_readl(dev,reg) \
 468         readl((dev)->sd_addr + ICH6_REG_##reg)
 469 #define azx_sd_writew(dev,reg,value) \
 470         writew(value, (dev)->sd_addr + ICH6_REG_##reg)
 471 #define azx_sd_readw(dev,reg) \
 472         readw((dev)->sd_addr + ICH6_REG_##reg)
 473 #define azx_sd_writeb(dev,reg,value) \
 474         writeb(value, (dev)->sd_addr + ICH6_REG_##reg)
 475 #define azx_sd_readb(dev,reg) \
 476         readb((dev)->sd_addr + ICH6_REG_##reg)
 477
 478 /* for pcm support */
 479 #define get_azx_dev(substream) (substream->runtime->private_data)
 480
 481 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
 482
 483 /*
 484  * Interface for HD codec
 485  */
 486
 487 /*
 488  * CORB / RIRB interface
 489  */
 490 static int azx_alloc_cmd_io(struct azx *chip)
 491 {
 492         int err;
 493
 494         /* single page (at least 4096 bytes) must suffice for both ringbuffes */
 495         err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
 496                                   snd_dma_pci_data(chip->pci),
 497                                   PAGE_SIZE, &chip->rb);
 498         if (err < 0) {
 499                 snd_printk(KERN_ERR SFX "cannot allocate CORB/RIRB\n");
 500                 return err;
 501         }
 502         return 0;
 503 }
 504
 505 static void azx_init_cmd_io(struct azx *chip)
 506 {
 507         /* CORB set up */
 508         chip->corb.addr = chip->rb.addr;
 509         chip->corb.buf = (u32 *)chip->rb.area;
 510         azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
 511         azx_writel(chip, CORBUBASE, upper_32_bits(chip->corb.addr));
 512
 513         /* set the corb size to 256 entries (ULI requires explicitly) */
 514         azx_writeb(chip, CORBSIZE, 0x02);
 515         /* set the corb write pointer to 0 */
 516         azx_writew(chip, CORBWP, 0);
 517         /* reset the corb hw read pointer */
 518         azx_writew(chip, CORBRP, ICH6_RBRWP_CLR);
 519         /* enable corb dma */
 520         azx_writeb(chip, CORBCTL, ICH6_RBCTL_DMA_EN);
 521
 522         /* RIRB set up */
 523         chip->rirb.addr = chip->rb.addr + 2048;
 524         chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
 525         azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
 526         azx_writel(chip, RIRBUBASE, upper_32_bits(chip->rirb.addr));
 527
 528         /* set the rirb size to 256 entries (ULI requires explicitly) */
 529         azx_writeb(chip, RIRBSIZE, 0x02);
 530         /* reset the rirb hw write pointer */
 531         azx_writew(chip, RIRBWP, ICH6_RBRWP_CLR);
 532         /* set N=1, get RIRB response interrupt for new entry */
 533         azx_writew(chip, RINTCNT, 1);
 534         /* enable rirb dma and response irq */
 535         azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN);
 536         chip->rirb.rp = chip->rirb.cmds = 0;
 537 }
 538
 539 static void azx_free_cmd_io(struct azx *chip)
 540 {
 541         /* disable ringbuffer DMAs */
 542         azx_writeb(chip, RIRBCTL, 0);
 543         azx_writeb(chip, CORBCTL, 0);
 544 }
 545
 546 /* send a command */
 547 static int azx_corb_send_cmd(struct hda_bus *bus, u32 val)
 548 {
 549         struct azx *chip = bus->private_data;
 550         unsigned int wp;
 551
 552         /* add command to corb */
 553         wp = azx_readb(chip, CORBWP);
 554         wp++;
 555         wp %= ICH6_MAX_CORB_ENTRIES;
 556
 557         spin_lock_irq(&chip->reg_lock);
 558         chip->rirb.cmds++;
 559         chip->corb.buf[wp] = cpu_to_le32(val);
 560         azx_writel(chip, CORBWP, wp);
 561         spin_unlock_irq(&chip->reg_lock);
 562
 563         return 0;
 564 }
 565
 566 #define ICH6_RIRB_EX_UNSOL_EV   (1<<4)
 567
 568 /* retrieve RIRB entry - called from interrupt handler */
 569 static void azx_update_rirb(struct azx *chip)
 570 {
 571         unsigned int rp, wp;
 572         u32 res, res_ex;
 573
 574         wp = azx_readb(chip, RIRBWP);
 575         if (wp == chip->rirb.wp)
 576                 return;
 577         chip->rirb.wp = wp;
 578
 579         while (chip->rirb.rp != wp) {
 580                 chip->rirb.rp++;
 581                 chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES;
 582
 583                 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
 584                 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
 585                 res = le32_to_cpu(chip->rirb.buf[rp]);
 586                 if (res_ex & ICH6_RIRB_EX_UNSOL_EV)
 587                         snd_hda_queue_unsol_event(chip->bus, res, res_ex);
 588                 else if (chip->rirb.cmds) {
 589                         chip->rirb.res = res;
 590                         smp_wmb();
 591                         chip->rirb.cmds--;
 592                 }
 593         }
 594 }
 595
 596 /* receive a response */
 597 static unsigned int azx_rirb_get_response(struct hda_bus *bus)
 598 {
 599         struct azx *chip = bus->private_data;
 600         unsigned long timeout;
 601
 602  again:
 603         timeout = jiffies + msecs_to_jiffies(1000);
 604         for (;;) {
 605                 if (chip->polling_mode) {
 606                         spin_lock_irq(&chip->reg_lock);
 607                         azx_update_rirb(chip);
 608                         spin_unlock_irq(&chip->reg_lock);
 609                 }
 610                 if (!chip->rirb.cmds) {
 611                         smp_rmb();
 612                         bus->rirb_error = 0;
 613                         return chip->rirb.res; /* the last value */
 614                 }
 615                 if (time_after(jiffies, timeout))
 616                         break;
 617                 if (bus->needs_damn_long_delay)
 618                         msleep(2); /* temporary workaround */
 619                 else {
 620                         udelay(10);
 621                         cond_resched();
 622                 }
 623         }
 624
 625         if (chip->msi) {
 626                 snd_printk(KERN_WARNING SFX "No response from codec, "
 627                            "disabling MSI: last cmd=0x%08x\n", chip->last_cmd);
 628                 free_irq(chip->irq, chip);
 629                 chip->irq = -1;
 630                 pci_disable_msi(chip->pci);
 631                 chip->msi = 0;
 632                 if (azx_acquire_irq(chip, 1) < 0) {
 633                         bus->rirb_error = 1;
 634                         return -1;
 635                 }
 636                 goto again;
 637         }
 638
 639         if (!chip->polling_mode) {
 640                 snd_printk(KERN_WARNING SFX "azx_get_response timeout, "
 641                            "switching to polling mode: last cmd=0x%08x\n",
 642                            chip->last_cmd);
 643                 chip->polling_mode = 1;
 644                 goto again;
 645         }
 646
 647         if (chip->probing) {
 648                 /* If this critical timeout happens during the codec probing
 649                  * phase, this is likely an access to a non-existing codec
 650                  * slot.  Better to return an error and reset the system.
 651                  */
 652                 return -1;
 653         }
 654
 655         snd_printk(KERN_ERR SFX "azx_get_response timeout (ERROR): "
 656                    "last cmd=0x%08x\n", chip->last_cmd);
 657         spin_lock_irq(&chip->reg_lock);
 658         chip->rirb.cmds = 0; /* reset the index */
 659         bus->rirb_error = 1;
 660         spin_unlock_irq(&chip->reg_lock);
 661         return -1;
 662 }
 663
 664 /*
 665  * Use the single immediate command instead of CORB/RIRB for simplicity
 666  *
 667  * Note: according to Intel, this is not preferred use.  The command was
 668  *       intended for the BIOS only, and may get confused with unsolicited
 669  *       responses.  So, we shouldn't use it for normal operation from the
 670  *       driver.
 671  *       I left the codes, however, for debugging/testing purposes.
 672  */
 673
 674 /* send a command */
 675 static int azx_single_send_cmd(struct hda_bus *bus, u32 val)
 676 {
 677         struct azx *chip = bus->private_data;
 678         int timeout = 50;
 679
 680         while (timeout--) {
 681                 /* check ICB busy bit */
 682                 if (!((azx_readw(chip, IRS) & ICH6_IRS_BUSY))) {
 683                         /* Clear IRV valid bit */
 684                         azx_writew(chip, IRS, azx_readw(chip, IRS) |
 685                                    ICH6_IRS_VALID);
 686                         azx_writel(chip, IC, val);
 687                         azx_writew(chip, IRS, azx_readw(chip, IRS) |
 688                                    ICH6_IRS_BUSY);
 689                         return 0;
 690                 }
 691                 udelay(1);
 692         }
 693         if (printk_ratelimit())
 694                 snd_printd(SFX "send_cmd timeout: IRS=0x%x, val=0x%x\n",
 695                            azx_readw(chip, IRS), val);
 696         return -EIO;
 697 }
 698
 699 /* receive a response */
 700 static unsigned int azx_single_get_response(struct hda_bus *bus)
 701 {
 702         struct azx *chip = bus->private_data;
 703         int timeout = 50;
 704
 705         while (timeout--) {
 706                 /* check IRV busy bit */
 707                 if (azx_readw(chip, IRS) & ICH6_IRS_VALID)
 708                         return azx_readl(chip, IR);
 709                 udelay(1);
 710         }
 711         if (printk_ratelimit())
 712                 snd_printd(SFX "get_response timeout: IRS=0x%x\n",
 713                            azx_readw(chip, IRS));
 714         return (unsigned int)-1;
 715 }
 716
 717 /*
 718  * The below are the main callbacks from hda_codec.
 719  *
 720  * They are just the skeleton to call sub-callbacks according to the
 721  * current setting of chip->single_cmd.
 722  */
 723
 724 /* send a command */
 725 static int azx_send_cmd(struct hda_bus *bus, unsigned int val)
 726 {
 727         struct azx *chip = bus->private_data;
 728
 729         chip->last_cmd = val;
 730         if (chip->single_cmd)
 731                 return azx_single_send_cmd(bus, val);
 732         else
 733                 return azx_corb_send_cmd(bus, val);
 734 }
 735
 736 /* get a response */
 737 static unsigned int azx_get_response(struct hda_bus *bus)
 738 {
 739         struct azx *chip = bus->private_data;
 740         if (chip->single_cmd)
 741                 return azx_single_get_response(bus);
 742         else
 743                 return azx_rirb_get_response(bus);
 744 }
 745
 746 #ifdef CONFIG_SND_HDA_POWER_SAVE
 747 static void azx_power_notify(struct hda_bus *bus);
 748 #endif
 749
 750 /* reset codec link */
 751 static int azx_reset(struct azx *chip)
 752 {
 753         int count;
 754
 755         /* clear STATESTS */
 756         azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
 757
 758         /* reset controller */
 759         azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);
 760
 761         count = 50;
 762         while (azx_readb(chip, GCTL) && --count)
 763                 msleep(1);
 764
 765         /* delay for >= 100us for codec PLL to settle per spec
 766          * Rev 0.9 section 5.5.1
 767          */
 768         msleep(1);
 769
 770         /* Bring controller out of reset */
 771         azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET);
 772
 773         count = 50;
 774         while (!azx_readb(chip, GCTL) && --count)
 775                 msleep(1);
 776
 777         /* Brent Chartrand said to wait >= 540us for codecs to initialize */
 778         msleep(1);
 779
 780         /* check to see if controller is ready */
 781         if (!azx_readb(chip, GCTL)) {
 782                 snd_printd(SFX "azx_reset: controller not ready!\n");
 783                 return -EBUSY;
 784         }
 785
 786         /* Accept unsolicited responses */
 787         azx_writel(chip, GCTL, azx_readl(chip, GCTL) | ICH6_GCTL_UREN);
 788
 789         /* detect codecs */
 790         if (!chip->codec_mask) {
 791                 chip->codec_mask = azx_readw(chip, STATESTS);
 792                 snd_printdd(SFX "codec_mask = 0x%x\n", chip->codec_mask);
 793         }
 794
 795         return 0;
 796 }
 797
 798
 799 /*
 800  * Lowlevel interface
 801  */
 802
 803 /* enable interrupts */
 804 static void azx_int_enable(struct azx *chip)
 805 {
 806         /* enable controller CIE and GIE */
 807         azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
 808                    ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN);
 809 }
 810
 811 /* disable interrupts */
 812 static void azx_int_disable(struct azx *chip)
 813 {
 814         int i;
 815
 816         /* disable interrupts in stream descriptor */
 817         for (i = 0; i < chip->num_streams; i++) {
 818                 struct azx_dev *azx_dev = &chip->azx_dev[i];
 819                 azx_sd_writeb(azx_dev, SD_CTL,
 820                               azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK);
 821         }
 822
 823         /* disable SIE for all streams */
 824         azx_writeb(chip, INTCTL, 0);
 825
 826         /* disable controller CIE and GIE */
 827         azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
 828                    ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN));
 829 }
 830
 831 /* clear interrupts */
 832 static void azx_int_clear(struct azx *chip)
 833 {
 834         int i;
 835
 836         /* clear stream status */
 837         for (i = 0; i < chip->num_streams; i++) {
 838                 struct azx_dev *azx_dev = &chip->azx_dev[i];
 839                 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
 840         }
 841
 842         /* clear STATESTS */
 843         azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
 844
 845         /* clear rirb status */
 846         azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
 847
 848         /* clear int status */
 849         azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM);
 850 }
 851
 852 /* start a stream */
 853 static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev)
 854 {
 855         /*
 856          * Before stream start, initialize parameter
 857          */
 858         azx_dev->insufficient = 1;
 859
 860         /* enable SIE */
 861         azx_writeb(chip, INTCTL,
 862                    azx_readb(chip, INTCTL) | (1 << azx_dev->index));
 863         /* set DMA start and interrupt mask */
 864         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
 865                       SD_CTL_DMA_START | SD_INT_MASK);
 866 }
 867
 868 /* stop DMA */
 869 static void azx_stream_clear(struct azx *chip, struct azx_dev *azx_dev)
 870 {
 871         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
 872                       ~(SD_CTL_DMA_START | SD_INT_MASK));
 873         azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
 874 }
 875
 876 /* stop a stream */
 877 static void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev)
 878 {
 879         azx_stream_clear(chip, azx_dev);
 880         /* disable SIE */
 881         azx_writeb(chip, INTCTL,
 882                    azx_readb(chip, INTCTL) & ~(1 << azx_dev->index));
 883 }
 884
 885
 886 /*
 887  * reset and start the controller registers
 888  */
 889 static void azx_init_chip(struct azx *chip)
 890 {
 891         if (chip->initialized)
 892                 return;
 893
 894         /* reset controller */
 895         azx_reset(chip);
 896
 897         /* initialize interrupts */
 898         azx_int_clear(chip);
 899         azx_int_enable(chip);
 900
 901         /* initialize the codec command I/O */
 902         if (!chip->single_cmd)
 903                 azx_init_cmd_io(chip);
 904
 905         /* program the position buffer */
 906         azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
 907         azx_writel(chip, DPUBASE, upper_32_bits(chip->posbuf.addr));
 908
 909         chip->initialized = 1;
 910 }
 911
 912 /*
 913  * initialize the PCI registers
 914  */
 915 /* update bits in a PCI register byte */
 916 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
 917                             unsigned char mask, unsigned char val)
 918 {
 919         unsigned char data;
 920
 921         pci_read_config_byte(pci, reg, &data);
 922         data &= ~mask;
 923         data |= (val & mask);
 924         pci_write_config_byte(pci, reg, data);
 925 }
 926
 927 static void azx_init_pci(struct azx *chip)
 928 {
 929         unsigned short snoop;
 930
 931         /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
 932          * TCSEL == Traffic Class Select Register, which sets PCI express QOS
 933          * Ensuring these bits are 0 clears playback static on some HD Audio
 934          * codecs
 935          */
 936         update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0);
 937
 938         switch (chip->driver_type) {
 939         case AZX_DRIVER_ATI:
 940                 /* For ATI SB450 azalia HD audio, we need to enable snoop */
 941                 update_pci_byte(chip->pci,
 942                                 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR,
 943                                 0x07, ATI_SB450_HDAUDIO_ENABLE_SNOOP);
 944                 break;
 945         case AZX_DRIVER_NVIDIA:
 946                 /* For NVIDIA HDA, enable snoop */
 947                 update_pci_byte(chip->pci,
 948                                 NVIDIA_HDA_TRANSREG_ADDR,
 949                                 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
 950                 update_pci_byte(chip->pci,
 951                                 NVIDIA_HDA_ISTRM_COH,
 952                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
 953                 update_pci_byte(chip->pci,
 954                                 NVIDIA_HDA_OSTRM_COH,
 955                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
 956                 break;
 957         case AZX_DRIVER_SCH:
 958                 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
 959                 if (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) {
 960                         pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC,
 961                                 snoop & (~INTEL_SCH_HDA_DEVC_NOSNOOP));
 962                         pci_read_config_word(chip->pci,
 963                                 INTEL_SCH_HDA_DEVC, &snoop);
 964                         snd_printdd(SFX "HDA snoop disabled, enabling ... %s\n",
 965                                 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)
 966                                 ? "Failed" : "OK");
 967                 }
 968                 break;
 969
 970         }
 971 }
 972
 973
 974 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
 975
 976 /*
 977  * interrupt handler
 978  */
 979 static irqreturn_t azx_interrupt(int irq, void *dev_id)
 980 {
 981         struct azx *chip = dev_id;
 982         struct azx_dev *azx_dev;
 983         u32 status;
 984         int i, ok;
 985
 986         spin_lock(&chip->reg_lock);
 987
 988         status = azx_readl(chip, INTSTS);
 989         if (status == 0) {
 990                 spin_unlock(&chip->reg_lock);
 991                 return IRQ_NONE;
 992         }
 993
 994         for (i = 0; i < chip->num_streams; i++) {
 995                 azx_dev = &chip->azx_dev[i];
 996                 if (status & azx_dev->sd_int_sta_mask) {
 997                         azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
 998                         if (!azx_dev->substream || !azx_dev->running)
 999                                 continue;
1000                         /* check whether this IRQ is really acceptable */
1001                         ok = azx_position_ok(chip, azx_dev);
1002                         if (ok == 1) {
1003                                 azx_dev->irq_pending = 0;
1004                                 spin_unlock(&chip->reg_lock);
1005                                 snd_pcm_period_elapsed(azx_dev->substream);
1006                                 spin_lock(&chip->reg_lock);
1007                         } else if (ok == 0 && chip->bus && chip->bus->workq) {
1008                                 /* bogus IRQ, process it later */
1009                                 azx_dev->irq_pending = 1;
1010                                 queue_work(chip->bus->workq,
1011                                            &chip->irq_pending_work);
1012                         }
1013                 }
1014         }
1015
1016         /* clear rirb int */
1017         status = azx_readb(chip, RIRBSTS);
1018         if (status & RIRB_INT_MASK) {
1019                 if (!chip->single_cmd && (status & RIRB_INT_RESPONSE))
1020                         azx_update_rirb(chip);
1021                 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1022         }
1023
1024 #if 0
1025         /* clear state status int */
1026         if (azx_readb(chip, STATESTS) & 0x04)
1027                 azx_writeb(chip, STATESTS, 0x04);
1028 #endif
1029         spin_unlock(&chip->reg_lock);
1030
1031         return IRQ_HANDLED;
1032 }
1033
1034
1035 /*
1036  * set up a BDL entry
1037  */
1038 static int setup_bdle(struct snd_pcm_substream *substream,
1039                       struct azx_dev *azx_dev, u32 **bdlp,
1040                       int ofs, int size, int with_ioc)
1041 {
1042         u32 *bdl = *bdlp;
1043
1044         while (size > 0) {
1045                 dma_addr_t addr;
1046                 int chunk;
1047
1048                 if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES)
1049                         return -EINVAL;
1050
1051                 addr = snd_pcm_sgbuf_get_addr(substream, ofs);
1052                 /* program the address field of the BDL entry */
1053                 bdl[0] = cpu_to_le32((u32)addr);
1054                 bdl[1] = cpu_to_le32(upper_32_bits(addr));
1055                 /* program the size field of the BDL entry */
1056                 chunk = snd_pcm_sgbuf_get_chunk_size(substream, ofs, size);
1057                 bdl[2] = cpu_to_le32(chunk);
1058                 /* program the IOC to enable interrupt
1059                  * only when the whole fragment is processed
1060                  */
1061                 size -= chunk;
1062                 bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);
1063                 bdl += 4;
1064                 azx_dev->frags++;
1065                 ofs += chunk;
1066         }
1067         *bdlp = bdl;
1068         return ofs;
1069 }
1070
1071 /*
1072  * set up BDL entries
1073  */
1074 static int azx_setup_periods(struct azx *chip,
1075                              struct snd_pcm_substream *substream,
1076                              struct azx_dev *azx_dev)
1077 {
1078         u32 *bdl;
1079         int i, ofs, periods, period_bytes;
1080         int pos_adj;
1081
1082         /* reset BDL address */
1083         azx_sd_writel(azx_dev, SD_BDLPL, 0);
1084         azx_sd_writel(azx_dev, SD_BDLPU, 0);
1085
1086         period_bytes = azx_dev->period_bytes;
1087         periods = azx_dev->bufsize / period_bytes;
1088
1089         /* program the initial BDL entries */
1090         bdl = (u32 *)azx_dev->bdl.area;
1091         ofs = 0;
1092         azx_dev->frags = 0;
1093         pos_adj = bdl_pos_adj[chip->dev_index];
1094         if (pos_adj > 0) {
1095                 struct snd_pcm_runtime *runtime = substream->runtime;
1096                 int pos_align = pos_adj;
1097                 pos_adj = (pos_adj * runtime->rate + 47999) / 48000;
1098                 if (!pos_adj)
1099                         pos_adj = pos_align;
1100                 else
1101                         pos_adj = ((pos_adj + pos_align - 1) / pos_align) *
1102                                 pos_align;
1103                 pos_adj = frames_to_bytes(runtime, pos_adj);
1104                 if (pos_adj >= period_bytes) {
1105                         snd_printk(KERN_WARNING SFX "Too big adjustment %d\n",
1106                                    bdl_pos_adj[chip->dev_index]);
1107                         pos_adj = 0;
1108                 } else {
1109                         ofs = setup_bdle(substream, azx_dev,
1110                                          &bdl, ofs, pos_adj, 1);
1111                         if (ofs < 0)
1112                                 goto error;
1113                 }
1114         } else
1115                 pos_adj = 0;
1116         for (i = 0; i < periods; i++) {
1117                 if (i == periods - 1 && pos_adj)
1118                         ofs = setup_bdle(substream, azx_dev, &bdl, ofs,
1119                                          period_bytes - pos_adj, 0);
1120                 else
1121                         ofs = setup_bdle(substream, azx_dev, &bdl, ofs,
1122                                          period_bytes, 1);
1123                 if (ofs < 0)
1124                         goto error;
1125         }
1126         return 0;
1127
1128  error:
1129         snd_printk(KERN_ERR SFX "Too many BDL entries: buffer=%d, period=%d\n",
1130                    azx_dev->bufsize, period_bytes);
1131         return -EINVAL;
1132 }
1133
1134 /* reset stream */
1135 static void azx_stream_reset(struct azx *chip, struct azx_dev *azx_dev)
1136 {
1137         unsigned char val;
1138         int timeout;
1139
1140         azx_stream_clear(chip, azx_dev);
1141
1142         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1143                       SD_CTL_STREAM_RESET);
1144         udelay(3);
1145         timeout = 300;
1146         while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1147                --timeout)
1148                 ;
1149         val &= ~SD_CTL_STREAM_RESET;
1150         azx_sd_writeb(azx_dev, SD_CTL, val);
1151         udelay(3);
1152
1153         timeout = 300;
1154         /* waiting for hardware to report that the stream is out of reset */
1155         while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1156                --timeout)
1157                 ;
1158
1159         /* reset first position - may not be synced with hw at this time */
1160         *azx_dev->posbuf = 0;
1161 }
1162
1163 /*
1164  * set up the SD for streaming
1165  */
1166 static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev)
1167 {
1168         /* make sure the run bit is zero for SD */
1169         azx_stream_clear(chip, azx_dev);
1170         /* program the stream_tag */
1171         azx_sd_writel(azx_dev, SD_CTL,
1172                       (azx_sd_readl(azx_dev, SD_CTL) & ~SD_CTL_STREAM_TAG_MASK)|
1173                       (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT));
1174
1175         /* program the length of samples in cyclic buffer */
1176         azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize);
1177
1178         /* program the stream format */
1179         /* this value needs to be the same as the one programmed */
1180         azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
1181
1182         /* program the stream LVI (last valid index) of the BDL */
1183         azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
1184
1185         /* program the BDL address */
1186         /* lower BDL address */
1187         azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
1188         /* upper BDL address */
1189         azx_sd_writel(azx_dev, SD_BDLPU, upper_32_bits(azx_dev->bdl.addr));
1190
1191         /* enable the position buffer */
1192         if (chip->position_fix == POS_FIX_POSBUF ||
1193             chip->position_fix == POS_FIX_AUTO ||
1194             chip->via_dmapos_patch) {
1195                 if (!(azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE))
1196                         azx_writel(chip, DPLBASE,
1197                                 (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE);
1198         }
1199
1200         /* set the interrupt enable bits in the descriptor control register */
1201         azx_sd_writel(azx_dev, SD_CTL,
1202                       azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK);
1203
1204         return 0;
1205 }
1206
1207 /*
1208  * Probe the given codec address
1209  */
1210 static int probe_codec(struct azx *chip, int addr)
1211 {
1212         unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) |
1213                 (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID;
1214         unsigned int res;
1215
1216         chip->probing = 1;
1217         azx_send_cmd(chip->bus, cmd);
1218         res = azx_get_response(chip->bus);
1219         chip->probing = 0;
1220         if (res == -1)
1221                 return -EIO;
1222         snd_printdd(SFX "codec #%d probed OK\n", addr);
1223         return 0;
1224 }
1225
1226 static int azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
1227                                  struct hda_pcm *cpcm);
1228 static void azx_stop_chip(struct azx *chip);
1229
1230 /*
1231  * Codec initialization
1232  */
1233
1234 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
1235 static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] __devinitdata = {
1236         [AZX_DRIVER_TERA] = 1,
1237 };
1238
1239 static int __devinit azx_codec_create(struct azx *chip, const char *model,
1240                                       int no_init)
1241 {
1242         struct hda_bus_template bus_temp;
1243         int c, codecs, err;
1244         int max_slots;
1245
1246         memset(&bus_temp, 0, sizeof(bus_temp));
1247         bus_temp.private_data = chip;
1248         bus_temp.modelname = model;
1249         bus_temp.pci = chip->pci;
1250         bus_temp.ops.command = azx_send_cmd;
1251         bus_temp.ops.get_response = azx_get_response;
1252         bus_temp.ops.attach_pcm = azx_attach_pcm_stream;
1253 #ifdef CONFIG_SND_HDA_POWER_SAVE
1254         bus_temp.power_save = &power_save;
1255         bus_temp.ops.pm_notify = azx_power_notify;
1256 #endif
1257
1258         err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus);
1259         if (err < 0)
1260                 return err;
1261
1262         if (chip->driver_type == AZX_DRIVER_NVIDIA)
1263                 chip->bus->needs_damn_long_delay = 1;
1264
1265         codecs = 0;
1266         max_slots = azx_max_codecs[chip->driver_type];
1267         if (!max_slots)
1268                 max_slots = AZX_MAX_CODECS;
1269
1270         /* First try to probe all given codec slots */
1271         for (c = 0; c < max_slots; c++) {
1272                 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1273                         if (probe_codec(chip, c) < 0) {
1274                                 /* Some BIOSen give you wrong codec addresses
1275                                  * that don't exist
1276                                  */
1277                                 snd_printk(KERN_WARNING SFX
1278                                            "Codec #%d probe error; "
1279                                            "disabling it...\n", c);
1280                                 chip->codec_mask &= ~(1 << c);
1281                                 /* More badly, accessing to a non-existing
1282                                  * codec often screws up the controller chip,
1283                                  * and distrubs the further communications.
1284                                  * Thus if an error occurs during probing,
1285                                  * better to reset the controller chip to
1286                                  * get back to the sanity state.
1287                                  */
1288                                 azx_stop_chip(chip);
1289                                 azx_init_chip(chip);
1290                         }
1291                 }
1292         }
1293
1294         /* Then create codec instances */
1295         for (c = 0; c < max_slots; c++) {
1296                 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1297                         struct hda_codec *codec;
1298                         err = snd_hda_codec_new(chip->bus, c, !no_init, &codec);
1299                         if (err < 0)
1300                                 continue;
1301                         codecs++;
1302                 }
1303         }
1304         if (!codecs) {
1305                 snd_printk(KERN_ERR SFX "no codecs initialized\n");
1306                 return -ENXIO;
1307         }
1308
1309         return 0;
1310 }
1311
1312
1313 /*
1314  * PCM support
1315  */
1316
1317 /* assign a stream for the PCM */
1318 static inline struct azx_dev *azx_assign_device(struct azx *chip, int stream)
1319 {
1320         int dev, i, nums;
1321         if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
1322                 dev = chip->playback_index_offset;
1323                 nums = chip->playback_streams;
1324         } else {
1325                 dev = chip->capture_index_offset;
1326                 nums = chip->capture_streams;
1327         }
1328         for (i = 0; i < nums; i++, dev++)
1329                 if (!chip->azx_dev[dev].opened) {
1330                         chip->azx_dev[dev].opened = 1;
1331                         return &chip->azx_dev[dev];
1332                 }
1333         return NULL;
1334 }
1335
1336 /* release the assigned stream */
1337 static inline void azx_release_device(struct azx_dev *azx_dev)
1338 {
1339         azx_dev->opened = 0;
1340 }
1341
1342 static struct snd_pcm_hardware azx_pcm_hw = {
1343         .info =                 (SNDRV_PCM_INFO_MMAP |
1344                                  SNDRV_PCM_INFO_INTERLEAVED |
1345                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
1346                                  SNDRV_PCM_INFO_MMAP_VALID |
1347                                  /* No full-resume yet implemented */
1348                                  /* SNDRV_PCM_INFO_RESUME |*/
1349                                  SNDRV_PCM_INFO_PAUSE |
1350                                  SNDRV_PCM_INFO_SYNC_START),
1351         .formats =              SNDRV_PCM_FMTBIT_S16_LE,
1352         .rates =                SNDRV_PCM_RATE_48000,
1353         .rate_min =             48000,
1354         .rate_max =             48000,
1355         .channels_min =         2,
1356         .channels_max =         2,
1357         .buffer_bytes_max =     AZX_MAX_BUF_SIZE,
1358         .period_bytes_min =     128,
1359         .period_bytes_max =     AZX_MAX_BUF_SIZE / 2,
1360         .periods_min =          2,
1361         .periods_max =          AZX_MAX_FRAG,
1362         .fifo_size =            0,
1363 };
1364
1365 struct azx_pcm {
1366         struct azx *chip;
1367         struct hda_codec *codec;
1368         struct hda_pcm_stream *hinfo[2];
1369 };
1370
1371 static int azx_pcm_open(struct snd_pcm_substream *substream)
1372 {
1373         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1374         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1375         struct azx *chip = apcm->chip;
1376         struct azx_dev *azx_dev;
1377         struct snd_pcm_runtime *runtime = substream->runtime;
1378         unsigned long flags;
1379         int err;
1380
1381         mutex_lock(&chip->open_mutex);
1382         azx_dev = azx_assign_device(chip, substream->stream);
1383         if (azx_dev == NULL) {
1384                 mutex_unlock(&chip->open_mutex);
1385                 return -EBUSY;
1386         }
1387         runtime->hw = azx_pcm_hw;
1388         runtime->hw.channels_min = hinfo->channels_min;
1389         runtime->hw.channels_max = hinfo->channels_max;
1390         runtime->hw.formats = hinfo->formats;
1391         runtime->hw.rates = hinfo->rates;
1392         snd_pcm_limit_hw_rates(runtime);
1393         snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
1394         snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
1395                                    128);
1396         snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1397                                    128);
1398         snd_hda_power_up(apcm->codec);
1399         err = hinfo->ops.open(hinfo, apcm->codec, substream);
1400         if (err < 0) {
1401                 azx_release_device(azx_dev);
1402                 snd_hda_power_down(apcm->codec);
1403                 mutex_unlock(&chip->open_mutex);
1404                 return err;
1405         }
1406         spin_lock_irqsave(&chip->reg_lock, flags);
1407         azx_dev->substream = substream;
1408         azx_dev->running = 0;
1409         spin_unlock_irqrestore(&chip->reg_lock, flags);
1410
1411         runtime->private_data = azx_dev;
1412         snd_pcm_set_sync(substream);
1413         mutex_unlock(&chip->open_mutex);
1414
1415         return 0;
1416 }
1417
1418 static int azx_pcm_close(struct snd_pcm_substream *substream)
1419 {
1420         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1421         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1422         struct azx *chip = apcm->chip;
1423         struct azx_dev *azx_dev = get_azx_dev(substream);
1424         unsigned long flags;
1425
1426         mutex_lock(&chip->open_mutex);
1427         spin_lock_irqsave(&chip->reg_lock, flags);
1428         azx_dev->substream = NULL;
1429         azx_dev->running = 0;
1430         spin_unlock_irqrestore(&chip->reg_lock, flags);
1431         azx_release_device(azx_dev);
1432         hinfo->ops.close(hinfo, apcm->codec, substream);
1433         snd_hda_power_down(apcm->codec);
1434         mutex_unlock(&chip->open_mutex);
1435         return 0;
1436 }
1437
1438 static int azx_pcm_hw_params(struct snd_pcm_substream *substream,
1439                              struct snd_pcm_hw_params *hw_params)
1440 {
1441         struct azx_dev *azx_dev = get_azx_dev(substream);
1442
1443         azx_dev->bufsize = 0;
1444         azx_dev->period_bytes = 0;
1445         azx_dev->format_val = 0;
1446         return snd_pcm_lib_malloc_pages(substream,
1447                                         params_buffer_bytes(hw_params));
1448 }
1449
1450 static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
1451 {
1452         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1453         struct azx_dev *azx_dev = get_azx_dev(substream);
1454         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1455
1456         /* reset BDL address */
1457         azx_sd_writel(azx_dev, SD_BDLPL, 0);
1458         azx_sd_writel(azx_dev, SD_BDLPU, 0);
1459         azx_sd_writel(azx_dev, SD_CTL, 0);
1460         azx_dev->bufsize = 0;
1461         azx_dev->period_bytes = 0;
1462         azx_dev->format_val = 0;
1463
1464         hinfo->ops.cleanup(hinfo, apcm->codec, substream);
1465
1466         return snd_pcm_lib_free_pages(substream);
1467 }
1468
1469 static int azx_pcm_prepare(struct snd_pcm_substream *substream)
1470 {
1471         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1472         struct azx *chip = apcm->chip;
1473         struct azx_dev *azx_dev = get_azx_dev(substream);
1474         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1475         struct snd_pcm_runtime *runtime = substream->runtime;
1476         unsigned int bufsize, period_bytes, format_val;
1477         int err;
1478
1479         azx_stream_reset(chip, azx_dev);
1480         format_val = snd_hda_calc_stream_format(runtime->rate,
1481                                                 runtime->channels,
1482                                                 runtime->format,
1483                                                 hinfo->maxbps);
1484         if (!format_val) {
1485                 snd_printk(KERN_ERR SFX
1486                            "invalid format_val, rate=%d, ch=%d, format=%d\n",
1487                            runtime->rate, runtime->channels, runtime->format);
1488                 return -EINVAL;
1489         }
1490
1491         bufsize = snd_pcm_lib_buffer_bytes(substream);
1492         period_bytes = snd_pcm_lib_period_bytes(substream);
1493
1494         snd_printdd(SFX "azx_pcm_prepare: bufsize=0x%x, format=0x%x\n",
1495                     bufsize, format_val);
1496
1497         if (bufsize != azx_dev->bufsize ||
1498             period_bytes != azx_dev->period_bytes ||
1499             format_val != azx_dev->format_val) {
1500                 azx_dev->bufsize = bufsize;
1501                 azx_dev->period_bytes = period_bytes;
1502                 azx_dev->format_val = format_val;
1503                 err = azx_setup_periods(chip, substream, azx_dev);
1504                 if (err < 0)
1505                         return err;
1506         }
1507
1508         azx_dev->min_jiffies = (runtime->period_size * HZ) /
1509                                                 (runtime->rate * 2);
1510         azx_setup_controller(chip, azx_dev);
1511         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1512                 azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1;
1513         else
1514                 azx_dev->fifo_size = 0;
1515
1516         return hinfo->ops.prepare(hinfo, apcm->codec, azx_dev->stream_tag,
1517                                   azx_dev->format_val, substream);
1518 }
1519
1520 static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
1521 {
1522         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1523         struct azx *chip = apcm->chip;
1524         struct azx_dev *azx_dev;
1525         struct snd_pcm_substream *s;
1526         int rstart = 0, start, nsync = 0, sbits = 0;
1527         int nwait, timeout;
1528
1529         switch (cmd) {
1530         case SNDRV_PCM_TRIGGER_START:
1531                 rstart = 1;
1532         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1533         case SNDRV_PCM_TRIGGER_RESUME:
1534                 start = 1;
1535                 break;
1536         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1537         case SNDRV_PCM_TRIGGER_SUSPEND:
1538         case SNDRV_PCM_TRIGGER_STOP:
1539                 start = 0;
1540                 break;
1541         default:
1542                 return -EINVAL;
1543         }
1544
1545         snd_pcm_group_for_each_entry(s, substream) {
1546                 if (s->pcm->card != substream->pcm->card)
1547                         continue;
1548                 azx_dev = get_azx_dev(s);
1549                 sbits |= 1 << azx_dev->index;
1550                 nsync++;
1551                 snd_pcm_trigger_done(s, substream);
1552         }
1553
1554         spin_lock(&chip->reg_lock);
1555         if (nsync > 1) {
1556                 /* first, set SYNC bits of corresponding streams */
1557                 azx_writel(chip, SYNC, azx_readl(chip, SYNC) | sbits);
1558         }
1559         snd_pcm_group_for_each_entry(s, substream) {
1560                 if (s->pcm->card != substream->pcm->card)
1561                         continue;
1562                 azx_dev = get_azx_dev(s);
1563                 if (rstart) {
1564                         azx_dev->start_flag = 1;
1565                         azx_dev->start_jiffies = jiffies + azx_dev->min_jiffies;
1566                 }
1567                 if (start)
1568                         azx_stream_start(chip, azx_dev);
1569                 else
1570                         azx_stream_stop(chip, azx_dev);
1571                 azx_dev->running = start;
1572         }
1573         spin_unlock(&chip->reg_lock);
1574         if (start) {
1575                 if (nsync == 1)
1576                         return 0;
1577                 /* wait until all FIFOs get ready */
1578                 for (timeout = 5000; timeout; timeout--) {
1579                         nwait = 0;
1580                         snd_pcm_group_for_each_entry(s, substream) {
1581                                 if (s->pcm->card != substream->pcm->card)
1582                                         continue;
1583                                 azx_dev = get_azx_dev(s);
1584                                 if (!(azx_sd_readb(azx_dev, SD_STS) &
1585                                       SD_STS_FIFO_READY))
1586                                         nwait++;
1587                         }
1588                         if (!nwait)
1589                                 break;
1590                         cpu_relax();
1591                 }
1592         } else {
1593                 /* wait until all RUN bits are cleared */
1594                 for (timeout = 5000; timeout; timeout--) {
1595                         nwait = 0;
1596                         snd_pcm_group_for_each_entry(s, substream) {
1597                                 if (s->pcm->card != substream->pcm->card)
1598                                         continue;
1599                                 azx_dev = get_azx_dev(s);
1600                                 if (azx_sd_readb(azx_dev, SD_CTL) &
1601                                     SD_CTL_DMA_START)
1602                                         nwait++;
1603                         }
1604                         if (!nwait)
1605                                 break;
1606                         cpu_relax();
1607                 }
1608         }
1609         if (nsync > 1) {
1610                 spin_lock(&chip->reg_lock);
1611                 /* reset SYNC bits */
1612                 azx_writel(chip, SYNC, azx_readl(chip, SYNC) & ~sbits);
1613                 spin_unlock(&chip->reg_lock);
1614         }
1615         return 0;
1616 }
1617
1618 /* get the current DMA position with correction on VIA chips */
1619 static unsigned int azx_via_get_position(struct azx *chip,
1620                                          struct azx_dev *azx_dev)
1621 {
1622         unsigned int link_pos, mini_pos, bound_pos;
1623         unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
1624         unsigned int fifo_size;
1625
1626         link_pos = azx_sd_readl(azx_dev, SD_LPIB);
1627         if (azx_dev->index >= 4) {
1628                 /* Playback, no problem using link position */
1629                 return link_pos;
1630         }
1631
1632         /* Capture */
1633         /* For new chipset,
1634          * use mod to get the DMA position just like old chipset
1635          */
1636         mod_dma_pos = le32_to_cpu(*azx_dev->posbuf);
1637         mod_dma_pos %= azx_dev->period_bytes;
1638
1639         /* azx_dev->fifo_size can't get FIFO size of in stream.
1640          * Get from base address + offset.
1641          */
1642         fifo_size = readw(chip->remap_addr + VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
1643
1644         if (azx_dev->insufficient) {
1645                 /* Link position never gather than FIFO size */
1646                 if (link_pos <= fifo_size)
1647                         return 0;
1648
1649                 azx_dev->insufficient = 0;
1650         }
1651
1652         if (link_pos <= fifo_size)
1653                 mini_pos = azx_dev->bufsize + link_pos - fifo_size;
1654         else
1655                 mini_pos = link_pos - fifo_size;
1656
1657         /* Find nearest previous boudary */
1658         mod_mini_pos = mini_pos % azx_dev->period_bytes;
1659         mod_link_pos = link_pos % azx_dev->period_bytes;
1660         if (mod_link_pos >= fifo_size)
1661                 bound_pos = link_pos - mod_link_pos;
1662         else if (mod_dma_pos >= mod_mini_pos)
1663                 bound_pos = mini_pos - mod_mini_pos;
1664         else {
1665                 bound_pos = mini_pos - mod_mini_pos + azx_dev->period_bytes;
1666                 if (bound_pos >= azx_dev->bufsize)
1667                         bound_pos = 0;
1668         }
1669
1670         /* Calculate real DMA position we want */
1671         return bound_pos + mod_dma_pos;
1672 }
1673
1674 static unsigned int azx_get_position(struct azx *chip,
1675                                      struct azx_dev *azx_dev)
1676 {
1677         unsigned int pos;
1678
1679         if (chip->via_dmapos_patch)
1680                 pos = azx_via_get_position(chip, azx_dev);
1681         else if (chip->position_fix == POS_FIX_POSBUF ||
1682                  chip->position_fix == POS_FIX_AUTO) {
1683                 /* use the position buffer */
1684                 pos = le32_to_cpu(*azx_dev->posbuf);
1685         } else {
1686                 /* read LPIB */
1687                 pos = azx_sd_readl(azx_dev, SD_LPIB);
1688         }
1689         if (pos >= azx_dev->bufsize)
1690                 pos = 0;
1691         return pos;
1692 }
1693
1694 static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
1695 {
1696         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1697         struct azx *chip = apcm->chip;
1698         struct azx_dev *azx_dev = get_azx_dev(substream);
1699         return bytes_to_frames(substream->runtime,
1700                                azx_get_position(chip, azx_dev));
1701 }
1702
1703 /*
1704  * Check whether the current DMA position is acceptable for updating
1705  * periods.  Returns non-zero if it's OK.
1706  *
1707  * Many HD-audio controllers appear pretty inaccurate about
1708  * the update-IRQ timing.  The IRQ is issued before actually the
1709  * data is processed.  So, we need to process it afterwords in a
1710  * workqueue.
1711  */
1712 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
1713 {
1714         unsigned int pos;
1715
1716         if (azx_dev->start_flag &&
1717             time_before_eq(jiffies, azx_dev->start_jiffies))
1718                 return -1;      /* bogus (too early) interrupt */
1719         azx_dev->start_flag = 0;
1720
1721         pos = azx_get_position(chip, azx_dev);
1722         if (chip->position_fix == POS_FIX_AUTO) {
1723                 if (!pos) {
1724                         printk(KERN_WARNING
1725                                "hda-intel: Invalid position buffer, "
1726                                "using LPIB read method instead.\n");
1727                         chip->position_fix = POS_FIX_LPIB;
1728                         pos = azx_get_position(chip, azx_dev);
1729                 } else
1730                         chip->position_fix = POS_FIX_POSBUF;
1731         }
1732
1733         if (!bdl_pos_adj[chip->dev_index])
1734                 return 1; /* no delayed ack */
1735         if (pos % azx_dev->period_bytes > azx_dev->period_bytes / 2)
1736                 return 0; /* NG - it's below the period boundary */
1737         return 1; /* OK, it's fine */
1738 }
1739
1740 /*
1741  * The work for pending PCM period updates.
1742  */
1743 static void azx_irq_pending_work(struct work_struct *work)
1744 {
1745         struct azx *chip = container_of(work, struct azx, irq_pending_work);
1746         int i, pending;
1747
1748         if (!chip->irq_pending_warned) {
1749                 printk(KERN_WARNING
1750                        "hda-intel: IRQ timing workaround is activated "
1751                        "for card #%d. Suggest a bigger bdl_pos_adj.\n",
1752                        chip->card->number);
1753                 chip->irq_pending_warned = 1;
1754         }
1755
1756         for (;;) {
1757                 pending = 0;
1758                 spin_lock_irq(&chip->reg_lock);
1759                 for (i = 0; i < chip->num_streams; i++) {
1760                         struct azx_dev *azx_dev = &chip->azx_dev[i];
1761                         if (!azx_dev->irq_pending ||
1762                             !azx_dev->substream ||
1763                             !azx_dev->running)
1764                                 continue;
1765                         if (azx_position_ok(chip, azx_dev)) {
1766                                 azx_dev->irq_pending = 0;
1767                                 spin_unlock(&chip->reg_lock);
1768                                 snd_pcm_period_elapsed(azx_dev->substream);
1769                                 spin_lock(&chip->reg_lock);
1770                         } else
1771                                 pending++;
1772                 }
1773                 spin_unlock_irq(&chip->reg_lock);
1774                 if (!pending)
1775                         return;
1776                 cond_resched();
1777         }
1778 }
1779
1780 /* clear irq_pending flags and assure no on-going workq */
1781 static void azx_clear_irq_pending(struct azx *chip)
1782 {
1783         int i;
1784
1785         spin_lock_irq(&chip->reg_lock);
1786         for (i = 0; i < chip->num_streams; i++)
1787                 chip->azx_dev[i].irq_pending = 0;
1788         spin_unlock_irq(&chip->reg_lock);
1789 }
1790
1791 static struct snd_pcm_ops azx_pcm_ops = {
1792         .open = azx_pcm_open,
1793         .close = azx_pcm_close,
1794         .ioctl = snd_pcm_lib_ioctl,
1795         .hw_params = azx_pcm_hw_params,
1796         .hw_free = azx_pcm_hw_free,
1797         .prepare = azx_pcm_prepare,
1798         .trigger = azx_pcm_trigger,
1799         .pointer = azx_pcm_pointer,
1800         .page = snd_pcm_sgbuf_ops_page,
1801 };
1802
1803 static void azx_pcm_free(struct snd_pcm *pcm)
1804 {
1805         struct azx_pcm *apcm = pcm->private_data;
1806         if (apcm) {
1807                 apcm->chip->pcm[pcm->device] = NULL;
1808                 kfree(apcm);
1809         }
1810 }
1811
1812 static int
1813 azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
1814                       struct hda_pcm *cpcm)
1815 {
1816         struct azx *chip = bus->private_data;
1817         struct snd_pcm *pcm;
1818         struct azx_pcm *apcm;
1819         int pcm_dev = cpcm->device;
1820         int s, err;
1821
1822         if (pcm_dev >= AZX_MAX_PCMS) {
1823                 snd_printk(KERN_ERR SFX "Invalid PCM device number %d\n",
1824                            pcm_dev);
1825                 return -EINVAL;
1826         }
1827         if (chip->pcm[pcm_dev]) {
1828                 snd_printk(KERN_ERR SFX "PCM %d already exists\n", pcm_dev);
1829                 return -EBUSY;
1830         }
1831         err = snd_pcm_new(chip->card, cpcm->name, pcm_dev,
1832                           cpcm->stream[SNDRV_PCM_STREAM_PLAYBACK].substreams,
1833                           cpcm->stream[SNDRV_PCM_STREAM_CAPTURE].substreams,
1834                           &pcm);
1835         if (err < 0)
1836                 return err;
1837         strlcpy(pcm->name, cpcm->name, sizeof(pcm->name));
1838         apcm = kzalloc(sizeof(*apcm), GFP_KERNEL);
1839         if (apcm == NULL)
1840                 return -ENOMEM;
1841         apcm->chip = chip;
1842         apcm->codec = codec;
1843         pcm->private_data = apcm;
1844         pcm->private_free = azx_pcm_free;
1845         if (cpcm->pcm_type == HDA_PCM_TYPE_MODEM)
1846                 pcm->dev_class = SNDRV_PCM_CLASS_MODEM;
1847         chip->pcm[pcm_dev] = pcm;
1848         cpcm->pcm = pcm;
1849         for (s = 0; s < 2; s++) {
1850                 apcm->hinfo[s] = &cpcm->stream[s];
1851                 if (cpcm->stream[s].substreams)
1852                         snd_pcm_set_ops(pcm, s, &azx_pcm_ops);
1853         }
1854         /* buffer pre-allocation */
1855         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV_SG,
1856                                               snd_dma_pci_data(chip->pci),
1857                                               1024 * 64, 32 * 1024 * 1024);
1858         return 0;
1859 }
1860
1861 /*
1862  * mixer creation - all stuff is implemented in hda module
1863  */
1864 static int __devinit azx_mixer_create(struct azx *chip)
1865 {
1866         return snd_hda_build_controls(chip->bus);
1867 }
1868
1869
1870 /*
1871  * initialize SD streams
1872  */
1873 static int __devinit azx_init_stream(struct azx *chip)
1874 {
1875         int i;
1876
1877         /* initialize each stream (aka device)
1878          * assign the starting bdl address to each stream (device)
1879          * and initialize
1880          */
1881         for (i = 0; i < chip->num_streams; i++) {
1882                 struct azx_dev *azx_dev = &chip->azx_dev[i];
1883                 azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8);
1884                 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
1885                 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
1886                 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
1887                 azx_dev->sd_int_sta_mask = 1 << i;
1888                 /* stream tag: must be non-zero and unique */
1889                 azx_dev->index = i;
1890                 azx_dev->stream_tag = i + 1;
1891         }
1892
1893         return 0;
1894 }
1895
1896 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
1897 {
1898         if (request_irq(chip->pci->irq, azx_interrupt,
1899                         chip->msi ? 0 : IRQF_SHARED,
1900                         "HDA Intel", chip)) {
1901                 printk(KERN_ERR "hda-intel: unable to grab IRQ %d, "
1902                        "disabling device\n", chip->pci->irq);
1903                 if (do_disconnect)
1904                         snd_card_disconnect(chip->card);
1905                 return -1;
1906         }
1907         chip->irq = chip->pci->irq;
1908         pci_intx(chip->pci, !chip->msi);
1909         return 0;
1910 }
1911
1912
1913 static void azx_stop_chip(struct azx *chip)
1914 {
1915         if (!chip->initialized)
1916                 return;
1917
1918         /* disable interrupts */
1919         azx_int_disable(chip);
1920         azx_int_clear(chip);
1921
1922         /* disable CORB/RIRB */
1923         azx_free_cmd_io(chip);
1924
1925         /* disable position buffer */
1926         azx_writel(chip, DPLBASE, 0);
1927         azx_writel(chip, DPUBASE, 0);
1928
1929         chip->initialized = 0;
1930 }
1931
1932 #ifdef CONFIG_SND_HDA_POWER_SAVE
1933 /* power-up/down the controller */
1934 static void azx_power_notify(struct hda_bus *bus)
1935 {
1936         struct azx *chip = bus->private_data;
1937         struct hda_codec *c;
1938         int power_on = 0;
1939
1940         list_for_each_entry(c, &bus->codec_list, list) {
1941                 if (c->power_on) {
1942                         power_on = 1;
1943                         break;
1944                 }
1945         }
1946         if (power_on)
1947                 azx_init_chip(chip);
1948         else if (chip->running && power_save_controller)
1949                 azx_stop_chip(chip);
1950 }
1951 #endif /* CONFIG_SND_HDA_POWER_SAVE */
1952
1953 #ifdef CONFIG_PM
1954 /*
1955  * power management
1956  */
1957
1958 static int snd_hda_codecs_inuse(struct hda_bus *bus)
1959 {
1960         struct hda_codec *codec;
1961
1962         list_for_each_entry(codec, &bus->codec_list, list) {
1963                 if (snd_hda_codec_needs_resume(codec))
1964                         return 1;
1965         }
1966         return 0;
1967 }
1968
1969 static int azx_suspend(struct pci_dev *pci, pm_message_t state)
1970 {
1971         struct snd_card *card = pci_get_drvdata(pci);
1972         struct azx *chip = card->private_data;
1973         int i;
1974
1975         snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
1976         azx_clear_irq_pending(chip);
1977         for (i = 0; i < AZX_MAX_PCMS; i++)
1978                 snd_pcm_suspend_all(chip->pcm[i]);
1979         if (chip->initialized)
1980                 snd_hda_suspend(chip->bus, state);
1981         azx_stop_chip(chip);
1982         if (chip->irq >= 0) {
1983                 free_irq(chip->irq, chip);
1984                 chip->irq = -1;
1985         }
1986         if (chip->msi)
1987                 pci_disable_msi(chip->pci);
1988         pci_disable_device(pci);
1989         pci_save_state(pci);
1990         pci_set_power_state(pci, pci_choose_state(pci, state));
1991         return 0;
1992 }
1993
1994 static int azx_resume(struct pci_dev *pci)
1995 {
1996         struct snd_card *card = pci_get_drvdata(pci);
1997         struct azx *chip = card->private_data;
1998
1999         pci_set_power_state(pci, PCI_D0);
2000         pci_restore_state(pci);
2001         if (pci_enable_device(pci) < 0) {
2002                 printk(KERN_ERR "hda-intel: pci_enable_device failed, "
2003                        "disabling device\n");
2004                 snd_card_disconnect(card);
2005                 return -EIO;
2006         }
2007         pci_set_master(pci);
2008         if (chip->msi)
2009                 if (pci_enable_msi(pci) < 0)
2010                         chip->msi = 0;
2011         if (azx_acquire_irq(chip, 1) < 0)
2012                 return -EIO;
2013         azx_init_pci(chip);
2014
2015         if (snd_hda_codecs_inuse(chip->bus))
2016                 azx_init_chip(chip);
2017
2018         snd_hda_resume(chip->bus);
2019         snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2020         return 0;
2021 }
2022 #endif /* CONFIG_PM */
2023
2024
2025 /*
2026  * reboot notifier for hang-up problem at power-down
2027  */
2028 static int azx_halt(struct notifier_block *nb, unsigned long event, void *buf)
2029 {
2030         struct azx *chip = container_of(nb, struct azx, reboot_notifier);
2031         azx_stop_chip(chip);
2032         return NOTIFY_OK;
2033 }
2034
2035 static void azx_notifier_register(struct azx *chip)
2036 {
2037         chip->reboot_notifier.notifier_call = azx_halt;
2038         register_reboot_notifier(&chip->reboot_notifier);
2039 }
2040
2041 static void azx_notifier_unregister(struct azx *chip)
2042 {
2043         if (chip->reboot_notifier.notifier_call)
2044                 unregister_reboot_notifier(&chip->reboot_notifier);
2045 }
2046
2047 /*
2048  * destructor
2049  */
2050 static int azx_free(struct azx *chip)
2051 {
2052         int i;
2053
2054         azx_notifier_unregister(chip);
2055
2056         if (chip->initialized) {
2057                 azx_clear_irq_pending(chip);
2058                 for (i = 0; i < chip->num_streams; i++)
2059                         azx_stream_stop(chip, &chip->azx_dev[i]);
2060                 azx_stop_chip(chip);
2061         }
2062
2063         if (chip->irq >= 0)
2064                 free_irq(chip->irq, (void*)chip);
2065         if (chip->msi)
2066                 pci_disable_msi(chip->pci);
2067         if (chip->remap_addr)
2068                 iounmap(chip->remap_addr);
2069
2070         if (chip->azx_dev) {
2071                 for (i = 0; i < chip->num_streams; i++)
2072                         if (chip->azx_dev[i].bdl.area)
2073                                 snd_dma_free_pages(&chip->azx_dev[i].bdl);
2074         }
2075         if (chip->rb.area)
2076                 snd_dma_free_pages(&chip->rb);
2077         if (chip->posbuf.area)
2078                 snd_dma_free_pages(&chip->posbuf);
2079         pci_release_regions(chip->pci);
2080         pci_disable_device(chip->pci);
2081         kfree(chip->azx_dev);
2082         kfree(chip);
2083
2084         return 0;
2085 }
2086
2087 static int azx_dev_free(struct snd_device *device)
2088 {
2089         return azx_free(device->device_data);
2090 }
2091
2092 /*
2093  * white/black-listing for position_fix
2094  */
2095 static struct snd_pci_quirk position_fix_list[] __devinitdata = {
2096         SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
2097         SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
2098         SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
2099         {}
2100 };
2101
2102 static int __devinit check_position_fix(struct azx *chip, int fix)
2103 {
2104         const struct snd_pci_quirk *q;
2105
2106         switch (fix) {
2107         case POS_FIX_LPIB:
2108         case POS_FIX_POSBUF:
2109                 return fix;
2110         }
2111
2112         /* Check VIA/ATI HD Audio Controller exist */
2113         switch (chip->driver_type) {
2114         case AZX_DRIVER_VIA:
2115         case AZX_DRIVER_ATI:
2116                 chip->via_dmapos_patch = 1;
2117                 /* Use link position directly, avoid any transfer problem. */
2118                 return POS_FIX_LPIB;
2119         }
2120         chip->via_dmapos_patch = 0;
2121
2122         q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
2123         if (q) {
2124                 printk(KERN_INFO
2125                        "hda_intel: position_fix set to %d "
2126                        "for device %04x:%04x\n",
2127                        q->value, q->subvendor, q->subdevice);
2128                 return q->value;
2129         }
2130         return POS_FIX_AUTO;
2131 }
2132
2133 /*
2134  * black-lists for probe_mask
2135  */
2136 static struct snd_pci_quirk probe_mask_list[] __devinitdata = {
2137         /* Thinkpad often breaks the controller communication when accessing
2138          * to the non-working (or non-existing) modem codec slot.
2139          */
2140         SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
2141         SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
2142         SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
2143         /* broken BIOS */
2144         SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
2145         /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
2146         SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
2147         /* forced codec slots */
2148         SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
2149         {}
2150 };
2151
2152 #define AZX_FORCE_CODEC_MASK    0x100
2153
2154 static void __devinit check_probe_mask(struct azx *chip, int dev)
2155 {
2156         const struct snd_pci_quirk *q;
2157
2158         chip->codec_probe_mask = probe_mask[dev];
2159         if (chip->codec_probe_mask == -1) {
2160                 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
2161                 if (q) {
2162                         printk(KERN_INFO
2163                                "hda_intel: probe_mask set to 0x%x "
2164                                "for device %04x:%04x\n",
2165                                q->value, q->subvendor, q->subdevice);
2166                         chip->codec_probe_mask = q->value;
2167                 }
2168         }
2169
2170         /* check forced option */
2171         if (chip->codec_probe_mask != -1 &&
2172             (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
2173                 chip->codec_mask = chip->codec_probe_mask & 0xff;
2174                 printk(KERN_INFO "hda_intel: codec_mask forced to 0x%x\n",
2175                        chip->codec_mask);
2176         }
2177 }
2178
2179
2180 /*
2181  * constructor
2182  */
2183 static int __devinit azx_create(struct snd_card *card, struct pci_dev *pci,
2184                                 int dev, int driver_type,
2185                                 struct azx **rchip)
2186 {
2187         struct azx *chip;
2188         int i, err;
2189         unsigned short gcap;
2190         static struct snd_device_ops ops = {
2191                 .dev_free = azx_dev_free,
2192         };
2193
2194         *rchip = NULL;
2195
2196         err = pci_enable_device(pci);
2197         if (err < 0)
2198                 return err;
2199
2200         chip = kzalloc(sizeof(*chip), GFP_KERNEL);
2201         if (!chip) {
2202                 snd_printk(KERN_ERR SFX "cannot allocate chip\n");
2203                 pci_disable_device(pci);
2204                 return -ENOMEM;
2205         }
2206
2207         spin_lock_init(&chip->reg_lock);
2208         mutex_init(&chip->open_mutex);
2209         chip->card = card;
2210         chip->pci = pci;
2211         chip->irq = -1;
2212         chip->driver_type = driver_type;
2213         chip->msi = enable_msi;
2214         chip->dev_index = dev;
2215         INIT_WORK(&chip->irq_pending_work, azx_irq_pending_work);
2216
2217         chip->position_fix = check_position_fix(chip, position_fix[dev]);
2218         check_probe_mask(chip, dev);
2219
2220         chip->single_cmd = single_cmd;
2221
2222         if (bdl_pos_adj[dev] < 0) {
2223                 switch (chip->driver_type) {
2224                 case AZX_DRIVER_ICH:
2225                         bdl_pos_adj[dev] = 1;
2226                         break;
2227                 default:
2228                         bdl_pos_adj[dev] = 32;
2229                         break;
2230                 }
2231         }
2232
2233 #if BITS_PER_LONG != 64
2234         /* Fix up base address on ULI M5461 */
2235         if (chip->driver_type == AZX_DRIVER_ULI) {
2236                 u16 tmp3;
2237                 pci_read_config_word(pci, 0x40, &tmp3);
2238                 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
2239                 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
2240         }
2241 #endif
2242
2243         err = pci_request_regions(pci, "ICH HD audio");
2244         if (err < 0) {
2245                 kfree(chip);
2246                 pci_disable_device(pci);
2247                 return err;
2248         }
2249
2250         chip->addr = pci_resource_start(pci, 0);
2251         chip->remap_addr = pci_ioremap_bar(pci, 0);
2252         if (chip->remap_addr == NULL) {
2253                 snd_printk(KERN_ERR SFX "ioremap error\n");
2254                 err = -ENXIO;
2255                 goto errout;
2256         }
2257
2258         if (chip->msi)
2259                 if (pci_enable_msi(pci) < 0)
2260                         chip->msi = 0;
2261
2262         if (azx_acquire_irq(chip, 0) < 0) {
2263                 err = -EBUSY;
2264                 goto errout;
2265         }
2266
2267         pci_set_master(pci);
2268         synchronize_irq(chip->irq);
2269
2270         gcap = azx_readw(chip, GCAP);
2271         snd_printdd(SFX "chipset global capabilities = 0x%x\n", gcap);
2272
2273         /* ATI chips seems buggy about 64bit DMA addresses */
2274         if (chip->driver_type == AZX_DRIVER_ATI)
2275                 gcap &= ~0x01;
2276
2277         /* allow 64bit DMA address if supported by H/W */
2278         if ((gcap & 0x01) && !pci_set_dma_mask(pci, DMA_BIT_MASK(64)))
2279                 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(64));
2280         else {
2281                 pci_set_dma_mask(pci, DMA_BIT_MASK(32));
2282                 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(32));
2283         }
2284
2285         /* read number of streams from GCAP register instead of using
2286          * hardcoded value
2287          */
2288         chip->capture_streams = (gcap >> 8) & 0x0f;
2289         chip->playback_streams = (gcap >> 12) & 0x0f;
2290         if (!chip->playback_streams && !chip->capture_streams) {
2291                 /* gcap didn't give any info, switching to old method */
2292
2293                 switch (chip->driver_type) {
2294                 case AZX_DRIVER_ULI:
2295                         chip->playback_streams = ULI_NUM_PLAYBACK;
2296                         chip->capture_streams = ULI_NUM_CAPTURE;
2297                         break;
2298                 case AZX_DRIVER_ATIHDMI:
2299                         chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
2300                         chip->capture_streams = ATIHDMI_NUM_CAPTURE;
2301                         break;
2302                 case AZX_DRIVER_GENERIC:
2303                 default:
2304                         chip->playback_streams = ICH6_NUM_PLAYBACK;
2305                         chip->capture_streams = ICH6_NUM_CAPTURE;
2306                         break;
2307                 }
2308         }
2309         chip->capture_index_offset = 0;
2310         chip->playback_index_offset = chip->capture_streams;
2311         chip->num_streams = chip->playback_streams + chip->capture_streams;
2312         chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev),
2313                                 GFP_KERNEL);
2314         if (!chip->azx_dev) {
2315                 snd_printk(KERN_ERR SFX "cannot malloc azx_dev\n");
2316                 goto errout;
2317         }
2318
2319         for (i = 0; i < chip->num_streams; i++) {
2320                 /* allocate memory for the BDL for each stream */
2321                 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
2322                                           snd_dma_pci_data(chip->pci),
2323                                           BDL_SIZE, &chip->azx_dev[i].bdl);
2324                 if (err < 0) {
2325                         snd_printk(KERN_ERR SFX "cannot allocate BDL\n");
2326                         goto errout;
2327                 }
2328         }
2329         /* allocate memory for the position buffer */
2330         err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
2331                                   snd_dma_pci_data(chip->pci),
2332                                   chip->num_streams * 8, &chip->posbuf);
2333         if (err < 0) {
2334                 snd_printk(KERN_ERR SFX "cannot allocate posbuf\n");
2335                 goto errout;
2336         }
2337         /* allocate CORB/RIRB */
2338         if (!chip->single_cmd) {
2339                 err = azx_alloc_cmd_io(chip);
2340                 if (err < 0)
2341                         goto errout;
2342         }
2343
2344         /* initialize streams */
2345         azx_init_stream(chip);
2346
2347         /* initialize chip */
2348         azx_init_pci(chip);
2349         azx_init_chip(chip);
2350
2351         /* codec detection */
2352         if (!chip->codec_mask) {
2353                 snd_printk(KERN_ERR SFX "no codecs found!\n");
2354                 err = -ENODEV;
2355                 goto errout;
2356         }
2357
2358         err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
2359         if (err <0) {
2360                 snd_printk(KERN_ERR SFX "Error creating device [card]!\n");
2361                 goto errout;
2362         }
2363
2364         strcpy(card->driver, "HDA-Intel");
2365         strlcpy(card->shortname, driver_short_names[chip->driver_type],
2366                 sizeof(card->shortname));
2367         snprintf(card->longname, sizeof(card->longname),
2368                  "%s at 0x%lx irq %i",
2369                  card->shortname, chip->addr, chip->irq);
2370
2371         *rchip = chip;
2372         return 0;
2373
2374  errout:
2375         azx_free(chip);
2376         return err;
2377 }
2378
2379 static void power_down_all_codecs(struct azx *chip)
2380 {
2381 #ifdef CONFIG_SND_HDA_POWER_SAVE
2382         /* The codecs were powered up in snd_hda_codec_new().
2383          * Now all initialization done, so turn them down if possible
2384          */
2385         struct hda_codec *codec;
2386         list_for_each_entry(codec, &chip->bus->codec_list, list) {
2387                 snd_hda_power_down(codec);
2388         }
2389 #endif
2390 }
2391
2392 static int __devinit azx_probe(struct pci_dev *pci,
2393                                const struct pci_device_id *pci_id)
2394 {
2395         static int dev;
2396         struct snd_card *card;
2397         struct azx *chip;
2398         int err;
2399
2400         if (dev >= SNDRV_CARDS)
2401                 return -ENODEV;
2402         if (!enable[dev]) {
2403                 dev++;
2404                 return -ENOENT;
2405         }
2406
2407         err = snd_card_create(index[dev], id[dev], THIS_MODULE, 0, &card);
2408         if (err < 0) {
2409                 snd_printk(KERN_ERR SFX "Error creating card!\n");
2410                 return err;
2411         }
2412
2413         err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
2414         if (err < 0)
2415                 goto out_free;
2416         card->private_data = chip;
2417
2418         /* create codec instances */
2419         err = azx_codec_create(chip, model[dev], probe_only[dev]);
2420         if (err < 0)
2421                 goto out_free;
2422
2423         /* create PCM streams */
2424         err = snd_hda_build_pcms(chip->bus);
2425         if (err < 0)
2426                 goto out_free;
2427
2428         /* create mixer controls */
2429         err = azx_mixer_create(chip);
2430         if (err < 0)
2431                 goto out_free;
2432
2433         snd_card_set_dev(card, &pci->dev);
2434
2435         err = snd_card_register(card);
2436         if (err < 0)
2437                 goto out_free;
2438
2439         pci_set_drvdata(pci, card);
2440         chip->running = 1;
2441         power_down_all_codecs(chip);
2442         azx_notifier_register(chip);
2443
2444         dev++;
2445         return err;
2446 out_free:
2447         snd_card_free(card);
2448         return err;
2449 }
2450
2451 static void __devexit azx_remove(struct pci_dev *pci)
2452 {
2453         snd_card_free(pci_get_drvdata(pci));
2454         pci_set_drvdata(pci, NULL);
2455 }
2456
2457 /* PCI IDs */
2458 static struct pci_device_id azx_ids[] = {
2459         /* ICH 6..10 */
2460         { PCI_DEVICE(0x8086, 0x2668), .driver_data = AZX_DRIVER_ICH },
2461         { PCI_DEVICE(0x8086, 0x27d8), .driver_data = AZX_DRIVER_ICH },
2462         { PCI_DEVICE(0x8086, 0x269a), .driver_data = AZX_DRIVER_ICH },
2463         { PCI_DEVICE(0x8086, 0x284b), .driver_data = AZX_DRIVER_ICH },
2464         { PCI_DEVICE(0x8086, 0x2911), .driver_data = AZX_DRIVER_ICH },
2465         { PCI_DEVICE(0x8086, 0x293e), .driver_data = AZX_DRIVER_ICH },
2466         { PCI_DEVICE(0x8086, 0x293f), .driver_data = AZX_DRIVER_ICH },
2467         { PCI_DEVICE(0x8086, 0x3a3e), .driver_data = AZX_DRIVER_ICH },
2468         { PCI_DEVICE(0x8086, 0x3a6e), .driver_data = AZX_DRIVER_ICH },
2469         /* PCH */
2470         { PCI_DEVICE(0x8086, 0x3b56), .driver_data = AZX_DRIVER_ICH },
2471         /* SCH */
2472         { PCI_DEVICE(0x8086, 0x811b), .driver_data = AZX_DRIVER_SCH },
2473         /* ATI SB 450/600 */
2474         { PCI_DEVICE(0x1002, 0x437b), .driver_data = AZX_DRIVER_ATI },
2475         { PCI_DEVICE(0x1002, 0x4383), .driver_data = AZX_DRIVER_ATI },
2476         /* ATI HDMI */
2477         { PCI_DEVICE(0x1002, 0x793b), .driver_data = AZX_DRIVER_ATIHDMI },
2478         { PCI_DEVICE(0x1002, 0x7919), .driver_data = AZX_DRIVER_ATIHDMI },
2479         { PCI_DEVICE(0x1002, 0x960f), .driver_data = AZX_DRIVER_ATIHDMI },
2480         { PCI_DEVICE(0x1002, 0x970f), .driver_data = AZX_DRIVER_ATIHDMI },
2481         { PCI_DEVICE(0x1002, 0xaa00), .driver_data = AZX_DRIVER_ATIHDMI },
2482         { PCI_DEVICE(0x1002, 0xaa08), .driver_data = AZX_DRIVER_ATIHDMI },
2483         { PCI_DEVICE(0x1002, 0xaa10), .driver_data = AZX_DRIVER_ATIHDMI },
2484         { PCI_DEVICE(0x1002, 0xaa18), .driver_data = AZX_DRIVER_ATIHDMI },
2485         { PCI_DEVICE(0x1002, 0xaa20), .driver_data = AZX_DRIVER_ATIHDMI },
2486         { PCI_DEVICE(0x1002, 0xaa28), .driver_data = AZX_DRIVER_ATIHDMI },
2487         { PCI_DEVICE(0x1002, 0xaa30), .driver_data = AZX_DRIVER_ATIHDMI },
2488         { PCI_DEVICE(0x1002, 0xaa38), .driver_data = AZX_DRIVER_ATIHDMI },
2489         { PCI_DEVICE(0x1002, 0xaa40), .driver_data = AZX_DRIVER_ATIHDMI },
2490         { PCI_DEVICE(0x1002, 0xaa48), .driver_data = AZX_DRIVER_ATIHDMI },
2491         /* VIA VT8251/VT8237A */
2492         { PCI_DEVICE(0x1106, 0x3288), .driver_data = AZX_DRIVER_VIA },
2493         /* SIS966 */
2494         { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
2495         /* ULI M5461 */
2496         { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
2497         /* NVIDIA MCP */
2498         { PCI_DEVICE(0x10de, 0x026c), .driver_data = AZX_DRIVER_NVIDIA },
2499         { PCI_DEVICE(0x10de, 0x0371), .driver_data = AZX_DRIVER_NVIDIA },
2500         { PCI_DEVICE(0x10de, 0x03e4), .driver_data = AZX_DRIVER_NVIDIA },
2501         { PCI_DEVICE(0x10de, 0x03f0), .driver_data = AZX_DRIVER_NVIDIA },
2502         { PCI_DEVICE(0x10de, 0x044a), .driver_data = AZX_DRIVER_NVIDIA },
2503         { PCI_DEVICE(0x10de, 0x044b), .driver_data = AZX_DRIVER_NVIDIA },
2504         { PCI_DEVICE(0x10de, 0x055c), .driver_data = AZX_DRIVER_NVIDIA },
2505         { PCI_DEVICE(0x10de, 0x055d), .driver_data = AZX_DRIVER_NVIDIA },
2506         { PCI_DEVICE(0x10de, 0x0774), .driver_data = AZX_DRIVER_NVIDIA },
2507         { PCI_DEVICE(0x10de, 0x0775), .driver_data = AZX_DRIVER_NVIDIA },
2508         { PCI_DEVICE(0x10de, 0x0776), .driver_data = AZX_DRIVER_NVIDIA },
2509         { PCI_DEVICE(0x10de, 0x0777), .driver_data = AZX_DRIVER_NVIDIA },
2510         { PCI_DEVICE(0x10de, 0x07fc), .driver_data = AZX_DRIVER_NVIDIA },
2511         { PCI_DEVICE(0x10de, 0x07fd), .driver_data = AZX_DRIVER_NVIDIA },
2512         { PCI_DEVICE(0x10de, 0x0ac0), .driver_data = AZX_DRIVER_NVIDIA },
2513         { PCI_DEVICE(0x10de, 0x0ac1), .driver_data = AZX_DRIVER_NVIDIA },
2514         { PCI_DEVICE(0x10de, 0x0ac2), .driver_data = AZX_DRIVER_NVIDIA },
2515         { PCI_DEVICE(0x10de, 0x0ac3), .driver_data = AZX_DRIVER_NVIDIA },
2516         { PCI_DEVICE(0x10de, 0x0d94), .driver_data = AZX_DRIVER_NVIDIA },
2517         { PCI_DEVICE(0x10de, 0x0d95), .driver_data = AZX_DRIVER_NVIDIA },
2518         { PCI_DEVICE(0x10de, 0x0d96), .driver_data = AZX_DRIVER_NVIDIA },
2519         { PCI_DEVICE(0x10de, 0x0d97), .driver_data = AZX_DRIVER_NVIDIA },
2520         /* Teradici */
2521         { PCI_DEVICE(0x6549, 0x1200), .driver_data = AZX_DRIVER_TERA },
2522         /* Creative X-Fi (CA0110-IBG) */
2523 #if !defined(CONFIG_SND_CTXFI) && !defined(CONFIG_SND_CTXFI_MODULE)
2524         /* the following entry conflicts with snd-ctxfi driver,
2525          * as ctxfi driver mutates from HD-audio to native mode with
2526          * a special command sequence.
2527          */
2528         { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
2529           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2530           .class_mask = 0xffffff,
2531           .driver_data = AZX_DRIVER_GENERIC },
2532 #else
2533         /* this entry seems still valid -- i.e. without emu20kx chip */
2534         { PCI_DEVICE(0x1102, 0x0009), .driver_data = AZX_DRIVER_GENERIC },
2535 #endif
2536         /* AMD Generic, PCI class code and Vendor ID for HD Audio */
2537         { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
2538           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2539           .class_mask = 0xffffff,
2540           .driver_data = AZX_DRIVER_GENERIC },
2541         { 0, }
2542 };
2543 MODULE_DEVICE_TABLE(pci, azx_ids);
2544
2545 /* pci_driver definition */
2546 static struct pci_driver driver = {
2547         .name = "HDA Intel",
2548         .id_table = azx_ids,
2549         .probe = azx_probe,
2550         .remove = __devexit_p(azx_remove),
2551 #ifdef CONFIG_PM
2552         .suspend = azx_suspend,
2553         .resume = azx_resume,
2554 #endif
2555 };
2556
2557 static int __init alsa_card_azx_init(void)
2558 {
2559         return pci_register_driver(&driver);
2560 }
2561
2562 static void __exit alsa_card_azx_exit(void)
2563 {
2564         pci_unregister_driver(&driver);
2565 }
2566
2567 module_init(alsa_card_azx_init)
2568 module_exit(alsa_card_azx_exit)