SAFE public projects git trees. - safe/jmp/linux-2.6/blob - sound/pci/hda/hda_intel.c

   1 /*
   2  *
   3  *  hda_intel.c - Implementation of primary alsa driver code base
   4  *                for Intel HD Audio.
   5  *
   6  *  Copyright(c) 2004 Intel Corporation. All rights reserved.
   7  *
   8  *  Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
   9  *                     PeiSen Hou <pshou@realtek.com.tw>
  10  *
  11  *  This program is free software; you can redistribute it and/or modify it
  12  *  under the terms of the GNU General Public License as published by the Free
  13  *  Software Foundation; either version 2 of the License, or (at your option)
  14  *  any later version.
  15  *
  16  *  This program is distributed in the hope that it will be useful, but WITHOUT
  17  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  18  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  19  *  more details.
  20  *
  21  *  You should have received a copy of the GNU General Public License along with
  22  *  this program; if not, write to the Free Software Foundation, Inc., 59
  23  *  Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  24  *
  25  *  CONTACTS:
  26  *
  27  *  Matt Jared          matt.jared@intel.com
  28  *  Andy Kopp           andy.kopp@intel.com
  29  *  Dan Kogan           dan.d.kogan@intel.com
  30  *
  31  *  CHANGES:
  32  *
  33  *  2004.12.01  Major rewrite by tiwai, merged the work of pshou
  34  *
  35  */
  36
  37 #include <asm/io.h>
  38 #include <linux/delay.h>
  39 #include <linux/interrupt.h>
  40 #include <linux/kernel.h>
  41 #include <linux/module.h>
  42 #include <linux/moduleparam.h>
  43 #include <linux/init.h>
  44 #include <linux/slab.h>
  45 #include <linux/pci.h>
  46 #include <linux/mutex.h>
  47 #include <sound/core.h>
  48 #include <sound/initval.h>
  49 #include "hda_codec.h"
  50
  51
  52 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
  53 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
  54 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
  55 static char *model[SNDRV_CARDS];
  56 static int position_fix[SNDRV_CARDS];
  57 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
  58 static int single_cmd;
  59 static int enable_msi;
  60
  61 module_param_array(index, int, NULL, 0444);
  62 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
  63 module_param_array(id, charp, NULL, 0444);
  64 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
  65 module_param_array(enable, bool, NULL, 0444);
  66 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
  67 module_param_array(model, charp, NULL, 0444);
  68 MODULE_PARM_DESC(model, "Use the given board model.");
  69 module_param_array(position_fix, int, NULL, 0444);
  70 MODULE_PARM_DESC(position_fix, "Fix DMA pointer "
  71                  "(0 = auto, 1 = none, 2 = POSBUF, 3 = FIFO size).");
  72 module_param_array(probe_mask, int, NULL, 0444);
  73 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
  74 module_param(single_cmd, bool, 0444);
  75 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
  76                  "(for debugging only).");
  77 module_param(enable_msi, int, 0444);
  78 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
  79
  80 #ifdef CONFIG_SND_HDA_POWER_SAVE
  81 /* power_save option is defined in hda_codec.c */
  82
  83 /* reset the HD-audio controller in power save mode.
  84  * this may give more power-saving, but will take longer time to
  85  * wake up.
  86  */
  87 static int power_save_controller = 1;
  88 module_param(power_save_controller, bool, 0644);
  89 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
  90 #endif
  91
  92 MODULE_LICENSE("GPL");
  93 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
  94                          "{Intel, ICH6M},"
  95                          "{Intel, ICH7},"
  96                          "{Intel, ESB2},"
  97                          "{Intel, ICH8},"
  98                          "{Intel, ICH9},"
  99                          "{Intel, ICH10},"
 100                          "{Intel, SCH},"
 101                          "{ATI, SB450},"
 102                          "{ATI, SB600},"
 103                          "{ATI, RS600},"
 104                          "{ATI, RS690},"
 105                          "{ATI, RS780},"
 106                          "{ATI, R600},"
 107                          "{ATI, RV630},"
 108                          "{ATI, RV610},"
 109                          "{ATI, RV670},"
 110                          "{ATI, RV635},"
 111                          "{ATI, RV620},"
 112                          "{ATI, RV770},"
 113                          "{VIA, VT8251},"
 114                          "{VIA, VT8237A},"
 115                          "{SiS, SIS966},"
 116                          "{ULI, M5461}}");
 117 MODULE_DESCRIPTION("Intel HDA driver");
 118
 119 #define SFX     "hda-intel: "
 120
 121
 122 /*
 123  * registers
 124  */
 125 #define ICH6_REG_GCAP                   0x00
 126 #define ICH6_REG_VMIN                   0x02
 127 #define ICH6_REG_VMAJ                   0x03
 128 #define ICH6_REG_OUTPAY                 0x04
 129 #define ICH6_REG_INPAY                  0x06
 130 #define ICH6_REG_GCTL                   0x08
 131 #define ICH6_REG_WAKEEN                 0x0c
 132 #define ICH6_REG_STATESTS               0x0e
 133 #define ICH6_REG_GSTS                   0x10
 134 #define ICH6_REG_INTCTL                 0x20
 135 #define ICH6_REG_INTSTS                 0x24
 136 #define ICH6_REG_WALCLK                 0x30
 137 #define ICH6_REG_SYNC                   0x34
 138 #define ICH6_REG_CORBLBASE              0x40
 139 #define ICH6_REG_CORBUBASE              0x44
 140 #define ICH6_REG_CORBWP                 0x48
 141 #define ICH6_REG_CORBRP                 0x4A
 142 #define ICH6_REG_CORBCTL                0x4c
 143 #define ICH6_REG_CORBSTS                0x4d
 144 #define ICH6_REG_CORBSIZE               0x4e
 145
 146 #define ICH6_REG_RIRBLBASE              0x50
 147 #define ICH6_REG_RIRBUBASE              0x54
 148 #define ICH6_REG_RIRBWP                 0x58
 149 #define ICH6_REG_RINTCNT                0x5a
 150 #define ICH6_REG_RIRBCTL                0x5c
 151 #define ICH6_REG_RIRBSTS                0x5d
 152 #define ICH6_REG_RIRBSIZE               0x5e
 153
 154 #define ICH6_REG_IC                     0x60
 155 #define ICH6_REG_IR                     0x64
 156 #define ICH6_REG_IRS                    0x68
 157 #define   ICH6_IRS_VALID        (1<<1)
 158 #define   ICH6_IRS_BUSY         (1<<0)
 159
 160 #define ICH6_REG_DPLBASE                0x70
 161 #define ICH6_REG_DPUBASE                0x74
 162 #define   ICH6_DPLBASE_ENABLE   0x1     /* Enable position buffer */
 163
 164 /* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
 165 enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
 166
 167 /* stream register offsets from stream base */
 168 #define ICH6_REG_SD_CTL                 0x00
 169 #define ICH6_REG_SD_STS                 0x03
 170 #define ICH6_REG_SD_LPIB                0x04
 171 #define ICH6_REG_SD_CBL                 0x08
 172 #define ICH6_REG_SD_LVI                 0x0c
 173 #define ICH6_REG_SD_FIFOW               0x0e
 174 #define ICH6_REG_SD_FIFOSIZE            0x10
 175 #define ICH6_REG_SD_FORMAT              0x12
 176 #define ICH6_REG_SD_BDLPL               0x18
 177 #define ICH6_REG_SD_BDLPU               0x1c
 178
 179 /* PCI space */
 180 #define ICH6_PCIREG_TCSEL       0x44
 181
 182 /*
 183  * other constants
 184  */
 185
 186 /* max number of SDs */
 187 /* ICH, ATI and VIA have 4 playback and 4 capture */
 188 #define ICH6_NUM_CAPTURE        4
 189 #define ICH6_NUM_PLAYBACK       4
 190
 191 /* ULI has 6 playback and 5 capture */
 192 #define ULI_NUM_CAPTURE         5
 193 #define ULI_NUM_PLAYBACK        6
 194
 195 /* ATI HDMI has 1 playback and 0 capture */
 196 #define ATIHDMI_NUM_CAPTURE     0
 197 #define ATIHDMI_NUM_PLAYBACK    1
 198
 199 /* this number is statically defined for simplicity */
 200 #define MAX_AZX_DEV             16
 201
 202 /* max number of fragments - we may use more if allocating more pages for BDL */
 203 #define BDL_SIZE                4096
 204 #define AZX_MAX_BDL_ENTRIES     (BDL_SIZE / 16)
 205 #define AZX_MAX_FRAG            32
 206 /* max buffer size - no h/w limit, you can increase as you like */
 207 #define AZX_MAX_BUF_SIZE        (1024*1024*1024)
 208 /* max number of PCM devics per card */
 209 #define AZX_MAX_PCMS            8
 210
 211 /* RIRB int mask: overrun[2], response[0] */
 212 #define RIRB_INT_RESPONSE       0x01
 213 #define RIRB_INT_OVERRUN        0x04
 214 #define RIRB_INT_MASK           0x05
 215
 216 /* STATESTS int mask: SD2,SD1,SD0 */
 217 #define AZX_MAX_CODECS          3
 218 #define STATESTS_INT_MASK       0x07
 219
 220 /* SD_CTL bits */
 221 #define SD_CTL_STREAM_RESET     0x01    /* stream reset bit */
 222 #define SD_CTL_DMA_START        0x02    /* stream DMA start bit */
 223 #define SD_CTL_STREAM_TAG_MASK  (0xf << 20)
 224 #define SD_CTL_STREAM_TAG_SHIFT 20
 225
 226 /* SD_CTL and SD_STS */
 227 #define SD_INT_DESC_ERR         0x10    /* descriptor error interrupt */
 228 #define SD_INT_FIFO_ERR         0x08    /* FIFO error interrupt */
 229 #define SD_INT_COMPLETE         0x04    /* completion interrupt */
 230 #define SD_INT_MASK             (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\
 231                                  SD_INT_COMPLETE)
 232
 233 /* SD_STS */
 234 #define SD_STS_FIFO_READY       0x20    /* FIFO ready */
 235
 236 /* INTCTL and INTSTS */
 237 #define ICH6_INT_ALL_STREAM     0xff       /* all stream interrupts */
 238 #define ICH6_INT_CTRL_EN        0x40000000 /* controller interrupt enable bit */
 239 #define ICH6_INT_GLOBAL_EN      0x80000000 /* global interrupt enable bit */
 240
 241 /* GCTL unsolicited response enable bit */
 242 #define ICH6_GCTL_UREN          (1<<8)
 243
 244 /* GCTL reset bit */
 245 #define ICH6_GCTL_RESET         (1<<0)
 246
 247 /* CORB/RIRB control, read/write pointer */
 248 #define ICH6_RBCTL_DMA_EN       0x02    /* enable DMA */
 249 #define ICH6_RBCTL_IRQ_EN       0x01    /* enable IRQ */
 250 #define ICH6_RBRWP_CLR          0x8000  /* read/write pointer clear */
 251 /* below are so far hardcoded - should read registers in future */
 252 #define ICH6_MAX_CORB_ENTRIES   256
 253 #define ICH6_MAX_RIRB_ENTRIES   256
 254
 255 /* position fix mode */
 256 enum {
 257         POS_FIX_AUTO,
 258         POS_FIX_NONE,
 259         POS_FIX_POSBUF,
 260         POS_FIX_FIFO,
 261 };
 262
 263 /* Defines for ATI HD Audio support in SB450 south bridge */
 264 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR   0x42
 265 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP      0x02
 266
 267 /* Defines for Nvidia HDA support */
 268 #define NVIDIA_HDA_TRANSREG_ADDR      0x4e
 269 #define NVIDIA_HDA_ENABLE_COHBITS     0x0f
 270
 271 /* Defines for Intel SCH HDA snoop control */
 272 #define INTEL_SCH_HDA_DEVC      0x78
 273 #define INTEL_SCH_HDA_DEVC_NOSNOOP       (0x1<<11)
 274
 275
 276 /*
 277  */
 278
 279 struct azx_dev {
 280         struct snd_dma_buffer bdl; /* BDL buffer */
 281         u32 *posbuf;            /* position buffer pointer */
 282
 283         unsigned int bufsize;   /* size of the play buffer in bytes */
 284         unsigned int frags;     /* number for period in the play buffer */
 285         unsigned int fifo_size; /* FIFO size */
 286
 287         void __iomem *sd_addr;  /* stream descriptor pointer */
 288
 289         u32 sd_int_sta_mask;    /* stream int status mask */
 290
 291         /* pcm support */
 292         struct snd_pcm_substream *substream;    /* assigned substream,
 293                                                  * set in PCM open
 294                                                  */
 295         unsigned int format_val;        /* format value to be set in the
 296                                          * controller and the codec
 297                                          */
 298         unsigned char stream_tag;       /* assigned stream */
 299         unsigned char index;            /* stream index */
 300         /* for sanity check of position buffer */
 301         unsigned int period_intr;
 302
 303         unsigned int opened :1;
 304         unsigned int running :1;
 305 };
 306
 307 /* CORB/RIRB */
 308 struct azx_rb {
 309         u32 *buf;               /* CORB/RIRB buffer
 310                                  * Each CORB entry is 4byte, RIRB is 8byte
 311                                  */
 312         dma_addr_t addr;        /* physical address of CORB/RIRB buffer */
 313         /* for RIRB */
 314         unsigned short rp, wp;  /* read/write pointers */
 315         int cmds;               /* number of pending requests */
 316         u32 res;                /* last read value */
 317 };
 318
 319 struct azx {
 320         struct snd_card *card;
 321         struct pci_dev *pci;
 322
 323         /* chip type specific */
 324         int driver_type;
 325         int playback_streams;
 326         int playback_index_offset;
 327         int capture_streams;
 328         int capture_index_offset;
 329         int num_streams;
 330
 331         /* pci resources */
 332         unsigned long addr;
 333         void __iomem *remap_addr;
 334         int irq;
 335
 336         /* locks */
 337         spinlock_t reg_lock;
 338         struct mutex open_mutex;
 339
 340         /* streams (x num_streams) */
 341         struct azx_dev *azx_dev;
 342
 343         /* PCM */
 344         struct snd_pcm *pcm[AZX_MAX_PCMS];
 345
 346         /* HD codec */
 347         unsigned short codec_mask;
 348         struct hda_bus *bus;
 349
 350         /* CORB/RIRB */
 351         struct azx_rb corb;
 352         struct azx_rb rirb;
 353
 354         /* CORB/RIRB and position buffers */
 355         struct snd_dma_buffer rb;
 356         struct snd_dma_buffer posbuf;
 357
 358         /* flags */
 359         int position_fix;
 360         unsigned int running :1;
 361         unsigned int initialized :1;
 362         unsigned int single_cmd :1;
 363         unsigned int polling_mode :1;
 364         unsigned int msi :1;
 365
 366         /* for debugging */
 367         unsigned int last_cmd;  /* last issued command (to sync) */
 368 };
 369
 370 /* driver types */
 371 enum {
 372         AZX_DRIVER_ICH,
 373         AZX_DRIVER_SCH,
 374         AZX_DRIVER_ATI,
 375         AZX_DRIVER_ATIHDMI,
 376         AZX_DRIVER_VIA,
 377         AZX_DRIVER_SIS,
 378         AZX_DRIVER_ULI,
 379         AZX_DRIVER_NVIDIA,
 380 };
 381
 382 static char *driver_short_names[] __devinitdata = {
 383         [AZX_DRIVER_ICH] = "HDA Intel",
 384         [AZX_DRIVER_SCH] = "HDA Intel MID",
 385         [AZX_DRIVER_ATI] = "HDA ATI SB",
 386         [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
 387         [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
 388         [AZX_DRIVER_SIS] = "HDA SIS966",
 389         [AZX_DRIVER_ULI] = "HDA ULI M5461",
 390         [AZX_DRIVER_NVIDIA] = "HDA NVidia",
 391 };
 392
 393 /*
 394  * macros for easy use
 395  */
 396 #define azx_writel(chip,reg,value) \
 397         writel(value, (chip)->remap_addr + ICH6_REG_##reg)
 398 #define azx_readl(chip,reg) \
 399         readl((chip)->remap_addr + ICH6_REG_##reg)
 400 #define azx_writew(chip,reg,value) \
 401         writew(value, (chip)->remap_addr + ICH6_REG_##reg)
 402 #define azx_readw(chip,reg) \
 403         readw((chip)->remap_addr + ICH6_REG_##reg)
 404 #define azx_writeb(chip,reg,value) \
 405         writeb(value, (chip)->remap_addr + ICH6_REG_##reg)
 406 #define azx_readb(chip,reg) \
 407         readb((chip)->remap_addr + ICH6_REG_##reg)
 408
 409 #define azx_sd_writel(dev,reg,value) \
 410         writel(value, (dev)->sd_addr + ICH6_REG_##reg)
 411 #define azx_sd_readl(dev,reg) \
 412         readl((dev)->sd_addr + ICH6_REG_##reg)
 413 #define azx_sd_writew(dev,reg,value) \
 414         writew(value, (dev)->sd_addr + ICH6_REG_##reg)
 415 #define azx_sd_readw(dev,reg) \
 416         readw((dev)->sd_addr + ICH6_REG_##reg)
 417 #define azx_sd_writeb(dev,reg,value) \
 418         writeb(value, (dev)->sd_addr + ICH6_REG_##reg)
 419 #define azx_sd_readb(dev,reg) \
 420         readb((dev)->sd_addr + ICH6_REG_##reg)
 421
 422 /* for pcm support */
 423 #define get_azx_dev(substream) (substream->runtime->private_data)
 424
 425 /* Get the upper 32bit of the given dma_addr_t
 426  * Compiler should optimize and eliminate the code if dma_addr_t is 32bit
 427  */
 428 #define upper_32bit(addr) (sizeof(addr) > 4 ? (u32)((addr) >> 32) : (u32)0)
 429
 430 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
 431
 432 /*
 433  * Interface for HD codec
 434  */
 435
 436 /*
 437  * CORB / RIRB interface
 438  */
 439 static int azx_alloc_cmd_io(struct azx *chip)
 440 {
 441         int err;
 442
 443         /* single page (at least 4096 bytes) must suffice for both ringbuffes */
 444         err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
 445                                   snd_dma_pci_data(chip->pci),
 446                                   PAGE_SIZE, &chip->rb);
 447         if (err < 0) {
 448                 snd_printk(KERN_ERR SFX "cannot allocate CORB/RIRB\n");
 449                 return err;
 450         }
 451         return 0;
 452 }
 453
 454 static void azx_init_cmd_io(struct azx *chip)
 455 {
 456         /* CORB set up */
 457         chip->corb.addr = chip->rb.addr;
 458         chip->corb.buf = (u32 *)chip->rb.area;
 459         azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
 460         azx_writel(chip, CORBUBASE, upper_32bit(chip->corb.addr));
 461
 462         /* set the corb size to 256 entries (ULI requires explicitly) */
 463         azx_writeb(chip, CORBSIZE, 0x02);
 464         /* set the corb write pointer to 0 */
 465         azx_writew(chip, CORBWP, 0);
 466         /* reset the corb hw read pointer */
 467         azx_writew(chip, CORBRP, ICH6_RBRWP_CLR);
 468         /* enable corb dma */
 469         azx_writeb(chip, CORBCTL, ICH6_RBCTL_DMA_EN);
 470
 471         /* RIRB set up */
 472         chip->rirb.addr = chip->rb.addr + 2048;
 473         chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
 474         azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
 475         azx_writel(chip, RIRBUBASE, upper_32bit(chip->rirb.addr));
 476
 477         /* set the rirb size to 256 entries (ULI requires explicitly) */
 478         azx_writeb(chip, RIRBSIZE, 0x02);
 479         /* reset the rirb hw write pointer */
 480         azx_writew(chip, RIRBWP, ICH6_RBRWP_CLR);
 481         /* set N=1, get RIRB response interrupt for new entry */
 482         azx_writew(chip, RINTCNT, 1);
 483         /* enable rirb dma and response irq */
 484         azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN);
 485         chip->rirb.rp = chip->rirb.cmds = 0;
 486 }
 487
 488 static void azx_free_cmd_io(struct azx *chip)
 489 {
 490         /* disable ringbuffer DMAs */
 491         azx_writeb(chip, RIRBCTL, 0);
 492         azx_writeb(chip, CORBCTL, 0);
 493 }
 494
 495 /* send a command */
 496 static int azx_corb_send_cmd(struct hda_codec *codec, u32 val)
 497 {
 498         struct azx *chip = codec->bus->private_data;
 499         unsigned int wp;
 500
 501         /* add command to corb */
 502         wp = azx_readb(chip, CORBWP);
 503         wp++;
 504         wp %= ICH6_MAX_CORB_ENTRIES;
 505
 506         spin_lock_irq(&chip->reg_lock);
 507         chip->rirb.cmds++;
 508         chip->corb.buf[wp] = cpu_to_le32(val);
 509         azx_writel(chip, CORBWP, wp);
 510         spin_unlock_irq(&chip->reg_lock);
 511
 512         return 0;
 513 }
 514
 515 #define ICH6_RIRB_EX_UNSOL_EV   (1<<4)
 516
 517 /* retrieve RIRB entry - called from interrupt handler */
 518 static void azx_update_rirb(struct azx *chip)
 519 {
 520         unsigned int rp, wp;
 521         u32 res, res_ex;
 522
 523         wp = azx_readb(chip, RIRBWP);
 524         if (wp == chip->rirb.wp)
 525                 return;
 526         chip->rirb.wp = wp;
 527
 528         while (chip->rirb.rp != wp) {
 529                 chip->rirb.rp++;
 530                 chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES;
 531
 532                 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
 533                 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
 534                 res = le32_to_cpu(chip->rirb.buf[rp]);
 535                 if (res_ex & ICH6_RIRB_EX_UNSOL_EV)
 536                         snd_hda_queue_unsol_event(chip->bus, res, res_ex);
 537                 else if (chip->rirb.cmds) {
 538                         chip->rirb.cmds--;
 539                         chip->rirb.res = res;
 540                 }
 541         }
 542 }
 543
 544 /* receive a response */
 545 static unsigned int azx_rirb_get_response(struct hda_codec *codec)
 546 {
 547         struct azx *chip = codec->bus->private_data;
 548         unsigned long timeout;
 549
 550  again:
 551         timeout = jiffies + msecs_to_jiffies(1000);
 552         for (;;) {
 553                 if (chip->polling_mode) {
 554                         spin_lock_irq(&chip->reg_lock);
 555                         azx_update_rirb(chip);
 556                         spin_unlock_irq(&chip->reg_lock);
 557                 }
 558                 if (!chip->rirb.cmds)
 559                         return chip->rirb.res; /* the last value */
 560                 if (time_after(jiffies, timeout))
 561                         break;
 562                 if (codec->bus->needs_damn_long_delay)
 563                         msleep(2); /* temporary workaround */
 564                 else {
 565                         udelay(10);
 566                         cond_resched();
 567                 }
 568         }
 569
 570         if (chip->msi) {
 571                 snd_printk(KERN_WARNING "hda_intel: No response from codec, "
 572                            "disabling MSI: last cmd=0x%08x\n", chip->last_cmd);
 573                 free_irq(chip->irq, chip);
 574                 chip->irq = -1;
 575                 pci_disable_msi(chip->pci);
 576                 chip->msi = 0;
 577                 if (azx_acquire_irq(chip, 1) < 0)
 578                         return -1;
 579                 goto again;
 580         }
 581
 582         if (!chip->polling_mode) {
 583                 snd_printk(KERN_WARNING "hda_intel: azx_get_response timeout, "
 584                            "switching to polling mode: last cmd=0x%08x\n",
 585                            chip->last_cmd);
 586                 chip->polling_mode = 1;
 587                 goto again;
 588         }
 589
 590         snd_printk(KERN_ERR "hda_intel: azx_get_response timeout, "
 591                    "switching to single_cmd mode: last cmd=0x%08x\n",
 592                    chip->last_cmd);
 593         chip->rirb.rp = azx_readb(chip, RIRBWP);
 594         chip->rirb.cmds = 0;
 595         /* switch to single_cmd mode */
 596         chip->single_cmd = 1;
 597         azx_free_cmd_io(chip);
 598         return -1;
 599 }
 600
 601 /*
 602  * Use the single immediate command instead of CORB/RIRB for simplicity
 603  *
 604  * Note: according to Intel, this is not preferred use.  The command was
 605  *       intended for the BIOS only, and may get confused with unsolicited
 606  *       responses.  So, we shouldn't use it for normal operation from the
 607  *       driver.
 608  *       I left the codes, however, for debugging/testing purposes.
 609  */
 610
 611 /* send a command */
 612 static int azx_single_send_cmd(struct hda_codec *codec, u32 val)
 613 {
 614         struct azx *chip = codec->bus->private_data;
 615         int timeout = 50;
 616
 617         while (timeout--) {
 618                 /* check ICB busy bit */
 619                 if (!((azx_readw(chip, IRS) & ICH6_IRS_BUSY))) {
 620                         /* Clear IRV valid bit */
 621                         azx_writew(chip, IRS, azx_readw(chip, IRS) |
 622                                    ICH6_IRS_VALID);
 623                         azx_writel(chip, IC, val);
 624                         azx_writew(chip, IRS, azx_readw(chip, IRS) |
 625                                    ICH6_IRS_BUSY);
 626                         return 0;
 627                 }
 628                 udelay(1);
 629         }
 630         if (printk_ratelimit())
 631                 snd_printd(SFX "send_cmd timeout: IRS=0x%x, val=0x%x\n",
 632                            azx_readw(chip, IRS), val);
 633         return -EIO;
 634 }
 635
 636 /* receive a response */
 637 static unsigned int azx_single_get_response(struct hda_codec *codec)
 638 {
 639         struct azx *chip = codec->bus->private_data;
 640         int timeout = 50;
 641
 642         while (timeout--) {
 643                 /* check IRV busy bit */
 644                 if (azx_readw(chip, IRS) & ICH6_IRS_VALID)
 645                         return azx_readl(chip, IR);
 646                 udelay(1);
 647         }
 648         if (printk_ratelimit())
 649                 snd_printd(SFX "get_response timeout: IRS=0x%x\n",
 650                            azx_readw(chip, IRS));
 651         return (unsigned int)-1;
 652 }
 653
 654 /*
 655  * The below are the main callbacks from hda_codec.
 656  *
 657  * They are just the skeleton to call sub-callbacks according to the
 658  * current setting of chip->single_cmd.
 659  */
 660
 661 /* send a command */
 662 static int azx_send_cmd(struct hda_codec *codec, hda_nid_t nid,
 663                         int direct, unsigned int verb,
 664                         unsigned int para)
 665 {
 666         struct azx *chip = codec->bus->private_data;
 667         u32 val;
 668
 669         val = (u32)(codec->addr & 0x0f) << 28;
 670         val |= (u32)direct << 27;
 671         val |= (u32)nid << 20;
 672         val |= verb << 8;
 673         val |= para;
 674         chip->last_cmd = val;
 675
 676         if (chip->single_cmd)
 677                 return azx_single_send_cmd(codec, val);
 678         else
 679                 return azx_corb_send_cmd(codec, val);
 680 }
 681
 682 /* get a response */
 683 static unsigned int azx_get_response(struct hda_codec *codec)
 684 {
 685         struct azx *chip = codec->bus->private_data;
 686         if (chip->single_cmd)
 687                 return azx_single_get_response(codec);
 688         else
 689                 return azx_rirb_get_response(codec);
 690 }
 691
 692 #ifdef CONFIG_SND_HDA_POWER_SAVE
 693 static void azx_power_notify(struct hda_codec *codec);
 694 #endif
 695
 696 /* reset codec link */
 697 static int azx_reset(struct azx *chip)
 698 {
 699         int count;
 700
 701         /* clear STATESTS */
 702         azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
 703
 704         /* reset controller */
 705         azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);
 706
 707         count = 50;
 708         while (azx_readb(chip, GCTL) && --count)
 709                 msleep(1);
 710
 711         /* delay for >= 100us for codec PLL to settle per spec
 712          * Rev 0.9 section 5.5.1
 713          */
 714         msleep(1);
 715
 716         /* Bring controller out of reset */
 717         azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET);
 718
 719         count = 50;
 720         while (!azx_readb(chip, GCTL) && --count)
 721                 msleep(1);
 722
 723         /* Brent Chartrand said to wait >= 540us for codecs to initialize */
 724         msleep(1);
 725
 726         /* check to see if controller is ready */
 727         if (!azx_readb(chip, GCTL)) {
 728                 snd_printd("azx_reset: controller not ready!\n");
 729                 return -EBUSY;
 730         }
 731
 732         /* Accept unsolicited responses */
 733         azx_writel(chip, GCTL, azx_readl(chip, GCTL) | ICH6_GCTL_UREN);
 734
 735         /* detect codecs */
 736         if (!chip->codec_mask) {
 737                 chip->codec_mask = azx_readw(chip, STATESTS);
 738                 snd_printdd("codec_mask = 0x%x\n", chip->codec_mask);
 739         }
 740
 741         return 0;
 742 }
 743
 744
 745 /*
 746  * Lowlevel interface
 747  */
 748
 749 /* enable interrupts */
 750 static void azx_int_enable(struct azx *chip)
 751 {
 752         /* enable controller CIE and GIE */
 753         azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
 754                    ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN);
 755 }
 756
 757 /* disable interrupts */
 758 static void azx_int_disable(struct azx *chip)
 759 {
 760         int i;
 761
 762         /* disable interrupts in stream descriptor */
 763         for (i = 0; i < chip->num_streams; i++) {
 764                 struct azx_dev *azx_dev = &chip->azx_dev[i];
 765                 azx_sd_writeb(azx_dev, SD_CTL,
 766                               azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK);
 767         }
 768
 769         /* disable SIE for all streams */
 770         azx_writeb(chip, INTCTL, 0);
 771
 772         /* disable controller CIE and GIE */
 773         azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
 774                    ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN));
 775 }
 776
 777 /* clear interrupts */
 778 static void azx_int_clear(struct azx *chip)
 779 {
 780         int i;
 781
 782         /* clear stream status */
 783         for (i = 0; i < chip->num_streams; i++) {
 784                 struct azx_dev *azx_dev = &chip->azx_dev[i];
 785                 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
 786         }
 787
 788         /* clear STATESTS */
 789         azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
 790
 791         /* clear rirb status */
 792         azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
 793
 794         /* clear int status */
 795         azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM);
 796 }
 797
 798 /* start a stream */
 799 static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev)
 800 {
 801         /* enable SIE */
 802         azx_writeb(chip, INTCTL,
 803                    azx_readb(chip, INTCTL) | (1 << azx_dev->index));
 804         /* set DMA start and interrupt mask */
 805         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
 806                       SD_CTL_DMA_START | SD_INT_MASK);
 807 }
 808
 809 /* stop a stream */
 810 static void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev)
 811 {
 812         /* stop DMA */
 813         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
 814                       ~(SD_CTL_DMA_START | SD_INT_MASK));
 815         azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
 816         /* disable SIE */
 817         azx_writeb(chip, INTCTL,
 818                    azx_readb(chip, INTCTL) & ~(1 << azx_dev->index));
 819 }
 820
 821
 822 /*
 823  * reset and start the controller registers
 824  */
 825 static void azx_init_chip(struct azx *chip)
 826 {
 827         if (chip->initialized)
 828                 return;
 829
 830         /* reset controller */
 831         azx_reset(chip);
 832
 833         /* initialize interrupts */
 834         azx_int_clear(chip);
 835         azx_int_enable(chip);
 836
 837         /* initialize the codec command I/O */
 838         if (!chip->single_cmd)
 839                 azx_init_cmd_io(chip);
 840
 841         /* program the position buffer */
 842         azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
 843         azx_writel(chip, DPUBASE, upper_32bit(chip->posbuf.addr));
 844
 845         chip->initialized = 1;
 846 }
 847
 848 /*
 849  * initialize the PCI registers
 850  */
 851 /* update bits in a PCI register byte */
 852 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
 853                             unsigned char mask, unsigned char val)
 854 {
 855         unsigned char data;
 856
 857         pci_read_config_byte(pci, reg, &data);
 858         data &= ~mask;
 859         data |= (val & mask);
 860         pci_write_config_byte(pci, reg, data);
 861 }
 862
 863 static void azx_init_pci(struct azx *chip)
 864 {
 865         unsigned short snoop;
 866
 867         /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
 868          * TCSEL == Traffic Class Select Register, which sets PCI express QOS
 869          * Ensuring these bits are 0 clears playback static on some HD Audio
 870          * codecs
 871          */
 872         update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0);
 873
 874         switch (chip->driver_type) {
 875         case AZX_DRIVER_ATI:
 876                 /* For ATI SB450 azalia HD audio, we need to enable snoop */
 877                 update_pci_byte(chip->pci,
 878                                 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR,
 879                                 0x07, ATI_SB450_HDAUDIO_ENABLE_SNOOP);
 880                 break;
 881         case AZX_DRIVER_NVIDIA:
 882                 /* For NVIDIA HDA, enable snoop */
 883                 update_pci_byte(chip->pci,
 884                                 NVIDIA_HDA_TRANSREG_ADDR,
 885                                 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
 886                 break;
 887         case AZX_DRIVER_SCH:
 888                 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
 889                 if (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) {
 890                         pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, \
 891                                 snoop & (~INTEL_SCH_HDA_DEVC_NOSNOOP));
 892                         pci_read_config_word(chip->pci,
 893                                 INTEL_SCH_HDA_DEVC, &snoop);
 894                         snd_printdd("HDA snoop disabled, enabling ... %s\n",\
 895                                 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) \
 896                                 ? "Failed" : "OK");
 897                 }
 898                 break;
 899
 900         }
 901 }
 902
 903
 904 /*
 905  * interrupt handler
 906  */
 907 static irqreturn_t azx_interrupt(int irq, void *dev_id)
 908 {
 909         struct azx *chip = dev_id;
 910         struct azx_dev *azx_dev;
 911         u32 status;
 912         int i;
 913
 914         spin_lock(&chip->reg_lock);
 915
 916         status = azx_readl(chip, INTSTS);
 917         if (status == 0) {
 918                 spin_unlock(&chip->reg_lock);
 919                 return IRQ_NONE;
 920         }
 921
 922         for (i = 0; i < chip->num_streams; i++) {
 923                 azx_dev = &chip->azx_dev[i];
 924                 if (status & azx_dev->sd_int_sta_mask) {
 925                         azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
 926                         if (azx_dev->substream && azx_dev->running) {
 927                                 azx_dev->period_intr++;
 928                                 spin_unlock(&chip->reg_lock);
 929                                 snd_pcm_period_elapsed(azx_dev->substream);
 930                                 spin_lock(&chip->reg_lock);
 931                         }
 932                 }
 933         }
 934
 935         /* clear rirb int */
 936         status = azx_readb(chip, RIRBSTS);
 937         if (status & RIRB_INT_MASK) {
 938                 if (!chip->single_cmd && (status & RIRB_INT_RESPONSE))
 939                         azx_update_rirb(chip);
 940                 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
 941         }
 942
 943 #if 0
 944         /* clear state status int */
 945         if (azx_readb(chip, STATESTS) & 0x04)
 946                 azx_writeb(chip, STATESTS, 0x04);
 947 #endif
 948         spin_unlock(&chip->reg_lock);
 949
 950         return IRQ_HANDLED;
 951 }
 952
 953
 954 /*
 955  * set up BDL entries
 956  */
 957 static int azx_setup_periods(struct snd_pcm_substream *substream,
 958                              struct azx_dev *azx_dev)
 959 {
 960         struct snd_sg_buf *sgbuf = snd_pcm_substream_sgbuf(substream);
 961         u32 *bdl;
 962         int i, ofs, periods, period_bytes;
 963
 964         /* reset BDL address */
 965         azx_sd_writel(azx_dev, SD_BDLPL, 0);
 966         azx_sd_writel(azx_dev, SD_BDLPU, 0);
 967
 968         period_bytes = snd_pcm_lib_period_bytes(substream);
 969         periods = azx_dev->bufsize / period_bytes;
 970
 971         /* program the initial BDL entries */
 972         bdl = (u32 *)azx_dev->bdl.area;
 973         ofs = 0;
 974         azx_dev->frags = 0;
 975         for (i = 0; i < periods; i++) {
 976                 int size, rest;
 977                 if (i >= AZX_MAX_BDL_ENTRIES) {
 978                         snd_printk(KERN_ERR "Too many BDL entries: "
 979                                    "buffer=%d, period=%d\n",
 980                                    azx_dev->bufsize, period_bytes);
 981                         /* reset */
 982                         azx_sd_writel(azx_dev, SD_BDLPL, 0);
 983                         azx_sd_writel(azx_dev, SD_BDLPU, 0);
 984                         return -EINVAL;
 985                 }
 986                 rest = period_bytes;
 987                 do {
 988                         dma_addr_t addr = snd_pcm_sgbuf_get_addr(sgbuf, ofs);
 989                         /* program the address field of the BDL entry */
 990                         bdl[0] = cpu_to_le32((u32)addr);
 991                         bdl[1] = cpu_to_le32(upper_32bit(addr));
 992                         /* program the size field of the BDL entry */
 993                         size = PAGE_SIZE - (ofs % PAGE_SIZE);
 994                         if (rest < size)
 995                                 size = rest;
 996                         bdl[2] = cpu_to_le32(size);
 997                         /* program the IOC to enable interrupt
 998                          * only when the whole fragment is processed
 999                          */
1000                         rest -= size;
1001                         bdl[3] = rest ? 0 : cpu_to_le32(0x01);
1002                         bdl += 4;
1003                         azx_dev->frags++;
1004                         ofs += size;
1005                 } while (rest > 0);
1006         }
1007         return 0;
1008 }
1009
1010 /*
1011  * set up the SD for streaming
1012  */
1013 static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev)
1014 {
1015         unsigned char val;
1016         int timeout;
1017
1018         /* make sure the run bit is zero for SD */
1019         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
1020                       ~SD_CTL_DMA_START);
1021         /* reset stream */
1022         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1023                       SD_CTL_STREAM_RESET);
1024         udelay(3);
1025         timeout = 300;
1026         while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1027                --timeout)
1028                 ;
1029         val &= ~SD_CTL_STREAM_RESET;
1030         azx_sd_writeb(azx_dev, SD_CTL, val);
1031         udelay(3);
1032
1033         timeout = 300;
1034         /* waiting for hardware to report that the stream is out of reset */
1035         while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1036                --timeout)
1037                 ;
1038
1039         /* program the stream_tag */
1040         azx_sd_writel(azx_dev, SD_CTL,
1041                       (azx_sd_readl(azx_dev, SD_CTL) & ~SD_CTL_STREAM_TAG_MASK)|
1042                       (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT));
1043
1044         /* program the length of samples in cyclic buffer */
1045         azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize);
1046
1047         /* program the stream format */
1048         /* this value needs to be the same as the one programmed */
1049         azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
1050
1051         /* program the stream LVI (last valid index) of the BDL */
1052         azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
1053
1054         /* program the BDL address */
1055         /* lower BDL address */
1056         azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
1057         /* upper BDL address */
1058         azx_sd_writel(azx_dev, SD_BDLPU, upper_32bit(azx_dev->bdl.addr));
1059
1060         /* enable the position buffer */
1061         if (!(azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE))
1062                 azx_writel(chip, DPLBASE,
1063                            (u32)chip->posbuf.addr |ICH6_DPLBASE_ENABLE);
1064
1065         /* set the interrupt enable bits in the descriptor control register */
1066         azx_sd_writel(azx_dev, SD_CTL,
1067                       azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK);
1068
1069         return 0;
1070 }
1071
1072
1073 /*
1074  * Codec initialization
1075  */
1076
1077 static unsigned int azx_max_codecs[] __devinitdata = {
1078         [AZX_DRIVER_ICH] = 3,
1079         [AZX_DRIVER_SCH] = 3,
1080         [AZX_DRIVER_ATI] = 4,
1081         [AZX_DRIVER_ATIHDMI] = 4,
1082         [AZX_DRIVER_VIA] = 3,           /* FIXME: correct? */
1083         [AZX_DRIVER_SIS] = 3,           /* FIXME: correct? */
1084         [AZX_DRIVER_ULI] = 3,           /* FIXME: correct? */
1085         [AZX_DRIVER_NVIDIA] = 3,        /* FIXME: correct? */
1086 };
1087
1088 static int __devinit azx_codec_create(struct azx *chip, const char *model,
1089                                       unsigned int codec_probe_mask)
1090 {
1091         struct hda_bus_template bus_temp;
1092         int c, codecs, audio_codecs, err;
1093
1094         memset(&bus_temp, 0, sizeof(bus_temp));
1095         bus_temp.private_data = chip;
1096         bus_temp.modelname = model;
1097         bus_temp.pci = chip->pci;
1098         bus_temp.ops.command = azx_send_cmd;
1099         bus_temp.ops.get_response = azx_get_response;
1100 #ifdef CONFIG_SND_HDA_POWER_SAVE
1101         bus_temp.ops.pm_notify = azx_power_notify;
1102 #endif
1103
1104         err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus);
1105         if (err < 0)
1106                 return err;
1107
1108         codecs = audio_codecs = 0;
1109         for (c = 0; c < AZX_MAX_CODECS; c++) {
1110                 if ((chip->codec_mask & (1 << c)) & codec_probe_mask) {
1111                         struct hda_codec *codec;
1112                         err = snd_hda_codec_new(chip->bus, c, &codec);
1113                         if (err < 0)
1114                                 continue;
1115                         codecs++;
1116                         if (codec->afg)
1117                                 audio_codecs++;
1118                 }
1119         }
1120         if (!audio_codecs) {
1121                 /* probe additional slots if no codec is found */
1122                 for (; c < azx_max_codecs[chip->driver_type]; c++) {
1123                         if ((chip->codec_mask & (1 << c)) & codec_probe_mask) {
1124                                 err = snd_hda_codec_new(chip->bus, c, NULL);
1125                                 if (err < 0)
1126                                         continue;
1127                                 codecs++;
1128                         }
1129                 }
1130         }
1131         if (!codecs) {
1132                 snd_printk(KERN_ERR SFX "no codecs initialized\n");
1133                 return -ENXIO;
1134         }
1135
1136         return 0;
1137 }
1138
1139
1140 /*
1141  * PCM support
1142  */
1143
1144 /* assign a stream for the PCM */
1145 static inline struct azx_dev *azx_assign_device(struct azx *chip, int stream)
1146 {
1147         int dev, i, nums;
1148         if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
1149                 dev = chip->playback_index_offset;
1150                 nums = chip->playback_streams;
1151         } else {
1152                 dev = chip->capture_index_offset;
1153                 nums = chip->capture_streams;
1154         }
1155         for (i = 0; i < nums; i++, dev++)
1156                 if (!chip->azx_dev[dev].opened) {
1157                         chip->azx_dev[dev].opened = 1;
1158                         return &chip->azx_dev[dev];
1159                 }
1160         return NULL;
1161 }
1162
1163 /* release the assigned stream */
1164 static inline void azx_release_device(struct azx_dev *azx_dev)
1165 {
1166         azx_dev->opened = 0;
1167 }
1168
1169 static struct snd_pcm_hardware azx_pcm_hw = {
1170         .info =                 (SNDRV_PCM_INFO_MMAP |
1171                                  SNDRV_PCM_INFO_INTERLEAVED |
1172                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
1173                                  SNDRV_PCM_INFO_MMAP_VALID |
1174                                  /* No full-resume yet implemented */
1175                                  /* SNDRV_PCM_INFO_RESUME |*/
1176                                  SNDRV_PCM_INFO_PAUSE),
1177         .formats =              SNDRV_PCM_FMTBIT_S16_LE,
1178         .rates =                SNDRV_PCM_RATE_48000,
1179         .rate_min =             48000,
1180         .rate_max =             48000,
1181         .channels_min =         2,
1182         .channels_max =         2,
1183         .buffer_bytes_max =     AZX_MAX_BUF_SIZE,
1184         .period_bytes_min =     128,
1185         .period_bytes_max =     AZX_MAX_BUF_SIZE / 2,
1186         .periods_min =          2,
1187         .periods_max =          AZX_MAX_FRAG,
1188         .fifo_size =            0,
1189 };
1190
1191 struct azx_pcm {
1192         struct azx *chip;
1193         struct hda_codec *codec;
1194         struct hda_pcm_stream *hinfo[2];
1195 };
1196
1197 static int azx_pcm_open(struct snd_pcm_substream *substream)
1198 {
1199         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1200         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1201         struct azx *chip = apcm->chip;
1202         struct azx_dev *azx_dev;
1203         struct snd_pcm_runtime *runtime = substream->runtime;
1204         unsigned long flags;
1205         int err;
1206
1207         mutex_lock(&chip->open_mutex);
1208         azx_dev = azx_assign_device(chip, substream->stream);
1209         if (azx_dev == NULL) {
1210                 mutex_unlock(&chip->open_mutex);
1211                 return -EBUSY;
1212         }
1213         runtime->hw = azx_pcm_hw;
1214         runtime->hw.channels_min = hinfo->channels_min;
1215         runtime->hw.channels_max = hinfo->channels_max;
1216         runtime->hw.formats = hinfo->formats;
1217         runtime->hw.rates = hinfo->rates;
1218         snd_pcm_limit_hw_rates(runtime);
1219         snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
1220         snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
1221                                    128);
1222         snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1223                                    128);
1224         snd_hda_power_up(apcm->codec);
1225         err = hinfo->ops.open(hinfo, apcm->codec, substream);
1226         if (err < 0) {
1227                 azx_release_device(azx_dev);
1228                 snd_hda_power_down(apcm->codec);
1229                 mutex_unlock(&chip->open_mutex);
1230                 return err;
1231         }
1232         spin_lock_irqsave(&chip->reg_lock, flags);
1233         azx_dev->substream = substream;
1234         azx_dev->running = 0;
1235         spin_unlock_irqrestore(&chip->reg_lock, flags);
1236
1237         runtime->private_data = azx_dev;
1238         mutex_unlock(&chip->open_mutex);
1239         return 0;
1240 }
1241
1242 static int azx_pcm_close(struct snd_pcm_substream *substream)
1243 {
1244         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1245         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1246         struct azx *chip = apcm->chip;
1247         struct azx_dev *azx_dev = get_azx_dev(substream);
1248         unsigned long flags;
1249
1250         mutex_lock(&chip->open_mutex);
1251         spin_lock_irqsave(&chip->reg_lock, flags);
1252         azx_dev->substream = NULL;
1253         azx_dev->running = 0;
1254         spin_unlock_irqrestore(&chip->reg_lock, flags);
1255         azx_release_device(azx_dev);
1256         hinfo->ops.close(hinfo, apcm->codec, substream);
1257         snd_hda_power_down(apcm->codec);
1258         mutex_unlock(&chip->open_mutex);
1259         return 0;
1260 }
1261
1262 static int azx_pcm_hw_params(struct snd_pcm_substream *substream,
1263                              struct snd_pcm_hw_params *hw_params)
1264 {
1265         return snd_pcm_lib_malloc_pages(substream,
1266                                         params_buffer_bytes(hw_params));
1267 }
1268
1269 static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
1270 {
1271         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1272         struct azx_dev *azx_dev = get_azx_dev(substream);
1273         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1274
1275         /* reset BDL address */
1276         azx_sd_writel(azx_dev, SD_BDLPL, 0);
1277         azx_sd_writel(azx_dev, SD_BDLPU, 0);
1278         azx_sd_writel(azx_dev, SD_CTL, 0);
1279
1280         hinfo->ops.cleanup(hinfo, apcm->codec, substream);
1281
1282         return snd_pcm_lib_free_pages(substream);
1283 }
1284
1285 static int azx_pcm_prepare(struct snd_pcm_substream *substream)
1286 {
1287         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1288         struct azx *chip = apcm->chip;
1289         struct azx_dev *azx_dev = get_azx_dev(substream);
1290         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1291         struct snd_pcm_runtime *runtime = substream->runtime;
1292
1293         azx_dev->bufsize = snd_pcm_lib_buffer_bytes(substream);
1294         azx_dev->format_val = snd_hda_calc_stream_format(runtime->rate,
1295                                                          runtime->channels,
1296                                                          runtime->format,
1297                                                          hinfo->maxbps);
1298         if (!azx_dev->format_val) {
1299                 snd_printk(KERN_ERR SFX
1300                            "invalid format_val, rate=%d, ch=%d, format=%d\n",
1301                            runtime->rate, runtime->channels, runtime->format);
1302                 return -EINVAL;
1303         }
1304
1305         snd_printdd("azx_pcm_prepare: bufsize=0x%x, format=0x%x\n",
1306                     azx_dev->bufsize, azx_dev->format_val);
1307         if (azx_setup_periods(substream, azx_dev) < 0)
1308                 return -EINVAL;
1309         azx_setup_controller(chip, azx_dev);
1310         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1311                 azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1;
1312         else
1313                 azx_dev->fifo_size = 0;
1314
1315         return hinfo->ops.prepare(hinfo, apcm->codec, azx_dev->stream_tag,
1316                                   azx_dev->format_val, substream);
1317 }
1318
1319 static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
1320 {
1321         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1322         struct azx_dev *azx_dev = get_azx_dev(substream);
1323         struct azx *chip = apcm->chip;
1324         int err = 0;
1325
1326         spin_lock(&chip->reg_lock);
1327         switch (cmd) {
1328         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1329         case SNDRV_PCM_TRIGGER_RESUME:
1330         case SNDRV_PCM_TRIGGER_START:
1331                 azx_stream_start(chip, azx_dev);
1332                 azx_dev->running = 1;
1333                 break;
1334         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1335         case SNDRV_PCM_TRIGGER_SUSPEND:
1336         case SNDRV_PCM_TRIGGER_STOP:
1337                 azx_stream_stop(chip, azx_dev);
1338                 azx_dev->running = 0;
1339                 break;
1340         default:
1341                 err = -EINVAL;
1342         }
1343         spin_unlock(&chip->reg_lock);
1344         if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH ||
1345             cmd == SNDRV_PCM_TRIGGER_SUSPEND ||
1346             cmd == SNDRV_PCM_TRIGGER_STOP) {
1347                 int timeout = 5000;
1348                 while ((azx_sd_readb(azx_dev, SD_CTL) & SD_CTL_DMA_START) &&
1349                        --timeout)
1350                         ;
1351         }
1352         return err;
1353 }
1354
1355 static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
1356 {
1357         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1358         struct azx *chip = apcm->chip;
1359         struct azx_dev *azx_dev = get_azx_dev(substream);
1360         unsigned int pos;
1361
1362         if (chip->position_fix == POS_FIX_POSBUF ||
1363             chip->position_fix == POS_FIX_AUTO) {
1364                 /* use the position buffer */
1365                 pos = le32_to_cpu(*azx_dev->posbuf);
1366                 if (chip->position_fix == POS_FIX_AUTO &&
1367                     azx_dev->period_intr == 1 && !pos) {
1368                         printk(KERN_WARNING
1369                                "hda-intel: Invalid position buffer, "
1370                                "using LPIB read method instead.\n");
1371                         chip->position_fix = POS_FIX_NONE;
1372                         goto read_lpib;
1373                 }
1374         } else {
1375         read_lpib:
1376                 /* read LPIB */
1377                 pos = azx_sd_readl(azx_dev, SD_LPIB);
1378                 if (chip->position_fix == POS_FIX_FIFO)
1379                         pos += azx_dev->fifo_size;
1380         }
1381         if (pos >= azx_dev->bufsize)
1382                 pos = 0;
1383         return bytes_to_frames(substream->runtime, pos);
1384 }
1385
1386 static struct snd_pcm_ops azx_pcm_ops = {
1387         .open = azx_pcm_open,
1388         .close = azx_pcm_close,
1389         .ioctl = snd_pcm_lib_ioctl,
1390         .hw_params = azx_pcm_hw_params,
1391         .hw_free = azx_pcm_hw_free,
1392         .prepare = azx_pcm_prepare,
1393         .trigger = azx_pcm_trigger,
1394         .pointer = azx_pcm_pointer,
1395         .page = snd_pcm_sgbuf_ops_page,
1396 };
1397
1398 static void azx_pcm_free(struct snd_pcm *pcm)
1399 {
1400         kfree(pcm->private_data);
1401 }
1402
1403 static int __devinit create_codec_pcm(struct azx *chip, struct hda_codec *codec,
1404                                       struct hda_pcm *cpcm)
1405 {
1406         int err;
1407         struct snd_pcm *pcm;
1408         struct azx_pcm *apcm;
1409
1410         /* if no substreams are defined for both playback and capture,
1411          * it's just a placeholder.  ignore it.
1412          */
1413         if (!cpcm->stream[0].substreams && !cpcm->stream[1].substreams)
1414                 return 0;
1415
1416         snd_assert(cpcm->name, return -EINVAL);
1417
1418         err = snd_pcm_new(chip->card, cpcm->name, cpcm->device,
1419                           cpcm->stream[0].substreams,
1420                           cpcm->stream[1].substreams,
1421                           &pcm);
1422         if (err < 0)
1423                 return err;
1424         strcpy(pcm->name, cpcm->name);
1425         apcm = kmalloc(sizeof(*apcm), GFP_KERNEL);
1426         if (apcm == NULL)
1427                 return -ENOMEM;
1428         apcm->chip = chip;
1429         apcm->codec = codec;
1430         apcm->hinfo[0] = &cpcm->stream[0];
1431         apcm->hinfo[1] = &cpcm->stream[1];
1432         pcm->private_data = apcm;
1433         pcm->private_free = azx_pcm_free;
1434         if (cpcm->stream[0].substreams)
1435                 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &azx_pcm_ops);
1436         if (cpcm->stream[1].substreams)
1437                 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &azx_pcm_ops);
1438         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV_SG,
1439                                               snd_dma_pci_data(chip->pci),
1440                                               1024 * 64, 1024 * 1024);
1441         chip->pcm[cpcm->device] = pcm;
1442         return 0;
1443 }
1444
1445 static int __devinit azx_pcm_create(struct azx *chip)
1446 {
1447         static const char *dev_name[HDA_PCM_NTYPES] = {
1448                 "Audio", "SPDIF", "HDMI", "Modem"
1449         };
1450         /* starting device index for each PCM type */
1451         static int dev_idx[HDA_PCM_NTYPES] = {
1452                 [HDA_PCM_TYPE_AUDIO] = 0,
1453                 [HDA_PCM_TYPE_SPDIF] = 1,
1454                 [HDA_PCM_TYPE_HDMI] = 3,
1455                 [HDA_PCM_TYPE_MODEM] = 6
1456         };
1457         /* normal audio device indices; not linear to keep compatibility */
1458         static int audio_idx[4] = { 0, 2, 4, 5 };
1459         struct hda_codec *codec;
1460         int c, err;
1461         int num_devs[HDA_PCM_NTYPES];
1462
1463         err = snd_hda_build_pcms(chip->bus);
1464         if (err < 0)
1465                 return err;
1466
1467         /* create audio PCMs */
1468         memset(num_devs, 0, sizeof(num_devs));
1469         list_for_each_entry(codec, &chip->bus->codec_list, list) {
1470                 for (c = 0; c < codec->num_pcms; c++) {
1471                         struct hda_pcm *cpcm = &codec->pcm_info[c];
1472                         int type = cpcm->pcm_type;
1473                         switch (type) {
1474                         case HDA_PCM_TYPE_AUDIO:
1475                                 if (num_devs[type] >= ARRAY_SIZE(audio_idx)) {
1476                                         snd_printk(KERN_WARNING
1477                                                    "Too many audio devices\n");
1478                                         continue;
1479                                 }
1480                                 cpcm->device = audio_idx[num_devs[type]];
1481                                 break;
1482                         case HDA_PCM_TYPE_SPDIF:
1483                         case HDA_PCM_TYPE_HDMI:
1484                         case HDA_PCM_TYPE_MODEM:
1485                                 if (num_devs[type]) {
1486                                         snd_printk(KERN_WARNING
1487                                                    "%s already defined\n",
1488                                                    dev_name[type]);
1489                                         continue;
1490                                 }
1491                                 cpcm->device = dev_idx[type];
1492                                 break;
1493                         default:
1494                                 snd_printk(KERN_WARNING
1495                                            "Invalid PCM type %d\n", type);
1496                                 continue;
1497                         }
1498                         num_devs[type]++;
1499                         err = create_codec_pcm(chip, codec, cpcm);
1500                         if (err < 0)
1501                                 return err;
1502                 }
1503         }
1504         return 0;
1505 }
1506
1507 /*
1508  * mixer creation - all stuff is implemented in hda module
1509  */
1510 static int __devinit azx_mixer_create(struct azx *chip)
1511 {
1512         return snd_hda_build_controls(chip->bus);
1513 }
1514
1515
1516 /*
1517  * initialize SD streams
1518  */
1519 static int __devinit azx_init_stream(struct azx *chip)
1520 {
1521         int i;
1522
1523         /* initialize each stream (aka device)
1524          * assign the starting bdl address to each stream (device)
1525          * and initialize
1526          */
1527         for (i = 0; i < chip->num_streams; i++) {
1528                 struct azx_dev *azx_dev = &chip->azx_dev[i];
1529                 azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8);
1530                 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
1531                 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
1532                 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
1533                 azx_dev->sd_int_sta_mask = 1 << i;
1534                 /* stream tag: must be non-zero and unique */
1535                 azx_dev->index = i;
1536                 azx_dev->stream_tag = i + 1;
1537         }
1538
1539         return 0;
1540 }
1541
1542 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
1543 {
1544         if (request_irq(chip->pci->irq, azx_interrupt,
1545                         chip->msi ? 0 : IRQF_SHARED,
1546                         "HDA Intel", chip)) {
1547                 printk(KERN_ERR "hda-intel: unable to grab IRQ %d, "
1548                        "disabling device\n", chip->pci->irq);
1549                 if (do_disconnect)
1550                         snd_card_disconnect(chip->card);
1551                 return -1;
1552         }
1553         chip->irq = chip->pci->irq;
1554         pci_intx(chip->pci, !chip->msi);
1555         return 0;
1556 }
1557
1558
1559 static void azx_stop_chip(struct azx *chip)
1560 {
1561         if (!chip->initialized)
1562                 return;
1563
1564         /* disable interrupts */
1565         azx_int_disable(chip);
1566         azx_int_clear(chip);
1567
1568         /* disable CORB/RIRB */
1569         azx_free_cmd_io(chip);
1570
1571         /* disable position buffer */
1572         azx_writel(chip, DPLBASE, 0);
1573         azx_writel(chip, DPUBASE, 0);
1574
1575         chip->initialized = 0;
1576 }
1577
1578 #ifdef CONFIG_SND_HDA_POWER_SAVE
1579 /* power-up/down the controller */
1580 static void azx_power_notify(struct hda_codec *codec)
1581 {
1582         struct azx *chip = codec->bus->private_data;
1583         struct hda_codec *c;
1584         int power_on = 0;
1585
1586         list_for_each_entry(c, &codec->bus->codec_list, list) {
1587                 if (c->power_on) {
1588                         power_on = 1;
1589                         break;
1590                 }
1591         }
1592         if (power_on)
1593                 azx_init_chip(chip);
1594         else if (chip->running && power_save_controller)
1595                 azx_stop_chip(chip);
1596 }
1597 #endif /* CONFIG_SND_HDA_POWER_SAVE */
1598
1599 #ifdef CONFIG_PM
1600 /*
1601  * power management
1602  */
1603 static int azx_suspend(struct pci_dev *pci, pm_message_t state)
1604 {
1605         struct snd_card *card = pci_get_drvdata(pci);
1606         struct azx *chip = card->private_data;
1607         int i;
1608
1609         snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
1610         for (i = 0; i < AZX_MAX_PCMS; i++)
1611                 snd_pcm_suspend_all(chip->pcm[i]);
1612         if (chip->initialized)
1613                 snd_hda_suspend(chip->bus, state);
1614         azx_stop_chip(chip);
1615         if (chip->irq >= 0) {
1616                 synchronize_irq(chip->irq);
1617                 free_irq(chip->irq, chip);
1618                 chip->irq = -1;
1619         }
1620         if (chip->msi)
1621                 pci_disable_msi(chip->pci);
1622         pci_disable_device(pci);
1623         pci_save_state(pci);
1624         pci_set_power_state(pci, pci_choose_state(pci, state));
1625         return 0;
1626 }
1627
1628 static int azx_resume(struct pci_dev *pci)
1629 {
1630         struct snd_card *card = pci_get_drvdata(pci);
1631         struct azx *chip = card->private_data;
1632
1633         pci_set_power_state(pci, PCI_D0);
1634         pci_restore_state(pci);
1635         if (pci_enable_device(pci) < 0) {
1636                 printk(KERN_ERR "hda-intel: pci_enable_device failed, "
1637                        "disabling device\n");
1638                 snd_card_disconnect(card);
1639                 return -EIO;
1640         }
1641         pci_set_master(pci);
1642         if (chip->msi)
1643                 if (pci_enable_msi(pci) < 0)
1644                         chip->msi = 0;
1645         if (azx_acquire_irq(chip, 1) < 0)
1646                 return -EIO;
1647         azx_init_pci(chip);
1648
1649         if (snd_hda_codecs_inuse(chip->bus))
1650                 azx_init_chip(chip);
1651
1652         snd_hda_resume(chip->bus);
1653         snd_power_change_state(card, SNDRV_CTL_POWER_D0);
1654         return 0;
1655 }
1656 #endif /* CONFIG_PM */
1657
1658
1659 /*
1660  * destructor
1661  */
1662 static int azx_free(struct azx *chip)
1663 {
1664         int i;
1665
1666         if (chip->initialized) {
1667                 for (i = 0; i < chip->num_streams; i++)
1668                         azx_stream_stop(chip, &chip->azx_dev[i]);
1669                 azx_stop_chip(chip);
1670         }
1671
1672         if (chip->irq >= 0) {
1673                 synchronize_irq(chip->irq);
1674                 free_irq(chip->irq, (void*)chip);
1675         }
1676         if (chip->msi)
1677                 pci_disable_msi(chip->pci);
1678         if (chip->remap_addr)
1679                 iounmap(chip->remap_addr);
1680
1681         if (chip->azx_dev) {
1682                 for (i = 0; i < chip->num_streams; i++)
1683                         if (chip->azx_dev[i].bdl.area)
1684                                 snd_dma_free_pages(&chip->azx_dev[i].bdl);
1685         }
1686         if (chip->rb.area)
1687                 snd_dma_free_pages(&chip->rb);
1688         if (chip->posbuf.area)
1689                 snd_dma_free_pages(&chip->posbuf);
1690         pci_release_regions(chip->pci);
1691         pci_disable_device(chip->pci);
1692         kfree(chip->azx_dev);
1693         kfree(chip);
1694
1695         return 0;
1696 }
1697
1698 static int azx_dev_free(struct snd_device *device)
1699 {
1700         return azx_free(device->device_data);
1701 }
1702
1703 /*
1704  * white/black-listing for position_fix
1705  */
1706 static struct snd_pci_quirk position_fix_list[] __devinitdata = {
1707         SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_NONE),
1708         SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_NONE),
1709         {}
1710 };
1711
1712 static int __devinit check_position_fix(struct azx *chip, int fix)
1713 {
1714         const struct snd_pci_quirk *q;
1715
1716         if (fix == POS_FIX_AUTO) {
1717                 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
1718                 if (q) {
1719                         printk(KERN_INFO
1720                                     "hda_intel: position_fix set to %d "
1721                                     "for device %04x:%04x\n",
1722                                     q->value, q->subvendor, q->subdevice);
1723                         return q->value;
1724                 }
1725         }
1726         return fix;
1727 }
1728
1729 /*
1730  * black-lists for probe_mask
1731  */
1732 static struct snd_pci_quirk probe_mask_list[] __devinitdata = {
1733         /* Thinkpad often breaks the controller communication when accessing
1734          * to the non-working (or non-existing) modem codec slot.
1735          */
1736         SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
1737         SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
1738         SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
1739         {}
1740 };
1741
1742 static void __devinit check_probe_mask(struct azx *chip, int dev)
1743 {
1744         const struct snd_pci_quirk *q;
1745
1746         if (probe_mask[dev] == -1) {
1747                 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
1748                 if (q) {
1749                         printk(KERN_INFO
1750                                "hda_intel: probe_mask set to 0x%x "
1751                                "for device %04x:%04x\n",
1752                                q->value, q->subvendor, q->subdevice);
1753                         probe_mask[dev] = q->value;
1754                 }
1755         }
1756 }
1757
1758
1759 /*
1760  * constructor
1761  */
1762 static int __devinit azx_create(struct snd_card *card, struct pci_dev *pci,
1763                                 int dev, int driver_type,
1764                                 struct azx **rchip)
1765 {
1766         struct azx *chip;
1767         int i, err;
1768         unsigned short gcap;
1769         static struct snd_device_ops ops = {
1770                 .dev_free = azx_dev_free,
1771         };
1772
1773         *rchip = NULL;
1774
1775         err = pci_enable_device(pci);
1776         if (err < 0)
1777                 return err;
1778
1779         chip = kzalloc(sizeof(*chip), GFP_KERNEL);
1780         if (!chip) {
1781                 snd_printk(KERN_ERR SFX "cannot allocate chip\n");
1782                 pci_disable_device(pci);
1783                 return -ENOMEM;
1784         }
1785
1786         spin_lock_init(&chip->reg_lock);
1787         mutex_init(&chip->open_mutex);
1788         chip->card = card;
1789         chip->pci = pci;
1790         chip->irq = -1;
1791         chip->driver_type = driver_type;
1792         chip->msi = enable_msi;
1793
1794         chip->position_fix = check_position_fix(chip, position_fix[dev]);
1795         check_probe_mask(chip, dev);
1796
1797         chip->single_cmd = single_cmd;
1798
1799 #if BITS_PER_LONG != 64
1800         /* Fix up base address on ULI M5461 */
1801         if (chip->driver_type == AZX_DRIVER_ULI) {
1802                 u16 tmp3;
1803                 pci_read_config_word(pci, 0x40, &tmp3);
1804                 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
1805                 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
1806         }
1807 #endif
1808
1809         err = pci_request_regions(pci, "ICH HD audio");
1810         if (err < 0) {
1811                 kfree(chip);
1812                 pci_disable_device(pci);
1813                 return err;
1814         }
1815
1816         chip->addr = pci_resource_start(pci, 0);
1817         chip->remap_addr = ioremap_nocache(chip->addr, pci_resource_len(pci,0));
1818         if (chip->remap_addr == NULL) {
1819                 snd_printk(KERN_ERR SFX "ioremap error\n");
1820                 err = -ENXIO;
1821                 goto errout;
1822         }
1823
1824         if (chip->msi)
1825                 if (pci_enable_msi(pci) < 0)
1826                         chip->msi = 0;
1827
1828         if (azx_acquire_irq(chip, 0) < 0) {
1829                 err = -EBUSY;
1830                 goto errout;
1831         }
1832
1833         pci_set_master(pci);
1834         synchronize_irq(chip->irq);
1835
1836         gcap = azx_readw(chip, GCAP);
1837         snd_printdd("chipset global capabilities = 0x%x\n", gcap);
1838
1839         /* allow 64bit DMA address if supported by H/W */
1840         if ((gcap & 0x01) && !pci_set_dma_mask(pci, DMA_64BIT_MASK))
1841                 pci_set_consistent_dma_mask(pci, DMA_64BIT_MASK);
1842
1843         /* read number of streams from GCAP register instead of using
1844          * hardcoded value
1845          */
1846         chip->capture_streams = (gcap >> 8) & 0x0f;
1847         chip->playback_streams = (gcap >> 12) & 0x0f;
1848         if (!chip->playback_streams && !chip->capture_streams) {
1849                 /* gcap didn't give any info, switching to old method */
1850
1851                 switch (chip->driver_type) {
1852                 case AZX_DRIVER_ULI:
1853                         chip->playback_streams = ULI_NUM_PLAYBACK;
1854                         chip->capture_streams = ULI_NUM_CAPTURE;
1855                         break;
1856                 case AZX_DRIVER_ATIHDMI:
1857                         chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
1858                         chip->capture_streams = ATIHDMI_NUM_CAPTURE;
1859                         break;
1860                 default:
1861                         chip->playback_streams = ICH6_NUM_PLAYBACK;
1862                         chip->capture_streams = ICH6_NUM_CAPTURE;
1863                         break;
1864                 }
1865         }
1866         chip->capture_index_offset = 0;
1867         chip->playback_index_offset = chip->capture_streams;
1868         chip->num_streams = chip->playback_streams + chip->capture_streams;
1869         chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev),
1870                                 GFP_KERNEL);
1871         if (!chip->azx_dev) {
1872                 snd_printk(KERN_ERR "cannot malloc azx_dev\n");
1873                 goto errout;
1874         }
1875
1876         for (i = 0; i < chip->num_streams; i++) {
1877                 /* allocate memory for the BDL for each stream */
1878                 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
1879                                           snd_dma_pci_data(chip->pci),
1880                                           BDL_SIZE, &chip->azx_dev[i].bdl);
1881                 if (err < 0) {
1882                         snd_printk(KERN_ERR SFX "cannot allocate BDL\n");
1883                         goto errout;
1884                 }
1885         }
1886         /* allocate memory for the position buffer */
1887         err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
1888                                   snd_dma_pci_data(chip->pci),
1889                                   chip->num_streams * 8, &chip->posbuf);
1890         if (err < 0) {
1891                 snd_printk(KERN_ERR SFX "cannot allocate posbuf\n");
1892                 goto errout;
1893         }
1894         /* allocate CORB/RIRB */
1895         if (!chip->single_cmd) {
1896                 err = azx_alloc_cmd_io(chip);
1897                 if (err < 0)
1898                         goto errout;
1899         }
1900
1901         /* initialize streams */
1902         azx_init_stream(chip);
1903
1904         /* initialize chip */
1905         azx_init_pci(chip);
1906         azx_init_chip(chip);
1907
1908         /* codec detection */
1909         if (!chip->codec_mask) {
1910                 snd_printk(KERN_ERR SFX "no codecs found!\n");
1911                 err = -ENODEV;
1912                 goto errout;
1913         }
1914
1915         err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
1916         if (err <0) {
1917                 snd_printk(KERN_ERR SFX "Error creating device [card]!\n");
1918                 goto errout;
1919         }
1920
1921         strcpy(card->driver, "HDA-Intel");
1922         strcpy(card->shortname, driver_short_names[chip->driver_type]);
1923         sprintf(card->longname, "%s at 0x%lx irq %i",
1924                 card->shortname, chip->addr, chip->irq);
1925
1926         *rchip = chip;
1927         return 0;
1928
1929  errout:
1930         azx_free(chip);
1931         return err;
1932 }
1933
1934 static void power_down_all_codecs(struct azx *chip)
1935 {
1936 #ifdef CONFIG_SND_HDA_POWER_SAVE
1937         /* The codecs were powered up in snd_hda_codec_new().
1938          * Now all initialization done, so turn them down if possible
1939          */
1940         struct hda_codec *codec;
1941         list_for_each_entry(codec, &chip->bus->codec_list, list) {
1942                 snd_hda_power_down(codec);
1943         }
1944 #endif
1945 }
1946
1947 static int __devinit azx_probe(struct pci_dev *pci,
1948                                const struct pci_device_id *pci_id)
1949 {
1950         static int dev;
1951         struct snd_card *card;
1952         struct azx *chip;
1953         int err;
1954
1955         if (dev >= SNDRV_CARDS)
1956                 return -ENODEV;
1957         if (!enable[dev]) {
1958                 dev++;
1959                 return -ENOENT;
1960         }
1961
1962         card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0);
1963         if (!card) {
1964                 snd_printk(KERN_ERR SFX "Error creating card!\n");
1965                 return -ENOMEM;
1966         }
1967
1968         err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
1969         if (err < 0) {
1970                 snd_card_free(card);
1971                 return err;
1972         }
1973         card->private_data = chip;
1974
1975         /* create codec instances */
1976         err = azx_codec_create(chip, model[dev], probe_mask[dev]);
1977         if (err < 0) {
1978                 snd_card_free(card);
1979                 return err;
1980         }
1981
1982         /* create PCM streams */
1983         err = azx_pcm_create(chip);
1984         if (err < 0) {
1985                 snd_card_free(card);
1986                 return err;
1987         }
1988
1989         /* create mixer controls */
1990         err = azx_mixer_create(chip);
1991         if (err < 0) {
1992                 snd_card_free(card);
1993                 return err;
1994         }
1995
1996         snd_card_set_dev(card, &pci->dev);
1997
1998         err = snd_card_register(card);
1999         if (err < 0) {
2000                 snd_card_free(card);
2001                 return err;
2002         }
2003
2004         pci_set_drvdata(pci, card);
2005         chip->running = 1;
2006         power_down_all_codecs(chip);
2007
2008         dev++;
2009         return err;
2010 }
2011
2012 static void __devexit azx_remove(struct pci_dev *pci)
2013 {
2014         snd_card_free(pci_get_drvdata(pci));
2015         pci_set_drvdata(pci, NULL);
2016 }
2017
2018 /* PCI IDs */
2019 static struct pci_device_id azx_ids[] = {
2020         { 0x8086, 0x2668, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ICH }, /* ICH6 */
2021         { 0x8086, 0x27d8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ICH }, /* ICH7 */
2022         { 0x8086, 0x269a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ICH }, /* ESB2 */
2023         { 0x8086, 0x284b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ICH }, /* ICH8 */
2024         { 0x8086, 0x293e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ICH }, /* ICH9 */
2025         { 0x8086, 0x293f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ICH }, /* ICH9 */
2026         { 0x8086, 0x3a3e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ICH }, /* ICH10 */
2027         { 0x8086, 0x3a6e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ICH }, /* ICH10 */
2028         { 0x8086, 0x811b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_SCH }, /* SCH*/
2029         { 0x1002, 0x437b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATI }, /* ATI SB450 */
2030         { 0x1002, 0x4383, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATI }, /* ATI SB600 */
2031         { 0x1002, 0x793b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATIHDMI }, /* ATI RS600 HDMI */
2032         { 0x1002, 0x7919, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATIHDMI }, /* ATI RS690 HDMI */
2033         { 0x1002, 0x960f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATIHDMI }, /* ATI RS780 HDMI */
2034         { 0x1002, 0xaa00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATIHDMI }, /* ATI R600 HDMI */
2035         { 0x1002, 0xaa08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATIHDMI }, /* ATI RV630 HDMI */
2036         { 0x1002, 0xaa10, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATIHDMI }, /* ATI RV610 HDMI */
2037         { 0x1002, 0xaa18, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATIHDMI }, /* ATI RV670 HDMI */
2038         { 0x1002, 0xaa20, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATIHDMI }, /* ATI RV635 HDMI */
2039         { 0x1002, 0xaa28, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATIHDMI }, /* ATI RV620 HDMI */
2040         { 0x1002, 0xaa30, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATIHDMI }, /* ATI RV770 HDMI */
2041         { 0x1002, 0xaa38, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATIHDMI }, /* ATI RV730 HDMI */
2042         { 0x1002, 0xaa40, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATIHDMI }, /* ATI RV710 HDMI */
2043         { 0x1002, 0xaa48, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATIHDMI }, /* ATI RV740 HDMI */
2044         { 0x1106, 0x3288, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_VIA }, /* VIA VT8251/VT8237A */
2045         { 0x1039, 0x7502, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_SIS }, /* SIS966 */
2046         { 0x10b9, 0x5461, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ULI }, /* ULI M5461 */
2047         { 0x10de, 0x026c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP51 */
2048         { 0x10de, 0x0371, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP55 */
2049         { 0x10de, 0x03e4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP61 */
2050         { 0x10de, 0x03f0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP61 */
2051         { 0x10de, 0x044a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP65 */
2052         { 0x10de, 0x044b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP65 */
2053         { 0x10de, 0x055c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP67 */
2054         { 0x10de, 0x055d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP67 */
2055         { 0x10de, 0x07fc, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP73 */
2056         { 0x10de, 0x07fd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP73 */
2057         { 0x10de, 0x0774, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP77 */
2058         { 0x10de, 0x0775, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP77 */
2059         { 0x10de, 0x0776, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP77 */
2060         { 0x10de, 0x0777, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP77 */
2061         { 0x10de, 0x0ac0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP79 */
2062         { 0x10de, 0x0ac1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP79 */
2063         { 0x10de, 0x0ac2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP79 */
2064         { 0x10de, 0x0ac3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP79 */
2065         { 0, }
2066 };
2067 MODULE_DEVICE_TABLE(pci, azx_ids);
2068
2069 /* pci_driver definition */
2070 static struct pci_driver driver = {
2071         .name = "HDA Intel",
2072         .id_table = azx_ids,
2073         .probe = azx_probe,
2074         .remove = __devexit_p(azx_remove),
2075 #ifdef CONFIG_PM
2076         .suspend = azx_suspend,
2077         .resume = azx_resume,
2078 #endif
2079 };
2080
2081 static int __init alsa_card_azx_init(void)
2082 {
2083         return pci_register_driver(&driver);
2084 }
2085
2086 static void __exit alsa_card_azx_exit(void)
2087 {
2088         pci_unregister_driver(&driver);
2089 }
2090
2091 module_init(alsa_card_azx_init)
2092 module_exit(alsa_card_azx_exit)