SAFE public projects git trees. - safe/jmp/linux-2.6/blob - sound/pci/hda/hda_intel.c

   1 /*
   2  *
   3  *  hda_intel.c - Implementation of primary alsa driver code base
   4  *                for Intel HD Audio.
   5  *
   6  *  Copyright(c) 2004 Intel Corporation. All rights reserved.
   7  *
   8  *  Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
   9  *                     PeiSen Hou <pshou@realtek.com.tw>
  10  *
  11  *  This program is free software; you can redistribute it and/or modify it
  12  *  under the terms of the GNU General Public License as published by the Free
  13  *  Software Foundation; either version 2 of the License, or (at your option)
  14  *  any later version.
  15  *
  16  *  This program is distributed in the hope that it will be useful, but WITHOUT
  17  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  18  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  19  *  more details.
  20  *
  21  *  You should have received a copy of the GNU General Public License along with
  22  *  this program; if not, write to the Free Software Foundation, Inc., 59
  23  *  Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  24  *
  25  *  CONTACTS:
  26  *
  27  *  Matt Jared          matt.jared@intel.com
  28  *  Andy Kopp           andy.kopp@intel.com
  29  *  Dan Kogan           dan.d.kogan@intel.com
  30  *
  31  *  CHANGES:
  32  *
  33  *  2004.12.01  Major rewrite by tiwai, merged the work of pshou
  34  *
  35  */
  36
  37 #include <asm/io.h>
  38 #include <linux/delay.h>
  39 #include <linux/interrupt.h>
  40 #include <linux/kernel.h>
  41 #include <linux/module.h>
  42 #include <linux/dma-mapping.h>
  43 #include <linux/moduleparam.h>
  44 #include <linux/init.h>
  45 #include <linux/slab.h>
  46 #include <linux/pci.h>
  47 #include <linux/mutex.h>
  48 #include <linux/reboot.h>
  49 #include <sound/core.h>
  50 #include <sound/initval.h>
  51 #include "hda_codec.h"
  52
  53
  54 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
  55 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
  56 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
  57 static char *model[SNDRV_CARDS];
  58 static int position_fix[SNDRV_CARDS];
  59 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
  60 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
  61 static int probe_only[SNDRV_CARDS];
  62 static int single_cmd;
  63 static int enable_msi;
  64
  65 module_param_array(index, int, NULL, 0444);
  66 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
  67 module_param_array(id, charp, NULL, 0444);
  68 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
  69 module_param_array(enable, bool, NULL, 0444);
  70 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
  71 module_param_array(model, charp, NULL, 0444);
  72 MODULE_PARM_DESC(model, "Use the given board model.");
  73 module_param_array(position_fix, int, NULL, 0444);
  74 MODULE_PARM_DESC(position_fix, "Fix DMA pointer "
  75                  "(0 = auto, 1 = none, 2 = POSBUF).");
  76 module_param_array(bdl_pos_adj, int, NULL, 0644);
  77 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
  78 module_param_array(probe_mask, int, NULL, 0444);
  79 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
  80 module_param_array(probe_only, bool, NULL, 0444);
  81 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
  82 module_param(single_cmd, bool, 0444);
  83 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
  84                  "(for debugging only).");
  85 module_param(enable_msi, int, 0444);
  86 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
  87
  88 #ifdef CONFIG_SND_HDA_POWER_SAVE
  89 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
  90 module_param(power_save, int, 0644);
  91 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
  92                  "(in second, 0 = disable).");
  93
  94 /* reset the HD-audio controller in power save mode.
  95  * this may give more power-saving, but will take longer time to
  96  * wake up.
  97  */
  98 static int power_save_controller = 1;
  99 module_param(power_save_controller, bool, 0644);
 100 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
 101 #endif
 102
 103 MODULE_LICENSE("GPL");
 104 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
 105                          "{Intel, ICH6M},"
 106                          "{Intel, ICH7},"
 107                          "{Intel, ESB2},"
 108                          "{Intel, ICH8},"
 109                          "{Intel, ICH9},"
 110                          "{Intel, ICH10},"
 111                          "{Intel, PCH},"
 112                          "{Intel, SCH},"
 113                          "{ATI, SB450},"
 114                          "{ATI, SB600},"
 115                          "{ATI, RS600},"
 116                          "{ATI, RS690},"
 117                          "{ATI, RS780},"
 118                          "{ATI, R600},"
 119                          "{ATI, RV630},"
 120                          "{ATI, RV610},"
 121                          "{ATI, RV670},"
 122                          "{ATI, RV635},"
 123                          "{ATI, RV620},"
 124                          "{ATI, RV770},"
 125                          "{VIA, VT8251},"
 126                          "{VIA, VT8237A},"
 127                          "{SiS, SIS966},"
 128                          "{ULI, M5461}}");
 129 MODULE_DESCRIPTION("Intel HDA driver");
 130
 131 #ifdef CONFIG_SND_VERBOSE_PRINTK
 132 #define SFX     /* nop */
 133 #else
 134 #define SFX     "hda-intel: "
 135 #endif
 136
 137 /*
 138  * registers
 139  */
 140 #define ICH6_REG_GCAP                   0x00
 141 #define ICH6_REG_VMIN                   0x02
 142 #define ICH6_REG_VMAJ                   0x03
 143 #define ICH6_REG_OUTPAY                 0x04
 144 #define ICH6_REG_INPAY                  0x06
 145 #define ICH6_REG_GCTL                   0x08
 146 #define ICH6_REG_WAKEEN                 0x0c
 147 #define ICH6_REG_STATESTS               0x0e
 148 #define ICH6_REG_GSTS                   0x10
 149 #define ICH6_REG_INTCTL                 0x20
 150 #define ICH6_REG_INTSTS                 0x24
 151 #define ICH6_REG_WALCLK                 0x30
 152 #define ICH6_REG_SYNC                   0x34
 153 #define ICH6_REG_CORBLBASE              0x40
 154 #define ICH6_REG_CORBUBASE              0x44
 155 #define ICH6_REG_CORBWP                 0x48
 156 #define ICH6_REG_CORBRP                 0x4A
 157 #define ICH6_REG_CORBCTL                0x4c
 158 #define ICH6_REG_CORBSTS                0x4d
 159 #define ICH6_REG_CORBSIZE               0x4e
 160
 161 #define ICH6_REG_RIRBLBASE              0x50
 162 #define ICH6_REG_RIRBUBASE              0x54
 163 #define ICH6_REG_RIRBWP                 0x58
 164 #define ICH6_REG_RINTCNT                0x5a
 165 #define ICH6_REG_RIRBCTL                0x5c
 166 #define ICH6_REG_RIRBSTS                0x5d
 167 #define ICH6_REG_RIRBSIZE               0x5e
 168
 169 #define ICH6_REG_IC                     0x60
 170 #define ICH6_REG_IR                     0x64
 171 #define ICH6_REG_IRS                    0x68
 172 #define   ICH6_IRS_VALID        (1<<1)
 173 #define   ICH6_IRS_BUSY         (1<<0)
 174
 175 #define ICH6_REG_DPLBASE                0x70
 176 #define ICH6_REG_DPUBASE                0x74
 177 #define   ICH6_DPLBASE_ENABLE   0x1     /* Enable position buffer */
 178
 179 /* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
 180 enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
 181
 182 /* stream register offsets from stream base */
 183 #define ICH6_REG_SD_CTL                 0x00
 184 #define ICH6_REG_SD_STS                 0x03
 185 #define ICH6_REG_SD_LPIB                0x04
 186 #define ICH6_REG_SD_CBL                 0x08
 187 #define ICH6_REG_SD_LVI                 0x0c
 188 #define ICH6_REG_SD_FIFOW               0x0e
 189 #define ICH6_REG_SD_FIFOSIZE            0x10
 190 #define ICH6_REG_SD_FORMAT              0x12
 191 #define ICH6_REG_SD_BDLPL               0x18
 192 #define ICH6_REG_SD_BDLPU               0x1c
 193
 194 /* PCI space */
 195 #define ICH6_PCIREG_TCSEL       0x44
 196
 197 /*
 198  * other constants
 199  */
 200
 201 /* max number of SDs */
 202 /* ICH, ATI and VIA have 4 playback and 4 capture */
 203 #define ICH6_NUM_CAPTURE        4
 204 #define ICH6_NUM_PLAYBACK       4
 205
 206 /* ULI has 6 playback and 5 capture */
 207 #define ULI_NUM_CAPTURE         5
 208 #define ULI_NUM_PLAYBACK        6
 209
 210 /* ATI HDMI has 1 playback and 0 capture */
 211 #define ATIHDMI_NUM_CAPTURE     0
 212 #define ATIHDMI_NUM_PLAYBACK    1
 213
 214 /* TERA has 4 playback and 3 capture */
 215 #define TERA_NUM_CAPTURE        3
 216 #define TERA_NUM_PLAYBACK       4
 217
 218 /* this number is statically defined for simplicity */
 219 #define MAX_AZX_DEV             16
 220
 221 /* max number of fragments - we may use more if allocating more pages for BDL */
 222 #define BDL_SIZE                4096
 223 #define AZX_MAX_BDL_ENTRIES     (BDL_SIZE / 16)
 224 #define AZX_MAX_FRAG            32
 225 /* max buffer size - no h/w limit, you can increase as you like */
 226 #define AZX_MAX_BUF_SIZE        (1024*1024*1024)
 227 /* max number of PCM devics per card */
 228 #define AZX_MAX_PCMS            8
 229
 230 /* RIRB int mask: overrun[2], response[0] */
 231 #define RIRB_INT_RESPONSE       0x01
 232 #define RIRB_INT_OVERRUN        0x04
 233 #define RIRB_INT_MASK           0x05
 234
 235 /* STATESTS int mask: S3,SD2,SD1,SD0 */
 236 #define AZX_MAX_CODECS          4
 237 #define STATESTS_INT_MASK       0x0f
 238
 239 /* SD_CTL bits */
 240 #define SD_CTL_STREAM_RESET     0x01    /* stream reset bit */
 241 #define SD_CTL_DMA_START        0x02    /* stream DMA start bit */
 242 #define SD_CTL_STRIPE           (3 << 16)       /* stripe control */
 243 #define SD_CTL_TRAFFIC_PRIO     (1 << 18)       /* traffic priority */
 244 #define SD_CTL_DIR              (1 << 19)       /* bi-directional stream */
 245 #define SD_CTL_STREAM_TAG_MASK  (0xf << 20)
 246 #define SD_CTL_STREAM_TAG_SHIFT 20
 247
 248 /* SD_CTL and SD_STS */
 249 #define SD_INT_DESC_ERR         0x10    /* descriptor error interrupt */
 250 #define SD_INT_FIFO_ERR         0x08    /* FIFO error interrupt */
 251 #define SD_INT_COMPLETE         0x04    /* completion interrupt */
 252 #define SD_INT_MASK             (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\
 253                                  SD_INT_COMPLETE)
 254
 255 /* SD_STS */
 256 #define SD_STS_FIFO_READY       0x20    /* FIFO ready */
 257
 258 /* INTCTL and INTSTS */
 259 #define ICH6_INT_ALL_STREAM     0xff       /* all stream interrupts */
 260 #define ICH6_INT_CTRL_EN        0x40000000 /* controller interrupt enable bit */
 261 #define ICH6_INT_GLOBAL_EN      0x80000000 /* global interrupt enable bit */
 262
 263 /* GCTL unsolicited response enable bit */
 264 #define ICH6_GCTL_UREN          (1<<8)
 265
 266 /* GCTL reset bit */
 267 #define ICH6_GCTL_RESET         (1<<0)
 268
 269 /* CORB/RIRB control, read/write pointer */
 270 #define ICH6_RBCTL_DMA_EN       0x02    /* enable DMA */
 271 #define ICH6_RBCTL_IRQ_EN       0x01    /* enable IRQ */
 272 #define ICH6_RBRWP_CLR          0x8000  /* read/write pointer clear */
 273 /* below are so far hardcoded - should read registers in future */
 274 #define ICH6_MAX_CORB_ENTRIES   256
 275 #define ICH6_MAX_RIRB_ENTRIES   256
 276
 277 /* position fix mode */
 278 enum {
 279         POS_FIX_AUTO,
 280         POS_FIX_LPIB,
 281         POS_FIX_POSBUF,
 282 };
 283
 284 /* Defines for ATI HD Audio support in SB450 south bridge */
 285 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR   0x42
 286 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP      0x02
 287
 288 /* Defines for Nvidia HDA support */
 289 #define NVIDIA_HDA_TRANSREG_ADDR      0x4e
 290 #define NVIDIA_HDA_ENABLE_COHBITS     0x0f
 291 #define NVIDIA_HDA_ISTRM_COH          0x4d
 292 #define NVIDIA_HDA_OSTRM_COH          0x4c
 293 #define NVIDIA_HDA_ENABLE_COHBIT      0x01
 294
 295 /* Defines for Intel SCH HDA snoop control */
 296 #define INTEL_SCH_HDA_DEVC      0x78
 297 #define INTEL_SCH_HDA_DEVC_NOSNOOP       (0x1<<11)
 298
 299 /* Define IN stream 0 FIFO size offset in VIA controller */
 300 #define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
 301 /* Define VIA HD Audio Device ID*/
 302 #define VIA_HDAC_DEVICE_ID              0x3288
 303
 304 /* HD Audio class code */
 305 #define PCI_CLASS_MULTIMEDIA_HD_AUDIO   0x0403
 306
 307 /*
 308  */
 309
 310 struct azx_dev {
 311         struct snd_dma_buffer bdl; /* BDL buffer */
 312         u32 *posbuf;            /* position buffer pointer */
 313
 314         unsigned int bufsize;   /* size of the play buffer in bytes */
 315         unsigned int period_bytes; /* size of the period in bytes */
 316         unsigned int frags;     /* number for period in the play buffer */
 317         unsigned int fifo_size; /* FIFO size */
 318         unsigned long start_jiffies;    /* start + minimum jiffies */
 319         unsigned long min_jiffies;      /* minimum jiffies before position is valid */
 320
 321         void __iomem *sd_addr;  /* stream descriptor pointer */
 322
 323         u32 sd_int_sta_mask;    /* stream int status mask */
 324
 325         /* pcm support */
 326         struct snd_pcm_substream *substream;    /* assigned substream,
 327                                                  * set in PCM open
 328                                                  */
 329         unsigned int format_val;        /* format value to be set in the
 330                                          * controller and the codec
 331                                          */
 332         unsigned char stream_tag;       /* assigned stream */
 333         unsigned char index;            /* stream index */
 334
 335         unsigned int opened :1;
 336         unsigned int running :1;
 337         unsigned int irq_pending :1;
 338         unsigned int start_flag: 1;     /* stream full start flag */
 339         /*
 340          * For VIA:
 341          *  A flag to ensure DMA position is 0
 342          *  when link position is not greater than FIFO size
 343          */
 344         unsigned int insufficient :1;
 345 };
 346
 347 /* CORB/RIRB */
 348 struct azx_rb {
 349         u32 *buf;               /* CORB/RIRB buffer
 350                                  * Each CORB entry is 4byte, RIRB is 8byte
 351                                  */
 352         dma_addr_t addr;        /* physical address of CORB/RIRB buffer */
 353         /* for RIRB */
 354         unsigned short rp, wp;  /* read/write pointers */
 355         int cmds;               /* number of pending requests */
 356         u32 res;                /* last read value */
 357 };
 358
 359 struct azx {
 360         struct snd_card *card;
 361         struct pci_dev *pci;
 362         int dev_index;
 363
 364         /* chip type specific */
 365         int driver_type;
 366         int playback_streams;
 367         int playback_index_offset;
 368         int capture_streams;
 369         int capture_index_offset;
 370         int num_streams;
 371
 372         /* pci resources */
 373         unsigned long addr;
 374         void __iomem *remap_addr;
 375         int irq;
 376
 377         /* locks */
 378         spinlock_t reg_lock;
 379         struct mutex open_mutex;
 380
 381         /* streams (x num_streams) */
 382         struct azx_dev *azx_dev;
 383
 384         /* PCM */
 385         struct snd_pcm *pcm[AZX_MAX_PCMS];
 386
 387         /* HD codec */
 388         unsigned short codec_mask;
 389         int  codec_probe_mask; /* copied from probe_mask option */
 390         struct hda_bus *bus;
 391
 392         /* CORB/RIRB */
 393         struct azx_rb corb;
 394         struct azx_rb rirb;
 395
 396         /* CORB/RIRB and position buffers */
 397         struct snd_dma_buffer rb;
 398         struct snd_dma_buffer posbuf;
 399
 400         /* flags */
 401         int position_fix;
 402         unsigned int running :1;
 403         unsigned int initialized :1;
 404         unsigned int single_cmd :1;
 405         unsigned int polling_mode :1;
 406         unsigned int msi :1;
 407         unsigned int irq_pending_warned :1;
 408         unsigned int via_dmapos_patch :1; /* enable DMA-position fix for VIA */
 409         unsigned int probing :1; /* codec probing phase */
 410
 411         /* for debugging */
 412         unsigned int last_cmd;  /* last issued command (to sync) */
 413
 414         /* for pending irqs */
 415         struct work_struct irq_pending_work;
 416
 417         /* reboot notifier (for mysterious hangup problem at power-down) */
 418         struct notifier_block reboot_notifier;
 419 };
 420
 421 /* driver types */
 422 enum {
 423         AZX_DRIVER_ICH,
 424         AZX_DRIVER_SCH,
 425         AZX_DRIVER_ATI,
 426         AZX_DRIVER_ATIHDMI,
 427         AZX_DRIVER_VIA,
 428         AZX_DRIVER_SIS,
 429         AZX_DRIVER_ULI,
 430         AZX_DRIVER_NVIDIA,
 431         AZX_DRIVER_TERA,
 432         AZX_DRIVER_GENERIC,
 433         AZX_NUM_DRIVERS, /* keep this as last entry */
 434 };
 435
 436 static char *driver_short_names[] __devinitdata = {
 437         [AZX_DRIVER_ICH] = "HDA Intel",
 438         [AZX_DRIVER_SCH] = "HDA Intel MID",
 439         [AZX_DRIVER_ATI] = "HDA ATI SB",
 440         [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
 441         [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
 442         [AZX_DRIVER_SIS] = "HDA SIS966",
 443         [AZX_DRIVER_ULI] = "HDA ULI M5461",
 444         [AZX_DRIVER_NVIDIA] = "HDA NVidia",
 445         [AZX_DRIVER_TERA] = "HDA Teradici",
 446         [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
 447 };
 448
 449 /*
 450  * macros for easy use
 451  */
 452 #define azx_writel(chip,reg,value) \
 453         writel(value, (chip)->remap_addr + ICH6_REG_##reg)
 454 #define azx_readl(chip,reg) \
 455         readl((chip)->remap_addr + ICH6_REG_##reg)
 456 #define azx_writew(chip,reg,value) \
 457         writew(value, (chip)->remap_addr + ICH6_REG_##reg)
 458 #define azx_readw(chip,reg) \
 459         readw((chip)->remap_addr + ICH6_REG_##reg)
 460 #define azx_writeb(chip,reg,value) \
 461         writeb(value, (chip)->remap_addr + ICH6_REG_##reg)
 462 #define azx_readb(chip,reg) \
 463         readb((chip)->remap_addr + ICH6_REG_##reg)
 464
 465 #define azx_sd_writel(dev,reg,value) \
 466         writel(value, (dev)->sd_addr + ICH6_REG_##reg)
 467 #define azx_sd_readl(dev,reg) \
 468         readl((dev)->sd_addr + ICH6_REG_##reg)
 469 #define azx_sd_writew(dev,reg,value) \
 470         writew(value, (dev)->sd_addr + ICH6_REG_##reg)
 471 #define azx_sd_readw(dev,reg) \
 472         readw((dev)->sd_addr + ICH6_REG_##reg)
 473 #define azx_sd_writeb(dev,reg,value) \
 474         writeb(value, (dev)->sd_addr + ICH6_REG_##reg)
 475 #define azx_sd_readb(dev,reg) \
 476         readb((dev)->sd_addr + ICH6_REG_##reg)
 477
 478 /* for pcm support */
 479 #define get_azx_dev(substream) (substream->runtime->private_data)
 480
 481 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
 482
 483 /*
 484  * Interface for HD codec
 485  */
 486
 487 /*
 488  * CORB / RIRB interface
 489  */
 490 static int azx_alloc_cmd_io(struct azx *chip)
 491 {
 492         int err;
 493
 494         /* single page (at least 4096 bytes) must suffice for both ringbuffes */
 495         err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
 496                                   snd_dma_pci_data(chip->pci),
 497                                   PAGE_SIZE, &chip->rb);
 498         if (err < 0) {
 499                 snd_printk(KERN_ERR SFX "cannot allocate CORB/RIRB\n");
 500                 return err;
 501         }
 502         return 0;
 503 }
 504
 505 static void azx_init_cmd_io(struct azx *chip)
 506 {
 507         /* CORB set up */
 508         chip->corb.addr = chip->rb.addr;
 509         chip->corb.buf = (u32 *)chip->rb.area;
 510         azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
 511         azx_writel(chip, CORBUBASE, upper_32_bits(chip->corb.addr));
 512
 513         /* set the corb size to 256 entries (ULI requires explicitly) */
 514         azx_writeb(chip, CORBSIZE, 0x02);
 515         /* set the corb write pointer to 0 */
 516         azx_writew(chip, CORBWP, 0);
 517         /* reset the corb hw read pointer */
 518         azx_writew(chip, CORBRP, ICH6_RBRWP_CLR);
 519         /* enable corb dma */
 520         azx_writeb(chip, CORBCTL, ICH6_RBCTL_DMA_EN);
 521
 522         /* RIRB set up */
 523         chip->rirb.addr = chip->rb.addr + 2048;
 524         chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
 525         chip->rirb.wp = chip->rirb.rp = chip->rirb.cmds = 0;
 526         azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
 527         azx_writel(chip, RIRBUBASE, upper_32_bits(chip->rirb.addr));
 528
 529         /* set the rirb size to 256 entries (ULI requires explicitly) */
 530         azx_writeb(chip, RIRBSIZE, 0x02);
 531         /* reset the rirb hw write pointer */
 532         azx_writew(chip, RIRBWP, ICH6_RBRWP_CLR);
 533         /* set N=1, get RIRB response interrupt for new entry */
 534         azx_writew(chip, RINTCNT, 1);
 535         /* enable rirb dma and response irq */
 536         azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN);
 537 }
 538
 539 static void azx_free_cmd_io(struct azx *chip)
 540 {
 541         /* disable ringbuffer DMAs */
 542         azx_writeb(chip, RIRBCTL, 0);
 543         azx_writeb(chip, CORBCTL, 0);
 544 }
 545
 546 /* send a command */
 547 static int azx_corb_send_cmd(struct hda_bus *bus, u32 val)
 548 {
 549         struct azx *chip = bus->private_data;
 550         unsigned int wp;
 551
 552         /* add command to corb */
 553         wp = azx_readb(chip, CORBWP);
 554         wp++;
 555         wp %= ICH6_MAX_CORB_ENTRIES;
 556
 557         spin_lock_irq(&chip->reg_lock);
 558         chip->rirb.cmds++;
 559         chip->corb.buf[wp] = cpu_to_le32(val);
 560         azx_writel(chip, CORBWP, wp);
 561         spin_unlock_irq(&chip->reg_lock);
 562
 563         return 0;
 564 }
 565
 566 #define ICH6_RIRB_EX_UNSOL_EV   (1<<4)
 567
 568 /* retrieve RIRB entry - called from interrupt handler */
 569 static void azx_update_rirb(struct azx *chip)
 570 {
 571         unsigned int rp, wp;
 572         u32 res, res_ex;
 573
 574         wp = azx_readb(chip, RIRBWP);
 575         if (wp == chip->rirb.wp)
 576                 return;
 577         chip->rirb.wp = wp;
 578
 579         while (chip->rirb.rp != wp) {
 580                 chip->rirb.rp++;
 581                 chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES;
 582
 583                 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
 584                 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
 585                 res = le32_to_cpu(chip->rirb.buf[rp]);
 586                 if (res_ex & ICH6_RIRB_EX_UNSOL_EV)
 587                         snd_hda_queue_unsol_event(chip->bus, res, res_ex);
 588                 else if (chip->rirb.cmds) {
 589                         chip->rirb.res = res;
 590                         smp_wmb();
 591                         chip->rirb.cmds--;
 592                 }
 593         }
 594 }
 595
 596 /* receive a response */
 597 static unsigned int azx_rirb_get_response(struct hda_bus *bus)
 598 {
 599         struct azx *chip = bus->private_data;
 600         unsigned long timeout;
 601
 602  again:
 603         timeout = jiffies + msecs_to_jiffies(1000);
 604         for (;;) {
 605                 if (chip->polling_mode) {
 606                         spin_lock_irq(&chip->reg_lock);
 607                         azx_update_rirb(chip);
 608                         spin_unlock_irq(&chip->reg_lock);
 609                 }
 610                 if (!chip->rirb.cmds) {
 611                         smp_rmb();
 612                         bus->rirb_error = 0;
 613                         return chip->rirb.res; /* the last value */
 614                 }
 615                 if (time_after(jiffies, timeout))
 616                         break;
 617                 if (bus->needs_damn_long_delay)
 618                         msleep(2); /* temporary workaround */
 619                 else {
 620                         udelay(10);
 621                         cond_resched();
 622                 }
 623         }
 624
 625         if (chip->msi) {
 626                 snd_printk(KERN_WARNING SFX "No response from codec, "
 627                            "disabling MSI: last cmd=0x%08x\n", chip->last_cmd);
 628                 free_irq(chip->irq, chip);
 629                 chip->irq = -1;
 630                 pci_disable_msi(chip->pci);
 631                 chip->msi = 0;
 632                 if (azx_acquire_irq(chip, 1) < 0) {
 633                         bus->rirb_error = 1;
 634                         return -1;
 635                 }
 636                 goto again;
 637         }
 638
 639         if (!chip->polling_mode) {
 640                 snd_printk(KERN_WARNING SFX "azx_get_response timeout, "
 641                            "switching to polling mode: last cmd=0x%08x\n",
 642                            chip->last_cmd);
 643                 chip->polling_mode = 1;
 644                 goto again;
 645         }
 646
 647         if (chip->probing) {
 648                 /* If this critical timeout happens during the codec probing
 649                  * phase, this is likely an access to a non-existing codec
 650                  * slot.  Better to return an error and reset the system.
 651                  */
 652                 return -1;
 653         }
 654
 655         snd_printk(KERN_ERR SFX "azx_get_response timeout (ERROR): "
 656                    "last cmd=0x%08x\n", chip->last_cmd);
 657         /* re-initialize CORB/RIRB */
 658         spin_lock_irq(&chip->reg_lock);
 659         bus->rirb_error = 1;
 660         azx_free_cmd_io(chip);
 661         azx_init_cmd_io(chip);
 662         spin_unlock_irq(&chip->reg_lock);
 663         return -1;
 664 }
 665
 666 /*
 667  * Use the single immediate command instead of CORB/RIRB for simplicity
 668  *
 669  * Note: according to Intel, this is not preferred use.  The command was
 670  *       intended for the BIOS only, and may get confused with unsolicited
 671  *       responses.  So, we shouldn't use it for normal operation from the
 672  *       driver.
 673  *       I left the codes, however, for debugging/testing purposes.
 674  */
 675
 676 /* receive a response */
 677 static int azx_single_wait_for_response(struct azx *chip)
 678 {
 679         int timeout = 50;
 680
 681         while (timeout--) {
 682                 /* check IRV busy bit */
 683                 if (azx_readw(chip, IRS) & ICH6_IRS_VALID) {
 684                         /* reuse rirb.res as the response return value */
 685                         chip->rirb.res = azx_readl(chip, IR);
 686                         return 0;
 687                 }
 688                 udelay(1);
 689         }
 690         if (printk_ratelimit())
 691                 snd_printd(SFX "get_response timeout: IRS=0x%x\n",
 692                            azx_readw(chip, IRS));
 693         chip->rirb.res = -1;
 694         return -EIO;
 695 }
 696
 697 /* send a command */
 698 static int azx_single_send_cmd(struct hda_bus *bus, u32 val)
 699 {
 700         struct azx *chip = bus->private_data;
 701         int timeout = 50;
 702
 703         while (timeout--) {
 704                 /* check ICB busy bit */
 705                 if (!((azx_readw(chip, IRS) & ICH6_IRS_BUSY))) {
 706                         /* Clear IRV valid bit */
 707                         azx_writew(chip, IRS, azx_readw(chip, IRS) |
 708                                    ICH6_IRS_VALID);
 709                         azx_writel(chip, IC, val);
 710                         azx_writew(chip, IRS, azx_readw(chip, IRS) |
 711                                    ICH6_IRS_BUSY);
 712                         return azx_single_wait_for_response(chip);
 713                 }
 714                 udelay(1);
 715         }
 716         if (printk_ratelimit())
 717                 snd_printd(SFX "send_cmd timeout: IRS=0x%x, val=0x%x\n",
 718                            azx_readw(chip, IRS), val);
 719         return -EIO;
 720 }
 721
 722 /* receive a response */
 723 static unsigned int azx_single_get_response(struct hda_bus *bus)
 724 {
 725         struct azx *chip = bus->private_data;
 726         return chip->rirb.res;
 727 }
 728
 729 /*
 730  * The below are the main callbacks from hda_codec.
 731  *
 732  * They are just the skeleton to call sub-callbacks according to the
 733  * current setting of chip->single_cmd.
 734  */
 735
 736 /* send a command */
 737 static int azx_send_cmd(struct hda_bus *bus, unsigned int val)
 738 {
 739         struct azx *chip = bus->private_data;
 740
 741         chip->last_cmd = val;
 742         if (chip->single_cmd)
 743                 return azx_single_send_cmd(bus, val);
 744         else
 745                 return azx_corb_send_cmd(bus, val);
 746 }
 747
 748 /* get a response */
 749 static unsigned int azx_get_response(struct hda_bus *bus)
 750 {
 751         struct azx *chip = bus->private_data;
 752         if (chip->single_cmd)
 753                 return azx_single_get_response(bus);
 754         else
 755                 return azx_rirb_get_response(bus);
 756 }
 757
 758 #ifdef CONFIG_SND_HDA_POWER_SAVE
 759 static void azx_power_notify(struct hda_bus *bus);
 760 #endif
 761
 762 /* reset codec link */
 763 static int azx_reset(struct azx *chip)
 764 {
 765         int count;
 766
 767         /* clear STATESTS */
 768         azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
 769
 770         /* reset controller */
 771         azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);
 772
 773         count = 50;
 774         while (azx_readb(chip, GCTL) && --count)
 775                 msleep(1);
 776
 777         /* delay for >= 100us for codec PLL to settle per spec
 778          * Rev 0.9 section 5.5.1
 779          */
 780         msleep(1);
 781
 782         /* Bring controller out of reset */
 783         azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET);
 784
 785         count = 50;
 786         while (!azx_readb(chip, GCTL) && --count)
 787                 msleep(1);
 788
 789         /* Brent Chartrand said to wait >= 540us for codecs to initialize */
 790         msleep(1);
 791
 792         /* check to see if controller is ready */
 793         if (!azx_readb(chip, GCTL)) {
 794                 snd_printd(SFX "azx_reset: controller not ready!\n");
 795                 return -EBUSY;
 796         }
 797
 798         /* Accept unsolicited responses */
 799         azx_writel(chip, GCTL, azx_readl(chip, GCTL) | ICH6_GCTL_UREN);
 800
 801         /* detect codecs */
 802         if (!chip->codec_mask) {
 803                 chip->codec_mask = azx_readw(chip, STATESTS);
 804                 snd_printdd(SFX "codec_mask = 0x%x\n", chip->codec_mask);
 805         }
 806
 807         return 0;
 808 }
 809
 810
 811 /*
 812  * Lowlevel interface
 813  */
 814
 815 /* enable interrupts */
 816 static void azx_int_enable(struct azx *chip)
 817 {
 818         /* enable controller CIE and GIE */
 819         azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
 820                    ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN);
 821 }
 822
 823 /* disable interrupts */
 824 static void azx_int_disable(struct azx *chip)
 825 {
 826         int i;
 827
 828         /* disable interrupts in stream descriptor */
 829         for (i = 0; i < chip->num_streams; i++) {
 830                 struct azx_dev *azx_dev = &chip->azx_dev[i];
 831                 azx_sd_writeb(azx_dev, SD_CTL,
 832                               azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK);
 833         }
 834
 835         /* disable SIE for all streams */
 836         azx_writeb(chip, INTCTL, 0);
 837
 838         /* disable controller CIE and GIE */
 839         azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
 840                    ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN));
 841 }
 842
 843 /* clear interrupts */
 844 static void azx_int_clear(struct azx *chip)
 845 {
 846         int i;
 847
 848         /* clear stream status */
 849         for (i = 0; i < chip->num_streams; i++) {
 850                 struct azx_dev *azx_dev = &chip->azx_dev[i];
 851                 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
 852         }
 853
 854         /* clear STATESTS */
 855         azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
 856
 857         /* clear rirb status */
 858         azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
 859
 860         /* clear int status */
 861         azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM);
 862 }
 863
 864 /* start a stream */
 865 static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev)
 866 {
 867         /*
 868          * Before stream start, initialize parameter
 869          */
 870         azx_dev->insufficient = 1;
 871
 872         /* enable SIE */
 873         azx_writeb(chip, INTCTL,
 874                    azx_readb(chip, INTCTL) | (1 << azx_dev->index));
 875         /* set DMA start and interrupt mask */
 876         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
 877                       SD_CTL_DMA_START | SD_INT_MASK);
 878 }
 879
 880 /* stop DMA */
 881 static void azx_stream_clear(struct azx *chip, struct azx_dev *azx_dev)
 882 {
 883         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
 884                       ~(SD_CTL_DMA_START | SD_INT_MASK));
 885         azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
 886 }
 887
 888 /* stop a stream */
 889 static void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev)
 890 {
 891         azx_stream_clear(chip, azx_dev);
 892         /* disable SIE */
 893         azx_writeb(chip, INTCTL,
 894                    azx_readb(chip, INTCTL) & ~(1 << azx_dev->index));
 895 }
 896
 897
 898 /*
 899  * reset and start the controller registers
 900  */
 901 static void azx_init_chip(struct azx *chip)
 902 {
 903         if (chip->initialized)
 904                 return;
 905
 906         /* reset controller */
 907         azx_reset(chip);
 908
 909         /* initialize interrupts */
 910         azx_int_clear(chip);
 911         azx_int_enable(chip);
 912
 913         /* initialize the codec command I/O */
 914         azx_init_cmd_io(chip);
 915
 916         /* program the position buffer */
 917         azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
 918         azx_writel(chip, DPUBASE, upper_32_bits(chip->posbuf.addr));
 919
 920         chip->initialized = 1;
 921 }
 922
 923 /*
 924  * initialize the PCI registers
 925  */
 926 /* update bits in a PCI register byte */
 927 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
 928                             unsigned char mask, unsigned char val)
 929 {
 930         unsigned char data;
 931
 932         pci_read_config_byte(pci, reg, &data);
 933         data &= ~mask;
 934         data |= (val & mask);
 935         pci_write_config_byte(pci, reg, data);
 936 }
 937
 938 static void azx_init_pci(struct azx *chip)
 939 {
 940         unsigned short snoop;
 941
 942         /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
 943          * TCSEL == Traffic Class Select Register, which sets PCI express QOS
 944          * Ensuring these bits are 0 clears playback static on some HD Audio
 945          * codecs
 946          */
 947         update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0);
 948
 949         switch (chip->driver_type) {
 950         case AZX_DRIVER_ATI:
 951                 /* For ATI SB450 azalia HD audio, we need to enable snoop */
 952                 update_pci_byte(chip->pci,
 953                                 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR,
 954                                 0x07, ATI_SB450_HDAUDIO_ENABLE_SNOOP);
 955                 break;
 956         case AZX_DRIVER_NVIDIA:
 957                 /* For NVIDIA HDA, enable snoop */
 958                 update_pci_byte(chip->pci,
 959                                 NVIDIA_HDA_TRANSREG_ADDR,
 960                                 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
 961                 update_pci_byte(chip->pci,
 962                                 NVIDIA_HDA_ISTRM_COH,
 963                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
 964                 update_pci_byte(chip->pci,
 965                                 NVIDIA_HDA_OSTRM_COH,
 966                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
 967                 break;
 968         case AZX_DRIVER_SCH:
 969                 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
 970                 if (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) {
 971                         pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC,
 972                                 snoop & (~INTEL_SCH_HDA_DEVC_NOSNOOP));
 973                         pci_read_config_word(chip->pci,
 974                                 INTEL_SCH_HDA_DEVC, &snoop);
 975                         snd_printdd(SFX "HDA snoop disabled, enabling ... %s\n",
 976                                 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)
 977                                 ? "Failed" : "OK");
 978                 }
 979                 break;
 980
 981         }
 982 }
 983
 984
 985 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
 986
 987 /*
 988  * interrupt handler
 989  */
 990 static irqreturn_t azx_interrupt(int irq, void *dev_id)
 991 {
 992         struct azx *chip = dev_id;
 993         struct azx_dev *azx_dev;
 994         u32 status;
 995         int i, ok;
 996
 997         spin_lock(&chip->reg_lock);
 998
 999         status = azx_readl(chip, INTSTS);
1000         if (status == 0) {
1001                 spin_unlock(&chip->reg_lock);
1002                 return IRQ_NONE;
1003         }
1004
1005         for (i = 0; i < chip->num_streams; i++) {
1006                 azx_dev = &chip->azx_dev[i];
1007                 if (status & azx_dev->sd_int_sta_mask) {
1008                         azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
1009                         if (!azx_dev->substream || !azx_dev->running)
1010                                 continue;
1011                         /* check whether this IRQ is really acceptable */
1012                         ok = azx_position_ok(chip, azx_dev);
1013                         if (ok == 1) {
1014                                 azx_dev->irq_pending = 0;
1015                                 spin_unlock(&chip->reg_lock);
1016                                 snd_pcm_period_elapsed(azx_dev->substream);
1017                                 spin_lock(&chip->reg_lock);
1018                         } else if (ok == 0 && chip->bus && chip->bus->workq) {
1019                                 /* bogus IRQ, process it later */
1020                                 azx_dev->irq_pending = 1;
1021                                 queue_work(chip->bus->workq,
1022                                            &chip->irq_pending_work);
1023                         }
1024                 }
1025         }
1026
1027         /* clear rirb int */
1028         status = azx_readb(chip, RIRBSTS);
1029         if (status & RIRB_INT_MASK) {
1030                 if (status & RIRB_INT_RESPONSE)
1031                         azx_update_rirb(chip);
1032                 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1033         }
1034
1035 #if 0
1036         /* clear state status int */
1037         if (azx_readb(chip, STATESTS) & 0x04)
1038                 azx_writeb(chip, STATESTS, 0x04);
1039 #endif
1040         spin_unlock(&chip->reg_lock);
1041
1042         return IRQ_HANDLED;
1043 }
1044
1045
1046 /*
1047  * set up a BDL entry
1048  */
1049 static int setup_bdle(struct snd_pcm_substream *substream,
1050                       struct azx_dev *azx_dev, u32 **bdlp,
1051                       int ofs, int size, int with_ioc)
1052 {
1053         u32 *bdl = *bdlp;
1054
1055         while (size > 0) {
1056                 dma_addr_t addr;
1057                 int chunk;
1058
1059                 if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES)
1060                         return -EINVAL;
1061
1062                 addr = snd_pcm_sgbuf_get_addr(substream, ofs);
1063                 /* program the address field of the BDL entry */
1064                 bdl[0] = cpu_to_le32((u32)addr);
1065                 bdl[1] = cpu_to_le32(upper_32_bits(addr));
1066                 /* program the size field of the BDL entry */
1067                 chunk = snd_pcm_sgbuf_get_chunk_size(substream, ofs, size);
1068                 bdl[2] = cpu_to_le32(chunk);
1069                 /* program the IOC to enable interrupt
1070                  * only when the whole fragment is processed
1071                  */
1072                 size -= chunk;
1073                 bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);
1074                 bdl += 4;
1075                 azx_dev->frags++;
1076                 ofs += chunk;
1077         }
1078         *bdlp = bdl;
1079         return ofs;
1080 }
1081
1082 /*
1083  * set up BDL entries
1084  */
1085 static int azx_setup_periods(struct azx *chip,
1086                              struct snd_pcm_substream *substream,
1087                              struct azx_dev *azx_dev)
1088 {
1089         u32 *bdl;
1090         int i, ofs, periods, period_bytes;
1091         int pos_adj;
1092
1093         /* reset BDL address */
1094         azx_sd_writel(azx_dev, SD_BDLPL, 0);
1095         azx_sd_writel(azx_dev, SD_BDLPU, 0);
1096
1097         period_bytes = azx_dev->period_bytes;
1098         periods = azx_dev->bufsize / period_bytes;
1099
1100         /* program the initial BDL entries */
1101         bdl = (u32 *)azx_dev->bdl.area;
1102         ofs = 0;
1103         azx_dev->frags = 0;
1104         pos_adj = bdl_pos_adj[chip->dev_index];
1105         if (pos_adj > 0) {
1106                 struct snd_pcm_runtime *runtime = substream->runtime;
1107                 int pos_align = pos_adj;
1108                 pos_adj = (pos_adj * runtime->rate + 47999) / 48000;
1109                 if (!pos_adj)
1110                         pos_adj = pos_align;
1111                 else
1112                         pos_adj = ((pos_adj + pos_align - 1) / pos_align) *
1113                                 pos_align;
1114                 pos_adj = frames_to_bytes(runtime, pos_adj);
1115                 if (pos_adj >= period_bytes) {
1116                         snd_printk(KERN_WARNING SFX "Too big adjustment %d\n",
1117                                    bdl_pos_adj[chip->dev_index]);
1118                         pos_adj = 0;
1119                 } else {
1120                         ofs = setup_bdle(substream, azx_dev,
1121                                          &bdl, ofs, pos_adj, 1);
1122                         if (ofs < 0)
1123                                 goto error;
1124                 }
1125         } else
1126                 pos_adj = 0;
1127         for (i = 0; i < periods; i++) {
1128                 if (i == periods - 1 && pos_adj)
1129                         ofs = setup_bdle(substream, azx_dev, &bdl, ofs,
1130                                          period_bytes - pos_adj, 0);
1131                 else
1132                         ofs = setup_bdle(substream, azx_dev, &bdl, ofs,
1133                                          period_bytes, 1);
1134                 if (ofs < 0)
1135                         goto error;
1136         }
1137         return 0;
1138
1139  error:
1140         snd_printk(KERN_ERR SFX "Too many BDL entries: buffer=%d, period=%d\n",
1141                    azx_dev->bufsize, period_bytes);
1142         return -EINVAL;
1143 }
1144
1145 /* reset stream */
1146 static void azx_stream_reset(struct azx *chip, struct azx_dev *azx_dev)
1147 {
1148         unsigned char val;
1149         int timeout;
1150
1151         azx_stream_clear(chip, azx_dev);
1152
1153         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1154                       SD_CTL_STREAM_RESET);
1155         udelay(3);
1156         timeout = 300;
1157         while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1158                --timeout)
1159                 ;
1160         val &= ~SD_CTL_STREAM_RESET;
1161         azx_sd_writeb(azx_dev, SD_CTL, val);
1162         udelay(3);
1163
1164         timeout = 300;
1165         /* waiting for hardware to report that the stream is out of reset */
1166         while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1167                --timeout)
1168                 ;
1169
1170         /* reset first position - may not be synced with hw at this time */
1171         *azx_dev->posbuf = 0;
1172 }
1173
1174 /*
1175  * set up the SD for streaming
1176  */
1177 static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev)
1178 {
1179         /* make sure the run bit is zero for SD */
1180         azx_stream_clear(chip, azx_dev);
1181         /* program the stream_tag */
1182         azx_sd_writel(azx_dev, SD_CTL,
1183                       (azx_sd_readl(azx_dev, SD_CTL) & ~SD_CTL_STREAM_TAG_MASK)|
1184                       (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT));
1185
1186         /* program the length of samples in cyclic buffer */
1187         azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize);
1188
1189         /* program the stream format */
1190         /* this value needs to be the same as the one programmed */
1191         azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
1192
1193         /* program the stream LVI (last valid index) of the BDL */
1194         azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
1195
1196         /* program the BDL address */
1197         /* lower BDL address */
1198         azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
1199         /* upper BDL address */
1200         azx_sd_writel(azx_dev, SD_BDLPU, upper_32_bits(azx_dev->bdl.addr));
1201
1202         /* enable the position buffer */
1203         if (chip->position_fix == POS_FIX_POSBUF ||
1204             chip->position_fix == POS_FIX_AUTO ||
1205             chip->via_dmapos_patch) {
1206                 if (!(azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE))
1207                         azx_writel(chip, DPLBASE,
1208                                 (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE);
1209         }
1210
1211         /* set the interrupt enable bits in the descriptor control register */
1212         azx_sd_writel(azx_dev, SD_CTL,
1213                       azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK);
1214
1215         return 0;
1216 }
1217
1218 /*
1219  * Probe the given codec address
1220  */
1221 static int probe_codec(struct azx *chip, int addr)
1222 {
1223         unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) |
1224                 (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID;
1225         unsigned int res;
1226
1227         chip->probing = 1;
1228         azx_send_cmd(chip->bus, cmd);
1229         res = azx_get_response(chip->bus);
1230         chip->probing = 0;
1231         if (res == -1)
1232                 return -EIO;
1233         snd_printdd(SFX "codec #%d probed OK\n", addr);
1234         return 0;
1235 }
1236
1237 static int azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
1238                                  struct hda_pcm *cpcm);
1239 static void azx_stop_chip(struct azx *chip);
1240
1241 /*
1242  * Codec initialization
1243  */
1244
1245 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
1246 static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] __devinitdata = {
1247         [AZX_DRIVER_TERA] = 1,
1248 };
1249
1250 static int __devinit azx_codec_create(struct azx *chip, const char *model,
1251                                       int no_init)
1252 {
1253         struct hda_bus_template bus_temp;
1254         int c, codecs, err;
1255         int max_slots;
1256
1257         memset(&bus_temp, 0, sizeof(bus_temp));
1258         bus_temp.private_data = chip;
1259         bus_temp.modelname = model;
1260         bus_temp.pci = chip->pci;
1261         bus_temp.ops.command = azx_send_cmd;
1262         bus_temp.ops.get_response = azx_get_response;
1263         bus_temp.ops.attach_pcm = azx_attach_pcm_stream;
1264 #ifdef CONFIG_SND_HDA_POWER_SAVE
1265         bus_temp.power_save = &power_save;
1266         bus_temp.ops.pm_notify = azx_power_notify;
1267 #endif
1268
1269         err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus);
1270         if (err < 0)
1271                 return err;
1272
1273         if (chip->driver_type == AZX_DRIVER_NVIDIA)
1274                 chip->bus->needs_damn_long_delay = 1;
1275
1276         codecs = 0;
1277         max_slots = azx_max_codecs[chip->driver_type];
1278         if (!max_slots)
1279                 max_slots = AZX_MAX_CODECS;
1280
1281         /* First try to probe all given codec slots */
1282         for (c = 0; c < max_slots; c++) {
1283                 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1284                         if (probe_codec(chip, c) < 0) {
1285                                 /* Some BIOSen give you wrong codec addresses
1286                                  * that don't exist
1287                                  */
1288                                 snd_printk(KERN_WARNING SFX
1289                                            "Codec #%d probe error; "
1290                                            "disabling it...\n", c);
1291                                 chip->codec_mask &= ~(1 << c);
1292                                 /* More badly, accessing to a non-existing
1293                                  * codec often screws up the controller chip,
1294                                  * and distrubs the further communications.
1295                                  * Thus if an error occurs during probing,
1296                                  * better to reset the controller chip to
1297                                  * get back to the sanity state.
1298                                  */
1299                                 azx_stop_chip(chip);
1300                                 azx_init_chip(chip);
1301                         }
1302                 }
1303         }
1304
1305         /* Then create codec instances */
1306         for (c = 0; c < max_slots; c++) {
1307                 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1308                         struct hda_codec *codec;
1309                         err = snd_hda_codec_new(chip->bus, c, !no_init, &codec);
1310                         if (err < 0)
1311                                 continue;
1312                         codecs++;
1313                 }
1314         }
1315         if (!codecs) {
1316                 snd_printk(KERN_ERR SFX "no codecs initialized\n");
1317                 return -ENXIO;
1318         }
1319
1320         return 0;
1321 }
1322
1323
1324 /*
1325  * PCM support
1326  */
1327
1328 /* assign a stream for the PCM */
1329 static inline struct azx_dev *azx_assign_device(struct azx *chip, int stream)
1330 {
1331         int dev, i, nums;
1332         if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
1333                 dev = chip->playback_index_offset;
1334                 nums = chip->playback_streams;
1335         } else {
1336                 dev = chip->capture_index_offset;
1337                 nums = chip->capture_streams;
1338         }
1339         for (i = 0; i < nums; i++, dev++)
1340                 if (!chip->azx_dev[dev].opened) {
1341                         chip->azx_dev[dev].opened = 1;
1342                         return &chip->azx_dev[dev];
1343                 }
1344         return NULL;
1345 }
1346
1347 /* release the assigned stream */
1348 static inline void azx_release_device(struct azx_dev *azx_dev)
1349 {
1350         azx_dev->opened = 0;
1351 }
1352
1353 static struct snd_pcm_hardware azx_pcm_hw = {
1354         .info =                 (SNDRV_PCM_INFO_MMAP |
1355                                  SNDRV_PCM_INFO_INTERLEAVED |
1356                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
1357                                  SNDRV_PCM_INFO_MMAP_VALID |
1358                                  /* No full-resume yet implemented */
1359                                  /* SNDRV_PCM_INFO_RESUME |*/
1360                                  SNDRV_PCM_INFO_PAUSE |
1361                                  SNDRV_PCM_INFO_SYNC_START),
1362         .formats =              SNDRV_PCM_FMTBIT_S16_LE,
1363         .rates =                SNDRV_PCM_RATE_48000,
1364         .rate_min =             48000,
1365         .rate_max =             48000,
1366         .channels_min =         2,
1367         .channels_max =         2,
1368         .buffer_bytes_max =     AZX_MAX_BUF_SIZE,
1369         .period_bytes_min =     128,
1370         .period_bytes_max =     AZX_MAX_BUF_SIZE / 2,
1371         .periods_min =          2,
1372         .periods_max =          AZX_MAX_FRAG,
1373         .fifo_size =            0,
1374 };
1375
1376 struct azx_pcm {
1377         struct azx *chip;
1378         struct hda_codec *codec;
1379         struct hda_pcm_stream *hinfo[2];
1380 };
1381
1382 static int azx_pcm_open(struct snd_pcm_substream *substream)
1383 {
1384         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1385         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1386         struct azx *chip = apcm->chip;
1387         struct azx_dev *azx_dev;
1388         struct snd_pcm_runtime *runtime = substream->runtime;
1389         unsigned long flags;
1390         int err;
1391
1392         mutex_lock(&chip->open_mutex);
1393         azx_dev = azx_assign_device(chip, substream->stream);
1394         if (azx_dev == NULL) {
1395                 mutex_unlock(&chip->open_mutex);
1396                 return -EBUSY;
1397         }
1398         runtime->hw = azx_pcm_hw;
1399         runtime->hw.channels_min = hinfo->channels_min;
1400         runtime->hw.channels_max = hinfo->channels_max;
1401         runtime->hw.formats = hinfo->formats;
1402         runtime->hw.rates = hinfo->rates;
1403         snd_pcm_limit_hw_rates(runtime);
1404         snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
1405         snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
1406                                    128);
1407         snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1408                                    128);
1409         snd_hda_power_up(apcm->codec);
1410         err = hinfo->ops.open(hinfo, apcm->codec, substream);
1411         if (err < 0) {
1412                 azx_release_device(azx_dev);
1413                 snd_hda_power_down(apcm->codec);
1414                 mutex_unlock(&chip->open_mutex);
1415                 return err;
1416         }
1417         spin_lock_irqsave(&chip->reg_lock, flags);
1418         azx_dev->substream = substream;
1419         azx_dev->running = 0;
1420         spin_unlock_irqrestore(&chip->reg_lock, flags);
1421
1422         runtime->private_data = azx_dev;
1423         snd_pcm_set_sync(substream);
1424         mutex_unlock(&chip->open_mutex);
1425
1426         return 0;
1427 }
1428
1429 static int azx_pcm_close(struct snd_pcm_substream *substream)
1430 {
1431         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1432         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1433         struct azx *chip = apcm->chip;
1434         struct azx_dev *azx_dev = get_azx_dev(substream);
1435         unsigned long flags;
1436
1437         mutex_lock(&chip->open_mutex);
1438         spin_lock_irqsave(&chip->reg_lock, flags);
1439         azx_dev->substream = NULL;
1440         azx_dev->running = 0;
1441         spin_unlock_irqrestore(&chip->reg_lock, flags);
1442         azx_release_device(azx_dev);
1443         hinfo->ops.close(hinfo, apcm->codec, substream);
1444         snd_hda_power_down(apcm->codec);
1445         mutex_unlock(&chip->open_mutex);
1446         return 0;
1447 }
1448
1449 static int azx_pcm_hw_params(struct snd_pcm_substream *substream,
1450                              struct snd_pcm_hw_params *hw_params)
1451 {
1452         struct azx_dev *azx_dev = get_azx_dev(substream);
1453
1454         azx_dev->bufsize = 0;
1455         azx_dev->period_bytes = 0;
1456         azx_dev->format_val = 0;
1457         return snd_pcm_lib_malloc_pages(substream,
1458                                         params_buffer_bytes(hw_params));
1459 }
1460
1461 static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
1462 {
1463         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1464         struct azx_dev *azx_dev = get_azx_dev(substream);
1465         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1466
1467         /* reset BDL address */
1468         azx_sd_writel(azx_dev, SD_BDLPL, 0);
1469         azx_sd_writel(azx_dev, SD_BDLPU, 0);
1470         azx_sd_writel(azx_dev, SD_CTL, 0);
1471         azx_dev->bufsize = 0;
1472         azx_dev->period_bytes = 0;
1473         azx_dev->format_val = 0;
1474
1475         hinfo->ops.cleanup(hinfo, apcm->codec, substream);
1476
1477         return snd_pcm_lib_free_pages(substream);
1478 }
1479
1480 static int azx_pcm_prepare(struct snd_pcm_substream *substream)
1481 {
1482         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1483         struct azx *chip = apcm->chip;
1484         struct azx_dev *azx_dev = get_azx_dev(substream);
1485         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1486         struct snd_pcm_runtime *runtime = substream->runtime;
1487         unsigned int bufsize, period_bytes, format_val;
1488         int err;
1489
1490         azx_stream_reset(chip, azx_dev);
1491         format_val = snd_hda_calc_stream_format(runtime->rate,
1492                                                 runtime->channels,
1493                                                 runtime->format,
1494                                                 hinfo->maxbps);
1495         if (!format_val) {
1496                 snd_printk(KERN_ERR SFX
1497                            "invalid format_val, rate=%d, ch=%d, format=%d\n",
1498                            runtime->rate, runtime->channels, runtime->format);
1499                 return -EINVAL;
1500         }
1501
1502         bufsize = snd_pcm_lib_buffer_bytes(substream);
1503         period_bytes = snd_pcm_lib_period_bytes(substream);
1504
1505         snd_printdd(SFX "azx_pcm_prepare: bufsize=0x%x, format=0x%x\n",
1506                     bufsize, format_val);
1507
1508         if (bufsize != azx_dev->bufsize ||
1509             period_bytes != azx_dev->period_bytes ||
1510             format_val != azx_dev->format_val) {
1511                 azx_dev->bufsize = bufsize;
1512                 azx_dev->period_bytes = period_bytes;
1513                 azx_dev->format_val = format_val;
1514                 err = azx_setup_periods(chip, substream, azx_dev);
1515                 if (err < 0)
1516                         return err;
1517         }
1518
1519         azx_dev->min_jiffies = (runtime->period_size * HZ) /
1520                                                 (runtime->rate * 2);
1521         azx_setup_controller(chip, azx_dev);
1522         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1523                 azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1;
1524         else
1525                 azx_dev->fifo_size = 0;
1526
1527         return hinfo->ops.prepare(hinfo, apcm->codec, azx_dev->stream_tag,
1528                                   azx_dev->format_val, substream);
1529 }
1530
1531 static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
1532 {
1533         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1534         struct azx *chip = apcm->chip;
1535         struct azx_dev *azx_dev;
1536         struct snd_pcm_substream *s;
1537         int rstart = 0, start, nsync = 0, sbits = 0;
1538         int nwait, timeout;
1539
1540         switch (cmd) {
1541         case SNDRV_PCM_TRIGGER_START:
1542                 rstart = 1;
1543         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1544         case SNDRV_PCM_TRIGGER_RESUME:
1545                 start = 1;
1546                 break;
1547         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1548         case SNDRV_PCM_TRIGGER_SUSPEND:
1549         case SNDRV_PCM_TRIGGER_STOP:
1550                 start = 0;
1551                 break;
1552         default:
1553                 return -EINVAL;
1554         }
1555
1556         snd_pcm_group_for_each_entry(s, substream) {
1557                 if (s->pcm->card != substream->pcm->card)
1558                         continue;
1559                 azx_dev = get_azx_dev(s);
1560                 sbits |= 1 << azx_dev->index;
1561                 nsync++;
1562                 snd_pcm_trigger_done(s, substream);
1563         }
1564
1565         spin_lock(&chip->reg_lock);
1566         if (nsync > 1) {
1567                 /* first, set SYNC bits of corresponding streams */
1568                 azx_writel(chip, SYNC, azx_readl(chip, SYNC) | sbits);
1569         }
1570         snd_pcm_group_for_each_entry(s, substream) {
1571                 if (s->pcm->card != substream->pcm->card)
1572                         continue;
1573                 azx_dev = get_azx_dev(s);
1574                 if (rstart) {
1575                         azx_dev->start_flag = 1;
1576                         azx_dev->start_jiffies = jiffies + azx_dev->min_jiffies;
1577                 }
1578                 if (start)
1579                         azx_stream_start(chip, azx_dev);
1580                 else
1581                         azx_stream_stop(chip, azx_dev);
1582                 azx_dev->running = start;
1583         }
1584         spin_unlock(&chip->reg_lock);
1585         if (start) {
1586                 if (nsync == 1)
1587                         return 0;
1588                 /* wait until all FIFOs get ready */
1589                 for (timeout = 5000; timeout; timeout--) {
1590                         nwait = 0;
1591                         snd_pcm_group_for_each_entry(s, substream) {
1592                                 if (s->pcm->card != substream->pcm->card)
1593                                         continue;
1594                                 azx_dev = get_azx_dev(s);
1595                                 if (!(azx_sd_readb(azx_dev, SD_STS) &
1596                                       SD_STS_FIFO_READY))
1597                                         nwait++;
1598                         }
1599                         if (!nwait)
1600                                 break;
1601                         cpu_relax();
1602                 }
1603         } else {
1604                 /* wait until all RUN bits are cleared */
1605                 for (timeout = 5000; timeout; timeout--) {
1606                         nwait = 0;
1607                         snd_pcm_group_for_each_entry(s, substream) {
1608                                 if (s->pcm->card != substream->pcm->card)
1609                                         continue;
1610                                 azx_dev = get_azx_dev(s);
1611                                 if (azx_sd_readb(azx_dev, SD_CTL) &
1612                                     SD_CTL_DMA_START)
1613                                         nwait++;
1614                         }
1615                         if (!nwait)
1616                                 break;
1617                         cpu_relax();
1618                 }
1619         }
1620         if (nsync > 1) {
1621                 spin_lock(&chip->reg_lock);
1622                 /* reset SYNC bits */
1623                 azx_writel(chip, SYNC, azx_readl(chip, SYNC) & ~sbits);
1624                 spin_unlock(&chip->reg_lock);
1625         }
1626         return 0;
1627 }
1628
1629 /* get the current DMA position with correction on VIA chips */
1630 static unsigned int azx_via_get_position(struct azx *chip,
1631                                          struct azx_dev *azx_dev)
1632 {
1633         unsigned int link_pos, mini_pos, bound_pos;
1634         unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
1635         unsigned int fifo_size;
1636
1637         link_pos = azx_sd_readl(azx_dev, SD_LPIB);
1638         if (azx_dev->index >= 4) {
1639                 /* Playback, no problem using link position */
1640                 return link_pos;
1641         }
1642
1643         /* Capture */
1644         /* For new chipset,
1645          * use mod to get the DMA position just like old chipset
1646          */
1647         mod_dma_pos = le32_to_cpu(*azx_dev->posbuf);
1648         mod_dma_pos %= azx_dev->period_bytes;
1649
1650         /* azx_dev->fifo_size can't get FIFO size of in stream.
1651          * Get from base address + offset.
1652          */
1653         fifo_size = readw(chip->remap_addr + VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
1654
1655         if (azx_dev->insufficient) {
1656                 /* Link position never gather than FIFO size */
1657                 if (link_pos <= fifo_size)
1658                         return 0;
1659
1660                 azx_dev->insufficient = 0;
1661         }
1662
1663         if (link_pos <= fifo_size)
1664                 mini_pos = azx_dev->bufsize + link_pos - fifo_size;
1665         else
1666                 mini_pos = link_pos - fifo_size;
1667
1668         /* Find nearest previous boudary */
1669         mod_mini_pos = mini_pos % azx_dev->period_bytes;
1670         mod_link_pos = link_pos % azx_dev->period_bytes;
1671         if (mod_link_pos >= fifo_size)
1672                 bound_pos = link_pos - mod_link_pos;
1673         else if (mod_dma_pos >= mod_mini_pos)
1674                 bound_pos = mini_pos - mod_mini_pos;
1675         else {
1676                 bound_pos = mini_pos - mod_mini_pos + azx_dev->period_bytes;
1677                 if (bound_pos >= azx_dev->bufsize)
1678                         bound_pos = 0;
1679         }
1680
1681         /* Calculate real DMA position we want */
1682         return bound_pos + mod_dma_pos;
1683 }
1684
1685 static unsigned int azx_get_position(struct azx *chip,
1686                                      struct azx_dev *azx_dev)
1687 {
1688         unsigned int pos;
1689
1690         if (chip->via_dmapos_patch)
1691                 pos = azx_via_get_position(chip, azx_dev);
1692         else if (chip->position_fix == POS_FIX_POSBUF ||
1693                  chip->position_fix == POS_FIX_AUTO) {
1694                 /* use the position buffer */
1695                 pos = le32_to_cpu(*azx_dev->posbuf);
1696         } else {
1697                 /* read LPIB */
1698                 pos = azx_sd_readl(azx_dev, SD_LPIB);
1699         }
1700         if (pos >= azx_dev->bufsize)
1701                 pos = 0;
1702         return pos;
1703 }
1704
1705 static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
1706 {
1707         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1708         struct azx *chip = apcm->chip;
1709         struct azx_dev *azx_dev = get_azx_dev(substream);
1710         return bytes_to_frames(substream->runtime,
1711                                azx_get_position(chip, azx_dev));
1712 }
1713
1714 /*
1715  * Check whether the current DMA position is acceptable for updating
1716  * periods.  Returns non-zero if it's OK.
1717  *
1718  * Many HD-audio controllers appear pretty inaccurate about
1719  * the update-IRQ timing.  The IRQ is issued before actually the
1720  * data is processed.  So, we need to process it afterwords in a
1721  * workqueue.
1722  */
1723 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
1724 {
1725         unsigned int pos;
1726
1727         if (azx_dev->start_flag &&
1728             time_before_eq(jiffies, azx_dev->start_jiffies))
1729                 return -1;      /* bogus (too early) interrupt */
1730         azx_dev->start_flag = 0;
1731
1732         pos = azx_get_position(chip, azx_dev);
1733         if (chip->position_fix == POS_FIX_AUTO) {
1734                 if (!pos) {
1735                         printk(KERN_WARNING
1736                                "hda-intel: Invalid position buffer, "
1737                                "using LPIB read method instead.\n");
1738                         chip->position_fix = POS_FIX_LPIB;
1739                         pos = azx_get_position(chip, azx_dev);
1740                 } else
1741                         chip->position_fix = POS_FIX_POSBUF;
1742         }
1743
1744         if (!bdl_pos_adj[chip->dev_index])
1745                 return 1; /* no delayed ack */
1746         if (pos % azx_dev->period_bytes > azx_dev->period_bytes / 2)
1747                 return 0; /* NG - it's below the period boundary */
1748         return 1; /* OK, it's fine */
1749 }
1750
1751 /*
1752  * The work for pending PCM period updates.
1753  */
1754 static void azx_irq_pending_work(struct work_struct *work)
1755 {
1756         struct azx *chip = container_of(work, struct azx, irq_pending_work);
1757         int i, pending;
1758
1759         if (!chip->irq_pending_warned) {
1760                 printk(KERN_WARNING
1761                        "hda-intel: IRQ timing workaround is activated "
1762                        "for card #%d. Suggest a bigger bdl_pos_adj.\n",
1763                        chip->card->number);
1764                 chip->irq_pending_warned = 1;
1765         }
1766
1767         for (;;) {
1768                 pending = 0;
1769                 spin_lock_irq(&chip->reg_lock);
1770                 for (i = 0; i < chip->num_streams; i++) {
1771                         struct azx_dev *azx_dev = &chip->azx_dev[i];
1772                         if (!azx_dev->irq_pending ||
1773                             !azx_dev->substream ||
1774                             !azx_dev->running)
1775                                 continue;
1776                         if (azx_position_ok(chip, azx_dev)) {
1777                                 azx_dev->irq_pending = 0;
1778                                 spin_unlock(&chip->reg_lock);
1779                                 snd_pcm_period_elapsed(azx_dev->substream);
1780                                 spin_lock(&chip->reg_lock);
1781                         } else
1782                                 pending++;
1783                 }
1784                 spin_unlock_irq(&chip->reg_lock);
1785                 if (!pending)
1786                         return;
1787                 cond_resched();
1788         }
1789 }
1790
1791 /* clear irq_pending flags and assure no on-going workq */
1792 static void azx_clear_irq_pending(struct azx *chip)
1793 {
1794         int i;
1795
1796         spin_lock_irq(&chip->reg_lock);
1797         for (i = 0; i < chip->num_streams; i++)
1798                 chip->azx_dev[i].irq_pending = 0;
1799         spin_unlock_irq(&chip->reg_lock);
1800 }
1801
1802 static struct snd_pcm_ops azx_pcm_ops = {
1803         .open = azx_pcm_open,
1804         .close = azx_pcm_close,
1805         .ioctl = snd_pcm_lib_ioctl,
1806         .hw_params = azx_pcm_hw_params,
1807         .hw_free = azx_pcm_hw_free,
1808         .prepare = azx_pcm_prepare,
1809         .trigger = azx_pcm_trigger,
1810         .pointer = azx_pcm_pointer,
1811         .page = snd_pcm_sgbuf_ops_page,
1812 };
1813
1814 static void azx_pcm_free(struct snd_pcm *pcm)
1815 {
1816         struct azx_pcm *apcm = pcm->private_data;
1817         if (apcm) {
1818                 apcm->chip->pcm[pcm->device] = NULL;
1819                 kfree(apcm);
1820         }
1821 }
1822
1823 static int
1824 azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
1825                       struct hda_pcm *cpcm)
1826 {
1827         struct azx *chip = bus->private_data;
1828         struct snd_pcm *pcm;
1829         struct azx_pcm *apcm;
1830         int pcm_dev = cpcm->device;
1831         int s, err;
1832
1833         if (pcm_dev >= AZX_MAX_PCMS) {
1834                 snd_printk(KERN_ERR SFX "Invalid PCM device number %d\n",
1835                            pcm_dev);
1836                 return -EINVAL;
1837         }
1838         if (chip->pcm[pcm_dev]) {
1839                 snd_printk(KERN_ERR SFX "PCM %d already exists\n", pcm_dev);
1840                 return -EBUSY;
1841         }
1842         err = snd_pcm_new(chip->card, cpcm->name, pcm_dev,
1843                           cpcm->stream[SNDRV_PCM_STREAM_PLAYBACK].substreams,
1844                           cpcm->stream[SNDRV_PCM_STREAM_CAPTURE].substreams,
1845                           &pcm);
1846         if (err < 0)
1847                 return err;
1848         strlcpy(pcm->name, cpcm->name, sizeof(pcm->name));
1849         apcm = kzalloc(sizeof(*apcm), GFP_KERNEL);
1850         if (apcm == NULL)
1851                 return -ENOMEM;
1852         apcm->chip = chip;
1853         apcm->codec = codec;
1854         pcm->private_data = apcm;
1855         pcm->private_free = azx_pcm_free;
1856         if (cpcm->pcm_type == HDA_PCM_TYPE_MODEM)
1857                 pcm->dev_class = SNDRV_PCM_CLASS_MODEM;
1858         chip->pcm[pcm_dev] = pcm;
1859         cpcm->pcm = pcm;
1860         for (s = 0; s < 2; s++) {
1861                 apcm->hinfo[s] = &cpcm->stream[s];
1862                 if (cpcm->stream[s].substreams)
1863                         snd_pcm_set_ops(pcm, s, &azx_pcm_ops);
1864         }
1865         /* buffer pre-allocation */
1866         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV_SG,
1867                                               snd_dma_pci_data(chip->pci),
1868                                               1024 * 64, 32 * 1024 * 1024);
1869         return 0;
1870 }
1871
1872 /*
1873  * mixer creation - all stuff is implemented in hda module
1874  */
1875 static int __devinit azx_mixer_create(struct azx *chip)
1876 {
1877         return snd_hda_build_controls(chip->bus);
1878 }
1879
1880
1881 /*
1882  * initialize SD streams
1883  */
1884 static int __devinit azx_init_stream(struct azx *chip)
1885 {
1886         int i;
1887
1888         /* initialize each stream (aka device)
1889          * assign the starting bdl address to each stream (device)
1890          * and initialize
1891          */
1892         for (i = 0; i < chip->num_streams; i++) {
1893                 struct azx_dev *azx_dev = &chip->azx_dev[i];
1894                 azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8);
1895                 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
1896                 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
1897                 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
1898                 azx_dev->sd_int_sta_mask = 1 << i;
1899                 /* stream tag: must be non-zero and unique */
1900                 azx_dev->index = i;
1901                 azx_dev->stream_tag = i + 1;
1902         }
1903
1904         return 0;
1905 }
1906
1907 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
1908 {
1909         if (request_irq(chip->pci->irq, azx_interrupt,
1910                         chip->msi ? 0 : IRQF_SHARED,
1911                         "HDA Intel", chip)) {
1912                 printk(KERN_ERR "hda-intel: unable to grab IRQ %d, "
1913                        "disabling device\n", chip->pci->irq);
1914                 if (do_disconnect)
1915                         snd_card_disconnect(chip->card);
1916                 return -1;
1917         }
1918         chip->irq = chip->pci->irq;
1919         pci_intx(chip->pci, !chip->msi);
1920         return 0;
1921 }
1922
1923
1924 static void azx_stop_chip(struct azx *chip)
1925 {
1926         if (!chip->initialized)
1927                 return;
1928
1929         /* disable interrupts */
1930         azx_int_disable(chip);
1931         azx_int_clear(chip);
1932
1933         /* disable CORB/RIRB */
1934         azx_free_cmd_io(chip);
1935
1936         /* disable position buffer */
1937         azx_writel(chip, DPLBASE, 0);
1938         azx_writel(chip, DPUBASE, 0);
1939
1940         chip->initialized = 0;
1941 }
1942
1943 #ifdef CONFIG_SND_HDA_POWER_SAVE
1944 /* power-up/down the controller */
1945 static void azx_power_notify(struct hda_bus *bus)
1946 {
1947         struct azx *chip = bus->private_data;
1948         struct hda_codec *c;
1949         int power_on = 0;
1950
1951         list_for_each_entry(c, &bus->codec_list, list) {
1952                 if (c->power_on) {
1953                         power_on = 1;
1954                         break;
1955                 }
1956         }
1957         if (power_on)
1958                 azx_init_chip(chip);
1959         else if (chip->running && power_save_controller)
1960                 azx_stop_chip(chip);
1961 }
1962 #endif /* CONFIG_SND_HDA_POWER_SAVE */
1963
1964 #ifdef CONFIG_PM
1965 /*
1966  * power management
1967  */
1968
1969 static int snd_hda_codecs_inuse(struct hda_bus *bus)
1970 {
1971         struct hda_codec *codec;
1972
1973         list_for_each_entry(codec, &bus->codec_list, list) {
1974                 if (snd_hda_codec_needs_resume(codec))
1975                         return 1;
1976         }
1977         return 0;
1978 }
1979
1980 static int azx_suspend(struct pci_dev *pci, pm_message_t state)
1981 {
1982         struct snd_card *card = pci_get_drvdata(pci);
1983         struct azx *chip = card->private_data;
1984         int i;
1985
1986         snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
1987         azx_clear_irq_pending(chip);
1988         for (i = 0; i < AZX_MAX_PCMS; i++)
1989                 snd_pcm_suspend_all(chip->pcm[i]);
1990         if (chip->initialized)
1991                 snd_hda_suspend(chip->bus, state);
1992         azx_stop_chip(chip);
1993         if (chip->irq >= 0) {
1994                 free_irq(chip->irq, chip);
1995                 chip->irq = -1;
1996         }
1997         if (chip->msi)
1998                 pci_disable_msi(chip->pci);
1999         pci_disable_device(pci);
2000         pci_save_state(pci);
2001         pci_set_power_state(pci, pci_choose_state(pci, state));
2002         return 0;
2003 }
2004
2005 static int azx_resume(struct pci_dev *pci)
2006 {
2007         struct snd_card *card = pci_get_drvdata(pci);
2008         struct azx *chip = card->private_data;
2009
2010         pci_set_power_state(pci, PCI_D0);
2011         pci_restore_state(pci);
2012         if (pci_enable_device(pci) < 0) {
2013                 printk(KERN_ERR "hda-intel: pci_enable_device failed, "
2014                        "disabling device\n");
2015                 snd_card_disconnect(card);
2016                 return -EIO;
2017         }
2018         pci_set_master(pci);
2019         if (chip->msi)
2020                 if (pci_enable_msi(pci) < 0)
2021                         chip->msi = 0;
2022         if (azx_acquire_irq(chip, 1) < 0)
2023                 return -EIO;
2024         azx_init_pci(chip);
2025
2026         if (snd_hda_codecs_inuse(chip->bus))
2027                 azx_init_chip(chip);
2028
2029         snd_hda_resume(chip->bus);
2030         snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2031         return 0;
2032 }
2033 #endif /* CONFIG_PM */
2034
2035
2036 /*
2037  * reboot notifier for hang-up problem at power-down
2038  */
2039 static int azx_halt(struct notifier_block *nb, unsigned long event, void *buf)
2040 {
2041         struct azx *chip = container_of(nb, struct azx, reboot_notifier);
2042         azx_stop_chip(chip);
2043         return NOTIFY_OK;
2044 }
2045
2046 static void azx_notifier_register(struct azx *chip)
2047 {
2048         chip->reboot_notifier.notifier_call = azx_halt;
2049         register_reboot_notifier(&chip->reboot_notifier);
2050 }
2051
2052 static void azx_notifier_unregister(struct azx *chip)
2053 {
2054         if (chip->reboot_notifier.notifier_call)
2055                 unregister_reboot_notifier(&chip->reboot_notifier);
2056 }
2057
2058 /*
2059  * destructor
2060  */
2061 static int azx_free(struct azx *chip)
2062 {
2063         int i;
2064
2065         azx_notifier_unregister(chip);
2066
2067         if (chip->initialized) {
2068                 azx_clear_irq_pending(chip);
2069                 for (i = 0; i < chip->num_streams; i++)
2070                         azx_stream_stop(chip, &chip->azx_dev[i]);
2071                 azx_stop_chip(chip);
2072         }
2073
2074         if (chip->irq >= 0)
2075                 free_irq(chip->irq, (void*)chip);
2076         if (chip->msi)
2077                 pci_disable_msi(chip->pci);
2078         if (chip->remap_addr)
2079                 iounmap(chip->remap_addr);
2080
2081         if (chip->azx_dev) {
2082                 for (i = 0; i < chip->num_streams; i++)
2083                         if (chip->azx_dev[i].bdl.area)
2084                                 snd_dma_free_pages(&chip->azx_dev[i].bdl);
2085         }
2086         if (chip->rb.area)
2087                 snd_dma_free_pages(&chip->rb);
2088         if (chip->posbuf.area)
2089                 snd_dma_free_pages(&chip->posbuf);
2090         pci_release_regions(chip->pci);
2091         pci_disable_device(chip->pci);
2092         kfree(chip->azx_dev);
2093         kfree(chip);
2094
2095         return 0;
2096 }
2097
2098 static int azx_dev_free(struct snd_device *device)
2099 {
2100         return azx_free(device->device_data);
2101 }
2102
2103 /*
2104  * white/black-listing for position_fix
2105  */
2106 static struct snd_pci_quirk position_fix_list[] __devinitdata = {
2107         SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
2108         SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
2109         SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
2110         {}
2111 };
2112
2113 static int __devinit check_position_fix(struct azx *chip, int fix)
2114 {
2115         const struct snd_pci_quirk *q;
2116
2117         switch (fix) {
2118         case POS_FIX_LPIB:
2119         case POS_FIX_POSBUF:
2120                 return fix;
2121         }
2122
2123         /* Check VIA/ATI HD Audio Controller exist */
2124         switch (chip->driver_type) {
2125         case AZX_DRIVER_VIA:
2126         case AZX_DRIVER_ATI:
2127                 chip->via_dmapos_patch = 1;
2128                 /* Use link position directly, avoid any transfer problem. */
2129                 return POS_FIX_LPIB;
2130         }
2131         chip->via_dmapos_patch = 0;
2132
2133         q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
2134         if (q) {
2135                 printk(KERN_INFO
2136                        "hda_intel: position_fix set to %d "
2137                        "for device %04x:%04x\n",
2138                        q->value, q->subvendor, q->subdevice);
2139                 return q->value;
2140         }
2141         return POS_FIX_AUTO;
2142 }
2143
2144 /*
2145  * black-lists for probe_mask
2146  */
2147 static struct snd_pci_quirk probe_mask_list[] __devinitdata = {
2148         /* Thinkpad often breaks the controller communication when accessing
2149          * to the non-working (or non-existing) modem codec slot.
2150          */
2151         SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
2152         SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
2153         SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
2154         /* broken BIOS */
2155         SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
2156         /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
2157         SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
2158         /* forced codec slots */
2159         SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
2160         SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
2161         {}
2162 };
2163
2164 #define AZX_FORCE_CODEC_MASK    0x100
2165
2166 static void __devinit check_probe_mask(struct azx *chip, int dev)
2167 {
2168         const struct snd_pci_quirk *q;
2169
2170         chip->codec_probe_mask = probe_mask[dev];
2171         if (chip->codec_probe_mask == -1) {
2172                 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
2173                 if (q) {
2174                         printk(KERN_INFO
2175                                "hda_intel: probe_mask set to 0x%x "
2176                                "for device %04x:%04x\n",
2177                                q->value, q->subvendor, q->subdevice);
2178                         chip->codec_probe_mask = q->value;
2179                 }
2180         }
2181
2182         /* check forced option */
2183         if (chip->codec_probe_mask != -1 &&
2184             (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
2185                 chip->codec_mask = chip->codec_probe_mask & 0xff;
2186                 printk(KERN_INFO "hda_intel: codec_mask forced to 0x%x\n",
2187                        chip->codec_mask);
2188         }
2189 }
2190
2191
2192 /*
2193  * constructor
2194  */
2195 static int __devinit azx_create(struct snd_card *card, struct pci_dev *pci,
2196                                 int dev, int driver_type,
2197                                 struct azx **rchip)
2198 {
2199         struct azx *chip;
2200         int i, err;
2201         unsigned short gcap;
2202         static struct snd_device_ops ops = {
2203                 .dev_free = azx_dev_free,
2204         };
2205
2206         *rchip = NULL;
2207
2208         err = pci_enable_device(pci);
2209         if (err < 0)
2210                 return err;
2211
2212         chip = kzalloc(sizeof(*chip), GFP_KERNEL);
2213         if (!chip) {
2214                 snd_printk(KERN_ERR SFX "cannot allocate chip\n");
2215                 pci_disable_device(pci);
2216                 return -ENOMEM;
2217         }
2218
2219         spin_lock_init(&chip->reg_lock);
2220         mutex_init(&chip->open_mutex);
2221         chip->card = card;
2222         chip->pci = pci;
2223         chip->irq = -1;
2224         chip->driver_type = driver_type;
2225         chip->msi = enable_msi;
2226         chip->dev_index = dev;
2227         INIT_WORK(&chip->irq_pending_work, azx_irq_pending_work);
2228
2229         chip->position_fix = check_position_fix(chip, position_fix[dev]);
2230         check_probe_mask(chip, dev);
2231
2232         chip->single_cmd = single_cmd;
2233
2234         if (bdl_pos_adj[dev] < 0) {
2235                 switch (chip->driver_type) {
2236                 case AZX_DRIVER_ICH:
2237                         bdl_pos_adj[dev] = 1;
2238                         break;
2239                 default:
2240                         bdl_pos_adj[dev] = 32;
2241                         break;
2242                 }
2243         }
2244
2245 #if BITS_PER_LONG != 64
2246         /* Fix up base address on ULI M5461 */
2247         if (chip->driver_type == AZX_DRIVER_ULI) {
2248                 u16 tmp3;
2249                 pci_read_config_word(pci, 0x40, &tmp3);
2250                 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
2251                 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
2252         }
2253 #endif
2254
2255         err = pci_request_regions(pci, "ICH HD audio");
2256         if (err < 0) {
2257                 kfree(chip);
2258                 pci_disable_device(pci);
2259                 return err;
2260         }
2261
2262         chip->addr = pci_resource_start(pci, 0);
2263         chip->remap_addr = pci_ioremap_bar(pci, 0);
2264         if (chip->remap_addr == NULL) {
2265                 snd_printk(KERN_ERR SFX "ioremap error\n");
2266                 err = -ENXIO;
2267                 goto errout;
2268         }
2269
2270         if (chip->msi)
2271                 if (pci_enable_msi(pci) < 0)
2272                         chip->msi = 0;
2273
2274         if (azx_acquire_irq(chip, 0) < 0) {
2275                 err = -EBUSY;
2276                 goto errout;
2277         }
2278
2279         pci_set_master(pci);
2280         synchronize_irq(chip->irq);
2281
2282         gcap = azx_readw(chip, GCAP);
2283         snd_printdd(SFX "chipset global capabilities = 0x%x\n", gcap);
2284
2285         /* ATI chips seems buggy about 64bit DMA addresses */
2286         if (chip->driver_type == AZX_DRIVER_ATI)
2287                 gcap &= ~0x01;
2288
2289         /* allow 64bit DMA address if supported by H/W */
2290         if ((gcap & 0x01) && !pci_set_dma_mask(pci, DMA_BIT_MASK(64)))
2291                 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(64));
2292         else {
2293                 pci_set_dma_mask(pci, DMA_BIT_MASK(32));
2294                 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(32));
2295         }
2296
2297         /* read number of streams from GCAP register instead of using
2298          * hardcoded value
2299          */
2300         chip->capture_streams = (gcap >> 8) & 0x0f;
2301         chip->playback_streams = (gcap >> 12) & 0x0f;
2302         if (!chip->playback_streams && !chip->capture_streams) {
2303                 /* gcap didn't give any info, switching to old method */
2304
2305                 switch (chip->driver_type) {
2306                 case AZX_DRIVER_ULI:
2307                         chip->playback_streams = ULI_NUM_PLAYBACK;
2308                         chip->capture_streams = ULI_NUM_CAPTURE;
2309                         break;
2310                 case AZX_DRIVER_ATIHDMI:
2311                         chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
2312                         chip->capture_streams = ATIHDMI_NUM_CAPTURE;
2313                         break;
2314                 case AZX_DRIVER_GENERIC:
2315                 default:
2316                         chip->playback_streams = ICH6_NUM_PLAYBACK;
2317                         chip->capture_streams = ICH6_NUM_CAPTURE;
2318                         break;
2319                 }
2320         }
2321         chip->capture_index_offset = 0;
2322         chip->playback_index_offset = chip->capture_streams;
2323         chip->num_streams = chip->playback_streams + chip->capture_streams;
2324         chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev),
2325                                 GFP_KERNEL);
2326         if (!chip->azx_dev) {
2327                 snd_printk(KERN_ERR SFX "cannot malloc azx_dev\n");
2328                 goto errout;
2329         }
2330
2331         for (i = 0; i < chip->num_streams; i++) {
2332                 /* allocate memory for the BDL for each stream */
2333                 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
2334                                           snd_dma_pci_data(chip->pci),
2335                                           BDL_SIZE, &chip->azx_dev[i].bdl);
2336                 if (err < 0) {
2337                         snd_printk(KERN_ERR SFX "cannot allocate BDL\n");
2338                         goto errout;
2339                 }
2340         }
2341         /* allocate memory for the position buffer */
2342         err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
2343                                   snd_dma_pci_data(chip->pci),
2344                                   chip->num_streams * 8, &chip->posbuf);
2345         if (err < 0) {
2346                 snd_printk(KERN_ERR SFX "cannot allocate posbuf\n");
2347                 goto errout;
2348         }
2349         /* allocate CORB/RIRB */
2350         err = azx_alloc_cmd_io(chip);
2351         if (err < 0)
2352                 goto errout;
2353
2354         /* initialize streams */
2355         azx_init_stream(chip);
2356
2357         /* initialize chip */
2358         azx_init_pci(chip);
2359         azx_init_chip(chip);
2360
2361         /* codec detection */
2362         if (!chip->codec_mask) {
2363                 snd_printk(KERN_ERR SFX "no codecs found!\n");
2364                 err = -ENODEV;
2365                 goto errout;
2366         }
2367
2368         err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
2369         if (err <0) {
2370                 snd_printk(KERN_ERR SFX "Error creating device [card]!\n");
2371                 goto errout;
2372         }
2373
2374         strcpy(card->driver, "HDA-Intel");
2375         strlcpy(card->shortname, driver_short_names[chip->driver_type],
2376                 sizeof(card->shortname));
2377         snprintf(card->longname, sizeof(card->longname),
2378                  "%s at 0x%lx irq %i",
2379                  card->shortname, chip->addr, chip->irq);
2380
2381         *rchip = chip;
2382         return 0;
2383
2384  errout:
2385         azx_free(chip);
2386         return err;
2387 }
2388
2389 static void power_down_all_codecs(struct azx *chip)
2390 {
2391 #ifdef CONFIG_SND_HDA_POWER_SAVE
2392         /* The codecs were powered up in snd_hda_codec_new().
2393          * Now all initialization done, so turn them down if possible
2394          */
2395         struct hda_codec *codec;
2396         list_for_each_entry(codec, &chip->bus->codec_list, list) {
2397                 snd_hda_power_down(codec);
2398         }
2399 #endif
2400 }
2401
2402 static int __devinit azx_probe(struct pci_dev *pci,
2403                                const struct pci_device_id *pci_id)
2404 {
2405         static int dev;
2406         struct snd_card *card;
2407         struct azx *chip;
2408         int err;
2409
2410         if (dev >= SNDRV_CARDS)
2411                 return -ENODEV;
2412         if (!enable[dev]) {
2413                 dev++;
2414                 return -ENOENT;
2415         }
2416
2417         err = snd_card_create(index[dev], id[dev], THIS_MODULE, 0, &card);
2418         if (err < 0) {
2419                 snd_printk(KERN_ERR SFX "Error creating card!\n");
2420                 return err;
2421         }
2422
2423         err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
2424         if (err < 0)
2425                 goto out_free;
2426         card->private_data = chip;
2427
2428         /* create codec instances */
2429         err = azx_codec_create(chip, model[dev], probe_only[dev]);
2430         if (err < 0)
2431                 goto out_free;
2432
2433         /* create PCM streams */
2434         err = snd_hda_build_pcms(chip->bus);
2435         if (err < 0)
2436                 goto out_free;
2437
2438         /* create mixer controls */
2439         err = azx_mixer_create(chip);
2440         if (err < 0)
2441                 goto out_free;
2442
2443         snd_card_set_dev(card, &pci->dev);
2444
2445         err = snd_card_register(card);
2446         if (err < 0)
2447                 goto out_free;
2448
2449         pci_set_drvdata(pci, card);
2450         chip->running = 1;
2451         power_down_all_codecs(chip);
2452         azx_notifier_register(chip);
2453
2454         dev++;
2455         return err;
2456 out_free:
2457         snd_card_free(card);
2458         return err;
2459 }
2460
2461 static void __devexit azx_remove(struct pci_dev *pci)
2462 {
2463         snd_card_free(pci_get_drvdata(pci));
2464         pci_set_drvdata(pci, NULL);
2465 }
2466
2467 /* PCI IDs */
2468 static struct pci_device_id azx_ids[] = {
2469         /* ICH 6..10 */
2470         { PCI_DEVICE(0x8086, 0x2668), .driver_data = AZX_DRIVER_ICH },
2471         { PCI_DEVICE(0x8086, 0x27d8), .driver_data = AZX_DRIVER_ICH },
2472         { PCI_DEVICE(0x8086, 0x269a), .driver_data = AZX_DRIVER_ICH },
2473         { PCI_DEVICE(0x8086, 0x284b), .driver_data = AZX_DRIVER_ICH },
2474         { PCI_DEVICE(0x8086, 0x2911), .driver_data = AZX_DRIVER_ICH },
2475         { PCI_DEVICE(0x8086, 0x293e), .driver_data = AZX_DRIVER_ICH },
2476         { PCI_DEVICE(0x8086, 0x293f), .driver_data = AZX_DRIVER_ICH },
2477         { PCI_DEVICE(0x8086, 0x3a3e), .driver_data = AZX_DRIVER_ICH },
2478         { PCI_DEVICE(0x8086, 0x3a6e), .driver_data = AZX_DRIVER_ICH },
2479         /* PCH */
2480         { PCI_DEVICE(0x8086, 0x3b56), .driver_data = AZX_DRIVER_ICH },
2481         /* SCH */
2482         { PCI_DEVICE(0x8086, 0x811b), .driver_data = AZX_DRIVER_SCH },
2483         /* ATI SB 450/600 */
2484         { PCI_DEVICE(0x1002, 0x437b), .driver_data = AZX_DRIVER_ATI },
2485         { PCI_DEVICE(0x1002, 0x4383), .driver_data = AZX_DRIVER_ATI },
2486         /* ATI HDMI */
2487         { PCI_DEVICE(0x1002, 0x793b), .driver_data = AZX_DRIVER_ATIHDMI },
2488         { PCI_DEVICE(0x1002, 0x7919), .driver_data = AZX_DRIVER_ATIHDMI },
2489         { PCI_DEVICE(0x1002, 0x960f), .driver_data = AZX_DRIVER_ATIHDMI },
2490         { PCI_DEVICE(0x1002, 0x970f), .driver_data = AZX_DRIVER_ATIHDMI },
2491         { PCI_DEVICE(0x1002, 0xaa00), .driver_data = AZX_DRIVER_ATIHDMI },
2492         { PCI_DEVICE(0x1002, 0xaa08), .driver_data = AZX_DRIVER_ATIHDMI },
2493         { PCI_DEVICE(0x1002, 0xaa10), .driver_data = AZX_DRIVER_ATIHDMI },
2494         { PCI_DEVICE(0x1002, 0xaa18), .driver_data = AZX_DRIVER_ATIHDMI },
2495         { PCI_DEVICE(0x1002, 0xaa20), .driver_data = AZX_DRIVER_ATIHDMI },
2496         { PCI_DEVICE(0x1002, 0xaa28), .driver_data = AZX_DRIVER_ATIHDMI },
2497         { PCI_DEVICE(0x1002, 0xaa30), .driver_data = AZX_DRIVER_ATIHDMI },
2498         { PCI_DEVICE(0x1002, 0xaa38), .driver_data = AZX_DRIVER_ATIHDMI },
2499         { PCI_DEVICE(0x1002, 0xaa40), .driver_data = AZX_DRIVER_ATIHDMI },
2500         { PCI_DEVICE(0x1002, 0xaa48), .driver_data = AZX_DRIVER_ATIHDMI },
2501         /* VIA VT8251/VT8237A */
2502         { PCI_DEVICE(0x1106, 0x3288), .driver_data = AZX_DRIVER_VIA },
2503         /* SIS966 */
2504         { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
2505         /* ULI M5461 */
2506         { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
2507         /* NVIDIA MCP */
2508         { PCI_DEVICE(0x10de, 0x026c), .driver_data = AZX_DRIVER_NVIDIA },
2509         { PCI_DEVICE(0x10de, 0x0371), .driver_data = AZX_DRIVER_NVIDIA },
2510         { PCI_DEVICE(0x10de, 0x03e4), .driver_data = AZX_DRIVER_NVIDIA },
2511         { PCI_DEVICE(0x10de, 0x03f0), .driver_data = AZX_DRIVER_NVIDIA },
2512         { PCI_DEVICE(0x10de, 0x044a), .driver_data = AZX_DRIVER_NVIDIA },
2513         { PCI_DEVICE(0x10de, 0x044b), .driver_data = AZX_DRIVER_NVIDIA },
2514         { PCI_DEVICE(0x10de, 0x055c), .driver_data = AZX_DRIVER_NVIDIA },
2515         { PCI_DEVICE(0x10de, 0x055d), .driver_data = AZX_DRIVER_NVIDIA },
2516         { PCI_DEVICE(0x10de, 0x0774), .driver_data = AZX_DRIVER_NVIDIA },
2517         { PCI_DEVICE(0x10de, 0x0775), .driver_data = AZX_DRIVER_NVIDIA },
2518         { PCI_DEVICE(0x10de, 0x0776), .driver_data = AZX_DRIVER_NVIDIA },
2519         { PCI_DEVICE(0x10de, 0x0777), .driver_data = AZX_DRIVER_NVIDIA },
2520         { PCI_DEVICE(0x10de, 0x07fc), .driver_data = AZX_DRIVER_NVIDIA },
2521         { PCI_DEVICE(0x10de, 0x07fd), .driver_data = AZX_DRIVER_NVIDIA },
2522         { PCI_DEVICE(0x10de, 0x0ac0), .driver_data = AZX_DRIVER_NVIDIA },
2523         { PCI_DEVICE(0x10de, 0x0ac1), .driver_data = AZX_DRIVER_NVIDIA },
2524         { PCI_DEVICE(0x10de, 0x0ac2), .driver_data = AZX_DRIVER_NVIDIA },
2525         { PCI_DEVICE(0x10de, 0x0ac3), .driver_data = AZX_DRIVER_NVIDIA },
2526         { PCI_DEVICE(0x10de, 0x0d94), .driver_data = AZX_DRIVER_NVIDIA },
2527         { PCI_DEVICE(0x10de, 0x0d95), .driver_data = AZX_DRIVER_NVIDIA },
2528         { PCI_DEVICE(0x10de, 0x0d96), .driver_data = AZX_DRIVER_NVIDIA },
2529         { PCI_DEVICE(0x10de, 0x0d97), .driver_data = AZX_DRIVER_NVIDIA },
2530         /* Teradici */
2531         { PCI_DEVICE(0x6549, 0x1200), .driver_data = AZX_DRIVER_TERA },
2532         /* Creative X-Fi (CA0110-IBG) */
2533 #if !defined(CONFIG_SND_CTXFI) && !defined(CONFIG_SND_CTXFI_MODULE)
2534         /* the following entry conflicts with snd-ctxfi driver,
2535          * as ctxfi driver mutates from HD-audio to native mode with
2536          * a special command sequence.
2537          */
2538         { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
2539           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2540           .class_mask = 0xffffff,
2541           .driver_data = AZX_DRIVER_GENERIC },
2542 #else
2543         /* this entry seems still valid -- i.e. without emu20kx chip */
2544         { PCI_DEVICE(0x1102, 0x0009), .driver_data = AZX_DRIVER_GENERIC },
2545 #endif
2546         /* AMD Generic, PCI class code and Vendor ID for HD Audio */
2547         { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
2548           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2549           .class_mask = 0xffffff,
2550           .driver_data = AZX_DRIVER_GENERIC },
2551         { 0, }
2552 };
2553 MODULE_DEVICE_TABLE(pci, azx_ids);
2554
2555 /* pci_driver definition */
2556 static struct pci_driver driver = {
2557         .name = "HDA Intel",
2558         .id_table = azx_ids,
2559         .probe = azx_probe,
2560         .remove = __devexit_p(azx_remove),
2561 #ifdef CONFIG_PM
2562         .suspend = azx_suspend,
2563         .resume = azx_resume,
2564 #endif
2565 };
2566
2567 static int __init alsa_card_azx_init(void)
2568 {
2569         return pci_register_driver(&driver);
2570 }
2571
2572 static void __exit alsa_card_azx_exit(void)
2573 {
2574         pci_unregister_driver(&driver);
2575 }
2576
2577 module_init(alsa_card_azx_init)
2578 module_exit(alsa_card_azx_exit)