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   1 /*
   2  *  Driver for Ensoniq ES1370/ES1371 AudioPCI soundcard
   3  *  Copyright (c) by Jaroslav Kysela <perex@suse.cz>,
   4  *                   Thomas Sailer <sailer@ife.ee.ethz.ch>
   5  *
   6  *   This program is free software; you can redistribute it and/or modify
   7  *   it under the terms of the GNU General Public License as published by
   8  *   the Free Software Foundation; either version 2 of the License, or
   9  *   (at your option) any later version.
  10  *
  11  *   This program is distributed in the hope that it will be useful,
  12  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  *   GNU General Public License for more details.
  15  *
  16  *   You should have received a copy of the GNU General Public License
  17  *   along with this program; if not, write to the Free Software
  18  *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  19  *
  20  */
  21
  22 #include <sound/driver.h>
  23 #include <asm/io.h>
  24 #include <linux/delay.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/init.h>
  27 #include <linux/pci.h>
  28 #include <linux/slab.h>
  29 #include <linux/gameport.h>
  30 #include <linux/moduleparam.h>
  31 #include <sound/core.h>
  32 #include <sound/control.h>
  33 #include <sound/pcm.h>
  34 #include <sound/rawmidi.h>
  35 #ifdef CHIP1371
  36 #include <sound/ac97_codec.h>
  37 #else
  38 #include <sound/ak4531_codec.h>
  39 #endif
  40 #include <sound/initval.h>
  41 #include <sound/asoundef.h>
  42
  43 #ifndef CHIP1371
  44 #undef CHIP1370
  45 #define CHIP1370
  46 #endif
  47
  48 #ifdef CHIP1370
  49 #define DRIVER_NAME "ENS1370"
  50 #else
  51 #define DRIVER_NAME "ENS1371"
  52 #endif
  53
  54
  55 MODULE_AUTHOR("Jaroslav Kysela <perex@suse.cz>, Thomas Sailer <sailer@ife.ee.ethz.ch>");
  56 MODULE_LICENSE("GPL");
  57 #ifdef CHIP1370
  58 MODULE_DESCRIPTION("Ensoniq AudioPCI ES1370");
  59 MODULE_SUPPORTED_DEVICE("{{Ensoniq,AudioPCI-97 ES1370},"
  60                 "{Creative Labs,SB PCI64/128 (ES1370)}}");
  61 #endif
  62 #ifdef CHIP1371
  63 MODULE_DESCRIPTION("Ensoniq/Creative AudioPCI ES1371+");
  64 MODULE_SUPPORTED_DEVICE("{{Ensoniq,AudioPCI ES1371/73},"
  65                 "{Ensoniq,AudioPCI ES1373},"
  66                 "{Creative Labs,Ectiva EV1938},"
  67                 "{Creative Labs,SB PCI64/128 (ES1371/73)},"
  68                 "{Creative Labs,Vibra PCI128},"
  69                 "{Ectiva,EV1938}}");
  70 #endif
  71
  72 #if defined(CONFIG_GAMEPORT) || (defined(MODULE) && defined(CONFIG_GAMEPORT_MODULE))
  73 #define SUPPORT_JOYSTICK
  74 #endif
  75
  76 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;      /* Index 0-MAX */
  77 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;       /* ID for this card */
  78 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;      /* Enable switches */
  79 #ifdef SUPPORT_JOYSTICK
  80 #ifdef CHIP1371
  81 static int joystick_port[SNDRV_CARDS];
  82 #else
  83 static int joystick[SNDRV_CARDS];
  84 #endif
  85 #endif
  86
  87 module_param_array(index, int, NULL, 0444);
  88 MODULE_PARM_DESC(index, "Index value for Ensoniq AudioPCI soundcard.");
  89 module_param_array(id, charp, NULL, 0444);
  90 MODULE_PARM_DESC(id, "ID string for Ensoniq AudioPCI soundcard.");
  91 module_param_array(enable, bool, NULL, 0444);
  92 MODULE_PARM_DESC(enable, "Enable Ensoniq AudioPCI soundcard.");
  93 #ifdef SUPPORT_JOYSTICK
  94 #ifdef CHIP1371
  95 module_param_array(joystick_port, int, NULL, 0444);
  96 MODULE_PARM_DESC(joystick_port, "Joystick port address.");
  97 #else
  98 module_param_array(joystick, bool, NULL, 0444);
  99 MODULE_PARM_DESC(joystick, "Enable joystick.");
 100 #endif
 101 #endif /* SUPPORT_JOYSTICK */
 102
 103 /* ES1371 chip ID */
 104 /* This is a little confusing because all ES1371 compatible chips have the
 105    same DEVICE_ID, the only thing differentiating them is the REV_ID field.
 106    This is only significant if you want to enable features on the later parts.
 107    Yes, I know it's stupid and why didn't we use the sub IDs?
 108 */
 109 #define ES1371REV_ES1373_A  0x04
 110 #define ES1371REV_ES1373_B  0x06
 111 #define ES1371REV_CT5880_A  0x07
 112 #define CT5880REV_CT5880_C  0x02
 113 #define CT5880REV_CT5880_D  0x03        /* ??? -jk */
 114 #define CT5880REV_CT5880_E  0x04        /* mw */
 115 #define ES1371REV_ES1371_B  0x09
 116 #define EV1938REV_EV1938_A  0x00
 117 #define ES1371REV_ES1373_8  0x08
 118
 119 /*
 120  * Direct registers
 121  */
 122
 123 #define ES_REG(ensoniq, x) ((ensoniq)->port + ES_REG_##x)
 124
 125 #define ES_REG_CONTROL  0x00    /* R/W: Interrupt/Chip select control register */
 126 #define   ES_1370_ADC_STOP      (1<<31)         /* disable capture buffer transfers */
 127 #define   ES_1370_XCTL1         (1<<30)         /* general purpose output bit */
 128 #define   ES_1373_BYPASS_P1     (1<<31)         /* bypass SRC for PB1 */
 129 #define   ES_1373_BYPASS_P2     (1<<30)         /* bypass SRC for PB2 */
 130 #define   ES_1373_BYPASS_R      (1<<29)         /* bypass SRC for REC */
 131 #define   ES_1373_TEST_BIT      (1<<28)         /* should be set to 0 for normal operation */
 132 #define   ES_1373_RECEN_B       (1<<27)         /* mix record with playback for I2S/SPDIF out */
 133 #define   ES_1373_SPDIF_THRU    (1<<26)         /* 0 = SPDIF thru mode, 1 = SPDIF == dig out */
 134 #define   ES_1371_JOY_ASEL(o)   (((o)&0x03)<<24)/* joystick port mapping */
 135 #define   ES_1371_JOY_ASELM     (0x03<<24)      /* mask for above */
 136 #define   ES_1371_JOY_ASELI(i)  (((i)>>24)&0x03)
 137 #define   ES_1371_GPIO_IN(i)    (((i)>>20)&0x0f)/* GPIO in [3:0] pins - R/O */
 138 #define   ES_1370_PCLKDIVO(o)   (((o)&0x1fff)<<16)/* clock divide ratio for DAC2 */
 139 #define   ES_1370_PCLKDIVM      ((0x1fff)<<16)  /* mask for above */
 140 #define   ES_1370_PCLKDIVI(i)   (((i)>>16)&0x1fff)/* clock divide ratio for DAC2 */
 141 #define   ES_1371_GPIO_OUT(o)   (((o)&0x0f)<<16)/* GPIO out [3:0] pins - W/R */
 142 #define   ES_1371_GPIO_OUTM     (0x0f<<16)      /* mask for above */
 143 #define   ES_MSFMTSEL           (1<<15)         /* MPEG serial data format; 0 = SONY, 1 = I2S */
 144 #define   ES_1370_M_SBB         (1<<14)         /* clock source for DAC - 0 = clock generator; 1 = MPEG clocks */
 145 #define   ES_1371_SYNC_RES      (1<<14)         /* Warm AC97 reset */
 146 #define   ES_1370_WTSRSEL(o)    (((o)&0x03)<<12)/* fixed frequency clock for DAC1 */
 147 #define   ES_1370_WTSRSELM      (0x03<<12)      /* mask for above */
 148 #define   ES_1371_ADC_STOP      (1<<13)         /* disable CCB transfer capture information */
 149 #define   ES_1371_PWR_INTRM     (1<<12)         /* power level change interrupts enable */
 150 #define   ES_1370_DAC_SYNC      (1<<11)         /* DAC's are synchronous */
 151 #define   ES_1371_M_CB          (1<<11)         /* capture clock source; 0 = AC'97 ADC; 1 = I2S */
 152 #define   ES_CCB_INTRM          (1<<10)         /* CCB voice interrupts enable */
 153 #define   ES_1370_M_CB          (1<<9)          /* capture clock source; 0 = ADC; 1 = MPEG */
 154 #define   ES_1370_XCTL0         (1<<8)          /* generap purpose output bit */
 155 #define   ES_1371_PDLEV(o)      (((o)&0x03)<<8) /* current power down level */
 156 #define   ES_1371_PDLEVM        (0x03<<8)       /* mask for above */
 157 #define   ES_BREQ               (1<<7)          /* memory bus request enable */
 158 #define   ES_DAC1_EN            (1<<6)          /* DAC1 playback channel enable */
 159 #define   ES_DAC2_EN            (1<<5)          /* DAC2 playback channel enable */
 160 #define   ES_ADC_EN             (1<<4)          /* ADC capture channel enable */
 161 #define   ES_UART_EN            (1<<3)          /* UART enable */
 162 #define   ES_JYSTK_EN           (1<<2)          /* Joystick module enable */
 163 #define   ES_1370_CDC_EN        (1<<1)          /* Codec interface enable */
 164 #define   ES_1371_XTALCKDIS     (1<<1)          /* Xtal clock disable */
 165 #define   ES_1370_SERR_DISABLE  (1<<0)          /* PCI serr signal disable */
 166 #define   ES_1371_PCICLKDIS     (1<<0)          /* PCI clock disable */
 167 #define ES_REG_STATUS   0x04    /* R/O: Interrupt/Chip select status register */
 168 #define   ES_INTR               (1<<31)         /* Interrupt is pending */
 169 #define   ES_1371_ST_AC97_RST   (1<<29)         /* CT5880 AC'97 Reset bit */
 170 #define   ES_1373_REAR_BIT27    (1<<27)         /* rear bits: 000 - front, 010 - mirror, 101 - separate */
 171 #define   ES_1373_REAR_BIT26    (1<<26)
 172 #define   ES_1373_REAR_BIT24    (1<<24)
 173 #define   ES_1373_GPIO_INT_EN(o)(((o)&0x0f)<<20)/* GPIO [3:0] pins - interrupt enable */
 174 #define   ES_1373_SPDIF_EN      (1<<18)         /* SPDIF enable */
 175 #define   ES_1373_SPDIF_TEST    (1<<17)         /* SPDIF test */
 176 #define   ES_1371_TEST          (1<<16)         /* test ASIC */
 177 #define   ES_1373_GPIO_INT(i)   (((i)&0x0f)>>12)/* GPIO [3:0] pins - interrupt pending */
 178 #define   ES_1370_CSTAT         (1<<10)         /* CODEC is busy or register write in progress */
 179 #define   ES_1370_CBUSY         (1<<9)          /* CODEC is busy */
 180 #define   ES_1370_CWRIP         (1<<8)          /* CODEC register write in progress */
 181 #define   ES_1371_SYNC_ERR      (1<<8)          /* CODEC synchronization error occurred */
 182 #define   ES_1371_VC(i)         (((i)>>6)&0x03) /* voice code from CCB module */
 183 #define   ES_1370_VC(i)         (((i)>>5)&0x03) /* voice code from CCB module */
 184 #define   ES_1371_MPWR          (1<<5)          /* power level interrupt pending */
 185 #define   ES_MCCB               (1<<4)          /* CCB interrupt pending */
 186 #define   ES_UART               (1<<3)          /* UART interrupt pending */
 187 #define   ES_DAC1               (1<<2)          /* DAC1 channel interrupt pending */
 188 #define   ES_DAC2               (1<<1)          /* DAC2 channel interrupt pending */
 189 #define   ES_ADC                (1<<0)          /* ADC channel interrupt pending */
 190 #define ES_REG_UART_DATA 0x08   /* R/W: UART data register */
 191 #define ES_REG_UART_STATUS 0x09 /* R/O: UART status register */
 192 #define   ES_RXINT              (1<<7)          /* RX interrupt occurred */
 193 #define   ES_TXINT              (1<<2)          /* TX interrupt occurred */
 194 #define   ES_TXRDY              (1<<1)          /* transmitter ready */
 195 #define   ES_RXRDY              (1<<0)          /* receiver ready */
 196 #define ES_REG_UART_CONTROL 0x09        /* W/O: UART control register */
 197 #define   ES_RXINTEN            (1<<7)          /* RX interrupt enable */
 198 #define   ES_TXINTENO(o)        (((o)&0x03)<<5) /* TX interrupt enable */
 199 #define   ES_TXINTENM           (0x03<<5)       /* mask for above */
 200 #define   ES_TXINTENI(i)        (((i)>>5)&0x03)
 201 #define   ES_CNTRL(o)           (((o)&0x03)<<0) /* control */
 202 #define   ES_CNTRLM             (0x03<<0)       /* mask for above */
 203 #define ES_REG_UART_RES 0x0a    /* R/W: UART reserver register */
 204 #define   ES_TEST_MODE          (1<<0)          /* test mode enabled */
 205 #define ES_REG_MEM_PAGE 0x0c    /* R/W: Memory page register */
 206 #define   ES_MEM_PAGEO(o)       (((o)&0x0f)<<0) /* memory page select - out */
 207 #define   ES_MEM_PAGEM          (0x0f<<0)       /* mask for above */
 208 #define   ES_MEM_PAGEI(i)       (((i)>>0)&0x0f) /* memory page select - in */
 209 #define ES_REG_1370_CODEC 0x10  /* W/O: Codec write register address */
 210 #define   ES_1370_CODEC_WRITE(a,d) ((((a)&0xff)<<8)|(((d)&0xff)<<0))
 211 #define ES_REG_1371_CODEC 0x14  /* W/R: Codec Read/Write register address */
 212 #define   ES_1371_CODEC_RDY        (1<<31)      /* codec ready */
 213 #define   ES_1371_CODEC_WIP        (1<<30)      /* codec register access in progress */
 214 #define   ES_1371_CODEC_PIRD       (1<<23)      /* codec read/write select register */
 215 #define   ES_1371_CODEC_WRITE(a,d) ((((a)&0x7f)<<16)|(((d)&0xffff)<<0))
 216 #define   ES_1371_CODEC_READS(a)   ((((a)&0x7f)<<16)|ES_1371_CODEC_PIRD)
 217 #define   ES_1371_CODEC_READ(i)    (((i)>>0)&0xffff)
 218
 219 #define ES_REG_1371_SMPRATE 0x10        /* W/R: Codec rate converter interface register */
 220 #define   ES_1371_SRC_RAM_ADDRO(o) (((o)&0x7f)<<25)/* address of the sample rate converter */
 221 #define   ES_1371_SRC_RAM_ADDRM    (0x7f<<25)   /* mask for above */
 222 #define   ES_1371_SRC_RAM_ADDRI(i) (((i)>>25)&0x7f)/* address of the sample rate converter */
 223 #define   ES_1371_SRC_RAM_WE       (1<<24)      /* R/W: read/write control for sample rate converter */
 224 #define   ES_1371_SRC_RAM_BUSY     (1<<23)      /* R/O: sample rate memory is busy */
 225 #define   ES_1371_SRC_DISABLE      (1<<22)      /* sample rate converter disable */
 226 #define   ES_1371_DIS_P1           (1<<21)      /* playback channel 1 accumulator update disable */
 227 #define   ES_1371_DIS_P2           (1<<20)      /* playback channel 1 accumulator update disable */
 228 #define   ES_1371_DIS_R1           (1<<19)      /* capture channel accumulator update disable */
 229 #define   ES_1371_SRC_RAM_DATAO(o) (((o)&0xffff)<<0)/* current value of the sample rate converter */
 230 #define   ES_1371_SRC_RAM_DATAM    (0xffff<<0)  /* mask for above */
 231 #define   ES_1371_SRC_RAM_DATAI(i) (((i)>>0)&0xffff)/* current value of the sample rate converter */
 232
 233 #define ES_REG_1371_LEGACY 0x18 /* W/R: Legacy control/status register */
 234 #define   ES_1371_JFAST         (1<<31)         /* fast joystick timing */
 235 #define   ES_1371_HIB           (1<<30)         /* host interrupt blocking enable */
 236 #define   ES_1371_VSB           (1<<29)         /* SB; 0 = addr 0x220xH, 1 = 0x22FxH */
 237 #define   ES_1371_VMPUO(o)      (((o)&0x03)<<27)/* base register address; 0 = 0x320xH; 1 = 0x330xH; 2 = 0x340xH; 3 = 0x350xH */
 238 #define   ES_1371_VMPUM         (0x03<<27)      /* mask for above */
 239 #define   ES_1371_VMPUI(i)      (((i)>>27)&0x03)/* base register address */
 240 #define   ES_1371_VCDCO(o)      (((o)&0x03)<<25)/* CODEC; 0 = 0x530xH; 1 = undefined; 2 = 0xe80xH; 3 = 0xF40xH */
 241 #define   ES_1371_VCDCM         (0x03<<25)      /* mask for above */
 242 #define   ES_1371_VCDCI(i)      (((i)>>25)&0x03)/* CODEC address */
 243 #define   ES_1371_FIRQ          (1<<24)         /* force an interrupt */
 244 #define   ES_1371_SDMACAP       (1<<23)         /* enable event capture for slave DMA controller */
 245 #define   ES_1371_SPICAP        (1<<22)         /* enable event capture for slave IRQ controller */
 246 #define   ES_1371_MDMACAP       (1<<21)         /* enable event capture for master DMA controller */
 247 #define   ES_1371_MPICAP        (1<<20)         /* enable event capture for master IRQ controller */
 248 #define   ES_1371_ADCAP         (1<<19)         /* enable event capture for ADLIB register; 0x388xH */
 249 #define   ES_1371_SVCAP         (1<<18)         /* enable event capture for SB registers */
 250 #define   ES_1371_CDCCAP        (1<<17)         /* enable event capture for CODEC registers */
 251 #define   ES_1371_BACAP         (1<<16)         /* enable event capture for SoundScape base address */
 252 #define   ES_1371_EXI(i)        (((i)>>8)&0x07) /* event number */
 253 #define   ES_1371_AI(i)         (((i)>>3)&0x1f) /* event significant I/O address */
 254 #define   ES_1371_WR            (1<<2)  /* event capture; 0 = read; 1 = write */
 255 #define   ES_1371_LEGINT        (1<<0)  /* interrupt for legacy events; 0 = interrupt did occur */
 256
 257 #define ES_REG_CHANNEL_STATUS 0x1c /* R/W: first 32-bits from S/PDIF channel status block, es1373 */
 258
 259 #define ES_REG_SERIAL   0x20    /* R/W: Serial interface control register */
 260 #define   ES_1371_DAC_TEST      (1<<22)         /* DAC test mode enable */
 261 #define   ES_P2_END_INCO(o)     (((o)&0x07)<<19)/* binary offset value to increment / loop end */
 262 #define   ES_P2_END_INCM        (0x07<<19)      /* mask for above */
 263 #define   ES_P2_END_INCI(i)     (((i)>>16)&0x07)/* binary offset value to increment / loop end */
 264 #define   ES_P2_ST_INCO(o)      (((o)&0x07)<<16)/* binary offset value to increment / start */
 265 #define   ES_P2_ST_INCM         (0x07<<16)      /* mask for above */
 266 #define   ES_P2_ST_INCI(i)      (((i)<<16)&0x07)/* binary offset value to increment / start */
 267 #define   ES_R1_LOOP_SEL        (1<<15)         /* ADC; 0 - loop mode; 1 = stop mode */
 268 #define   ES_P2_LOOP_SEL        (1<<14)         /* DAC2; 0 - loop mode; 1 = stop mode */
 269 #define   ES_P1_LOOP_SEL        (1<<13)         /* DAC1; 0 - loop mode; 1 = stop mode */
 270 #define   ES_P2_PAUSE           (1<<12)         /* DAC2; 0 - play mode; 1 = pause mode */
 271 #define   ES_P1_PAUSE           (1<<11)         /* DAC1; 0 - play mode; 1 = pause mode */
 272 #define   ES_R1_INT_EN          (1<<10)         /* ADC interrupt enable */
 273 #define   ES_P2_INT_EN          (1<<9)          /* DAC2 interrupt enable */
 274 #define   ES_P1_INT_EN          (1<<8)          /* DAC1 interrupt enable */
 275 #define   ES_P1_SCT_RLD         (1<<7)          /* force sample counter reload for DAC1 */
 276 #define   ES_P2_DAC_SEN         (1<<6)          /* when stop mode: 0 - DAC2 play back zeros; 1 = DAC2 play back last sample */
 277 #define   ES_R1_MODEO(o)        (((o)&0x03)<<4) /* ADC mode; 0 = 8-bit mono; 1 = 8-bit stereo; 2 = 16-bit mono; 3 = 16-bit stereo */
 278 #define   ES_R1_MODEM           (0x03<<4)       /* mask for above */
 279 #define   ES_R1_MODEI(i)        (((i)>>4)&0x03)
 280 #define   ES_P2_MODEO(o)        (((o)&0x03)<<2) /* DAC2 mode; -- '' -- */
 281 #define   ES_P2_MODEM           (0x03<<2)       /* mask for above */
 282 #define   ES_P2_MODEI(i)        (((i)>>2)&0x03)
 283 #define   ES_P1_MODEO(o)        (((o)&0x03)<<0) /* DAC1 mode; -- '' -- */
 284 #define   ES_P1_MODEM           (0x03<<0)       /* mask for above */
 285 #define   ES_P1_MODEI(i)        (((i)>>0)&0x03)
 286
 287 #define ES_REG_DAC1_COUNT 0x24  /* R/W: DAC1 sample count register */
 288 #define ES_REG_DAC2_COUNT 0x28  /* R/W: DAC2 sample count register */
 289 #define ES_REG_ADC_COUNT  0x2c  /* R/W: ADC sample count register */
 290 #define   ES_REG_CURR_COUNT(i)  (((i)>>16)&0xffff)
 291 #define   ES_REG_COUNTO(o)      (((o)&0xffff)<<0)
 292 #define   ES_REG_COUNTM         (0xffff<<0)
 293 #define   ES_REG_COUNTI(i)      (((i)>>0)&0xffff)
 294
 295 #define ES_REG_DAC1_FRAME 0x30  /* R/W: PAGE 0x0c; DAC1 frame address */
 296 #define ES_REG_DAC1_SIZE  0x34  /* R/W: PAGE 0x0c; DAC1 frame size */
 297 #define ES_REG_DAC2_FRAME 0x38  /* R/W: PAGE 0x0c; DAC2 frame address */
 298 #define ES_REG_DAC2_SIZE  0x3c  /* R/W: PAGE 0x0c; DAC2 frame size */
 299 #define ES_REG_ADC_FRAME  0x30  /* R/W: PAGE 0x0d; ADC frame address */
 300 #define ES_REG_ADC_SIZE   0x34  /* R/W: PAGE 0x0d; ADC frame size */
 301 #define   ES_REG_FCURR_COUNTO(o) (((o)&0xffff)<<16)
 302 #define   ES_REG_FCURR_COUNTM    (0xffff<<16)
 303 #define   ES_REG_FCURR_COUNTI(i) (((i)>>14)&0x3fffc)
 304 #define   ES_REG_FSIZEO(o)       (((o)&0xffff)<<0)
 305 #define   ES_REG_FSIZEM          (0xffff<<0)
 306 #define   ES_REG_FSIZEI(i)       (((i)>>0)&0xffff)
 307 #define ES_REG_PHANTOM_FRAME 0x38 /* R/W: PAGE 0x0d: phantom frame address */
 308 #define ES_REG_PHANTOM_COUNT 0x3c /* R/W: PAGE 0x0d: phantom frame count */
 309
 310 #define ES_REG_UART_FIFO  0x30  /* R/W: PAGE 0x0e; UART FIFO register */
 311 #define   ES_REG_UF_VALID        (1<<8)
 312 #define   ES_REG_UF_BYTEO(o)     (((o)&0xff)<<0)
 313 #define   ES_REG_UF_BYTEM        (0xff<<0)
 314 #define   ES_REG_UF_BYTEI(i)     (((i)>>0)&0xff)
 315
 316
 317 /*
 318  *  Pages
 319  */
 320
 321 #define ES_PAGE_DAC     0x0c
 322 #define ES_PAGE_ADC     0x0d
 323 #define ES_PAGE_UART    0x0e
 324 #define ES_PAGE_UART1   0x0f
 325
 326 /*
 327  *  Sample rate converter addresses
 328  */
 329
 330 #define ES_SMPREG_DAC1          0x70
 331 #define ES_SMPREG_DAC2          0x74
 332 #define ES_SMPREG_ADC           0x78
 333 #define ES_SMPREG_VOL_ADC       0x6c
 334 #define ES_SMPREG_VOL_DAC1      0x7c
 335 #define ES_SMPREG_VOL_DAC2      0x7e
 336 #define ES_SMPREG_TRUNC_N       0x00
 337 #define ES_SMPREG_INT_REGS      0x01
 338 #define ES_SMPREG_ACCUM_FRAC    0x02
 339 #define ES_SMPREG_VFREQ_FRAC    0x03
 340
 341 /*
 342  *  Some contants
 343  */
 344
 345 #define ES_1370_SRCLOCK    1411200
 346 #define ES_1370_SRTODIV(x) (ES_1370_SRCLOCK/(x)-2)
 347
 348 /*
 349  *  Open modes
 350  */
 351
 352 #define ES_MODE_PLAY1   0x0001
 353 #define ES_MODE_PLAY2   0x0002
 354 #define ES_MODE_CAPTURE 0x0004
 355
 356 #define ES_MODE_OUTPUT  0x0001  /* for MIDI */
 357 #define ES_MODE_INPUT   0x0002  /* for MIDI */
 358
 359 /*
 360
 361  */
 362
 363 typedef struct _snd_ensoniq ensoniq_t;
 364
 365 struct _snd_ensoniq {
 366         spinlock_t reg_lock;
 367         struct semaphore src_mutex;
 368
 369         int irq;
 370
 371         unsigned long playback1size;
 372         unsigned long playback2size;
 373         unsigned long capture3size;
 374
 375         unsigned long port;
 376         unsigned int mode;
 377         unsigned int uartm;     /* UART mode */
 378
 379         unsigned int ctrl;      /* control register */
 380         unsigned int sctrl;     /* serial control register */
 381         unsigned int cssr;      /* control status register */
 382         unsigned int uartc;     /* uart control register */
 383         unsigned int rev;       /* chip revision */
 384
 385         union {
 386 #ifdef CHIP1371
 387                 struct {
 388                         ac97_t *ac97;
 389                 } es1371;
 390 #else
 391                 struct {
 392                         int pclkdiv_lock;
 393                         ak4531_t *ak4531;
 394                 } es1370;
 395 #endif
 396         } u;
 397
 398         struct pci_dev *pci;
 399         unsigned short subsystem_vendor_id;
 400         unsigned short subsystem_device_id;
 401         snd_card_t *card;
 402         snd_pcm_t *pcm1;        /* DAC1/ADC PCM */
 403         snd_pcm_t *pcm2;        /* DAC2 PCM */
 404         snd_pcm_substream_t *playback1_substream;
 405         snd_pcm_substream_t *playback2_substream;
 406         snd_pcm_substream_t *capture_substream;
 407         unsigned int p1_dma_size;
 408         unsigned int p2_dma_size;
 409         unsigned int c_dma_size;
 410         unsigned int p1_period_size;
 411         unsigned int p2_period_size;
 412         unsigned int c_period_size;
 413         snd_rawmidi_t *rmidi;
 414         snd_rawmidi_substream_t *midi_input;
 415         snd_rawmidi_substream_t *midi_output;
 416
 417         unsigned int spdif;
 418         unsigned int spdif_default;
 419         unsigned int spdif_stream;
 420
 421 #ifdef CHIP1370
 422         struct snd_dma_buffer dma_bug;
 423 #endif
 424
 425 #ifdef SUPPORT_JOYSTICK
 426         struct gameport *gameport;
 427 #endif
 428 };
 429
 430 static irqreturn_t snd_audiopci_interrupt(int irq, void *dev_id, struct pt_regs *regs);
 431
 432 static struct pci_device_id snd_audiopci_ids[] = {
 433 #ifdef CHIP1370
 434         { 0x1274, 0x5000, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, },   /* ES1370 */
 435 #endif
 436 #ifdef CHIP1371
 437         { 0x1274, 0x1371, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, },   /* ES1371 */
 438         { 0x1274, 0x5880, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, },   /* ES1373 - CT5880 */
 439         { 0x1102, 0x8938, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, },   /* Ectiva EV1938 */
 440 #endif
 441         { 0, }
 442 };
 443
 444 MODULE_DEVICE_TABLE(pci, snd_audiopci_ids);
 445
 446 /*
 447  *  constants
 448  */
 449
 450 #define POLL_COUNT      0xa000
 451
 452 #ifdef CHIP1370
 453 static unsigned int snd_es1370_fixed_rates[] =
 454         {5512, 11025, 22050, 44100};
 455 static snd_pcm_hw_constraint_list_t snd_es1370_hw_constraints_rates = {
 456         .count = 4,
 457         .list = snd_es1370_fixed_rates,
 458         .mask = 0,
 459 };
 460 static ratnum_t es1370_clock = {
 461         .num = ES_1370_SRCLOCK,
 462         .den_min = 29,
 463         .den_max = 353,
 464         .den_step = 1,
 465 };
 466 static snd_pcm_hw_constraint_ratnums_t snd_es1370_hw_constraints_clock = {
 467         .nrats = 1,
 468         .rats = &es1370_clock,
 469 };
 470 #else
 471 static ratden_t es1371_dac_clock = {
 472         .num_min = 3000 * (1 << 15),
 473         .num_max = 48000 * (1 << 15),
 474         .num_step = 3000,
 475         .den = 1 << 15,
 476 };
 477 static snd_pcm_hw_constraint_ratdens_t snd_es1371_hw_constraints_dac_clock = {
 478         .nrats = 1,
 479         .rats = &es1371_dac_clock,
 480 };
 481 static ratnum_t es1371_adc_clock = {
 482         .num = 48000 << 15,
 483         .den_min = 32768,
 484         .den_max = 393216,
 485         .den_step = 1,
 486 };
 487 static snd_pcm_hw_constraint_ratnums_t snd_es1371_hw_constraints_adc_clock = {
 488         .nrats = 1,
 489         .rats = &es1371_adc_clock,
 490 };
 491 #endif
 492 static const unsigned int snd_ensoniq_sample_shift[] =
 493         {0, 1, 1, 2};
 494
 495 /*
 496  *  common I/O routines
 497  */
 498
 499 #ifdef CHIP1371
 500
 501 static unsigned int snd_es1371_wait_src_ready(ensoniq_t * ensoniq)
 502 {
 503         unsigned int t, r = 0;
 504
 505         for (t = 0; t < POLL_COUNT; t++) {
 506                 r = inl(ES_REG(ensoniq, 1371_SMPRATE));
 507                 if ((r & ES_1371_SRC_RAM_BUSY) == 0)
 508                         return r;
 509                 cond_resched();
 510         }
 511         snd_printk(KERN_ERR "wait source ready timeout 0x%lx [0x%x]\n", ES_REG(ensoniq, 1371_SMPRATE), r);
 512         return 0;
 513 }
 514
 515 static unsigned int snd_es1371_src_read(ensoniq_t * ensoniq, unsigned short reg)
 516 {
 517         unsigned int temp, i, orig, r;
 518
 519         /* wait for ready */
 520         temp = orig = snd_es1371_wait_src_ready(ensoniq);
 521
 522         /* expose the SRC state bits */
 523         r = temp & (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 |
 524                     ES_1371_DIS_P2 | ES_1371_DIS_R1);
 525         r |= ES_1371_SRC_RAM_ADDRO(reg) | 0x10000;
 526         outl(r, ES_REG(ensoniq, 1371_SMPRATE));
 527
 528         /* now, wait for busy and the correct time to read */
 529         temp = snd_es1371_wait_src_ready(ensoniq);
 530
 531         if ((temp & 0x00870000) != 0x00010000) {
 532                 /* wait for the right state */
 533                 for (i = 0; i < POLL_COUNT; i++) {
 534                         temp = inl(ES_REG(ensoniq, 1371_SMPRATE));
 535                         if ((temp & 0x00870000) == 0x00010000)
 536                                 break;
 537                 }
 538         }
 539
 540         /* hide the state bits */
 541         r = orig & (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 |
 542                    ES_1371_DIS_P2 | ES_1371_DIS_R1);
 543         r |= ES_1371_SRC_RAM_ADDRO(reg);
 544         outl(r, ES_REG(ensoniq, 1371_SMPRATE));
 545
 546         return temp;
 547 }
 548
 549 static void snd_es1371_src_write(ensoniq_t * ensoniq,
 550                                  unsigned short reg, unsigned short data)
 551 {
 552         unsigned int r;
 553
 554         r = snd_es1371_wait_src_ready(ensoniq) &
 555             (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 |
 556              ES_1371_DIS_P2 | ES_1371_DIS_R1);
 557         r |= ES_1371_SRC_RAM_ADDRO(reg) | ES_1371_SRC_RAM_DATAO(data);
 558         outl(r | ES_1371_SRC_RAM_WE, ES_REG(ensoniq, 1371_SMPRATE));
 559 }
 560
 561 #endif /* CHIP1371 */
 562
 563 #ifdef CHIP1370
 564
 565 static void snd_es1370_codec_write(ak4531_t *ak4531,
 566                                    unsigned short reg, unsigned short val)
 567 {
 568         ensoniq_t *ensoniq = ak4531->private_data;
 569         unsigned long end_time = jiffies + HZ / 10;
 570
 571 #if 0
 572         printk("CODEC WRITE: reg = 0x%x, val = 0x%x (0x%x), creg = 0x%x\n", reg, val, ES_1370_CODEC_WRITE(reg, val), ES_REG(ensoniq, 1370_CODEC));
 573 #endif
 574         do {
 575                 if (!(inl(ES_REG(ensoniq, STATUS)) & ES_1370_CSTAT)) {
 576                         outw(ES_1370_CODEC_WRITE(reg, val), ES_REG(ensoniq, 1370_CODEC));
 577                         return;
 578                 }
 579                 schedule_timeout_uninterruptible(1);
 580         } while (time_after(end_time, jiffies));
 581         snd_printk(KERN_ERR "codec write timeout, status = 0x%x\n", inl(ES_REG(ensoniq, STATUS)));
 582 }
 583
 584 #endif /* CHIP1370 */
 585
 586 #ifdef CHIP1371
 587
 588 static void snd_es1371_codec_write(ac97_t *ac97,
 589                                    unsigned short reg, unsigned short val)
 590 {
 591         ensoniq_t *ensoniq = ac97->private_data;
 592         unsigned int t, x;
 593
 594         down(&ensoniq->src_mutex);
 595         for (t = 0; t < POLL_COUNT; t++) {
 596                 if (!(inl(ES_REG(ensoniq, 1371_CODEC)) & ES_1371_CODEC_WIP)) {
 597                         /* save the current state for latter */
 598                         x = snd_es1371_wait_src_ready(ensoniq);
 599                         outl((x & (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 |
 600                                    ES_1371_DIS_P2 | ES_1371_DIS_R1)) | 0x00010000,
 601                              ES_REG(ensoniq, 1371_SMPRATE));
 602                         /* wait for not busy (state 0) first to avoid
 603                            transition states */
 604                         for (t = 0; t < POLL_COUNT; t++) {
 605                                 if ((inl(ES_REG(ensoniq, 1371_SMPRATE)) & 0x00870000) == 0x00000000)
 606                                         break;
 607                         }
 608                         /* wait for a SAFE time to write addr/data and then do it, dammit */
 609                         for (t = 0; t < POLL_COUNT; t++) {
 610                                 if ((inl(ES_REG(ensoniq, 1371_SMPRATE)) & 0x00870000) == 0x00010000)
 611                                         break;
 612                         }
 613                         outl(ES_1371_CODEC_WRITE(reg, val), ES_REG(ensoniq, 1371_CODEC));
 614                         /* restore SRC reg */
 615                         snd_es1371_wait_src_ready(ensoniq);
 616                         outl(x, ES_REG(ensoniq, 1371_SMPRATE));
 617                         up(&ensoniq->src_mutex);
 618                         return;
 619                 }
 620         }
 621         up(&ensoniq->src_mutex);
 622         snd_printk(KERN_ERR "codec write timeout at 0x%lx [0x%x]\n", ES_REG(ensoniq, 1371_CODEC), inl(ES_REG(ensoniq, 1371_CODEC)));
 623 }
 624
 625 static unsigned short snd_es1371_codec_read(ac97_t *ac97,
 626                                             unsigned short reg)
 627 {
 628         ensoniq_t *ensoniq = ac97->private_data;
 629         unsigned int t, x, fail = 0;
 630
 631       __again:
 632         down(&ensoniq->src_mutex);
 633         for (t = 0; t < POLL_COUNT; t++) {
 634                 if (!(inl(ES_REG(ensoniq, 1371_CODEC)) & ES_1371_CODEC_WIP)) {
 635                         /* save the current state for latter */
 636                         x = snd_es1371_wait_src_ready(ensoniq);
 637                         outl((x & (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 |
 638                                    ES_1371_DIS_P2 | ES_1371_DIS_R1)) | 0x00010000,
 639                              ES_REG(ensoniq, 1371_SMPRATE));
 640                         /* wait for not busy (state 0) first to avoid
 641                            transition states */
 642                         for (t = 0; t < POLL_COUNT; t++) {
 643                                 if ((inl(ES_REG(ensoniq, 1371_SMPRATE)) & 0x00870000) == 0x00000000)
 644                                         break;
 645                         }
 646                         /* wait for a SAFE time to write addr/data and then do it, dammit */
 647                         for (t = 0; t < POLL_COUNT; t++) {
 648                                 if ((inl(ES_REG(ensoniq, 1371_SMPRATE)) & 0x00870000) == 0x00010000)
 649                                         break;
 650                         }
 651                         outl(ES_1371_CODEC_READS(reg), ES_REG(ensoniq, 1371_CODEC));
 652                         /* restore SRC reg */
 653                         snd_es1371_wait_src_ready(ensoniq);
 654                         outl(x, ES_REG(ensoniq, 1371_SMPRATE));
 655                         /* wait for WIP again */
 656                         for (t = 0; t < POLL_COUNT; t++) {
 657                                 if (!(inl(ES_REG(ensoniq, 1371_CODEC)) & ES_1371_CODEC_WIP))
 658                                         break;
 659                         }
 660                         /* now wait for the stinkin' data (RDY) */
 661                         for (t = 0; t < POLL_COUNT; t++) {
 662                                 if ((x = inl(ES_REG(ensoniq, 1371_CODEC))) & ES_1371_CODEC_RDY) {
 663                                         up(&ensoniq->src_mutex);
 664                                         return ES_1371_CODEC_READ(x);
 665                                 }
 666                         }
 667                         up(&ensoniq->src_mutex);
 668                         if (++fail > 10) {
 669                                 snd_printk(KERN_ERR "codec read timeout (final) at 0x%lx, reg = 0x%x [0x%x]\n", ES_REG(ensoniq, 1371_CODEC), reg, inl(ES_REG(ensoniq, 1371_CODEC)));
 670                                 return 0;
 671                         }
 672                         goto __again;
 673                 }
 674         }
 675         up(&ensoniq->src_mutex);
 676         snd_printk(KERN_ERR "es1371: codec read timeout at 0x%lx [0x%x]\n", ES_REG(ensoniq, 1371_CODEC), inl(ES_REG(ensoniq, 1371_CODEC)));
 677         return 0;
 678 }
 679
 680 static void snd_es1371_codec_wait(ac97_t *ac97)
 681 {
 682         msleep(750);
 683         snd_es1371_codec_read(ac97, AC97_RESET);
 684         snd_es1371_codec_read(ac97, AC97_VENDOR_ID1);
 685         snd_es1371_codec_read(ac97, AC97_VENDOR_ID2);
 686         msleep(50);
 687 }
 688
 689 static void snd_es1371_adc_rate(ensoniq_t * ensoniq, unsigned int rate)
 690 {
 691         unsigned int n, truncm, freq, result;
 692
 693         down(&ensoniq->src_mutex);
 694         n = rate / 3000;
 695         if ((1 << n) & ((1 << 15) | (1 << 13) | (1 << 11) | (1 << 9)))
 696                 n--;
 697         truncm = (21 * n - 1) | 1;
 698         freq = ((48000UL << 15) / rate) * n;
 699         result = (48000UL << 15) / (freq / n);
 700         if (rate >= 24000) {
 701                 if (truncm > 239)
 702                         truncm = 239;
 703                 snd_es1371_src_write(ensoniq, ES_SMPREG_ADC + ES_SMPREG_TRUNC_N,
 704                                 (((239 - truncm) >> 1) << 9) | (n << 4));
 705         } else {
 706                 if (truncm > 119)
 707                         truncm = 119;
 708                 snd_es1371_src_write(ensoniq, ES_SMPREG_ADC + ES_SMPREG_TRUNC_N,
 709                                 0x8000 | (((119 - truncm) >> 1) << 9) | (n << 4));
 710         }
 711         snd_es1371_src_write(ensoniq, ES_SMPREG_ADC + ES_SMPREG_INT_REGS,
 712                              (snd_es1371_src_read(ensoniq, ES_SMPREG_ADC + ES_SMPREG_INT_REGS) & 0x00ff) |
 713                                      ((freq >> 5) & 0xfc00));
 714         snd_es1371_src_write(ensoniq, ES_SMPREG_ADC + ES_SMPREG_VFREQ_FRAC, freq & 0x7fff);
 715         snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_ADC, n << 8);
 716         snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_ADC + 1, n << 8);
 717         up(&ensoniq->src_mutex);
 718 }
 719
 720 static void snd_es1371_dac1_rate(ensoniq_t * ensoniq, unsigned int rate)
 721 {
 722         unsigned int freq, r;
 723
 724         down(&ensoniq->src_mutex);
 725         freq = ((rate << 15) + 1500) / 3000;
 726         r = (snd_es1371_wait_src_ready(ensoniq) & (ES_1371_SRC_DISABLE | ES_1371_DIS_P2 | ES_1371_DIS_R1)) | ES_1371_DIS_P1;
 727         outl(r, ES_REG(ensoniq, 1371_SMPRATE));
 728         snd_es1371_src_write(ensoniq, ES_SMPREG_DAC1 + ES_SMPREG_INT_REGS,
 729                              (snd_es1371_src_read(ensoniq, ES_SMPREG_DAC1 + ES_SMPREG_INT_REGS) & 0x00ff) |
 730                              ((freq >> 5) & 0xfc00));
 731         snd_es1371_src_write(ensoniq, ES_SMPREG_DAC1 + ES_SMPREG_VFREQ_FRAC, freq & 0x7fff);
 732         r = (snd_es1371_wait_src_ready(ensoniq) & (ES_1371_SRC_DISABLE | ES_1371_DIS_P2 | ES_1371_DIS_R1));
 733         outl(r, ES_REG(ensoniq, 1371_SMPRATE));
 734         up(&ensoniq->src_mutex);
 735 }
 736
 737 static void snd_es1371_dac2_rate(ensoniq_t * ensoniq, unsigned int rate)
 738 {
 739         unsigned int freq, r;
 740
 741         down(&ensoniq->src_mutex);
 742         freq = ((rate << 15) + 1500) / 3000;
 743         r = (snd_es1371_wait_src_ready(ensoniq) & (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 | ES_1371_DIS_R1)) | ES_1371_DIS_P2;
 744         outl(r, ES_REG(ensoniq, 1371_SMPRATE));
 745         snd_es1371_src_write(ensoniq, ES_SMPREG_DAC2 + ES_SMPREG_INT_REGS,
 746                              (snd_es1371_src_read(ensoniq, ES_SMPREG_DAC2 + ES_SMPREG_INT_REGS) & 0x00ff) |
 747                              ((freq >> 5) & 0xfc00));
 748         snd_es1371_src_write(ensoniq, ES_SMPREG_DAC2 + ES_SMPREG_VFREQ_FRAC, freq & 0x7fff);
 749         r = (snd_es1371_wait_src_ready(ensoniq) & (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 | ES_1371_DIS_R1));
 750         outl(r, ES_REG(ensoniq, 1371_SMPRATE));
 751         up(&ensoniq->src_mutex);
 752 }
 753
 754 #endif /* CHIP1371 */
 755
 756 static int snd_ensoniq_trigger(snd_pcm_substream_t *substream, int cmd)
 757 {
 758         ensoniq_t *ensoniq = snd_pcm_substream_chip(substream);
 759         switch (cmd) {
 760         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 761         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 762         {
 763                 unsigned int what = 0;
 764                 struct list_head *pos;
 765                 snd_pcm_substream_t *s;
 766                 snd_pcm_group_for_each(pos, substream) {
 767                         s = snd_pcm_group_substream_entry(pos);
 768                         if (s == ensoniq->playback1_substream) {
 769                                 what |= ES_P1_PAUSE;
 770                                 snd_pcm_trigger_done(s, substream);
 771                         } else if (s == ensoniq->playback2_substream) {
 772                                 what |= ES_P2_PAUSE;
 773                                 snd_pcm_trigger_done(s, substream);
 774                         } else if (s == ensoniq->capture_substream)
 775                                 return -EINVAL;
 776                 }
 777                 spin_lock(&ensoniq->reg_lock);
 778                 if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH)
 779                         ensoniq->sctrl |= what;
 780                 else
 781                         ensoniq->sctrl &= ~what;
 782                 outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
 783                 spin_unlock(&ensoniq->reg_lock);
 784                 break;
 785         }
 786         case SNDRV_PCM_TRIGGER_START:
 787         case SNDRV_PCM_TRIGGER_STOP:
 788         {
 789                 unsigned int what = 0;
 790                 struct list_head *pos;
 791                 snd_pcm_substream_t *s;
 792                 snd_pcm_group_for_each(pos, substream) {
 793                         s = snd_pcm_group_substream_entry(pos);
 794                         if (s == ensoniq->playback1_substream) {
 795                                 what |= ES_DAC1_EN;
 796                                 snd_pcm_trigger_done(s, substream);
 797                         } else if (s == ensoniq->playback2_substream) {
 798                                 what |= ES_DAC2_EN;
 799                                 snd_pcm_trigger_done(s, substream);
 800                         } else if (s == ensoniq->capture_substream) {
 801                                 what |= ES_ADC_EN;
 802                                 snd_pcm_trigger_done(s, substream);
 803                         }
 804                 }
 805                 spin_lock(&ensoniq->reg_lock);
 806                 if (cmd == SNDRV_PCM_TRIGGER_START)
 807                         ensoniq->ctrl |= what;
 808                 else
 809                         ensoniq->ctrl &= ~what;
 810                 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
 811                 spin_unlock(&ensoniq->reg_lock);
 812                 break;
 813         }
 814         default:
 815                 return -EINVAL;
 816         }
 817         return 0;
 818 }
 819
 820 /*
 821  *  PCM part
 822  */
 823
 824 static int snd_ensoniq_hw_params(snd_pcm_substream_t * substream,
 825                                  snd_pcm_hw_params_t * hw_params)
 826 {
 827         return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
 828 }
 829
 830 static int snd_ensoniq_hw_free(snd_pcm_substream_t * substream)
 831 {
 832         return snd_pcm_lib_free_pages(substream);
 833 }
 834
 835 static int snd_ensoniq_playback1_prepare(snd_pcm_substream_t * substream)
 836 {
 837         ensoniq_t *ensoniq = snd_pcm_substream_chip(substream);
 838         snd_pcm_runtime_t *runtime = substream->runtime;
 839         unsigned int mode = 0;
 840
 841         ensoniq->p1_dma_size = snd_pcm_lib_buffer_bytes(substream);
 842         ensoniq->p1_period_size = snd_pcm_lib_period_bytes(substream);
 843         if (snd_pcm_format_width(runtime->format) == 16)
 844                 mode |= 0x02;
 845         if (runtime->channels > 1)
 846                 mode |= 0x01;
 847         spin_lock_irq(&ensoniq->reg_lock);
 848         ensoniq->ctrl &= ~ES_DAC1_EN;
 849 #ifdef CHIP1371
 850         /* 48k doesn't need SRC (it breaks AC3-passthru) */
 851         if (runtime->rate == 48000)
 852                 ensoniq->ctrl |= ES_1373_BYPASS_P1;
 853         else
 854                 ensoniq->ctrl &= ~ES_1373_BYPASS_P1;
 855 #endif
 856         outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
 857         outl(ES_MEM_PAGEO(ES_PAGE_DAC), ES_REG(ensoniq, MEM_PAGE));
 858         outl(runtime->dma_addr, ES_REG(ensoniq, DAC1_FRAME));
 859         outl((ensoniq->p1_dma_size >> 2) - 1, ES_REG(ensoniq, DAC1_SIZE));
 860         ensoniq->sctrl &= ~(ES_P1_LOOP_SEL | ES_P1_PAUSE | ES_P1_SCT_RLD | ES_P1_MODEM);
 861         ensoniq->sctrl |= ES_P1_INT_EN | ES_P1_MODEO(mode);
 862         outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
 863         outl((ensoniq->p1_period_size >> snd_ensoniq_sample_shift[mode]) - 1, ES_REG(ensoniq, DAC1_COUNT));
 864 #ifdef CHIP1370
 865         ensoniq->ctrl &= ~ES_1370_WTSRSELM;
 866         switch (runtime->rate) {
 867         case 5512: ensoniq->ctrl |= ES_1370_WTSRSEL(0); break;
 868         case 11025: ensoniq->ctrl |= ES_1370_WTSRSEL(1); break;
 869         case 22050: ensoniq->ctrl |= ES_1370_WTSRSEL(2); break;
 870         case 44100: ensoniq->ctrl |= ES_1370_WTSRSEL(3); break;
 871         default: snd_BUG();
 872         }
 873 #endif
 874         outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
 875         spin_unlock_irq(&ensoniq->reg_lock);
 876 #ifndef CHIP1370
 877         snd_es1371_dac1_rate(ensoniq, runtime->rate);
 878 #endif
 879         return 0;
 880 }
 881
 882 static int snd_ensoniq_playback2_prepare(snd_pcm_substream_t * substream)
 883 {
 884         ensoniq_t *ensoniq = snd_pcm_substream_chip(substream);
 885         snd_pcm_runtime_t *runtime = substream->runtime;
 886         unsigned int mode = 0;
 887
 888         ensoniq->p2_dma_size = snd_pcm_lib_buffer_bytes(substream);
 889         ensoniq->p2_period_size = snd_pcm_lib_period_bytes(substream);
 890         if (snd_pcm_format_width(runtime->format) == 16)
 891                 mode |= 0x02;
 892         if (runtime->channels > 1)
 893                 mode |= 0x01;
 894         spin_lock_irq(&ensoniq->reg_lock);
 895         ensoniq->ctrl &= ~ES_DAC2_EN;
 896         outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
 897         outl(ES_MEM_PAGEO(ES_PAGE_DAC), ES_REG(ensoniq, MEM_PAGE));
 898         outl(runtime->dma_addr, ES_REG(ensoniq, DAC2_FRAME));
 899         outl((ensoniq->p2_dma_size >> 2) - 1, ES_REG(ensoniq, DAC2_SIZE));
 900         ensoniq->sctrl &= ~(ES_P2_LOOP_SEL | ES_P2_PAUSE | ES_P2_DAC_SEN |
 901                             ES_P2_END_INCM | ES_P2_ST_INCM | ES_P2_MODEM);
 902         ensoniq->sctrl |= ES_P2_INT_EN | ES_P2_MODEO(mode) |
 903                           ES_P2_END_INCO(mode & 2 ? 2 : 1) | ES_P2_ST_INCO(0);
 904         outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
 905         outl((ensoniq->p2_period_size >> snd_ensoniq_sample_shift[mode]) - 1, ES_REG(ensoniq, DAC2_COUNT));
 906 #ifdef CHIP1370
 907         if (!(ensoniq->u.es1370.pclkdiv_lock & ES_MODE_CAPTURE)) {
 908                 ensoniq->ctrl &= ~ES_1370_PCLKDIVM;
 909                 ensoniq->ctrl |= ES_1370_PCLKDIVO(ES_1370_SRTODIV(runtime->rate));
 910                 ensoniq->u.es1370.pclkdiv_lock |= ES_MODE_PLAY2;
 911         }
 912 #endif
 913         outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
 914         spin_unlock_irq(&ensoniq->reg_lock);
 915 #ifndef CHIP1370
 916         snd_es1371_dac2_rate(ensoniq, runtime->rate);
 917 #endif
 918         return 0;
 919 }
 920
 921 static int snd_ensoniq_capture_prepare(snd_pcm_substream_t * substream)
 922 {
 923         ensoniq_t *ensoniq = snd_pcm_substream_chip(substream);
 924         snd_pcm_runtime_t *runtime = substream->runtime;
 925         unsigned int mode = 0;
 926
 927         ensoniq->c_dma_size = snd_pcm_lib_buffer_bytes(substream);
 928         ensoniq->c_period_size = snd_pcm_lib_period_bytes(substream);
 929         if (snd_pcm_format_width(runtime->format) == 16)
 930                 mode |= 0x02;
 931         if (runtime->channels > 1)
 932                 mode |= 0x01;
 933         spin_lock_irq(&ensoniq->reg_lock);
 934         ensoniq->ctrl &= ~ES_ADC_EN;
 935         outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
 936         outl(ES_MEM_PAGEO(ES_PAGE_ADC), ES_REG(ensoniq, MEM_PAGE));
 937         outl(runtime->dma_addr, ES_REG(ensoniq, ADC_FRAME));
 938         outl((ensoniq->c_dma_size >> 2) - 1, ES_REG(ensoniq, ADC_SIZE));
 939         ensoniq->sctrl &= ~(ES_R1_LOOP_SEL | ES_R1_MODEM);
 940         ensoniq->sctrl |= ES_R1_INT_EN | ES_R1_MODEO(mode);
 941         outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
 942         outl((ensoniq->c_period_size >> snd_ensoniq_sample_shift[mode]) - 1, ES_REG(ensoniq, ADC_COUNT));
 943 #ifdef CHIP1370
 944         if (!(ensoniq->u.es1370.pclkdiv_lock & ES_MODE_PLAY2)) {
 945                 ensoniq->ctrl &= ~ES_1370_PCLKDIVM;
 946                 ensoniq->ctrl |= ES_1370_PCLKDIVO(ES_1370_SRTODIV(runtime->rate));
 947                 ensoniq->u.es1370.pclkdiv_lock |= ES_MODE_CAPTURE;
 948         }
 949 #endif
 950         outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
 951         spin_unlock_irq(&ensoniq->reg_lock);
 952 #ifndef CHIP1370
 953         snd_es1371_adc_rate(ensoniq, runtime->rate);
 954 #endif
 955         return 0;
 956 }
 957
 958 static snd_pcm_uframes_t snd_ensoniq_playback1_pointer(snd_pcm_substream_t * substream)
 959 {
 960         ensoniq_t *ensoniq = snd_pcm_substream_chip(substream);
 961         size_t ptr;
 962
 963         spin_lock(&ensoniq->reg_lock);
 964         if (inl(ES_REG(ensoniq, CONTROL)) & ES_DAC1_EN) {
 965                 outl(ES_MEM_PAGEO(ES_PAGE_DAC), ES_REG(ensoniq, MEM_PAGE));
 966                 ptr = ES_REG_FCURR_COUNTI(inl(ES_REG(ensoniq, DAC1_SIZE)));
 967                 ptr = bytes_to_frames(substream->runtime, ptr);
 968         } else {
 969                 ptr = 0;
 970         }
 971         spin_unlock(&ensoniq->reg_lock);
 972         return ptr;
 973 }
 974
 975 static snd_pcm_uframes_t snd_ensoniq_playback2_pointer(snd_pcm_substream_t * substream)
 976 {
 977         ensoniq_t *ensoniq = snd_pcm_substream_chip(substream);
 978         size_t ptr;
 979
 980         spin_lock(&ensoniq->reg_lock);
 981         if (inl(ES_REG(ensoniq, CONTROL)) & ES_DAC2_EN) {
 982                 outl(ES_MEM_PAGEO(ES_PAGE_DAC), ES_REG(ensoniq, MEM_PAGE));
 983                 ptr = ES_REG_FCURR_COUNTI(inl(ES_REG(ensoniq, DAC2_SIZE)));
 984                 ptr = bytes_to_frames(substream->runtime, ptr);
 985         } else {
 986                 ptr = 0;
 987         }
 988         spin_unlock(&ensoniq->reg_lock);
 989         return ptr;
 990 }
 991
 992 static snd_pcm_uframes_t snd_ensoniq_capture_pointer(snd_pcm_substream_t * substream)
 993 {
 994         ensoniq_t *ensoniq = snd_pcm_substream_chip(substream);
 995         size_t ptr;
 996
 997         spin_lock(&ensoniq->reg_lock);
 998         if (inl(ES_REG(ensoniq, CONTROL)) & ES_ADC_EN) {
 999                 outl(ES_MEM_PAGEO(ES_PAGE_ADC), ES_REG(ensoniq, MEM_PAGE));
1000                 ptr = ES_REG_FCURR_COUNTI(inl(ES_REG(ensoniq, ADC_SIZE)));
1001                 ptr = bytes_to_frames(substream->runtime, ptr);
1002         } else {
1003                 ptr = 0;
1004         }
1005         spin_unlock(&ensoniq->reg_lock);
1006         return ptr;
1007 }
1008
1009 static snd_pcm_hardware_t snd_ensoniq_playback1 =
1010 {
1011         .info =                 (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1012                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
1013                                  SNDRV_PCM_INFO_MMAP_VALID |
1014                                  SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_SYNC_START),
1015         .formats =              SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1016         .rates =
1017 #ifndef CHIP1370
1018                                 SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1019 #else
1020                                 (SNDRV_PCM_RATE_KNOT |  /* 5512Hz rate */
1021                                  SNDRV_PCM_RATE_11025 | SNDRV_PCM_RATE_22050 |
1022                                  SNDRV_PCM_RATE_44100),
1023 #endif
1024         .rate_min =             4000,
1025         .rate_max =             48000,
1026         .channels_min =         1,
1027         .channels_max =         2,
1028         .buffer_bytes_max =     (128*1024),
1029         .period_bytes_min =     64,
1030         .period_bytes_max =     (128*1024),
1031         .periods_min =          1,
1032         .periods_max =          1024,
1033         .fifo_size =            0,
1034 };
1035
1036 static snd_pcm_hardware_t snd_ensoniq_playback2 =
1037 {
1038         .info =                 (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1039                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
1040                                  SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_PAUSE |
1041                                  SNDRV_PCM_INFO_SYNC_START),
1042         .formats =              SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1043         .rates =                SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1044         .rate_min =             4000,
1045         .rate_max =             48000,
1046         .channels_min =         1,
1047         .channels_max =         2,
1048         .buffer_bytes_max =     (128*1024),
1049         .period_bytes_min =     64,
1050         .period_bytes_max =     (128*1024),
1051         .periods_min =          1,
1052         .periods_max =          1024,
1053         .fifo_size =            0,
1054 };
1055
1056 static snd_pcm_hardware_t snd_ensoniq_capture =
1057 {
1058         .info =                 (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1059                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
1060                                  SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_SYNC_START),
1061         .formats =              SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1062         .rates =                SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1063         .rate_min =             4000,
1064         .rate_max =             48000,
1065         .channels_min =         1,
1066         .channels_max =         2,
1067         .buffer_bytes_max =     (128*1024),
1068         .period_bytes_min =     64,
1069         .period_bytes_max =     (128*1024),
1070         .periods_min =          1,
1071         .periods_max =          1024,
1072         .fifo_size =            0,
1073 };
1074
1075 static int snd_ensoniq_playback1_open(snd_pcm_substream_t * substream)
1076 {
1077         ensoniq_t *ensoniq = snd_pcm_substream_chip(substream);
1078         snd_pcm_runtime_t *runtime = substream->runtime;
1079
1080         ensoniq->mode |= ES_MODE_PLAY1;
1081         ensoniq->playback1_substream = substream;
1082         runtime->hw = snd_ensoniq_playback1;
1083         snd_pcm_set_sync(substream);
1084         spin_lock_irq(&ensoniq->reg_lock);
1085         if (ensoniq->spdif && ensoniq->playback2_substream == NULL)
1086                 ensoniq->spdif_stream = ensoniq->spdif_default;
1087         spin_unlock_irq(&ensoniq->reg_lock);
1088 #ifdef CHIP1370
1089         snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
1090                                    &snd_es1370_hw_constraints_rates);
1091 #else
1092         snd_pcm_hw_constraint_ratdens(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
1093                                       &snd_es1371_hw_constraints_dac_clock);
1094 #endif
1095         return 0;
1096 }
1097
1098 static int snd_ensoniq_playback2_open(snd_pcm_substream_t * substream)
1099 {
1100         ensoniq_t *ensoniq = snd_pcm_substream_chip(substream);
1101         snd_pcm_runtime_t *runtime = substream->runtime;
1102
1103         ensoniq->mode |= ES_MODE_PLAY2;
1104         ensoniq->playback2_substream = substream;
1105         runtime->hw = snd_ensoniq_playback2;
1106         snd_pcm_set_sync(substream);
1107         spin_lock_irq(&ensoniq->reg_lock);
1108         if (ensoniq->spdif && ensoniq->playback1_substream == NULL)
1109                 ensoniq->spdif_stream = ensoniq->spdif_default;
1110         spin_unlock_irq(&ensoniq->reg_lock);
1111 #ifdef CHIP1370
1112         snd_pcm_hw_constraint_ratnums(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
1113                                       &snd_es1370_hw_constraints_clock);
1114 #else
1115         snd_pcm_hw_constraint_ratdens(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
1116                                       &snd_es1371_hw_constraints_dac_clock);
1117 #endif
1118         return 0;
1119 }
1120
1121 static int snd_ensoniq_capture_open(snd_pcm_substream_t * substream)
1122 {
1123         ensoniq_t *ensoniq = snd_pcm_substream_chip(substream);
1124         snd_pcm_runtime_t *runtime = substream->runtime;
1125
1126         ensoniq->mode |= ES_MODE_CAPTURE;
1127         ensoniq->capture_substream = substream;
1128         runtime->hw = snd_ensoniq_capture;
1129         snd_pcm_set_sync(substream);
1130 #ifdef CHIP1370
1131         snd_pcm_hw_constraint_ratnums(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
1132                                       &snd_es1370_hw_constraints_clock);
1133 #else
1134         snd_pcm_hw_constraint_ratnums(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
1135                                       &snd_es1371_hw_constraints_adc_clock);
1136 #endif
1137         return 0;
1138 }
1139
1140 static int snd_ensoniq_playback1_close(snd_pcm_substream_t * substream)
1141 {
1142         ensoniq_t *ensoniq = snd_pcm_substream_chip(substream);
1143
1144         ensoniq->playback1_substream = NULL;
1145         ensoniq->mode &= ~ES_MODE_PLAY1;
1146         return 0;
1147 }
1148
1149 static int snd_ensoniq_playback2_close(snd_pcm_substream_t * substream)
1150 {
1151         ensoniq_t *ensoniq = snd_pcm_substream_chip(substream);
1152
1153         ensoniq->playback2_substream = NULL;
1154         spin_lock_irq(&ensoniq->reg_lock);
1155 #ifdef CHIP1370
1156         ensoniq->u.es1370.pclkdiv_lock &= ~ES_MODE_PLAY2;
1157 #endif
1158         ensoniq->mode &= ~ES_MODE_PLAY2;
1159         spin_unlock_irq(&ensoniq->reg_lock);
1160         return 0;
1161 }
1162
1163 static int snd_ensoniq_capture_close(snd_pcm_substream_t * substream)
1164 {
1165         ensoniq_t *ensoniq = snd_pcm_substream_chip(substream);
1166
1167         ensoniq->capture_substream = NULL;
1168         spin_lock_irq(&ensoniq->reg_lock);
1169 #ifdef CHIP1370
1170         ensoniq->u.es1370.pclkdiv_lock &= ~ES_MODE_CAPTURE;
1171 #endif
1172         ensoniq->mode &= ~ES_MODE_CAPTURE;
1173         spin_unlock_irq(&ensoniq->reg_lock);
1174         return 0;
1175 }
1176
1177 static snd_pcm_ops_t snd_ensoniq_playback1_ops = {
1178         .open =         snd_ensoniq_playback1_open,
1179         .close =        snd_ensoniq_playback1_close,
1180         .ioctl =        snd_pcm_lib_ioctl,
1181         .hw_params =    snd_ensoniq_hw_params,
1182         .hw_free =      snd_ensoniq_hw_free,
1183         .prepare =      snd_ensoniq_playback1_prepare,
1184         .trigger =      snd_ensoniq_trigger,
1185         .pointer =      snd_ensoniq_playback1_pointer,
1186 };
1187
1188 static snd_pcm_ops_t snd_ensoniq_playback2_ops = {
1189         .open =         snd_ensoniq_playback2_open,
1190         .close =        snd_ensoniq_playback2_close,
1191         .ioctl =        snd_pcm_lib_ioctl,
1192         .hw_params =    snd_ensoniq_hw_params,
1193         .hw_free =      snd_ensoniq_hw_free,
1194         .prepare =      snd_ensoniq_playback2_prepare,
1195         .trigger =      snd_ensoniq_trigger,
1196         .pointer =      snd_ensoniq_playback2_pointer,
1197 };
1198
1199 static snd_pcm_ops_t snd_ensoniq_capture_ops = {
1200         .open =         snd_ensoniq_capture_open,
1201         .close =        snd_ensoniq_capture_close,
1202         .ioctl =        snd_pcm_lib_ioctl,
1203         .hw_params =    snd_ensoniq_hw_params,
1204         .hw_free =      snd_ensoniq_hw_free,
1205         .prepare =      snd_ensoniq_capture_prepare,
1206         .trigger =      snd_ensoniq_trigger,
1207         .pointer =      snd_ensoniq_capture_pointer,
1208 };
1209
1210 static void snd_ensoniq_pcm_free(snd_pcm_t *pcm)
1211 {
1212         ensoniq_t *ensoniq = pcm->private_data;
1213         ensoniq->pcm1 = NULL;
1214         snd_pcm_lib_preallocate_free_for_all(pcm);
1215 }
1216
1217 static int __devinit snd_ensoniq_pcm(ensoniq_t * ensoniq, int device, snd_pcm_t ** rpcm)
1218 {
1219         snd_pcm_t *pcm;
1220         int err;
1221
1222         if (rpcm)
1223                 *rpcm = NULL;
1224 #ifdef CHIP1370
1225         err = snd_pcm_new(ensoniq->card, "ES1370/1", device, 1, 1, &pcm);
1226 #else
1227         err = snd_pcm_new(ensoniq->card, "ES1371/1", device, 1, 1, &pcm);
1228 #endif
1229         if (err < 0)
1230                 return err;
1231
1232 #ifdef CHIP1370
1233         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ensoniq_playback2_ops);
1234 #else
1235         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ensoniq_playback1_ops);
1236 #endif
1237         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_ensoniq_capture_ops);
1238
1239         pcm->private_data = ensoniq;
1240         pcm->private_free = snd_ensoniq_pcm_free;
1241         pcm->info_flags = 0;
1242 #ifdef CHIP1370
1243         strcpy(pcm->name, "ES1370 DAC2/ADC");
1244 #else
1245         strcpy(pcm->name, "ES1371 DAC2/ADC");
1246 #endif
1247         ensoniq->pcm1 = pcm;
1248
1249         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1250                                               snd_dma_pci_data(ensoniq->pci), 64*1024, 128*1024);
1251
1252         if (rpcm)
1253                 *rpcm = pcm;
1254         return 0;
1255 }
1256
1257 static void snd_ensoniq_pcm_free2(snd_pcm_t *pcm)
1258 {
1259         ensoniq_t *ensoniq = pcm->private_data;
1260         ensoniq->pcm2 = NULL;
1261         snd_pcm_lib_preallocate_free_for_all(pcm);
1262 }
1263
1264 static int __devinit snd_ensoniq_pcm2(ensoniq_t * ensoniq, int device, snd_pcm_t ** rpcm)
1265 {
1266         snd_pcm_t *pcm;
1267         int err;
1268
1269         if (rpcm)
1270                 *rpcm = NULL;
1271 #ifdef CHIP1370
1272         err = snd_pcm_new(ensoniq->card, "ES1370/2", device, 1, 0, &pcm);
1273 #else
1274         err = snd_pcm_new(ensoniq->card, "ES1371/2", device, 1, 0, &pcm);
1275 #endif
1276         if (err < 0)
1277                 return err;
1278
1279 #ifdef CHIP1370
1280         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ensoniq_playback1_ops);
1281 #else
1282         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ensoniq_playback2_ops);
1283 #endif
1284         pcm->private_data = ensoniq;
1285         pcm->private_free = snd_ensoniq_pcm_free2;
1286         pcm->info_flags = 0;
1287 #ifdef CHIP1370
1288         strcpy(pcm->name, "ES1370 DAC1");
1289 #else
1290         strcpy(pcm->name, "ES1371 DAC1");
1291 #endif
1292         ensoniq->pcm2 = pcm;
1293
1294         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1295                                               snd_dma_pci_data(ensoniq->pci), 64*1024, 128*1024);
1296
1297         if (rpcm)
1298                 *rpcm = pcm;
1299         return 0;
1300 }
1301
1302 /*
1303  *  Mixer section
1304  */
1305
1306 /*
1307  * ENS1371 mixer (including SPDIF interface)
1308  */
1309 #ifdef CHIP1371
1310 static int snd_ens1373_spdif_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
1311 {
1312         uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1313         uinfo->count = 1;
1314         return 0;
1315 }
1316
1317 static int snd_ens1373_spdif_default_get(snd_kcontrol_t * kcontrol,
1318                                          snd_ctl_elem_value_t * ucontrol)
1319 {
1320         ensoniq_t *ensoniq = snd_kcontrol_chip(kcontrol);
1321         spin_lock_irq(&ensoniq->reg_lock);
1322         ucontrol->value.iec958.status[0] = (ensoniq->spdif_default >> 0) & 0xff;
1323         ucontrol->value.iec958.status[1] = (ensoniq->spdif_default >> 8) & 0xff;
1324         ucontrol->value.iec958.status[2] = (ensoniq->spdif_default >> 16) & 0xff;
1325         ucontrol->value.iec958.status[3] = (ensoniq->spdif_default >> 24) & 0xff;
1326         spin_unlock_irq(&ensoniq->reg_lock);
1327         return 0;
1328 }
1329
1330 static int snd_ens1373_spdif_default_put(snd_kcontrol_t * kcontrol,
1331                                          snd_ctl_elem_value_t * ucontrol)
1332 {
1333         ensoniq_t *ensoniq = snd_kcontrol_chip(kcontrol);
1334         unsigned int val;
1335         int change;
1336
1337         val = ((u32)ucontrol->value.iec958.status[0] << 0) |
1338               ((u32)ucontrol->value.iec958.status[1] << 8) |
1339               ((u32)ucontrol->value.iec958.status[2] << 16) |
1340               ((u32)ucontrol->value.iec958.status[3] << 24);
1341         spin_lock_irq(&ensoniq->reg_lock);
1342         change = ensoniq->spdif_default != val;
1343         ensoniq->spdif_default = val;
1344         if (change && ensoniq->playback1_substream == NULL && ensoniq->playback2_substream == NULL)
1345                 outl(val, ES_REG(ensoniq, CHANNEL_STATUS));
1346         spin_unlock_irq(&ensoniq->reg_lock);
1347         return change;
1348 }
1349
1350 static int snd_ens1373_spdif_mask_get(snd_kcontrol_t * kcontrol,
1351                                          snd_ctl_elem_value_t * ucontrol)
1352 {
1353         ucontrol->value.iec958.status[0] = 0xff;
1354         ucontrol->value.iec958.status[1] = 0xff;
1355         ucontrol->value.iec958.status[2] = 0xff;
1356         ucontrol->value.iec958.status[3] = 0xff;
1357         return 0;
1358 }
1359
1360 static int snd_ens1373_spdif_stream_get(snd_kcontrol_t * kcontrol,
1361                                          snd_ctl_elem_value_t * ucontrol)
1362 {
1363         ensoniq_t *ensoniq = snd_kcontrol_chip(kcontrol);
1364         spin_lock_irq(&ensoniq->reg_lock);
1365         ucontrol->value.iec958.status[0] = (ensoniq->spdif_stream >> 0) & 0xff;
1366         ucontrol->value.iec958.status[1] = (ensoniq->spdif_stream >> 8) & 0xff;
1367         ucontrol->value.iec958.status[2] = (ensoniq->spdif_stream >> 16) & 0xff;
1368         ucontrol->value.iec958.status[3] = (ensoniq->spdif_stream >> 24) & 0xff;
1369         spin_unlock_irq(&ensoniq->reg_lock);
1370         return 0;
1371 }
1372
1373 static int snd_ens1373_spdif_stream_put(snd_kcontrol_t * kcontrol,
1374                                         snd_ctl_elem_value_t * ucontrol)
1375 {
1376         ensoniq_t *ensoniq = snd_kcontrol_chip(kcontrol);
1377         unsigned int val;
1378         int change;
1379
1380         val = ((u32)ucontrol->value.iec958.status[0] << 0) |
1381               ((u32)ucontrol->value.iec958.status[1] << 8) |
1382               ((u32)ucontrol->value.iec958.status[2] << 16) |
1383               ((u32)ucontrol->value.iec958.status[3] << 24);
1384         spin_lock_irq(&ensoniq->reg_lock);
1385         change = ensoniq->spdif_stream != val;
1386         ensoniq->spdif_stream = val;
1387         if (change && (ensoniq->playback1_substream != NULL || ensoniq->playback2_substream != NULL))
1388                 outl(val, ES_REG(ensoniq, CHANNEL_STATUS));
1389         spin_unlock_irq(&ensoniq->reg_lock);
1390         return change;
1391 }
1392
1393 #define ES1371_SPDIF(xname) \
1394 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .info = snd_es1371_spdif_info, \
1395   .get = snd_es1371_spdif_get, .put = snd_es1371_spdif_put }
1396
1397 static int snd_es1371_spdif_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t *uinfo)
1398 {
1399         uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
1400         uinfo->count = 1;
1401         uinfo->value.integer.min = 0;
1402         uinfo->value.integer.max = 1;
1403         return 0;
1404 }
1405
1406 static int snd_es1371_spdif_get(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1407 {
1408         ensoniq_t *ensoniq = snd_kcontrol_chip(kcontrol);
1409
1410         spin_lock_irq(&ensoniq->reg_lock);
1411         ucontrol->value.integer.value[0] = ensoniq->ctrl & ES_1373_SPDIF_THRU ? 1 : 0;
1412         spin_unlock_irq(&ensoniq->reg_lock);
1413         return 0;
1414 }
1415
1416 static int snd_es1371_spdif_put(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1417 {
1418         ensoniq_t *ensoniq = snd_kcontrol_chip(kcontrol);
1419         unsigned int nval1, nval2;
1420         int change;
1421
1422         nval1 = ucontrol->value.integer.value[0] ? ES_1373_SPDIF_THRU : 0;
1423         nval2 = ucontrol->value.integer.value[0] ? ES_1373_SPDIF_EN : 0;
1424         spin_lock_irq(&ensoniq->reg_lock);
1425         change = (ensoniq->ctrl & ES_1373_SPDIF_THRU) != nval1;
1426         ensoniq->ctrl &= ~ES_1373_SPDIF_THRU;
1427         ensoniq->ctrl |= nval1;
1428         ensoniq->cssr &= ~ES_1373_SPDIF_EN;
1429         ensoniq->cssr |= nval2;
1430         outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1431         outl(ensoniq->cssr, ES_REG(ensoniq, STATUS));
1432         spin_unlock_irq(&ensoniq->reg_lock);
1433         return change;
1434 }
1435
1436
1437 /* spdif controls */
1438 static snd_kcontrol_new_t snd_es1371_mixer_spdif[] __devinitdata = {
1439         ES1371_SPDIF(SNDRV_CTL_NAME_IEC958("",PLAYBACK,SWITCH)),
1440         {
1441                 .iface =        SNDRV_CTL_ELEM_IFACE_PCM,
1442                 .name =         SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
1443                 .info =         snd_ens1373_spdif_info,
1444                 .get =          snd_ens1373_spdif_default_get,
1445                 .put =          snd_ens1373_spdif_default_put,
1446         },
1447         {
1448                 .access =       SNDRV_CTL_ELEM_ACCESS_READ,
1449                 .iface =        SNDRV_CTL_ELEM_IFACE_PCM,
1450                 .name =         SNDRV_CTL_NAME_IEC958("",PLAYBACK,MASK),
1451                 .info =         snd_ens1373_spdif_info,
1452                 .get =          snd_ens1373_spdif_mask_get
1453         },
1454         {
1455                 .iface =        SNDRV_CTL_ELEM_IFACE_PCM,
1456                 .name =         SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
1457                 .info =         snd_ens1373_spdif_info,
1458                 .get =          snd_ens1373_spdif_stream_get,
1459                 .put =          snd_ens1373_spdif_stream_put
1460         },
1461 };
1462
1463
1464 static int snd_es1373_rear_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t *uinfo)
1465 {
1466         uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
1467         uinfo->count = 1;
1468         uinfo->value.integer.min = 0;
1469         uinfo->value.integer.max = 1;
1470         return 0;
1471 }
1472
1473 static int snd_es1373_rear_get(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1474 {
1475         ensoniq_t *ensoniq = snd_kcontrol_chip(kcontrol);
1476         int val = 0;
1477
1478         spin_lock_irq(&ensoniq->reg_lock);
1479         if ((ensoniq->cssr & (ES_1373_REAR_BIT27|ES_1373_REAR_BIT26|ES_1373_REAR_BIT24)) == ES_1373_REAR_BIT26)
1480                 val = 1;
1481         ucontrol->value.integer.value[0] = val;
1482         spin_unlock_irq(&ensoniq->reg_lock);
1483         return 0;
1484 }
1485
1486 static int snd_es1373_rear_put(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1487 {
1488         ensoniq_t *ensoniq = snd_kcontrol_chip(kcontrol);
1489         unsigned int nval1;
1490         int change;
1491
1492         nval1 = ucontrol->value.integer.value[0] ? ES_1373_REAR_BIT26 : (ES_1373_REAR_BIT27|ES_1373_REAR_BIT24);
1493         spin_lock_irq(&ensoniq->reg_lock);
1494         change = (ensoniq->cssr & (ES_1373_REAR_BIT27|ES_1373_REAR_BIT26|ES_1373_REAR_BIT24)) != nval1;
1495         ensoniq->cssr &= ~(ES_1373_REAR_BIT27|ES_1373_REAR_BIT26|ES_1373_REAR_BIT24);
1496         ensoniq->cssr |= nval1;
1497         outl(ensoniq->cssr, ES_REG(ensoniq, STATUS));
1498         spin_unlock_irq(&ensoniq->reg_lock);
1499         return change;
1500 }
1501
1502 static snd_kcontrol_new_t snd_ens1373_rear __devinitdata =
1503 {
1504         .iface =        SNDRV_CTL_ELEM_IFACE_MIXER,
1505         .name =         "AC97 2ch->4ch Copy Switch",
1506         .info =         snd_es1373_rear_info,
1507         .get =          snd_es1373_rear_get,
1508         .put =          snd_es1373_rear_put,
1509 };
1510
1511 static int snd_es1373_line_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t *uinfo)
1512 {
1513         uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
1514         uinfo->count = 1;
1515         uinfo->value.integer.min = 0;
1516         uinfo->value.integer.max = 1;
1517         return 0;
1518 }
1519
1520 static int snd_es1373_line_get(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1521 {
1522         ensoniq_t *ensoniq = snd_kcontrol_chip(kcontrol);
1523         int val = 0;
1524
1525         spin_lock_irq(&ensoniq->reg_lock);
1526         if ((ensoniq->ctrl & ES_1371_GPIO_OUTM) >= 4)
1527                 val = 1;
1528         ucontrol->value.integer.value[0] = val;
1529         spin_unlock_irq(&ensoniq->reg_lock);
1530         return 0;
1531 }
1532
1533 static int snd_es1373_line_put(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1534 {
1535         ensoniq_t *ensoniq = snd_kcontrol_chip(kcontrol);
1536         int changed;
1537         unsigned int ctrl;
1538
1539         spin_lock_irq(&ensoniq->reg_lock);
1540         ctrl = ensoniq->ctrl;
1541         if (ucontrol->value.integer.value[0])
1542                 ensoniq->ctrl |= ES_1371_GPIO_OUT(4);   /* switch line-in -> rear out */
1543         else
1544                 ensoniq->ctrl &= ~ES_1371_GPIO_OUT(4);
1545         changed = (ctrl != ensoniq->ctrl);
1546         if (changed)
1547                 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1548         spin_unlock_irq(&ensoniq->reg_lock);
1549         return changed;
1550 }
1551
1552 static snd_kcontrol_new_t snd_ens1373_line __devinitdata =
1553 {
1554         .iface =        SNDRV_CTL_ELEM_IFACE_MIXER,
1555         .name =         "Line In->Rear Out Switch",
1556         .info =         snd_es1373_line_info,
1557         .get =          snd_es1373_line_get,
1558         .put =          snd_es1373_line_put,
1559 };
1560
1561 static void snd_ensoniq_mixer_free_ac97(ac97_t *ac97)
1562 {
1563         ensoniq_t *ensoniq = ac97->private_data;
1564         ensoniq->u.es1371.ac97 = NULL;
1565 }
1566
1567 static struct {
1568         unsigned short vid;             /* vendor ID */
1569         unsigned short did;             /* device ID */
1570         unsigned char rev;              /* revision */
1571 } es1371_spdif_present[] __devinitdata = {
1572         { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_C },
1573         { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_D },
1574         { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_E },
1575         { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_ES1371, .rev = ES1371REV_CT5880_A },
1576         { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_ES1371, .rev = ES1371REV_ES1373_8 },
1577         { .vid = PCI_ANY_ID, .did = PCI_ANY_ID }
1578 };
1579
1580 static int snd_ensoniq_1371_mixer(ensoniq_t * ensoniq)
1581 {
1582         snd_card_t *card = ensoniq->card;
1583         ac97_bus_t *pbus;
1584         ac97_template_t ac97;
1585         int err, idx;
1586         static ac97_bus_ops_t ops = {
1587                 .write = snd_es1371_codec_write,
1588                 .read = snd_es1371_codec_read,
1589                 .wait = snd_es1371_codec_wait,
1590         };
1591
1592         if ((err = snd_ac97_bus(card, 0, &ops, NULL, &pbus)) < 0)
1593                 return err;
1594
1595         memset(&ac97, 0, sizeof(ac97));
1596         ac97.private_data = ensoniq;
1597         ac97.private_free = snd_ensoniq_mixer_free_ac97;
1598         ac97.scaps = AC97_SCAP_AUDIO;
1599         if ((err = snd_ac97_mixer(pbus, &ac97, &ensoniq->u.es1371.ac97)) < 0)
1600                 return err;
1601         for (idx = 0; es1371_spdif_present[idx].vid != (unsigned short)PCI_ANY_ID; idx++)
1602                 if (ensoniq->pci->vendor == es1371_spdif_present[idx].vid &&
1603                     ensoniq->pci->device == es1371_spdif_present[idx].did &&
1604                     ensoniq->rev == es1371_spdif_present[idx].rev) {
1605                         snd_kcontrol_t *kctl;
1606                         int i, index = 0;
1607
1608                         ensoniq->spdif_default = ensoniq->spdif_stream = SNDRV_PCM_DEFAULT_CON_SPDIF;
1609                         outl(ensoniq->spdif_default, ES_REG(ensoniq, CHANNEL_STATUS));
1610
1611                         if (ensoniq->u.es1371.ac97->ext_id & AC97_EI_SPDIF)
1612                                 index++;
1613
1614                         for (i = 0; i < (int)ARRAY_SIZE(snd_es1371_mixer_spdif); i++) {
1615                                 kctl = snd_ctl_new1(&snd_es1371_mixer_spdif[i], ensoniq);
1616                                 if (! kctl)
1617                                         return -ENOMEM;
1618                                 kctl->id.index = index;
1619                                 if ((err = snd_ctl_add(card, kctl)) < 0)
1620                                         return err;
1621                         }
1622                         break;
1623                 }
1624         if (ensoniq->u.es1371.ac97->ext_id & AC97_EI_SDAC) {
1625                 /* mirror rear to front speakers */
1626                 ensoniq->cssr &= ~(ES_1373_REAR_BIT27|ES_1373_REAR_BIT24);
1627                 ensoniq->cssr |= ES_1373_REAR_BIT26;
1628                 err = snd_ctl_add(card, snd_ctl_new1(&snd_ens1373_rear, ensoniq));
1629                 if (err < 0)
1630                         return err;
1631         }
1632         if (((ensoniq->subsystem_vendor_id == 0x1274) &&
1633             (ensoniq->subsystem_device_id == 0x2000)) || /* GA-7DXR */
1634             ((ensoniq->subsystem_vendor_id == 0x1458) &&
1635             (ensoniq->subsystem_device_id == 0xa000))) { /* GA-8IEXP */
1636                  err = snd_ctl_add(card, snd_ctl_new1(&snd_ens1373_line, ensoniq));
1637                  if (err < 0)
1638                          return err;
1639         }
1640
1641         return 0;
1642 }
1643
1644 #endif /* CHIP1371 */
1645
1646 /* generic control callbacks for ens1370 */
1647 #ifdef CHIP1370
1648 #define ENSONIQ_CONTROL(xname, mask) \
1649 { .iface = SNDRV_CTL_ELEM_IFACE_CARD, .name = xname, .info = snd_ensoniq_control_info, \
1650   .get = snd_ensoniq_control_get, .put = snd_ensoniq_control_put, \
1651   .private_value = mask }
1652
1653 static int snd_ensoniq_control_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t *uinfo)
1654 {
1655         uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
1656         uinfo->count = 1;
1657         uinfo->value.integer.min = 0;
1658         uinfo->value.integer.max = 1;
1659         return 0;
1660 }
1661
1662 static int snd_ensoniq_control_get(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1663 {
1664         ensoniq_t *ensoniq = snd_kcontrol_chip(kcontrol);
1665         int mask = kcontrol->private_value;
1666
1667         spin_lock_irq(&ensoniq->reg_lock);
1668         ucontrol->value.integer.value[0] = ensoniq->ctrl & mask ? 1 : 0;
1669         spin_unlock_irq(&ensoniq->reg_lock);
1670         return 0;
1671 }
1672
1673 static int snd_ensoniq_control_put(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1674 {
1675         ensoniq_t *ensoniq = snd_kcontrol_chip(kcontrol);
1676         int mask = kcontrol->private_value;
1677         unsigned int nval;
1678         int change;
1679
1680         nval = ucontrol->value.integer.value[0] ? mask : 0;
1681         spin_lock_irq(&ensoniq->reg_lock);
1682         change = (ensoniq->ctrl & mask) != nval;
1683         ensoniq->ctrl &= ~mask;
1684         ensoniq->ctrl |= nval;
1685         outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1686         spin_unlock_irq(&ensoniq->reg_lock);
1687         return change;
1688 }
1689
1690 /*
1691  * ENS1370 mixer
1692  */
1693
1694 static snd_kcontrol_new_t snd_es1370_controls[2] __devinitdata = {
1695 ENSONIQ_CONTROL("PCM 0 Output also on Line-In Jack", ES_1370_XCTL0),
1696 ENSONIQ_CONTROL("Mic +5V bias", ES_1370_XCTL1)
1697 };
1698
1699 #define ES1370_CONTROLS ARRAY_SIZE(snd_es1370_controls)
1700
1701 static void snd_ensoniq_mixer_free_ak4531(ak4531_t *ak4531)
1702 {
1703         ensoniq_t *ensoniq = ak4531->private_data;
1704         ensoniq->u.es1370.ak4531 = NULL;
1705 }
1706
1707 static int __devinit snd_ensoniq_1370_mixer(ensoniq_t * ensoniq)
1708 {
1709         snd_card_t *card = ensoniq->card;
1710         ak4531_t ak4531;
1711         unsigned int idx;
1712         int err;
1713
1714         /* try reset AK4531 */
1715         outw(ES_1370_CODEC_WRITE(AK4531_RESET, 0x02), ES_REG(ensoniq, 1370_CODEC));
1716         inw(ES_REG(ensoniq, 1370_CODEC));
1717         udelay(100);
1718         outw(ES_1370_CODEC_WRITE(AK4531_RESET, 0x03), ES_REG(ensoniq, 1370_CODEC));
1719         inw(ES_REG(ensoniq, 1370_CODEC));
1720         udelay(100);
1721
1722         memset(&ak4531, 0, sizeof(ak4531));
1723         ak4531.write = snd_es1370_codec_write;
1724         ak4531.private_data = ensoniq;
1725         ak4531.private_free = snd_ensoniq_mixer_free_ak4531;
1726         if ((err = snd_ak4531_mixer(card, &ak4531, &ensoniq->u.es1370.ak4531)) < 0)
1727                 return err;
1728         for (idx = 0; idx < ES1370_CONTROLS; idx++) {
1729                 err = snd_ctl_add(card, snd_ctl_new1(&snd_es1370_controls[idx], ensoniq));
1730                 if (err < 0)
1731                         return err;
1732         }
1733         return 0;
1734 }
1735
1736 #endif /* CHIP1370 */
1737
1738 #ifdef SUPPORT_JOYSTICK
1739
1740 #ifdef CHIP1371
1741 static int __devinit snd_ensoniq_get_joystick_port(int dev)
1742 {
1743         switch (joystick_port[dev]) {
1744         case 0: /* disabled */
1745         case 1: /* auto-detect */
1746         case 0x200:
1747         case 0x208:
1748         case 0x210:
1749         case 0x218:
1750                 return joystick_port[dev];
1751
1752         default:
1753                 printk(KERN_ERR "ens1371: invalid joystick port %#x", joystick_port[dev]);
1754                 return 0;
1755         }
1756 }
1757 #else
1758 static inline int snd_ensoniq_get_joystick_port(int dev)
1759 {
1760         return joystick[dev] ? 0x200 : 0;
1761 }
1762 #endif
1763
1764 static int __devinit snd_ensoniq_create_gameport(ensoniq_t *ensoniq, int dev)
1765 {
1766         struct gameport *gp;
1767         int io_port;
1768
1769         io_port = snd_ensoniq_get_joystick_port(dev);
1770
1771         switch (io_port) {
1772         case 0:
1773                 return -ENOSYS;
1774
1775         case 1: /* auto_detect */
1776                 for (io_port = 0x200; io_port <= 0x218; io_port += 8)
1777                         if (request_region(io_port, 8, "ens137x: gameport"))
1778                                 break;
1779                 if (io_port > 0x218) {
1780                         printk(KERN_WARNING "ens137x: no gameport ports available\n");
1781                         return -EBUSY;
1782                 }
1783                 break;
1784
1785         default:
1786                 if (!request_region(io_port, 8, "ens137x: gameport")) {
1787                         printk(KERN_WARNING "ens137x: gameport io port 0x%#x in use\n", io_port);
1788                         return -EBUSY;
1789                 }
1790                 break;
1791         }
1792
1793         ensoniq->gameport = gp = gameport_allocate_port();
1794         if (!gp) {
1795                 printk(KERN_ERR "ens137x: cannot allocate memory for gameport\n");
1796                 release_region(io_port, 8);
1797                 return -ENOMEM;
1798         }
1799
1800         gameport_set_name(gp, "ES137x");
1801         gameport_set_phys(gp, "pci%s/gameport0", pci_name(ensoniq->pci));
1802         gameport_set_dev_parent(gp, &ensoniq->pci->dev);
1803         gp->io = io_port;
1804
1805         ensoniq->ctrl |= ES_JYSTK_EN;
1806 #ifdef CHIP1371
1807         ensoniq->ctrl &= ~ES_1371_JOY_ASELM;
1808         ensoniq->ctrl |= ES_1371_JOY_ASEL((io_port - 0x200) / 8);
1809 #endif
1810         outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1811
1812         gameport_register_port(ensoniq->gameport);
1813
1814         return 0;
1815 }
1816
1817 static void snd_ensoniq_free_gameport(ensoniq_t *ensoniq)
1818 {
1819         if (ensoniq->gameport) {
1820                 int port = ensoniq->gameport->io;
1821
1822                 gameport_unregister_port(ensoniq->gameport);
1823                 ensoniq->gameport = NULL;
1824                 ensoniq->ctrl &= ~ES_JYSTK_EN;
1825                 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1826                 release_region(port, 8);
1827         }
1828 }
1829 #else
1830 static inline int snd_ensoniq_create_gameport(ensoniq_t *ensoniq, long port) { return -ENOSYS; }
1831 static inline void snd_ensoniq_free_gameport(ensoniq_t *ensoniq) { }
1832 #endif /* SUPPORT_JOYSTICK */
1833
1834 /*
1835
1836  */
1837
1838 static void snd_ensoniq_proc_read(snd_info_entry_t *entry,
1839                                   snd_info_buffer_t * buffer)
1840 {
1841         ensoniq_t *ensoniq = entry->private_data;
1842
1843 #ifdef CHIP1370
1844         snd_iprintf(buffer, "Ensoniq AudioPCI ES1370\n\n");
1845 #else
1846         snd_iprintf(buffer, "Ensoniq AudioPCI ES1371\n\n");
1847 #endif
1848         snd_iprintf(buffer, "Joystick enable  : %s\n", ensoniq->ctrl & ES_JYSTK_EN ? "on" : "off");
1849 #ifdef CHIP1370
1850         snd_iprintf(buffer, "MIC +5V bias     : %s\n", ensoniq->ctrl & ES_1370_XCTL1 ? "on" : "off");
1851         snd_iprintf(buffer, "Line In to AOUT  : %s\n", ensoniq->ctrl & ES_1370_XCTL0 ? "on" : "off");
1852 #else
1853         snd_iprintf(buffer, "Joystick port    : 0x%x\n", (ES_1371_JOY_ASELI(ensoniq->ctrl) * 8) + 0x200);
1854 #endif
1855 }
1856
1857 static void __devinit snd_ensoniq_proc_init(ensoniq_t * ensoniq)
1858 {
1859         snd_info_entry_t *entry;
1860
1861         if (! snd_card_proc_new(ensoniq->card, "audiopci", &entry))
1862                 snd_info_set_text_ops(entry, ensoniq, 1024, snd_ensoniq_proc_read);
1863 }
1864
1865 /*
1866
1867  */
1868
1869 static int snd_ensoniq_free(ensoniq_t *ensoniq)
1870 {
1871         snd_ensoniq_free_gameport(ensoniq);
1872         if (ensoniq->irq < 0)
1873                 goto __hw_end;
1874 #ifdef CHIP1370
1875         outl(ES_1370_SERR_DISABLE, ES_REG(ensoniq, CONTROL));   /* switch everything off */
1876         outl(0, ES_REG(ensoniq, SERIAL));       /* clear serial interface */
1877 #else
1878         outl(0, ES_REG(ensoniq, CONTROL));      /* switch everything off */
1879         outl(0, ES_REG(ensoniq, SERIAL));       /* clear serial interface */
1880 #endif
1881         synchronize_irq(ensoniq->irq);
1882         pci_set_power_state(ensoniq->pci, 3);
1883       __hw_end:
1884 #ifdef CHIP1370
1885         if (ensoniq->dma_bug.area)
1886                 snd_dma_free_pages(&ensoniq->dma_bug);
1887 #endif
1888         if (ensoniq->irq >= 0)
1889                 free_irq(ensoniq->irq, (void *)ensoniq);
1890         pci_release_regions(ensoniq->pci);
1891         pci_disable_device(ensoniq->pci);
1892         kfree(ensoniq);
1893         return 0;
1894 }
1895
1896 static int snd_ensoniq_dev_free(snd_device_t *device)
1897 {
1898         ensoniq_t *ensoniq = device->device_data;
1899         return snd_ensoniq_free(ensoniq);
1900 }
1901
1902 #ifdef CHIP1371
1903 static struct {
1904         unsigned short svid;            /* subsystem vendor ID */
1905         unsigned short sdid;            /* subsystem device ID */
1906 } es1371_amplifier_hack[] = {
1907         { .svid = 0x107b, .sdid = 0x2150 },     /* Gateway Solo 2150 */
1908         { .svid = 0x13bd, .sdid = 0x100c },     /* EV1938 on Mebius PC-MJ100V */
1909         { .svid = 0x1102, .sdid = 0x5938 },     /* Targa Xtender300 */
1910         { .svid = 0x1102, .sdid = 0x8938 },     /* IPC Topnote G notebook */
1911         { .svid = PCI_ANY_ID, .sdid = PCI_ANY_ID }
1912 };
1913 static struct {
1914         unsigned short vid;             /* vendor ID */
1915         unsigned short did;             /* device ID */
1916         unsigned char rev;              /* revision */
1917 } es1371_ac97_reset_hack[] = {
1918         { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_C },
1919         { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_D },
1920         { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_E },
1921         { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_ES1371, .rev = ES1371REV_CT5880_A },
1922         { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_ES1371, .rev = ES1371REV_ES1373_8 },
1923         { .vid = PCI_ANY_ID, .did = PCI_ANY_ID }
1924 };
1925 #endif
1926
1927 static int __devinit snd_ensoniq_create(snd_card_t * card,
1928                                      struct pci_dev *pci,
1929                                      ensoniq_t ** rensoniq)
1930 {
1931         ensoniq_t *ensoniq;
1932         unsigned short cmdw;
1933         unsigned char cmdb;
1934 #ifdef CHIP1371
1935         int idx;
1936 #endif
1937         int err;
1938         static snd_device_ops_t ops = {
1939                 .dev_free =     snd_ensoniq_dev_free,
1940         };
1941
1942         *rensoniq = NULL;
1943         if ((err = pci_enable_device(pci)) < 0)
1944                 return err;
1945         ensoniq = kzalloc(sizeof(*ensoniq), GFP_KERNEL);
1946         if (ensoniq == NULL) {
1947                 pci_disable_device(pci);
1948                 return -ENOMEM;
1949         }
1950         spin_lock_init(&ensoniq->reg_lock);
1951         init_MUTEX(&ensoniq->src_mutex);
1952         ensoniq->card = card;
1953         ensoniq->pci = pci;
1954         ensoniq->irq = -1;
1955         if ((err = pci_request_regions(pci, "Ensoniq AudioPCI")) < 0) {
1956                 kfree(ensoniq);
1957                 pci_disable_device(pci);
1958                 return err;
1959         }
1960         ensoniq->port = pci_resource_start(pci, 0);
1961         if (request_irq(pci->irq, snd_audiopci_interrupt, SA_INTERRUPT|SA_SHIRQ, "Ensoniq AudioPCI", (void *)ensoniq)) {
1962                 snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq);
1963                 snd_ensoniq_free(ensoniq);
1964                 return -EBUSY;
1965         }
1966         ensoniq->irq = pci->irq;
1967 #ifdef CHIP1370
1968         if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(pci),
1969                                 16, &ensoniq->dma_bug) < 0) {
1970                 snd_printk(KERN_ERR "unable to allocate space for phantom area - dma_bug\n");
1971                 snd_ensoniq_free(ensoniq);
1972                 return -EBUSY;
1973         }
1974 #endif
1975         pci_set_master(pci);
1976         pci_read_config_byte(pci, PCI_REVISION_ID, &cmdb);
1977         ensoniq->rev = cmdb;
1978         pci_read_config_word(pci, PCI_SUBSYSTEM_VENDOR_ID, &cmdw);
1979         ensoniq->subsystem_vendor_id = cmdw;
1980         pci_read_config_word(pci, PCI_SUBSYSTEM_ID, &cmdw);
1981         ensoniq->subsystem_device_id = cmdw;
1982 #ifdef CHIP1370
1983 #if 0
1984         ensoniq->ctrl = ES_1370_CDC_EN | ES_1370_SERR_DISABLE | ES_1370_PCLKDIVO(ES_1370_SRTODIV(8000));
1985 #else   /* get microphone working */
1986         ensoniq->ctrl = ES_1370_CDC_EN | ES_1370_PCLKDIVO(ES_1370_SRTODIV(8000));
1987 #endif
1988         ensoniq->sctrl = 0;
1989         /* initialize the chips */
1990         outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1991         outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
1992         outl(ES_MEM_PAGEO(ES_PAGE_ADC), ES_REG(ensoniq, MEM_PAGE));
1993         outl(ensoniq->dma_bug.addr, ES_REG(ensoniq, PHANTOM_FRAME));
1994         outl(0, ES_REG(ensoniq, PHANTOM_COUNT));
1995 #else
1996         ensoniq->ctrl = 0;
1997         ensoniq->sctrl = 0;
1998         ensoniq->cssr = 0;
1999         for (idx = 0; es1371_amplifier_hack[idx].svid != (unsigned short)PCI_ANY_ID; idx++)
2000                 if (ensoniq->subsystem_vendor_id == es1371_amplifier_hack[idx].svid &&
2001                     ensoniq->subsystem_device_id == es1371_amplifier_hack[idx].sdid) {
2002                         ensoniq->ctrl |= ES_1371_GPIO_OUT(1);   /* turn amplifier on */
2003                         break;
2004                 }
2005         /* initialize the chips */
2006         outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
2007         outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
2008         outl(0, ES_REG(ensoniq, 1371_LEGACY));
2009         for (idx = 0; es1371_ac97_reset_hack[idx].vid != (unsigned short)PCI_ANY_ID; idx++)
2010                 if (pci->vendor == es1371_ac97_reset_hack[idx].vid &&
2011                     pci->device == es1371_ac97_reset_hack[idx].did &&
2012                     ensoniq->rev == es1371_ac97_reset_hack[idx].rev) {
2013                         ensoniq->cssr |= ES_1371_ST_AC97_RST;
2014                         outl(ensoniq->cssr, ES_REG(ensoniq, STATUS));
2015                         /* need to delay around 20ms(bleech) to give
2016                         some CODECs enough time to wakeup */
2017                         msleep(20);
2018                         break;
2019                 }
2020         /* AC'97 warm reset to start the bitclk */
2021         outl(ensoniq->ctrl | ES_1371_SYNC_RES, ES_REG(ensoniq, CONTROL));
2022         inl(ES_REG(ensoniq, CONTROL));
2023         udelay(20);
2024         outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
2025         /* Init the sample rate converter */
2026         snd_es1371_wait_src_ready(ensoniq);
2027         outl(ES_1371_SRC_DISABLE, ES_REG(ensoniq, 1371_SMPRATE));
2028         for (idx = 0; idx < 0x80; idx++)
2029                 snd_es1371_src_write(ensoniq, idx, 0);
2030         snd_es1371_src_write(ensoniq, ES_SMPREG_DAC1 + ES_SMPREG_TRUNC_N, 16 << 4);
2031         snd_es1371_src_write(ensoniq, ES_SMPREG_DAC1 + ES_SMPREG_INT_REGS, 16 << 10);
2032         snd_es1371_src_write(ensoniq, ES_SMPREG_DAC2 + ES_SMPREG_TRUNC_N, 16 << 4);
2033         snd_es1371_src_write(ensoniq, ES_SMPREG_DAC2 + ES_SMPREG_INT_REGS, 16 << 10);
2034         snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_ADC, 1 << 12);
2035         snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_ADC + 1, 1 << 12);
2036         snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_DAC1, 1 << 12);
2037         snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_DAC1 + 1, 1 << 12);
2038         snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_DAC2, 1 << 12);
2039         snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_DAC2 + 1, 1 << 12);
2040         snd_es1371_adc_rate(ensoniq, 22050);
2041         snd_es1371_dac1_rate(ensoniq, 22050);
2042         snd_es1371_dac2_rate(ensoniq, 22050);
2043         /* WARNING:
2044          * enabling the sample rate converter without properly programming
2045          * its parameters causes the chip to lock up (the SRC busy bit will
2046          * be stuck high, and I've found no way to rectify this other than
2047          * power cycle) - Thomas Sailer
2048          */
2049         snd_es1371_wait_src_ready(ensoniq);
2050         outl(0, ES_REG(ensoniq, 1371_SMPRATE));
2051         /* try reset codec directly */
2052         outl(ES_1371_CODEC_WRITE(0, 0), ES_REG(ensoniq, 1371_CODEC));
2053 #endif
2054         outb(ensoniq->uartc = 0x00, ES_REG(ensoniq, UART_CONTROL));
2055         outb(0x00, ES_REG(ensoniq, UART_RES));
2056         outl(ensoniq->cssr, ES_REG(ensoniq, STATUS));
2057         synchronize_irq(ensoniq->irq);
2058
2059         if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, ensoniq, &ops)) < 0) {
2060                 snd_ensoniq_free(ensoniq);
2061                 return err;
2062         }
2063
2064         snd_ensoniq_proc_init(ensoniq);
2065
2066         snd_card_set_dev(card, &pci->dev);
2067
2068         *rensoniq = ensoniq;
2069         return 0;
2070 }
2071
2072 /*
2073  *  MIDI section
2074  */
2075
2076 static void snd_ensoniq_midi_interrupt(ensoniq_t * ensoniq)
2077 {
2078         snd_rawmidi_t * rmidi = ensoniq->rmidi;
2079         unsigned char status, mask, byte;
2080
2081         if (rmidi == NULL)
2082                 return;
2083         /* do Rx at first */
2084         spin_lock(&ensoniq->reg_lock);
2085         mask = ensoniq->uartm & ES_MODE_INPUT ? ES_RXRDY : 0;
2086         while (mask) {
2087                 status = inb(ES_REG(ensoniq, UART_STATUS));
2088                 if ((status & mask) == 0)
2089                         break;
2090                 byte = inb(ES_REG(ensoniq, UART_DATA));
2091                 snd_rawmidi_receive(ensoniq->midi_input, &byte, 1);
2092         }
2093         spin_unlock(&ensoniq->reg_lock);
2094
2095         /* do Tx at second */
2096         spin_lock(&ensoniq->reg_lock);
2097         mask = ensoniq->uartm & ES_MODE_OUTPUT ? ES_TXRDY : 0;
2098         while (mask) {
2099                 status = inb(ES_REG(ensoniq, UART_STATUS));
2100                 if ((status & mask) == 0)
2101                         break;
2102                 if (snd_rawmidi_transmit(ensoniq->midi_output, &byte, 1) != 1) {
2103                         ensoniq->uartc &= ~ES_TXINTENM;
2104                         outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL));
2105                         mask &= ~ES_TXRDY;
2106                 } else {
2107                         outb(byte, ES_REG(ensoniq, UART_DATA));
2108                 }
2109         }
2110         spin_unlock(&ensoniq->reg_lock);
2111 }
2112
2113 static int snd_ensoniq_midi_input_open(snd_rawmidi_substream_t * substream)
2114 {
2115         ensoniq_t *ensoniq = substream->rmidi->private_data;
2116
2117         spin_lock_irq(&ensoniq->reg_lock);
2118         ensoniq->uartm |= ES_MODE_INPUT;
2119         ensoniq->midi_input = substream;
2120         if (!(ensoniq->uartm & ES_MODE_OUTPUT)) {
2121                 outb(ES_CNTRL(3), ES_REG(ensoniq, UART_CONTROL));
2122                 outb(ensoniq->uartc = 0, ES_REG(ensoniq, UART_CONTROL));
2123                 outl(ensoniq->ctrl |= ES_UART_EN, ES_REG(ensoniq, CONTROL));
2124         }
2125         spin_unlock_irq(&ensoniq->reg_lock);
2126         return 0;
2127 }
2128
2129 static int snd_ensoniq_midi_input_close(snd_rawmidi_substream_t * substream)
2130 {
2131         ensoniq_t *ensoniq = substream->rmidi->private_data;
2132
2133         spin_lock_irq(&ensoniq->reg_lock);
2134         if (!(ensoniq->uartm & ES_MODE_OUTPUT)) {
2135                 outb(ensoniq->uartc = 0, ES_REG(ensoniq, UART_CONTROL));
2136                 outl(ensoniq->ctrl &= ~ES_UART_EN, ES_REG(ensoniq, CONTROL));
2137         } else {
2138                 outb(ensoniq->uartc &= ~ES_RXINTEN, ES_REG(ensoniq, UART_CONTROL));
2139         }
2140         ensoniq->midi_input = NULL;
2141         ensoniq->uartm &= ~ES_MODE_INPUT;
2142         spin_unlock_irq(&ensoniq->reg_lock);
2143         return 0;
2144 }
2145
2146 static int snd_ensoniq_midi_output_open(snd_rawmidi_substream_t * substream)
2147 {
2148         ensoniq_t *ensoniq = substream->rmidi->private_data;
2149
2150         spin_lock_irq(&ensoniq->reg_lock);
2151         ensoniq->uartm |= ES_MODE_OUTPUT;
2152         ensoniq->midi_output = substream;
2153         if (!(ensoniq->uartm & ES_MODE_INPUT)) {
2154                 outb(ES_CNTRL(3), ES_REG(ensoniq, UART_CONTROL));
2155                 outb(ensoniq->uartc = 0, ES_REG(ensoniq, UART_CONTROL));
2156                 outl(ensoniq->ctrl |= ES_UART_EN, ES_REG(ensoniq, CONTROL));
2157         }
2158         spin_unlock_irq(&ensoniq->reg_lock);
2159         return 0;
2160 }
2161
2162 static int snd_ensoniq_midi_output_close(snd_rawmidi_substream_t * substream)
2163 {
2164         ensoniq_t *ensoniq = substream->rmidi->private_data;
2165
2166         spin_lock_irq(&ensoniq->reg_lock);
2167         if (!(ensoniq->uartm & ES_MODE_INPUT)) {
2168                 outb(ensoniq->uartc = 0, ES_REG(ensoniq, UART_CONTROL));
2169                 outl(ensoniq->ctrl &= ~ES_UART_EN, ES_REG(ensoniq, CONTROL));
2170         } else {
2171                 outb(ensoniq->uartc &= ~ES_TXINTENM, ES_REG(ensoniq, UART_CONTROL));
2172         }
2173         ensoniq->midi_output = NULL;
2174         ensoniq->uartm &= ~ES_MODE_OUTPUT;
2175         spin_unlock_irq(&ensoniq->reg_lock);
2176         return 0;
2177 }
2178
2179 static void snd_ensoniq_midi_input_trigger(snd_rawmidi_substream_t * substream, int up)
2180 {
2181         unsigned long flags;
2182         ensoniq_t *ensoniq = substream->rmidi->private_data;
2183         int idx;
2184
2185         spin_lock_irqsave(&ensoniq->reg_lock, flags);
2186         if (up) {
2187                 if ((ensoniq->uartc & ES_RXINTEN) == 0) {
2188                         /* empty input FIFO */
2189                         for (idx = 0; idx < 32; idx++)
2190                                 inb(ES_REG(ensoniq, UART_DATA));
2191                         ensoniq->uartc |= ES_RXINTEN;
2192                         outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL));
2193                 }
2194         } else {
2195                 if (ensoniq->uartc & ES_RXINTEN) {
2196                         ensoniq->uartc &= ~ES_RXINTEN;
2197                         outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL));
2198                 }
2199         }
2200         spin_unlock_irqrestore(&ensoniq->reg_lock, flags);
2201 }
2202
2203 static void snd_ensoniq_midi_output_trigger(snd_rawmidi_substream_t * substream, int up)
2204 {
2205         unsigned long flags;
2206         ensoniq_t *ensoniq = substream->rmidi->private_data;
2207         unsigned char byte;
2208
2209         spin_lock_irqsave(&ensoniq->reg_lock, flags);
2210         if (up) {
2211                 if (ES_TXINTENI(ensoniq->uartc) == 0) {
2212                         ensoniq->uartc |= ES_TXINTENO(1);
2213                         /* fill UART FIFO buffer at first, and turn Tx interrupts only if necessary */
2214                         while (ES_TXINTENI(ensoniq->uartc) == 1 &&
2215                                (inb(ES_REG(ensoniq, UART_STATUS)) & ES_TXRDY)) {
2216                                 if (snd_rawmidi_transmit(substream, &byte, 1) != 1) {
2217                                         ensoniq->uartc &= ~ES_TXINTENM;
2218                                 } else {
2219                                         outb(byte, ES_REG(ensoniq, UART_DATA));
2220                                 }
2221                         }
2222                         outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL));
2223                 }
2224         } else {
2225                 if (ES_TXINTENI(ensoniq->uartc) == 1) {
2226                         ensoniq->uartc &= ~ES_TXINTENM;
2227                         outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL));
2228                 }
2229         }
2230         spin_unlock_irqrestore(&ensoniq->reg_lock, flags);
2231 }
2232
2233 static snd_rawmidi_ops_t snd_ensoniq_midi_output =
2234 {
2235         .open =         snd_ensoniq_midi_output_open,
2236         .close =        snd_ensoniq_midi_output_close,
2237         .trigger =      snd_ensoniq_midi_output_trigger,
2238 };
2239
2240 static snd_rawmidi_ops_t snd_ensoniq_midi_input =
2241 {
2242         .open =         snd_ensoniq_midi_input_open,
2243         .close =        snd_ensoniq_midi_input_close,
2244         .trigger =      snd_ensoniq_midi_input_trigger,
2245 };
2246
2247 static int __devinit snd_ensoniq_midi(ensoniq_t * ensoniq, int device, snd_rawmidi_t **rrawmidi)
2248 {
2249         snd_rawmidi_t *rmidi;
2250         int err;
2251
2252         if (rrawmidi)
2253                 *rrawmidi = NULL;
2254         if ((err = snd_rawmidi_new(ensoniq->card, "ES1370/1", device, 1, 1, &rmidi)) < 0)
2255                 return err;
2256 #ifdef CHIP1370
2257         strcpy(rmidi->name, "ES1370");
2258 #else
2259         strcpy(rmidi->name, "ES1371");
2260 #endif
2261         snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_OUTPUT, &snd_ensoniq_midi_output);
2262         snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_INPUT, &snd_ensoniq_midi_input);
2263         rmidi->info_flags |= SNDRV_RAWMIDI_INFO_OUTPUT | SNDRV_RAWMIDI_INFO_INPUT | SNDRV_RAWMIDI_INFO_DUPLEX;
2264         rmidi->private_data = ensoniq;
2265         ensoniq->rmidi = rmidi;
2266         if (rrawmidi)
2267                 *rrawmidi = rmidi;
2268         return 0;
2269 }
2270
2271 /*
2272  *  Interrupt handler
2273  */
2274
2275 static irqreturn_t snd_audiopci_interrupt(int irq, void *dev_id, struct pt_regs *regs)
2276 {
2277         ensoniq_t *ensoniq = dev_id;
2278         unsigned int status, sctrl;
2279
2280         if (ensoniq == NULL)
2281                 return IRQ_NONE;
2282
2283         status = inl(ES_REG(ensoniq, STATUS));
2284         if (!(status & ES_INTR))
2285                 return IRQ_NONE;
2286
2287         spin_lock(&ensoniq->reg_lock);
2288         sctrl = ensoniq->sctrl;
2289         if (status & ES_DAC1)
2290                 sctrl &= ~ES_P1_INT_EN;
2291         if (status & ES_DAC2)
2292                 sctrl &= ~ES_P2_INT_EN;
2293         if (status & ES_ADC)
2294                 sctrl &= ~ES_R1_INT_EN;
2295         outl(sctrl, ES_REG(ensoniq, SERIAL));
2296         outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
2297         spin_unlock(&ensoniq->reg_lock);
2298
2299         if (status & ES_UART)
2300                 snd_ensoniq_midi_interrupt(ensoniq);
2301         if ((status & ES_DAC2) && ensoniq->playback2_substream)
2302                 snd_pcm_period_elapsed(ensoniq->playback2_substream);
2303         if ((status & ES_ADC) && ensoniq->capture_substream)
2304                 snd_pcm_period_elapsed(ensoniq->capture_substream);
2305         if ((status & ES_DAC1) && ensoniq->playback1_substream)
2306                 snd_pcm_period_elapsed(ensoniq->playback1_substream);
2307         return IRQ_HANDLED;
2308 }
2309
2310 static int __devinit snd_audiopci_probe(struct pci_dev *pci,
2311                                         const struct pci_device_id *pci_id)
2312 {
2313         static int dev;
2314         snd_card_t *card;
2315         ensoniq_t *ensoniq;
2316         int err, pcm_devs[2];
2317
2318         if (dev >= SNDRV_CARDS)
2319                 return -ENODEV;
2320         if (!enable[dev]) {
2321                 dev++;
2322                 return -ENOENT;
2323         }
2324
2325         card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0);
2326         if (card == NULL)
2327                 return -ENOMEM;
2328
2329         if ((err = snd_ensoniq_create(card, pci, &ensoniq)) < 0) {
2330                 snd_card_free(card);
2331                 return err;
2332         }
2333
2334         pcm_devs[0] = 0; pcm_devs[1] = 1;
2335 #ifdef CHIP1370
2336         if ((err = snd_ensoniq_1370_mixer(ensoniq)) < 0) {
2337                 snd_card_free(card);
2338                 return err;
2339         }
2340 #endif
2341 #ifdef CHIP1371
2342         if ((err = snd_ensoniq_1371_mixer(ensoniq)) < 0) {
2343                 snd_card_free(card);
2344                 return err;
2345         }
2346 #endif
2347         if ((err = snd_ensoniq_pcm(ensoniq, 0, NULL)) < 0) {
2348                 snd_card_free(card);
2349                 return err;
2350         }
2351         if ((err = snd_ensoniq_pcm2(ensoniq, 1, NULL)) < 0) {
2352                 snd_card_free(card);
2353                 return err;
2354         }
2355         if ((err = snd_ensoniq_midi(ensoniq, 0, NULL)) < 0) {
2356                 snd_card_free(card);
2357                 return err;
2358         }
2359
2360         snd_ensoniq_create_gameport(ensoniq, dev);
2361
2362         strcpy(card->driver, DRIVER_NAME);
2363
2364         strcpy(card->shortname, "Ensoniq AudioPCI");
2365         sprintf(card->longname, "%s %s at 0x%lx, irq %i",
2366                 card->shortname,
2367                 card->driver,
2368                 ensoniq->port,
2369                 ensoniq->irq);
2370
2371         if ((err = snd_card_register(card)) < 0) {
2372                 snd_card_free(card);
2373                 return err;
2374         }
2375
2376         pci_set_drvdata(pci, card);
2377         dev++;
2378         return 0;
2379 }
2380
2381 static void __devexit snd_audiopci_remove(struct pci_dev *pci)
2382 {
2383         snd_card_free(pci_get_drvdata(pci));
2384         pci_set_drvdata(pci, NULL);
2385 }
2386
2387 static struct pci_driver driver = {
2388         .name = DRIVER_NAME,
2389         .id_table = snd_audiopci_ids,
2390         .probe = snd_audiopci_probe,
2391         .remove = __devexit_p(snd_audiopci_remove),
2392 };
2393
2394 static int __init alsa_card_ens137x_init(void)
2395 {
2396         return pci_register_driver(&driver);
2397 }
2398
2399 static void __exit alsa_card_ens137x_exit(void)
2400 {
2401         pci_unregister_driver(&driver);
2402 }
2403
2404 module_init(alsa_card_ens137x_init)
2405 module_exit(alsa_card_ens137x_exit)