2 * Copyright (C) 2008, Creative Technology Ltd. All Rights Reserved.
4 * This source file is released under GPL v2 license (no other versions).
5 * See the COPYING file included in the main directory of this source
6 * distribution for the license terms and conditions.
11 * This file contains the implementation of hardware access methord for 20k2.
19 #include "ct20k2reg.h"
20 #include <linux/types.h>
21 #include <linux/slab.h>
22 #include <linux/pci.h>
24 #include <linux/string.h>
25 #include <linux/kernel.h>
26 #include <linux/interrupt.h>
27 #include <linux/delay.h>
29 #if BITS_PER_LONG == 32
30 #define CT_XFI_DMA_MASK DMA_BIT_MASK(32) /* 32 bit PTE */
32 #define CT_XFI_DMA_MASK DMA_BIT_MASK(64) /* 64 bit PTE */
35 static u32 hw_read_20kx(struct hw *hw, u32 reg);
36 static void hw_write_20kx(struct hw *hw, u32 reg, u32 data);
39 * Type definition block.
40 * The layout of control structures can be directly applied on 20k2 chip.
44 * SRC control block definitions.
47 /* SRC resource control block */
48 #define SRCCTL_STATE 0x00000007
49 #define SRCCTL_BM 0x00000008
50 #define SRCCTL_RSR 0x00000030
51 #define SRCCTL_SF 0x000001C0
52 #define SRCCTL_WR 0x00000200
53 #define SRCCTL_PM 0x00000400
54 #define SRCCTL_ROM 0x00001800
55 #define SRCCTL_VO 0x00002000
56 #define SRCCTL_ST 0x00004000
57 #define SRCCTL_IE 0x00008000
58 #define SRCCTL_ILSZ 0x000F0000
59 #define SRCCTL_BP 0x00100000
61 #define SRCCCR_CISZ 0x000007FF
62 #define SRCCCR_CWA 0x001FF800
63 #define SRCCCR_D 0x00200000
64 #define SRCCCR_RS 0x01C00000
65 #define SRCCCR_NAL 0x3E000000
66 #define SRCCCR_RA 0xC0000000
68 #define SRCCA_CA 0x0FFFFFFF
69 #define SRCCA_RS 0xE0000000
71 #define SRCSA_SA 0x0FFFFFFF
73 #define SRCLA_LA 0x0FFFFFFF
75 /* Mixer Parameter Ring ram Low and Hight register.
76 * Fixed-point value in 8.24 format for parameter channel */
77 #define MPRLH_PITCH 0xFFFFFFFF
79 /* SRC resource register dirty flags */
88 u16 czbfs:1; /* Clear Z-Buffers */
94 struct src_rsc_ctrl_blk {
101 union src_dirty dirty;
104 /* SRC manager control block */
105 union src_mgr_dirty {
121 struct src_mgr_ctrl_blk {
124 union src_mgr_dirty dirty;
127 /* SRCIMP manager control block */
128 #define SRCAIM_ARC 0x00000FFF
129 #define SRCAIM_NXT 0x00FF0000
130 #define SRCAIM_SRC 0xFF000000
137 /* SRCIMP manager register dirty flags */
138 union srcimp_mgr_dirty {
146 struct srcimp_mgr_ctrl_blk {
147 struct srcimap srcimap;
148 union srcimp_mgr_dirty dirty;
152 * Function implementation block.
155 static int src_get_rsc_ctrl_blk(void **rblk)
157 struct src_rsc_ctrl_blk *blk;
160 blk = kzalloc(sizeof(*blk), GFP_KERNEL);
169 static int src_put_rsc_ctrl_blk(void *blk)
171 kfree((struct src_rsc_ctrl_blk *)blk);
176 static int src_set_state(void *blk, unsigned int state)
178 struct src_rsc_ctrl_blk *ctl = blk;
180 set_field(&ctl->ctl, SRCCTL_STATE, state);
181 ctl->dirty.bf.ctl = 1;
185 static int src_set_bm(void *blk, unsigned int bm)
187 struct src_rsc_ctrl_blk *ctl = blk;
189 set_field(&ctl->ctl, SRCCTL_BM, bm);
190 ctl->dirty.bf.ctl = 1;
194 static int src_set_rsr(void *blk, unsigned int rsr)
196 struct src_rsc_ctrl_blk *ctl = blk;
198 set_field(&ctl->ctl, SRCCTL_RSR, rsr);
199 ctl->dirty.bf.ctl = 1;
203 static int src_set_sf(void *blk, unsigned int sf)
205 struct src_rsc_ctrl_blk *ctl = blk;
207 set_field(&ctl->ctl, SRCCTL_SF, sf);
208 ctl->dirty.bf.ctl = 1;
212 static int src_set_wr(void *blk, unsigned int wr)
214 struct src_rsc_ctrl_blk *ctl = blk;
216 set_field(&ctl->ctl, SRCCTL_WR, wr);
217 ctl->dirty.bf.ctl = 1;
221 static int src_set_pm(void *blk, unsigned int pm)
223 struct src_rsc_ctrl_blk *ctl = blk;
225 set_field(&ctl->ctl, SRCCTL_PM, pm);
226 ctl->dirty.bf.ctl = 1;
230 static int src_set_rom(void *blk, unsigned int rom)
232 struct src_rsc_ctrl_blk *ctl = blk;
234 set_field(&ctl->ctl, SRCCTL_ROM, rom);
235 ctl->dirty.bf.ctl = 1;
239 static int src_set_vo(void *blk, unsigned int vo)
241 struct src_rsc_ctrl_blk *ctl = blk;
243 set_field(&ctl->ctl, SRCCTL_VO, vo);
244 ctl->dirty.bf.ctl = 1;
248 static int src_set_st(void *blk, unsigned int st)
250 struct src_rsc_ctrl_blk *ctl = blk;
252 set_field(&ctl->ctl, SRCCTL_ST, st);
253 ctl->dirty.bf.ctl = 1;
257 static int src_set_ie(void *blk, unsigned int ie)
259 struct src_rsc_ctrl_blk *ctl = blk;
261 set_field(&ctl->ctl, SRCCTL_IE, ie);
262 ctl->dirty.bf.ctl = 1;
266 static int src_set_ilsz(void *blk, unsigned int ilsz)
268 struct src_rsc_ctrl_blk *ctl = blk;
270 set_field(&ctl->ctl, SRCCTL_ILSZ, ilsz);
271 ctl->dirty.bf.ctl = 1;
275 static int src_set_bp(void *blk, unsigned int bp)
277 struct src_rsc_ctrl_blk *ctl = blk;
279 set_field(&ctl->ctl, SRCCTL_BP, bp);
280 ctl->dirty.bf.ctl = 1;
284 static int src_set_cisz(void *blk, unsigned int cisz)
286 struct src_rsc_ctrl_blk *ctl = blk;
288 set_field(&ctl->ccr, SRCCCR_CISZ, cisz);
289 ctl->dirty.bf.ccr = 1;
293 static int src_set_ca(void *blk, unsigned int ca)
295 struct src_rsc_ctrl_blk *ctl = blk;
297 set_field(&ctl->ca, SRCCA_CA, ca);
298 ctl->dirty.bf.ca = 1;
302 static int src_set_sa(void *blk, unsigned int sa)
304 struct src_rsc_ctrl_blk *ctl = blk;
306 set_field(&ctl->sa, SRCSA_SA, sa);
307 ctl->dirty.bf.sa = 1;
311 static int src_set_la(void *blk, unsigned int la)
313 struct src_rsc_ctrl_blk *ctl = blk;
315 set_field(&ctl->la, SRCLA_LA, la);
316 ctl->dirty.bf.la = 1;
320 static int src_set_pitch(void *blk, unsigned int pitch)
322 struct src_rsc_ctrl_blk *ctl = blk;
324 set_field(&ctl->mpr, MPRLH_PITCH, pitch);
325 ctl->dirty.bf.mpr = 1;
329 static int src_set_clear_zbufs(void *blk, unsigned int clear)
331 ((struct src_rsc_ctrl_blk *)blk)->dirty.bf.czbfs = (clear ? 1 : 0);
335 static int src_set_dirty(void *blk, unsigned int flags)
337 ((struct src_rsc_ctrl_blk *)blk)->dirty.data = (flags & 0xffff);
341 static int src_set_dirty_all(void *blk)
343 ((struct src_rsc_ctrl_blk *)blk)->dirty.data = ~(0x0);
347 #define AR_SLOT_SIZE 4096
348 #define AR_SLOT_BLOCK_SIZE 16
349 #define AR_PTS_PITCH 6
350 #define AR_PARAM_SRC_OFFSET 0x60
352 static unsigned int src_param_pitch_mixer(unsigned int src_idx)
354 return ((src_idx << 4) + AR_PTS_PITCH + AR_SLOT_SIZE
355 - AR_PARAM_SRC_OFFSET) % AR_SLOT_SIZE;
359 static int src_commit_write(struct hw *hw, unsigned int idx, void *blk)
361 struct src_rsc_ctrl_blk *ctl = blk;
364 if (ctl->dirty.bf.czbfs) {
365 /* Clear Z-Buffer registers */
366 for (i = 0; i < 8; i++)
367 hw_write_20kx(hw, SRC_UPZ+idx*0x100+i*0x4, 0);
369 for (i = 0; i < 4; i++)
370 hw_write_20kx(hw, SRC_DN0Z+idx*0x100+i*0x4, 0);
372 for (i = 0; i < 8; i++)
373 hw_write_20kx(hw, SRC_DN1Z+idx*0x100+i*0x4, 0);
375 ctl->dirty.bf.czbfs = 0;
377 if (ctl->dirty.bf.mpr) {
378 /* Take the parameter mixer resource in the same group as that
379 * the idx src is in for simplicity. Unlike src, all conjugate
380 * parameter mixer resources must be programmed for
381 * corresponding conjugate src resources. */
382 unsigned int pm_idx = src_param_pitch_mixer(idx);
383 hw_write_20kx(hw, MIXER_PRING_LO_HI+4*pm_idx, ctl->mpr);
384 hw_write_20kx(hw, MIXER_PMOPLO+8*pm_idx, 0x3);
385 hw_write_20kx(hw, MIXER_PMOPHI+8*pm_idx, 0x0);
386 ctl->dirty.bf.mpr = 0;
388 if (ctl->dirty.bf.sa) {
389 hw_write_20kx(hw, SRC_SA+idx*0x100, ctl->sa);
390 ctl->dirty.bf.sa = 0;
392 if (ctl->dirty.bf.la) {
393 hw_write_20kx(hw, SRC_LA+idx*0x100, ctl->la);
394 ctl->dirty.bf.la = 0;
396 if (ctl->dirty.bf.ca) {
397 hw_write_20kx(hw, SRC_CA+idx*0x100, ctl->ca);
398 ctl->dirty.bf.ca = 0;
401 /* Write srccf register */
402 hw_write_20kx(hw, SRC_CF+idx*0x100, 0x0);
404 if (ctl->dirty.bf.ccr) {
405 hw_write_20kx(hw, SRC_CCR+idx*0x100, ctl->ccr);
406 ctl->dirty.bf.ccr = 0;
408 if (ctl->dirty.bf.ctl) {
409 hw_write_20kx(hw, SRC_CTL+idx*0x100, ctl->ctl);
410 ctl->dirty.bf.ctl = 0;
416 static int src_get_ca(struct hw *hw, unsigned int idx, void *blk)
418 struct src_rsc_ctrl_blk *ctl = blk;
420 ctl->ca = hw_read_20kx(hw, SRC_CA+idx*0x100);
421 ctl->dirty.bf.ca = 0;
423 return get_field(ctl->ca, SRCCA_CA);
426 static unsigned int src_get_dirty(void *blk)
428 return ((struct src_rsc_ctrl_blk *)blk)->dirty.data;
431 static unsigned int src_dirty_conj_mask(void)
436 static int src_mgr_enbs_src(void *blk, unsigned int idx)
438 ((struct src_mgr_ctrl_blk *)blk)->enbsa |= (0x1 << ((idx%128)/4));
439 ((struct src_mgr_ctrl_blk *)blk)->dirty.bf.enbsa = 1;
440 ((struct src_mgr_ctrl_blk *)blk)->enb[idx/32] |= (0x1 << (idx%32));
444 static int src_mgr_enb_src(void *blk, unsigned int idx)
446 ((struct src_mgr_ctrl_blk *)blk)->enb[idx/32] |= (0x1 << (idx%32));
447 ((struct src_mgr_ctrl_blk *)blk)->dirty.data |= (0x1 << (idx/32));
451 static int src_mgr_dsb_src(void *blk, unsigned int idx)
453 ((struct src_mgr_ctrl_blk *)blk)->enb[idx/32] &= ~(0x1 << (idx%32));
454 ((struct src_mgr_ctrl_blk *)blk)->dirty.data |= (0x1 << (idx/32));
458 static int src_mgr_commit_write(struct hw *hw, void *blk)
460 struct src_mgr_ctrl_blk *ctl = blk;
462 unsigned int ret = 0;
464 if (ctl->dirty.bf.enbsa) {
466 ret = hw_read_20kx(hw, SRC_ENBSTAT);
468 hw_write_20kx(hw, SRC_ENBSA, ctl->enbsa);
469 ctl->dirty.bf.enbsa = 0;
471 for (i = 0; i < 8; i++) {
472 if ((ctl->dirty.data & (0x1 << i))) {
473 hw_write_20kx(hw, SRC_ENB+(i*0x100), ctl->enb[i]);
474 ctl->dirty.data &= ~(0x1 << i);
481 static int src_mgr_get_ctrl_blk(void **rblk)
483 struct src_mgr_ctrl_blk *blk;
486 blk = kzalloc(sizeof(*blk), GFP_KERNEL);
495 static int src_mgr_put_ctrl_blk(void *blk)
497 kfree((struct src_mgr_ctrl_blk *)blk);
502 static int srcimp_mgr_get_ctrl_blk(void **rblk)
504 struct srcimp_mgr_ctrl_blk *blk;
507 blk = kzalloc(sizeof(*blk), GFP_KERNEL);
516 static int srcimp_mgr_put_ctrl_blk(void *blk)
518 kfree((struct srcimp_mgr_ctrl_blk *)blk);
523 static int srcimp_mgr_set_imaparc(void *blk, unsigned int slot)
525 struct srcimp_mgr_ctrl_blk *ctl = blk;
527 set_field(&ctl->srcimap.srcaim, SRCAIM_ARC, slot);
528 ctl->dirty.bf.srcimap = 1;
532 static int srcimp_mgr_set_imapuser(void *blk, unsigned int user)
534 struct srcimp_mgr_ctrl_blk *ctl = blk;
536 set_field(&ctl->srcimap.srcaim, SRCAIM_SRC, user);
537 ctl->dirty.bf.srcimap = 1;
541 static int srcimp_mgr_set_imapnxt(void *blk, unsigned int next)
543 struct srcimp_mgr_ctrl_blk *ctl = blk;
545 set_field(&ctl->srcimap.srcaim, SRCAIM_NXT, next);
546 ctl->dirty.bf.srcimap = 1;
550 static int srcimp_mgr_set_imapaddr(void *blk, unsigned int addr)
552 ((struct srcimp_mgr_ctrl_blk *)blk)->srcimap.idx = addr;
553 ((struct srcimp_mgr_ctrl_blk *)blk)->dirty.bf.srcimap = 1;
557 static int srcimp_mgr_commit_write(struct hw *hw, void *blk)
559 struct srcimp_mgr_ctrl_blk *ctl = blk;
561 if (ctl->dirty.bf.srcimap) {
562 hw_write_20kx(hw, SRC_IMAP+ctl->srcimap.idx*0x100,
563 ctl->srcimap.srcaim);
564 ctl->dirty.bf.srcimap = 0;
571 * AMIXER control block definitions.
574 #define AMOPLO_M 0x00000003
575 #define AMOPLO_IV 0x00000004
576 #define AMOPLO_X 0x0003FFF0
577 #define AMOPLO_Y 0xFFFC0000
579 #define AMOPHI_SADR 0x000000FF
580 #define AMOPHI_SE 0x80000000
582 /* AMIXER resource register dirty flags */
592 /* AMIXER resource control block */
593 struct amixer_rsc_ctrl_blk {
596 union amixer_dirty dirty;
599 static int amixer_set_mode(void *blk, unsigned int mode)
601 struct amixer_rsc_ctrl_blk *ctl = blk;
603 set_field(&ctl->amoplo, AMOPLO_M, mode);
604 ctl->dirty.bf.amoplo = 1;
608 static int amixer_set_iv(void *blk, unsigned int iv)
610 struct amixer_rsc_ctrl_blk *ctl = blk;
612 set_field(&ctl->amoplo, AMOPLO_IV, iv);
613 ctl->dirty.bf.amoplo = 1;
617 static int amixer_set_x(void *blk, unsigned int x)
619 struct amixer_rsc_ctrl_blk *ctl = blk;
621 set_field(&ctl->amoplo, AMOPLO_X, x);
622 ctl->dirty.bf.amoplo = 1;
626 static int amixer_set_y(void *blk, unsigned int y)
628 struct amixer_rsc_ctrl_blk *ctl = blk;
630 set_field(&ctl->amoplo, AMOPLO_Y, y);
631 ctl->dirty.bf.amoplo = 1;
635 static int amixer_set_sadr(void *blk, unsigned int sadr)
637 struct amixer_rsc_ctrl_blk *ctl = blk;
639 set_field(&ctl->amophi, AMOPHI_SADR, sadr);
640 ctl->dirty.bf.amophi = 1;
644 static int amixer_set_se(void *blk, unsigned int se)
646 struct amixer_rsc_ctrl_blk *ctl = blk;
648 set_field(&ctl->amophi, AMOPHI_SE, se);
649 ctl->dirty.bf.amophi = 1;
653 static int amixer_set_dirty(void *blk, unsigned int flags)
655 ((struct amixer_rsc_ctrl_blk *)blk)->dirty.data = (flags & 0xffff);
659 static int amixer_set_dirty_all(void *blk)
661 ((struct amixer_rsc_ctrl_blk *)blk)->dirty.data = ~(0x0);
665 static int amixer_commit_write(struct hw *hw, unsigned int idx, void *blk)
667 struct amixer_rsc_ctrl_blk *ctl = blk;
669 if (ctl->dirty.bf.amoplo || ctl->dirty.bf.amophi) {
670 hw_write_20kx(hw, MIXER_AMOPLO+idx*8, ctl->amoplo);
671 ctl->dirty.bf.amoplo = 0;
672 hw_write_20kx(hw, MIXER_AMOPHI+idx*8, ctl->amophi);
673 ctl->dirty.bf.amophi = 0;
679 static int amixer_get_y(void *blk)
681 struct amixer_rsc_ctrl_blk *ctl = blk;
683 return get_field(ctl->amoplo, AMOPLO_Y);
686 static unsigned int amixer_get_dirty(void *blk)
688 return ((struct amixer_rsc_ctrl_blk *)blk)->dirty.data;
691 static int amixer_rsc_get_ctrl_blk(void **rblk)
693 struct amixer_rsc_ctrl_blk *blk;
696 blk = kzalloc(sizeof(*blk), GFP_KERNEL);
705 static int amixer_rsc_put_ctrl_blk(void *blk)
707 kfree((struct amixer_rsc_ctrl_blk *)blk);
712 static int amixer_mgr_get_ctrl_blk(void **rblk)
719 static int amixer_mgr_put_ctrl_blk(void *blk)
725 * DAIO control block definitions.
728 /* Receiver Sample Rate Tracker Control register */
729 #define SRTCTL_SRCO 0x000000FF
730 #define SRTCTL_SRCM 0x0000FF00
731 #define SRTCTL_RSR 0x00030000
732 #define SRTCTL_DRAT 0x00300000
733 #define SRTCTL_EC 0x01000000
734 #define SRTCTL_ET 0x10000000
736 /* DAIO Receiver register dirty flags */
745 /* DAIO Receiver control block */
746 struct dai_ctrl_blk {
748 union dai_dirty dirty;
751 /* Audio Input Mapper RAM */
752 #define AIM_ARC 0x00000FFF
753 #define AIM_NXT 0x007F0000
760 /* Audio Transmitter Control and Status register */
761 #define ATXCTL_EN 0x00000001
762 #define ATXCTL_MODE 0x00000010
763 #define ATXCTL_CD 0x00000020
764 #define ATXCTL_RAW 0x00000100
765 #define ATXCTL_MT 0x00000200
766 #define ATXCTL_NUC 0x00003000
767 #define ATXCTL_BEN 0x00010000
768 #define ATXCTL_BMUX 0x00700000
769 #define ATXCTL_B24 0x01000000
770 #define ATXCTL_CPF 0x02000000
771 #define ATXCTL_RIV 0x10000000
772 #define ATXCTL_LIV 0x20000000
773 #define ATXCTL_RSAT 0x40000000
774 #define ATXCTL_LSAT 0x80000000
776 /* XDIF Transmitter register dirty flags */
785 /* XDIF Transmitter control block */
786 struct dao_ctrl_blk {
787 /* XDIF Transmitter Channel Status Low Register */
789 union dao_dirty dirty;
792 /* Audio Receiver Control register */
793 #define ARXCTL_EN 0x00000001
795 /* DAIO manager register dirty flags */
796 union daio_mgr_dirty {
806 /* DAIO manager control block */
807 struct daio_mgr_ctrl_blk {
808 struct daoimap daoimap;
809 unsigned int txctl[8];
810 unsigned int rxctl[8];
811 union daio_mgr_dirty dirty;
814 static int dai_srt_set_srco(void *blk, unsigned int src)
816 struct dai_ctrl_blk *ctl = blk;
818 set_field(&ctl->srt, SRTCTL_SRCO, src);
819 ctl->dirty.bf.srt = 1;
823 static int dai_srt_set_srcm(void *blk, unsigned int src)
825 struct dai_ctrl_blk *ctl = blk;
827 set_field(&ctl->srt, SRTCTL_SRCM, src);
828 ctl->dirty.bf.srt = 1;
832 static int dai_srt_set_rsr(void *blk, unsigned int rsr)
834 struct dai_ctrl_blk *ctl = blk;
836 set_field(&ctl->srt, SRTCTL_RSR, rsr);
837 ctl->dirty.bf.srt = 1;
841 static int dai_srt_set_drat(void *blk, unsigned int drat)
843 struct dai_ctrl_blk *ctl = blk;
845 set_field(&ctl->srt, SRTCTL_DRAT, drat);
846 ctl->dirty.bf.srt = 1;
850 static int dai_srt_set_ec(void *blk, unsigned int ec)
852 struct dai_ctrl_blk *ctl = blk;
854 set_field(&ctl->srt, SRTCTL_EC, ec ? 1 : 0);
855 ctl->dirty.bf.srt = 1;
859 static int dai_srt_set_et(void *blk, unsigned int et)
861 struct dai_ctrl_blk *ctl = blk;
863 set_field(&ctl->srt, SRTCTL_ET, et ? 1 : 0);
864 ctl->dirty.bf.srt = 1;
868 static int dai_commit_write(struct hw *hw, unsigned int idx, void *blk)
870 struct dai_ctrl_blk *ctl = blk;
872 if (ctl->dirty.bf.srt) {
873 hw_write_20kx(hw, AUDIO_IO_RX_SRT_CTL+0x40*idx, ctl->srt);
874 ctl->dirty.bf.srt = 0;
880 static int dai_get_ctrl_blk(void **rblk)
882 struct dai_ctrl_blk *blk;
885 blk = kzalloc(sizeof(*blk), GFP_KERNEL);
894 static int dai_put_ctrl_blk(void *blk)
896 kfree((struct dai_ctrl_blk *)blk);
901 static int dao_set_spos(void *blk, unsigned int spos)
903 ((struct dao_ctrl_blk *)blk)->atxcsl = spos;
904 ((struct dao_ctrl_blk *)blk)->dirty.bf.atxcsl = 1;
908 static int dao_commit_write(struct hw *hw, unsigned int idx, void *blk)
910 struct dao_ctrl_blk *ctl = blk;
912 if (ctl->dirty.bf.atxcsl) {
915 hw_write_20kx(hw, AUDIO_IO_TX_CSTAT_L+0x40*idx,
918 ctl->dirty.bf.atxcsl = 0;
924 static int dao_get_spos(void *blk, unsigned int *spos)
926 *spos = ((struct dao_ctrl_blk *)blk)->atxcsl;
930 static int dao_get_ctrl_blk(void **rblk)
932 struct dao_ctrl_blk *blk;
935 blk = kzalloc(sizeof(*blk), GFP_KERNEL);
944 static int dao_put_ctrl_blk(void *blk)
946 kfree((struct dao_ctrl_blk *)blk);
951 static int daio_mgr_enb_dai(void *blk, unsigned int idx)
953 struct daio_mgr_ctrl_blk *ctl = blk;
955 set_field(&ctl->rxctl[idx], ARXCTL_EN, 1);
956 ctl->dirty.bf.arxctl |= (0x1 << idx);
960 static int daio_mgr_dsb_dai(void *blk, unsigned int idx)
962 struct daio_mgr_ctrl_blk *ctl = blk;
964 set_field(&ctl->rxctl[idx], ARXCTL_EN, 0);
966 ctl->dirty.bf.arxctl |= (0x1 << idx);
970 static int daio_mgr_enb_dao(void *blk, unsigned int idx)
972 struct daio_mgr_ctrl_blk *ctl = blk;
974 set_field(&ctl->txctl[idx], ATXCTL_EN, 1);
975 ctl->dirty.bf.atxctl |= (0x1 << idx);
979 static int daio_mgr_dsb_dao(void *blk, unsigned int idx)
981 struct daio_mgr_ctrl_blk *ctl = blk;
983 set_field(&ctl->txctl[idx], ATXCTL_EN, 0);
984 ctl->dirty.bf.atxctl |= (0x1 << idx);
988 static int daio_mgr_dao_init(void *blk, unsigned int idx, unsigned int conf)
990 struct daio_mgr_ctrl_blk *ctl = blk;
994 switch ((conf & 0x7)) {
996 set_field(&ctl->txctl[idx], ATXCTL_NUC, 0);
999 set_field(&ctl->txctl[idx], ATXCTL_NUC, 1);
1002 set_field(&ctl->txctl[idx], ATXCTL_NUC, 2);
1005 set_field(&ctl->txctl[idx], ATXCTL_NUC, 3);
1011 set_field(&ctl->txctl[idx], ATXCTL_CD, (!(conf & 0x7)));
1013 set_field(&ctl->txctl[idx], ATXCTL_LIV, (conf >> 4) & 0x1);
1015 set_field(&ctl->txctl[idx], ATXCTL_RIV, (conf >> 4) & 0x1);
1016 set_field(&ctl->txctl[idx], ATXCTL_RAW,
1017 ((conf >> 3) & 0x1) ? 0 : 0);
1018 ctl->dirty.bf.atxctl |= (0x1 << idx);
1026 static int daio_mgr_set_imaparc(void *blk, unsigned int slot)
1028 struct daio_mgr_ctrl_blk *ctl = blk;
1030 set_field(&ctl->daoimap.aim, AIM_ARC, slot);
1031 ctl->dirty.bf.daoimap = 1;
1035 static int daio_mgr_set_imapnxt(void *blk, unsigned int next)
1037 struct daio_mgr_ctrl_blk *ctl = blk;
1039 set_field(&ctl->daoimap.aim, AIM_NXT, next);
1040 ctl->dirty.bf.daoimap = 1;
1044 static int daio_mgr_set_imapaddr(void *blk, unsigned int addr)
1046 ((struct daio_mgr_ctrl_blk *)blk)->daoimap.idx = addr;
1047 ((struct daio_mgr_ctrl_blk *)blk)->dirty.bf.daoimap = 1;
1051 static int daio_mgr_commit_write(struct hw *hw, void *blk)
1053 struct daio_mgr_ctrl_blk *ctl = blk;
1054 unsigned int data = 0;
1057 for (i = 0; i < 8; i++) {
1058 if ((ctl->dirty.bf.atxctl & (0x1 << i))) {
1059 data = ctl->txctl[i];
1060 hw_write_20kx(hw, (AUDIO_IO_TX_CTL+(0x40*i)), data);
1061 ctl->dirty.bf.atxctl &= ~(0x1 << i);
1064 if ((ctl->dirty.bf.arxctl & (0x1 << i))) {
1065 data = ctl->rxctl[i];
1066 hw_write_20kx(hw, (AUDIO_IO_RX_CTL+(0x40*i)), data);
1067 ctl->dirty.bf.arxctl &= ~(0x1 << i);
1071 if (ctl->dirty.bf.daoimap) {
1072 hw_write_20kx(hw, AUDIO_IO_AIM+ctl->daoimap.idx*4,
1074 ctl->dirty.bf.daoimap = 0;
1080 static int daio_mgr_get_ctrl_blk(struct hw *hw, void **rblk)
1082 struct daio_mgr_ctrl_blk *blk;
1086 blk = kzalloc(sizeof(*blk), GFP_KERNEL);
1090 for (i = 0; i < 8; i++) {
1091 blk->txctl[i] = hw_read_20kx(hw, AUDIO_IO_TX_CTL+(0x40*i));
1092 blk->rxctl[i] = hw_read_20kx(hw, AUDIO_IO_RX_CTL+(0x40*i));
1100 static int daio_mgr_put_ctrl_blk(void *blk)
1102 kfree((struct daio_mgr_ctrl_blk *)blk);
1107 /* Card hardware initialization block */
1109 unsigned int msr; /* master sample rate in rsrs */
1113 unsigned int msr; /* master sample rate in rsrs */
1114 unsigned char input; /* the input source of ADC */
1115 unsigned char mic20db; /* boost mic by 20db if input is microphone */
1119 unsigned int msr; /* master sample rate in rsrs */
1123 unsigned long vm_pgt_phys;
1126 static int hw_daio_init(struct hw *hw, const struct daio_conf *info)
1131 /* Program I2S with proper sample rate and enable the correct I2S
1132 * channel. ED(0/8/16/24): Enable all I2S/I2X master clock output */
1133 if (1 == info->msr) {
1134 hw_write_20kx(hw, AUDIO_IO_MCLK, 0x01010101);
1135 hw_write_20kx(hw, AUDIO_IO_TX_BLRCLK, 0x01010101);
1136 hw_write_20kx(hw, AUDIO_IO_RX_BLRCLK, 0);
1137 } else if (2 == info->msr) {
1138 hw_write_20kx(hw, AUDIO_IO_MCLK, 0x11111111);
1139 /* Specify all playing 96khz
1143 * RTB [12:13] - 96kHz
1145 * RTC [20:21] - 96kHz
1147 * RTD [28:29] - 96kHz */
1148 hw_write_20kx(hw, AUDIO_IO_TX_BLRCLK, 0x11111111);
1149 hw_write_20kx(hw, AUDIO_IO_RX_BLRCLK, 0);
1151 printk(KERN_ALERT "ctxfi: ERROR!!! Invalid sampling rate!!!\n");
1155 for (i = 0; i < 8; i++) {
1157 /* 1st 3 channels are SPDIFs (SB0960) */
1163 hw_write_20kx(hw, (AUDIO_IO_TX_CTL+(0x40*i)), dwData);
1164 hw_write_20kx(hw, (AUDIO_IO_RX_CTL+(0x40*i)), dwData);
1166 /* Initialize the SPDIF Out Channel status registers.
1167 * The value specified here is based on the typical
1168 * values provided in the specification, namely: Clock
1169 * Accuracy of 1000ppm, Sample Rate of 48KHz,
1170 * unspecified source number, Generation status = 1,
1171 * Category code = 0x12 (Digital Signal Mixer),
1172 * Mode = 0, Emph = 0, Copy Permitted, AN = 0
1173 * (indicating that we're transmitting digital audio,
1174 * and the Professional Use bit is 0. */
1176 hw_write_20kx(hw, AUDIO_IO_TX_CSTAT_L+(0x40*i),
1177 0x02109204); /* Default to 48kHz */
1179 hw_write_20kx(hw, AUDIO_IO_TX_CSTAT_H+(0x40*i), 0x0B);
1181 /* Next 5 channels are I2S (SB0960) */
1183 hw_write_20kx(hw, AUDIO_IO_RX_CTL+(0x40*i), dwData);
1184 if (2 == info->msr) {
1185 /* Four channels per sample period */
1188 hw_write_20kx(hw, AUDIO_IO_TX_CTL+(0x40*i), dwData);
1195 /* TRANSPORT operations */
1196 static int hw_trn_init(struct hw *hw, const struct trn_conf *info)
1198 u32 vmctl = 0, data = 0;
1199 unsigned long ptp_phys_low = 0, ptp_phys_high = 0;
1202 /* Set up device page table */
1203 if ((~0UL) == info->vm_pgt_phys) {
1204 printk(KERN_ALERT "ctxfi: "
1205 "Wrong device page table page address!!!\n");
1209 vmctl = 0x80000C0F; /* 32-bit, 4k-size page */
1210 ptp_phys_low = (u32)info->vm_pgt_phys;
1211 ptp_phys_high = upper_32_bits(info->vm_pgt_phys);
1212 if (sizeof(void *) == 8) /* 64bit address */
1214 /* Write page table physical address to all PTPAL registers */
1215 for (i = 0; i < 64; i++) {
1216 hw_write_20kx(hw, VMEM_PTPAL+(16*i), ptp_phys_low);
1217 hw_write_20kx(hw, VMEM_PTPAH+(16*i), ptp_phys_high);
1219 /* Enable virtual memory transfer */
1220 hw_write_20kx(hw, VMEM_CTL, vmctl);
1221 /* Enable transport bus master and queueing of request */
1222 hw_write_20kx(hw, TRANSPORT_CTL, 0x03);
1223 hw_write_20kx(hw, TRANSPORT_INT, 0x200c01);
1224 /* Enable transport ring */
1225 data = hw_read_20kx(hw, TRANSPORT_ENB);
1226 hw_write_20kx(hw, TRANSPORT_ENB, (data | 0x03));
1231 /* Card initialization */
1232 #define GCTL_AIE 0x00000001
1233 #define GCTL_UAA 0x00000002
1234 #define GCTL_DPC 0x00000004
1235 #define GCTL_DBP 0x00000008
1236 #define GCTL_ABP 0x00000010
1237 #define GCTL_TBP 0x00000020
1238 #define GCTL_SBP 0x00000040
1239 #define GCTL_FBP 0x00000080
1240 #define GCTL_ME 0x00000100
1241 #define GCTL_AID 0x00001000
1243 #define PLLCTL_SRC 0x00000007
1244 #define PLLCTL_SPE 0x00000008
1245 #define PLLCTL_RD 0x000000F0
1246 #define PLLCTL_FD 0x0001FF00
1247 #define PLLCTL_OD 0x00060000
1248 #define PLLCTL_B 0x00080000
1249 #define PLLCTL_AS 0x00100000
1250 #define PLLCTL_LF 0x03E00000
1251 #define PLLCTL_SPS 0x1C000000
1252 #define PLLCTL_AD 0x60000000
1254 #define PLLSTAT_CCS 0x00000007
1255 #define PLLSTAT_SPL 0x00000008
1256 #define PLLSTAT_CRD 0x000000F0
1257 #define PLLSTAT_CFD 0x0001FF00
1258 #define PLLSTAT_SL 0x00020000
1259 #define PLLSTAT_FAS 0x00040000
1260 #define PLLSTAT_B 0x00080000
1261 #define PLLSTAT_PD 0x00100000
1262 #define PLLSTAT_OCA 0x00200000
1263 #define PLLSTAT_NCA 0x00400000
1265 static int hw_pll_init(struct hw *hw, unsigned int rsr)
1267 unsigned int pllenb;
1268 unsigned int pllctl;
1269 unsigned int pllstat;
1273 hw_write_20kx(hw, PLL_ENB, pllenb);
1274 pllctl = 0x20D00000;
1275 set_field(&pllctl, PLLCTL_FD, 16 - 4);
1276 hw_write_20kx(hw, PLL_CTL, pllctl);
1278 pllctl = hw_read_20kx(hw, PLL_CTL);
1279 set_field(&pllctl, PLLCTL_B, 0);
1281 set_field(&pllctl, PLLCTL_FD, 16 - 2);
1282 set_field(&pllctl, PLLCTL_RD, 1 - 1);
1283 } else { /* 44100 */
1284 set_field(&pllctl, PLLCTL_FD, 147 - 2);
1285 set_field(&pllctl, PLLCTL_RD, 10 - 1);
1287 hw_write_20kx(hw, PLL_CTL, pllctl);
1289 for (i = 0; i < 1000; i++) {
1290 pllstat = hw_read_20kx(hw, PLL_STAT);
1291 if (get_field(pllstat, PLLSTAT_PD))
1294 if (get_field(pllstat, PLLSTAT_B) !=
1295 get_field(pllctl, PLLCTL_B))
1298 if (get_field(pllstat, PLLSTAT_CCS) !=
1299 get_field(pllctl, PLLCTL_SRC))
1302 if (get_field(pllstat, PLLSTAT_CRD) !=
1303 get_field(pllctl, PLLCTL_RD))
1306 if (get_field(pllstat, PLLSTAT_CFD) !=
1307 get_field(pllctl, PLLCTL_FD))
1313 printk(KERN_ALERT "ctxfi: PLL initialization failed!!!\n");
1320 static int hw_auto_init(struct hw *hw)
1325 gctl = hw_read_20kx(hw, GLOBAL_CNTL_GCTL);
1326 set_field(&gctl, GCTL_AIE, 0);
1327 hw_write_20kx(hw, GLOBAL_CNTL_GCTL, gctl);
1328 set_field(&gctl, GCTL_AIE, 1);
1329 hw_write_20kx(hw, GLOBAL_CNTL_GCTL, gctl);
1331 for (i = 0; i < 400000; i++) {
1332 gctl = hw_read_20kx(hw, GLOBAL_CNTL_GCTL);
1333 if (get_field(gctl, GCTL_AID))
1336 if (!get_field(gctl, GCTL_AID)) {
1337 printk(KERN_ALERT "ctxfi: Card Auto-init failed!!!\n");
1344 /* DAC operations */
1346 #define CS4382_MC1 0x1
1347 #define CS4382_MC2 0x2
1348 #define CS4382_MC3 0x3
1349 #define CS4382_FC 0x4
1350 #define CS4382_IC 0x5
1351 #define CS4382_XC1 0x6
1352 #define CS4382_VCA1 0x7
1353 #define CS4382_VCB1 0x8
1354 #define CS4382_XC2 0x9
1355 #define CS4382_VCA2 0xA
1356 #define CS4382_VCB2 0xB
1357 #define CS4382_XC3 0xC
1358 #define CS4382_VCA3 0xD
1359 #define CS4382_VCB3 0xE
1360 #define CS4382_XC4 0xF
1361 #define CS4382_VCA4 0x10
1362 #define CS4382_VCB4 0x11
1363 #define CS4382_CREV 0x12
1366 #define STATE_LOCKED 0x00
1367 #define STATE_UNLOCKED 0xAA
1368 #define DATA_READY 0x800000 /* Used with I2C_IF_STATUS */
1369 #define DATA_ABORT 0x10000 /* Used with I2C_IF_STATUS */
1371 #define I2C_STATUS_DCM 0x00000001
1372 #define I2C_STATUS_BC 0x00000006
1373 #define I2C_STATUS_APD 0x00000008
1374 #define I2C_STATUS_AB 0x00010000
1375 #define I2C_STATUS_DR 0x00800000
1377 #define I2C_ADDRESS_PTAD 0x0000FFFF
1378 #define I2C_ADDRESS_SLAD 0x007F0000
1380 struct REGS_CS4382 {
1381 u32 dwModeControl_1;
1382 u32 dwModeControl_2;
1383 u32 dwModeControl_3;
1385 u32 dwFilterControl;
1386 u32 dwInvertControl;
1388 u32 dwMixControl_P1;
1389 u32 dwVolControl_A1;
1390 u32 dwVolControl_B1;
1392 u32 dwMixControl_P2;
1393 u32 dwVolControl_A2;
1394 u32 dwVolControl_B2;
1396 u32 dwMixControl_P3;
1397 u32 dwVolControl_A3;
1398 u32 dwVolControl_B3;
1400 u32 dwMixControl_P4;
1401 u32 dwVolControl_A4;
1402 u32 dwVolControl_B4;
1405 static u8 m_bAddressSize, m_bDataSize, m_bDeviceID;
1407 static int I2CUnlockFullAccess(struct hw *hw)
1409 u8 UnlockKeySequence_FLASH_FULLACCESS_MODE[2] = {0xB3, 0xD4};
1411 /* Send keys for forced BIOS mode */
1412 hw_write_20kx(hw, I2C_IF_WLOCK,
1413 UnlockKeySequence_FLASH_FULLACCESS_MODE[0]);
1414 hw_write_20kx(hw, I2C_IF_WLOCK,
1415 UnlockKeySequence_FLASH_FULLACCESS_MODE[1]);
1416 /* Check whether the chip is unlocked */
1417 if (hw_read_20kx(hw, I2C_IF_WLOCK) == STATE_UNLOCKED)
1423 static int I2CLockChip(struct hw *hw)
1426 hw_write_20kx(hw, I2C_IF_WLOCK, STATE_LOCKED);
1427 hw_write_20kx(hw, I2C_IF_WLOCK, STATE_LOCKED);
1428 if (hw_read_20kx(hw, I2C_IF_WLOCK) == STATE_LOCKED)
1434 static int I2CInit(struct hw *hw, u8 bDeviceID, u8 bAddressSize, u8 bDataSize)
1437 unsigned int RegI2CStatus;
1438 unsigned int RegI2CAddress;
1440 err = I2CUnlockFullAccess(hw);
1444 m_bAddressSize = bAddressSize;
1445 m_bDataSize = bDataSize;
1446 m_bDeviceID = bDeviceID;
1449 set_field(&RegI2CAddress, I2C_ADDRESS_SLAD, bDeviceID);
1451 hw_write_20kx(hw, I2C_IF_ADDRESS, RegI2CAddress);
1453 RegI2CStatus = hw_read_20kx(hw, I2C_IF_STATUS);
1455 set_field(&RegI2CStatus, I2C_STATUS_DCM, 1); /* Direct control mode */
1457 hw_write_20kx(hw, I2C_IF_STATUS, RegI2CStatus);
1462 static int I2CUninit(struct hw *hw)
1464 unsigned int RegI2CStatus;
1465 unsigned int RegI2CAddress;
1468 set_field(&RegI2CAddress, I2C_ADDRESS_SLAD, 0x57); /* I2C id */
1470 hw_write_20kx(hw, I2C_IF_ADDRESS, RegI2CAddress);
1472 RegI2CStatus = hw_read_20kx(hw, I2C_IF_STATUS);
1474 set_field(&RegI2CStatus, I2C_STATUS_DCM, 0); /* I2C mode */
1476 hw_write_20kx(hw, I2C_IF_STATUS, RegI2CStatus);
1478 return I2CLockChip(hw);
1481 static int I2CWaitDataReady(struct hw *hw)
1484 unsigned int ret = 0;
1487 ret = hw_read_20kx(hw, I2C_IF_STATUS);
1488 } while ((!(ret & DATA_READY)) && --i);
1493 static int I2CRead(struct hw *hw, u16 wAddress, u32 *pdwData)
1495 unsigned int RegI2CStatus;
1497 RegI2CStatus = hw_read_20kx(hw, I2C_IF_STATUS);
1498 set_field(&RegI2CStatus, I2C_STATUS_BC,
1499 (4 == m_bAddressSize) ? 0 : m_bAddressSize);
1500 hw_write_20kx(hw, I2C_IF_STATUS, RegI2CStatus);
1501 if (!I2CWaitDataReady(hw))
1504 hw_write_20kx(hw, I2C_IF_WDATA, (u32)wAddress);
1505 if (!I2CWaitDataReady(hw))
1508 /* Force a read operation */
1509 hw_write_20kx(hw, I2C_IF_RDATA, 0);
1510 if (!I2CWaitDataReady(hw))
1513 *pdwData = hw_read_20kx(hw, I2C_IF_RDATA);
1518 static int I2CWrite(struct hw *hw, u16 wAddress, u32 dwData)
1520 unsigned int dwI2CData = (dwData << (m_bAddressSize * 8)) | wAddress;
1521 unsigned int RegI2CStatus;
1523 RegI2CStatus = hw_read_20kx(hw, I2C_IF_STATUS);
1525 set_field(&RegI2CStatus, I2C_STATUS_BC,
1526 (4 == (m_bAddressSize + m_bDataSize)) ?
1527 0 : (m_bAddressSize + m_bDataSize));
1529 hw_write_20kx(hw, I2C_IF_STATUS, RegI2CStatus);
1530 I2CWaitDataReady(hw);
1531 /* Dummy write to trigger the write oprtation */
1532 hw_write_20kx(hw, I2C_IF_WDATA, 0);
1533 I2CWaitDataReady(hw);
1535 /* This is the real data */
1536 hw_write_20kx(hw, I2C_IF_WDATA, dwI2CData);
1537 I2CWaitDataReady(hw);
1542 static int hw_dac_init(struct hw *hw, const struct dac_conf *info)
1547 struct REGS_CS4382 cs4382_Read = {0};
1548 struct REGS_CS4382 cs4382_Def = {
1549 0x00000001, /* Mode Control 1 */
1550 0x00000000, /* Mode Control 2 */
1551 0x00000084, /* Mode Control 3 */
1552 0x00000000, /* Filter Control */
1553 0x00000000, /* Invert Control */
1554 0x00000024, /* Mixing Control Pair 1 */
1555 0x00000000, /* Vol Control A1 */
1556 0x00000000, /* Vol Control B1 */
1557 0x00000024, /* Mixing Control Pair 2 */
1558 0x00000000, /* Vol Control A2 */
1559 0x00000000, /* Vol Control B2 */
1560 0x00000024, /* Mixing Control Pair 3 */
1561 0x00000000, /* Vol Control A3 */
1562 0x00000000, /* Vol Control B3 */
1563 0x00000024, /* Mixing Control Pair 4 */
1564 0x00000000, /* Vol Control A4 */
1565 0x00000000 /* Vol Control B4 */
1568 /* Set DAC reset bit as output */
1569 dwData = hw_read_20kx(hw, GPIO_CTRL);
1571 hw_write_20kx(hw, GPIO_CTRL, dwData);
1573 err = I2CInit(hw, 0x18, 1, 1);
1577 for (i = 0; i < 2; i++) {
1578 /* Reset DAC twice just in-case the chip
1579 * didn't initialized properly */
1580 dwData = hw_read_20kx(hw, GPIO_DATA);
1581 /* GPIO data bit 1 */
1582 dwData &= 0xFFFFFFFD;
1583 hw_write_20kx(hw, GPIO_DATA, dwData);
1586 hw_write_20kx(hw, GPIO_DATA, dwData);
1589 /* Reset the 2nd time */
1590 dwData &= 0xFFFFFFFD;
1591 hw_write_20kx(hw, GPIO_DATA, dwData);
1594 hw_write_20kx(hw, GPIO_DATA, dwData);
1597 if (I2CRead(hw, CS4382_MC1, &cs4382_Read.dwModeControl_1))
1600 if (I2CRead(hw, CS4382_MC2, &cs4382_Read.dwModeControl_2))
1603 if (I2CRead(hw, CS4382_MC3, &cs4382_Read.dwModeControl_3))
1606 if (I2CRead(hw, CS4382_FC, &cs4382_Read.dwFilterControl))
1609 if (I2CRead(hw, CS4382_IC, &cs4382_Read.dwInvertControl))
1612 if (I2CRead(hw, CS4382_XC1, &cs4382_Read.dwMixControl_P1))
1615 if (I2CRead(hw, CS4382_VCA1, &cs4382_Read.dwVolControl_A1))
1618 if (I2CRead(hw, CS4382_VCB1, &cs4382_Read.dwVolControl_B1))
1621 if (I2CRead(hw, CS4382_XC2, &cs4382_Read.dwMixControl_P2))
1624 if (I2CRead(hw, CS4382_VCA2, &cs4382_Read.dwVolControl_A2))
1627 if (I2CRead(hw, CS4382_VCB2, &cs4382_Read.dwVolControl_B2))
1630 if (I2CRead(hw, CS4382_XC3, &cs4382_Read.dwMixControl_P3))
1633 if (I2CRead(hw, CS4382_VCA3, &cs4382_Read.dwVolControl_A3))
1636 if (I2CRead(hw, CS4382_VCB3, &cs4382_Read.dwVolControl_B3))
1639 if (I2CRead(hw, CS4382_XC4, &cs4382_Read.dwMixControl_P4))
1642 if (I2CRead(hw, CS4382_VCA4, &cs4382_Read.dwVolControl_A4))
1645 if (I2CRead(hw, CS4382_VCB4, &cs4382_Read.dwVolControl_B4))
1648 if (memcmp(&cs4382_Read, &cs4382_Def,
1649 sizeof(struct REGS_CS4382)))
1658 /* Note: Every I2C write must have some delay.
1659 * This is not a requirement but the delay works here... */
1660 I2CWrite(hw, CS4382_MC1, 0x80);
1661 I2CWrite(hw, CS4382_MC2, 0x10);
1662 if (1 == info->msr) {
1663 I2CWrite(hw, CS4382_XC1, 0x24);
1664 I2CWrite(hw, CS4382_XC2, 0x24);
1665 I2CWrite(hw, CS4382_XC3, 0x24);
1666 I2CWrite(hw, CS4382_XC4, 0x24);
1667 } else if (2 == info->msr) {
1668 I2CWrite(hw, CS4382_XC1, 0x25);
1669 I2CWrite(hw, CS4382_XC2, 0x25);
1670 I2CWrite(hw, CS4382_XC3, 0x25);
1671 I2CWrite(hw, CS4382_XC4, 0x25);
1673 I2CWrite(hw, CS4382_XC1, 0x26);
1674 I2CWrite(hw, CS4382_XC2, 0x26);
1675 I2CWrite(hw, CS4382_XC3, 0x26);
1676 I2CWrite(hw, CS4382_XC4, 0x26);
1686 /* ADC operations */
1687 #define MAKE_WM8775_ADDR(addr, data) (u32)(((addr<<1)&0xFE)|((data>>8)&0x1))
1688 #define MAKE_WM8775_DATA(data) (u32)(data&0xFF)
1690 #define WM8775_IC 0x0B
1691 #define WM8775_MMC 0x0C
1692 #define WM8775_AADCL 0x0E
1693 #define WM8775_AADCR 0x0F
1694 #define WM8775_ADCMC 0x15
1695 #define WM8775_RESET 0x17
1697 static int hw_is_adc_input_selected(struct hw *hw, enum ADCSRC type)
1701 data = hw_read_20kx(hw, GPIO_DATA);
1704 data = (data & (0x1 << 14)) ? 1 : 0;
1707 data = (data & (0x1 << 14)) ? 0 : 1;
1715 static int hw_adc_input_select(struct hw *hw, enum ADCSRC type)
1719 data = hw_read_20kx(hw, GPIO_DATA);
1722 data |= (0x1 << 14);
1723 hw_write_20kx(hw, GPIO_DATA, data);
1724 I2CWrite(hw, MAKE_WM8775_ADDR(WM8775_ADCMC, 0x101),
1725 MAKE_WM8775_DATA(0x101)); /* Mic-in */
1726 I2CWrite(hw, MAKE_WM8775_ADDR(WM8775_AADCL, 0xE7),
1727 MAKE_WM8775_DATA(0xE7)); /* +12dB boost */
1728 I2CWrite(hw, MAKE_WM8775_ADDR(WM8775_AADCR, 0xE7),
1729 MAKE_WM8775_DATA(0xE7)); /* +12dB boost */
1732 data &= ~(0x1 << 14);
1733 hw_write_20kx(hw, GPIO_DATA, data);
1734 I2CWrite(hw, MAKE_WM8775_ADDR(WM8775_ADCMC, 0x102),
1735 MAKE_WM8775_DATA(0x102)); /* Line-in */
1736 I2CWrite(hw, MAKE_WM8775_ADDR(WM8775_AADCL, 0xCF),
1737 MAKE_WM8775_DATA(0xCF)); /* No boost */
1738 I2CWrite(hw, MAKE_WM8775_ADDR(WM8775_AADCR, 0xCF),
1739 MAKE_WM8775_DATA(0xCF)); /* No boost */
1748 static int hw_adc_init(struct hw *hw, const struct adc_conf *info)
1751 u32 dwMux = 2, dwData = 0, dwCtl = 0;
1753 /* Set ADC reset bit as output */
1754 dwData = hw_read_20kx(hw, GPIO_CTRL);
1755 dwData |= (0x1 << 15);
1756 hw_write_20kx(hw, GPIO_CTRL, dwData);
1758 /* Initialize I2C */
1759 err = I2CInit(hw, 0x1A, 1, 1);
1761 printk(KERN_ALERT "ctxfi: Failure to acquire I2C!!!\n");
1765 /* Make ADC in normal operation */
1766 dwData = hw_read_20kx(hw, GPIO_DATA);
1767 dwData &= ~(0x1 << 15);
1769 dwData |= (0x1 << 15);
1770 hw_write_20kx(hw, GPIO_DATA, dwData);
1773 /* Set the master mode (256fs) */
1774 if (1 == info->msr) {
1775 I2CWrite(hw, MAKE_WM8775_ADDR(WM8775_MMC, 0x02),
1776 MAKE_WM8775_DATA(0x02));
1777 } else if (2 == info->msr) {
1778 I2CWrite(hw, MAKE_WM8775_ADDR(WM8775_MMC, 0x0A),
1779 MAKE_WM8775_DATA(0x0A));
1781 printk(KERN_ALERT "ctxfi: Invalid master sampling "
1782 "rate (msr %d)!!!\n", info->msr);
1787 /* Configure GPIO bit 14 change to line-in/mic-in */
1788 dwCtl = hw_read_20kx(hw, GPIO_CTRL);
1790 hw_write_20kx(hw, GPIO_CTRL, dwCtl);
1792 /* Check using Mic-in or Line-in */
1793 dwData = hw_read_20kx(hw, GPIO_DATA);
1796 /* Configures GPIO data to select Mic-in */
1798 hw_write_20kx(hw, GPIO_DATA, dwData);
1800 I2CWrite(hw, MAKE_WM8775_ADDR(WM8775_ADCMC, 0x101),
1801 MAKE_WM8775_DATA(0x101)); /* Mic-in */
1802 I2CWrite(hw, MAKE_WM8775_ADDR(WM8775_AADCL, 0xE7),
1803 MAKE_WM8775_DATA(0xE7)); /* +12dB boost */
1804 I2CWrite(hw, MAKE_WM8775_ADDR(WM8775_AADCR, 0xE7),
1805 MAKE_WM8775_DATA(0xE7)); /* +12dB boost */
1806 } else if (dwMux == 2) {
1807 /* Configures GPIO data to select Line-in */
1808 dwData &= ~(0x1<<14);
1809 hw_write_20kx(hw, GPIO_DATA, dwData);
1812 I2CWrite(hw, MAKE_WM8775_ADDR(WM8775_ADCMC, 0x102),
1813 MAKE_WM8775_DATA(0x102)); /* Line-in */
1814 I2CWrite(hw, MAKE_WM8775_ADDR(WM8775_AADCL, 0xCF),
1815 MAKE_WM8775_DATA(0xCF)); /* No boost */
1816 I2CWrite(hw, MAKE_WM8775_ADDR(WM8775_AADCR, 0xCF),
1817 MAKE_WM8775_DATA(0xCF)); /* No boost */
1819 printk(KERN_ALERT "ctxfi: ERROR!!! Invalid input mux!!!\n");
1831 static int hw_have_digit_io_switch(struct hw *hw)
1836 static int hw_card_start(struct hw *hw)
1839 struct pci_dev *pci = hw->pci;
1842 err = pci_enable_device(pci);
1846 /* Set DMA transfer mask */
1847 if (pci_set_dma_mask(pci, CT_XFI_DMA_MASK) < 0 ||
1848 pci_set_consistent_dma_mask(pci, CT_XFI_DMA_MASK) < 0) {
1849 printk(KERN_ERR "ctxfi: architecture does not support PCI "
1850 "busmaster DMA with mask 0x%llx\n", CT_XFI_DMA_MASK);
1855 err = pci_request_regions(pci, "XFi");
1859 hw->io_base = pci_resource_start(hw->pci, 2);
1860 hw->mem_base = (unsigned long)ioremap(hw->io_base,
1861 pci_resource_len(hw->pci, 2));
1862 if (NULL == (void *)hw->mem_base) {
1867 /* Switch to 20k2 mode from UAA mode. */
1868 gctl = hw_read_20kx(hw, GLOBAL_CNTL_GCTL);
1869 set_field(&gctl, GCTL_UAA, 0);
1870 hw_write_20kx(hw, GLOBAL_CNTL_GCTL, gctl);
1872 /*if ((err = request_irq(pci->irq, ct_atc_interrupt, IRQF_SHARED,
1873 atc->chip_details->nm_card, hw))) {
1879 pci_set_master(pci);
1884 iounmap((void *)hw->mem_base);
1885 hw->mem_base = (unsigned long)NULL;*/
1887 pci_release_regions(pci);
1890 pci_disable_device(pci);
1894 static int hw_card_stop(struct hw *hw)
1896 /* TODO: Disable interrupt and so on... */
1900 static int hw_card_shutdown(struct hw *hw)
1903 free_irq(hw->irq, hw);
1907 if (NULL != ((void *)hw->mem_base))
1908 iounmap((void *)hw->mem_base);
1910 hw->mem_base = (unsigned long)NULL;
1913 pci_release_regions(hw->pci);
1917 pci_disable_device(hw->pci);
1922 static int hw_card_init(struct hw *hw, struct card_conf *info)
1927 struct dac_conf dac_info = {0};
1928 struct adc_conf adc_info = {0};
1929 struct daio_conf daio_info = {0};
1930 struct trn_conf trn_info = {0};
1932 /* Get PCI io port/memory base address and
1933 * do 20kx core switch if needed. */
1935 err = hw_card_start(hw);
1941 err = hw_pll_init(hw, info->rsr);
1945 /* kick off auto-init */
1946 err = hw_auto_init(hw);
1950 gctl = hw_read_20kx(hw, GLOBAL_CNTL_GCTL);
1951 set_field(&gctl, GCTL_DBP, 1);
1952 set_field(&gctl, GCTL_TBP, 1);
1953 set_field(&gctl, GCTL_FBP, 1);
1954 set_field(&gctl, GCTL_DPC, 0);
1955 hw_write_20kx(hw, GLOBAL_CNTL_GCTL, gctl);
1957 /* Reset all global pending interrupts */
1958 hw_write_20kx(hw, INTERRUPT_GIE, 0);
1959 /* Reset all SRC pending interrupts */
1960 hw_write_20kx(hw, SRC_IP, 0);
1962 /* TODO: detect the card ID and configure GPIO accordingly. */
1963 /* Configures GPIO (0xD802 0x98028) */
1964 /*hw_write_20kx(hw, GPIO_CTRL, 0x7F07);*/
1965 /* Configures GPIO (SB0880) */
1966 /*hw_write_20kx(hw, GPIO_CTRL, 0xFF07);*/
1967 hw_write_20kx(hw, GPIO_CTRL, 0xD802);
1969 /* Enable audio ring */
1970 hw_write_20kx(hw, MIXER_AR_ENABLE, 0x01);
1972 trn_info.vm_pgt_phys = info->vm_pgt_phys;
1973 err = hw_trn_init(hw, &trn_info);
1977 daio_info.msr = info->msr;
1978 err = hw_daio_init(hw, &daio_info);
1982 dac_info.msr = info->msr;
1983 err = hw_dac_init(hw, &dac_info);
1987 adc_info.msr = info->msr;
1988 adc_info.input = ADC_LINEIN;
1989 adc_info.mic20db = 0;
1990 err = hw_adc_init(hw, &adc_info);
1994 data = hw_read_20kx(hw, SRC_MCTL);
1995 data |= 0x1; /* Enables input from the audio ring */
1996 hw_write_20kx(hw, SRC_MCTL, data);
2001 static u32 hw_read_20kx(struct hw *hw, u32 reg)
2003 return readl((void *)(hw->mem_base + reg));
2006 static void hw_write_20kx(struct hw *hw, u32 reg, u32 data)
2008 writel(data, (void *)(hw->mem_base + reg));
2011 static struct hw ct20k2_preset __devinitdata = {
2014 .card_init = hw_card_init,
2015 .card_stop = hw_card_stop,
2016 .pll_init = hw_pll_init,
2017 .is_adc_source_selected = hw_is_adc_input_selected,
2018 .select_adc_source = hw_adc_input_select,
2019 .have_digit_io_switch = hw_have_digit_io_switch,
2021 .src_rsc_get_ctrl_blk = src_get_rsc_ctrl_blk,
2022 .src_rsc_put_ctrl_blk = src_put_rsc_ctrl_blk,
2023 .src_mgr_get_ctrl_blk = src_mgr_get_ctrl_blk,
2024 .src_mgr_put_ctrl_blk = src_mgr_put_ctrl_blk,
2025 .src_set_state = src_set_state,
2026 .src_set_bm = src_set_bm,
2027 .src_set_rsr = src_set_rsr,
2028 .src_set_sf = src_set_sf,
2029 .src_set_wr = src_set_wr,
2030 .src_set_pm = src_set_pm,
2031 .src_set_rom = src_set_rom,
2032 .src_set_vo = src_set_vo,
2033 .src_set_st = src_set_st,
2034 .src_set_ie = src_set_ie,
2035 .src_set_ilsz = src_set_ilsz,
2036 .src_set_bp = src_set_bp,
2037 .src_set_cisz = src_set_cisz,
2038 .src_set_ca = src_set_ca,
2039 .src_set_sa = src_set_sa,
2040 .src_set_la = src_set_la,
2041 .src_set_pitch = src_set_pitch,
2042 .src_set_dirty = src_set_dirty,
2043 .src_set_clear_zbufs = src_set_clear_zbufs,
2044 .src_set_dirty_all = src_set_dirty_all,
2045 .src_commit_write = src_commit_write,
2046 .src_get_ca = src_get_ca,
2047 .src_get_dirty = src_get_dirty,
2048 .src_dirty_conj_mask = src_dirty_conj_mask,
2049 .src_mgr_enbs_src = src_mgr_enbs_src,
2050 .src_mgr_enb_src = src_mgr_enb_src,
2051 .src_mgr_dsb_src = src_mgr_dsb_src,
2052 .src_mgr_commit_write = src_mgr_commit_write,
2054 .srcimp_mgr_get_ctrl_blk = srcimp_mgr_get_ctrl_blk,
2055 .srcimp_mgr_put_ctrl_blk = srcimp_mgr_put_ctrl_blk,
2056 .srcimp_mgr_set_imaparc = srcimp_mgr_set_imaparc,
2057 .srcimp_mgr_set_imapuser = srcimp_mgr_set_imapuser,
2058 .srcimp_mgr_set_imapnxt = srcimp_mgr_set_imapnxt,
2059 .srcimp_mgr_set_imapaddr = srcimp_mgr_set_imapaddr,
2060 .srcimp_mgr_commit_write = srcimp_mgr_commit_write,
2062 .amixer_rsc_get_ctrl_blk = amixer_rsc_get_ctrl_blk,
2063 .amixer_rsc_put_ctrl_blk = amixer_rsc_put_ctrl_blk,
2064 .amixer_mgr_get_ctrl_blk = amixer_mgr_get_ctrl_blk,
2065 .amixer_mgr_put_ctrl_blk = amixer_mgr_put_ctrl_blk,
2066 .amixer_set_mode = amixer_set_mode,
2067 .amixer_set_iv = amixer_set_iv,
2068 .amixer_set_x = amixer_set_x,
2069 .amixer_set_y = amixer_set_y,
2070 .amixer_set_sadr = amixer_set_sadr,
2071 .amixer_set_se = amixer_set_se,
2072 .amixer_set_dirty = amixer_set_dirty,
2073 .amixer_set_dirty_all = amixer_set_dirty_all,
2074 .amixer_commit_write = amixer_commit_write,
2075 .amixer_get_y = amixer_get_y,
2076 .amixer_get_dirty = amixer_get_dirty,
2078 .dai_get_ctrl_blk = dai_get_ctrl_blk,
2079 .dai_put_ctrl_blk = dai_put_ctrl_blk,
2080 .dai_srt_set_srco = dai_srt_set_srco,
2081 .dai_srt_set_srcm = dai_srt_set_srcm,
2082 .dai_srt_set_rsr = dai_srt_set_rsr,
2083 .dai_srt_set_drat = dai_srt_set_drat,
2084 .dai_srt_set_ec = dai_srt_set_ec,
2085 .dai_srt_set_et = dai_srt_set_et,
2086 .dai_commit_write = dai_commit_write,
2088 .dao_get_ctrl_blk = dao_get_ctrl_blk,
2089 .dao_put_ctrl_blk = dao_put_ctrl_blk,
2090 .dao_set_spos = dao_set_spos,
2091 .dao_commit_write = dao_commit_write,
2092 .dao_get_spos = dao_get_spos,
2094 .daio_mgr_get_ctrl_blk = daio_mgr_get_ctrl_blk,
2095 .daio_mgr_put_ctrl_blk = daio_mgr_put_ctrl_blk,
2096 .daio_mgr_enb_dai = daio_mgr_enb_dai,
2097 .daio_mgr_dsb_dai = daio_mgr_dsb_dai,
2098 .daio_mgr_enb_dao = daio_mgr_enb_dao,
2099 .daio_mgr_dsb_dao = daio_mgr_dsb_dao,
2100 .daio_mgr_dao_init = daio_mgr_dao_init,
2101 .daio_mgr_set_imaparc = daio_mgr_set_imaparc,
2102 .daio_mgr_set_imapnxt = daio_mgr_set_imapnxt,
2103 .daio_mgr_set_imapaddr = daio_mgr_set_imapaddr,
2104 .daio_mgr_commit_write = daio_mgr_commit_write,
2107 int __devinit create_20k2_hw_obj(struct hw **rhw)
2112 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
2116 *hw = ct20k2_preset;
2122 int destroy_20k2_hw_obj(struct hw *hw)
2125 hw_card_shutdown(hw);