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   1 /*
   2  * core.h  -- Core driver for NXP PCF50633
   3  *
   4  * (C) 2006-2008 by Openmoko, Inc.
   5  * All rights reserved.
   6  *
   7  * This program is free software; you can redistribute  it and/or modify it
   8  * under  the terms of  the GNU General  Public License as published by the
   9  * Free Software Foundation;  either version 2 of the  License, or (at your
  10  * option) any later version.
  11  */
  12
  13 #ifndef __LINUX_MFD_PCF50633_CORE_H
  14 #define __LINUX_MFD_PCF50633_CORE_H
  15
  16 #include <linux/i2c.h>
  17 #include <linux/workqueue.h>
  18 #include <linux/regulator/driver.h>
  19 #include <linux/regulator/machine.h>
  20 #include <linux/power_supply.h>
  21
  22 struct pcf50633;
  23
  24 #define PCF50633_NUM_REGULATORS 11
  25
  26 struct pcf50633_platform_data {
  27         struct regulator_init_data reg_init_data[PCF50633_NUM_REGULATORS];
  28
  29         char **batteries;
  30         int num_batteries;
  31
  32         int charging_restart_interval;
  33
  34         /* Callbacks */
  35         void (*probe_done)(struct pcf50633 *);
  36         void (*mbc_event_callback)(struct pcf50633 *, int);
  37         void (*regulator_registered)(struct pcf50633 *, int);
  38         void (*force_shutdown)(struct pcf50633 *);
  39
  40         u8 resumers[5];
  41 };
  42
  43 struct pcf50633_irq {
  44         void (*handler) (int, void *);
  45         void *data;
  46 };
  47
  48 int pcf50633_register_irq(struct pcf50633 *pcf, int irq,
  49                         void (*handler) (int, void *), void *data);
  50 int pcf50633_free_irq(struct pcf50633 *pcf, int irq);
  51
  52 int pcf50633_irq_mask(struct pcf50633 *pcf, int irq);
  53 int pcf50633_irq_unmask(struct pcf50633 *pcf, int irq);
  54 int pcf50633_irq_mask_get(struct pcf50633 *pcf, int irq);
  55
  56 int pcf50633_read_block(struct pcf50633 *, u8 reg,
  57                                         int nr_regs, u8 *data);
  58 int pcf50633_write_block(struct pcf50633 *pcf, u8 reg,
  59                                         int nr_regs, u8 *data);
  60 u8 pcf50633_reg_read(struct pcf50633 *, u8 reg);
  61 int pcf50633_reg_write(struct pcf50633 *pcf, u8 reg, u8 val);
  62
  63 int pcf50633_reg_set_bit_mask(struct pcf50633 *pcf, u8 reg, u8 mask, u8 val);
  64 int pcf50633_reg_clear_bits(struct pcf50633 *pcf, u8 reg, u8 bits);
  65
  66 /* Interrupt registers */
  67
  68 #define PCF50633_REG_INT1       0x02
  69 #define PCF50633_REG_INT2       0x03
  70 #define PCF50633_REG_INT3       0x04
  71 #define PCF50633_REG_INT4       0x05
  72 #define PCF50633_REG_INT5       0x06
  73
  74 #define PCF50633_REG_INT1M      0x07
  75 #define PCF50633_REG_INT2M      0x08
  76 #define PCF50633_REG_INT3M      0x09
  77 #define PCF50633_REG_INT4M      0x0a
  78 #define PCF50633_REG_INT5M      0x0b
  79
  80 enum {
  81         /* Chip IRQs */
  82         PCF50633_IRQ_ADPINS,
  83         PCF50633_IRQ_ADPREM,
  84         PCF50633_IRQ_USBINS,
  85         PCF50633_IRQ_USBREM,
  86         PCF50633_IRQ_RESERVED1,
  87         PCF50633_IRQ_RESERVED2,
  88         PCF50633_IRQ_ALARM,
  89         PCF50633_IRQ_SECOND,
  90         PCF50633_IRQ_ONKEYR,
  91         PCF50633_IRQ_ONKEYF,
  92         PCF50633_IRQ_EXTON1R,
  93         PCF50633_IRQ_EXTON1F,
  94         PCF50633_IRQ_EXTON2R,
  95         PCF50633_IRQ_EXTON2F,
  96         PCF50633_IRQ_EXTON3R,
  97         PCF50633_IRQ_EXTON3F,
  98         PCF50633_IRQ_BATFULL,
  99         PCF50633_IRQ_CHGHALT,
 100         PCF50633_IRQ_THLIMON,
 101         PCF50633_IRQ_THLIMOFF,
 102         PCF50633_IRQ_USBLIMON,
 103         PCF50633_IRQ_USBLIMOFF,
 104         PCF50633_IRQ_ADCRDY,
 105         PCF50633_IRQ_ONKEY1S,
 106         PCF50633_IRQ_LOWSYS,
 107         PCF50633_IRQ_LOWBAT,
 108         PCF50633_IRQ_HIGHTMP,
 109         PCF50633_IRQ_AUTOPWRFAIL,
 110         PCF50633_IRQ_DWN1PWRFAIL,
 111         PCF50633_IRQ_DWN2PWRFAIL,
 112         PCF50633_IRQ_LEDPWRFAIL,
 113         PCF50633_IRQ_LEDOVP,
 114         PCF50633_IRQ_LDO1PWRFAIL,
 115         PCF50633_IRQ_LDO2PWRFAIL,
 116         PCF50633_IRQ_LDO3PWRFAIL,
 117         PCF50633_IRQ_LDO4PWRFAIL,
 118         PCF50633_IRQ_LDO5PWRFAIL,
 119         PCF50633_IRQ_LDO6PWRFAIL,
 120         PCF50633_IRQ_HCLDOPWRFAIL,
 121         PCF50633_IRQ_HCLDOOVL,
 122
 123         /* Always last */
 124         PCF50633_NUM_IRQ,
 125 };
 126
 127 struct pcf50633 {
 128         struct device *dev;
 129         struct i2c_client *i2c_client;
 130
 131         struct pcf50633_platform_data *pdata;
 132         int irq;
 133         struct pcf50633_irq irq_handler[PCF50633_NUM_IRQ];
 134         struct work_struct irq_work;
 135         struct workqueue_struct *work_queue;
 136         struct mutex lock;
 137
 138         u8 mask_regs[5];
 139
 140         u8 suspend_irq_masks[5];
 141         u8 resume_reason[5];
 142         int is_suspended;
 143
 144         int onkey1s_held;
 145
 146         struct platform_device *rtc_pdev;
 147         struct platform_device *mbc_pdev;
 148         struct platform_device *adc_pdev;
 149         struct platform_device *input_pdev;
 150         struct platform_device *regulator_pdev[PCF50633_NUM_REGULATORS];
 151 };
 152
 153 enum pcf50633_reg_int1 {
 154         PCF50633_INT1_ADPINS    = 0x01, /* Adapter inserted */
 155         PCF50633_INT1_ADPREM    = 0x02, /* Adapter removed */
 156         PCF50633_INT1_USBINS    = 0x04, /* USB inserted */
 157         PCF50633_INT1_USBREM    = 0x08, /* USB removed */
 158         /* reserved */
 159         PCF50633_INT1_ALARM     = 0x40, /* RTC alarm time is reached */
 160         PCF50633_INT1_SECOND    = 0x80, /* RTC periodic second interrupt */
 161 };
 162
 163 enum pcf50633_reg_int2 {
 164         PCF50633_INT2_ONKEYR    = 0x01, /* ONKEY rising edge */
 165         PCF50633_INT2_ONKEYF    = 0x02, /* ONKEY falling edge */
 166         PCF50633_INT2_EXTON1R   = 0x04, /* EXTON1 rising edge */
 167         PCF50633_INT2_EXTON1F   = 0x08, /* EXTON1 falling edge */
 168         PCF50633_INT2_EXTON2R   = 0x10, /* EXTON2 rising edge */
 169         PCF50633_INT2_EXTON2F   = 0x20, /* EXTON2 falling edge */
 170         PCF50633_INT2_EXTON3R   = 0x40, /* EXTON3 rising edge */
 171         PCF50633_INT2_EXTON3F   = 0x80, /* EXTON3 falling edge */
 172 };
 173
 174 enum pcf50633_reg_int3 {
 175         PCF50633_INT3_BATFULL   = 0x01, /* Battery full */
 176         PCF50633_INT3_CHGHALT   = 0x02, /* Charger halt */
 177         PCF50633_INT3_THLIMON   = 0x04,
 178         PCF50633_INT3_THLIMOFF  = 0x08,
 179         PCF50633_INT3_USBLIMON  = 0x10,
 180         PCF50633_INT3_USBLIMOFF = 0x20,
 181         PCF50633_INT3_ADCRDY    = 0x40, /* ADC result ready */
 182         PCF50633_INT3_ONKEY1S   = 0x80, /* ONKEY pressed 1 second */
 183 };
 184
 185 enum pcf50633_reg_int4 {
 186         PCF50633_INT4_LOWSYS            = 0x01,
 187         PCF50633_INT4_LOWBAT            = 0x02,
 188         PCF50633_INT4_HIGHTMP           = 0x04,
 189         PCF50633_INT4_AUTOPWRFAIL       = 0x08,
 190         PCF50633_INT4_DWN1PWRFAIL       = 0x10,
 191         PCF50633_INT4_DWN2PWRFAIL       = 0x20,
 192         PCF50633_INT4_LEDPWRFAIL        = 0x40,
 193         PCF50633_INT4_LEDOVP            = 0x80,
 194 };
 195
 196 enum pcf50633_reg_int5 {
 197         PCF50633_INT5_LDO1PWRFAIL       = 0x01,
 198         PCF50633_INT5_LDO2PWRFAIL       = 0x02,
 199         PCF50633_INT5_LDO3PWRFAIL       = 0x04,
 200         PCF50633_INT5_LDO4PWRFAIL       = 0x08,
 201         PCF50633_INT5_LDO5PWRFAIL       = 0x10,
 202         PCF50633_INT5_LDO6PWRFAIL       = 0x20,
 203         PCF50633_INT5_HCLDOPWRFAIL      = 0x40,
 204         PCF50633_INT5_HCLDOOVL          = 0x80,
 205 };
 206
 207 /* misc. registers */
 208 #define PCF50633_REG_OOCSHDWN   0x0c
 209
 210 /* LED registers */
 211 #define PCF50633_REG_LEDOUT 0x28
 212 #define PCF50633_REG_LEDENA 0x29
 213 #define PCF50633_REG_LEDCTL 0x2a
 214 #define PCF50633_REG_LEDDIM 0x2b
 215
 216 static inline struct pcf50633 *dev_to_pcf50633(struct device *dev)
 217 {
 218         return dev_get_drvdata(dev);
 219 }
 220
 221 #endif