2 * twl4030.h - header for TWL4030 PM and audio CODEC device
4 * Copyright (C) 2005-2006 Texas Instruments, Inc.
6 * Based on tlv320aic23.c:
7 * Copyright (c) by Kai Svahn <kai.svahn@nokia.com>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
28 #include <linux/types.h>
29 #include <linux/input/matrix_keypad.h>
32 * Using the twl4030 core we address registers using a pair
33 * { module id, relative register offset }
34 * which that core then maps to the relevant
35 * { i2c slave, absolute register address }
37 * The module IDs are meaningful only to the twl4030 core code,
38 * which uses them as array indices to look up the first register
39 * address each module uses within a given i2c slave.
42 /* Slave 0 (i2c address 0x48) */
43 #define TWL4030_MODULE_USB 0x00
45 /* Slave 1 (i2c address 0x49) */
46 #define TWL4030_MODULE_AUDIO_VOICE 0x01
47 #define TWL4030_MODULE_GPIO 0x02
48 #define TWL4030_MODULE_INTBR 0x03
49 #define TWL4030_MODULE_PIH 0x04
50 #define TWL4030_MODULE_TEST 0x05
52 /* Slave 2 (i2c address 0x4a) */
53 #define TWL4030_MODULE_KEYPAD 0x06
54 #define TWL4030_MODULE_MADC 0x07
55 #define TWL4030_MODULE_INTERRUPTS 0x08
56 #define TWL4030_MODULE_LED 0x09
57 #define TWL4030_MODULE_MAIN_CHARGE 0x0A
58 #define TWL4030_MODULE_PRECHARGE 0x0B
59 #define TWL4030_MODULE_PWM0 0x0C
60 #define TWL4030_MODULE_PWM1 0x0D
61 #define TWL4030_MODULE_PWMA 0x0E
62 #define TWL4030_MODULE_PWMB 0x0F
64 #define TWL5031_MODULE_ACCESSORY 0x10
65 #define TWL5031_MODULE_INTERRUPTS 0x11
67 /* Slave 3 (i2c address 0x4b) */
68 #define TWL4030_MODULE_BACKUP 0x12
69 #define TWL4030_MODULE_INT 0x13
70 #define TWL4030_MODULE_PM_MASTER 0x14
71 #define TWL4030_MODULE_PM_RECEIVER 0x15
72 #define TWL4030_MODULE_RTC 0x16
73 #define TWL4030_MODULE_SECURED_REG 0x17
76 * Read and write single 8-bit registers
78 int twl4030_i2c_write_u8(u8 mod_no, u8 val, u8 reg);
79 int twl4030_i2c_read_u8(u8 mod_no, u8 *val, u8 reg);
82 * Read and write several 8-bit registers at once.
84 * IMPORTANT: For twl4030_i2c_write(), allocate num_bytes + 1
85 * for the value, and populate your data starting at offset 1.
87 int twl4030_i2c_write(u8 mod_no, u8 *value, u8 reg, unsigned num_bytes);
88 int twl4030_i2c_read(u8 mod_no, u8 *value, u8 reg, unsigned num_bytes);
90 /*----------------------------------------------------------------------*/
93 * NOTE: at up to 1024 registers, this is a big chip.
95 * Avoid putting register declarations in this file, instead of into
96 * a driver-private file, unless some of the registers in a block
97 * need to be shared with other drivers. One example is blocks that
98 * have Secondary IRQ Handler (SIH) registers.
101 #define TWL4030_SIH_CTRL_EXCLEN_MASK BIT(0)
102 #define TWL4030_SIH_CTRL_PENDDIS_MASK BIT(1)
103 #define TWL4030_SIH_CTRL_COR_MASK BIT(2)
105 /*----------------------------------------------------------------------*/
108 * GPIO Block Register offsets (use TWL4030_MODULE_GPIO)
111 #define REG_GPIODATAIN1 0x0
112 #define REG_GPIODATAIN2 0x1
113 #define REG_GPIODATAIN3 0x2
114 #define REG_GPIODATADIR1 0x3
115 #define REG_GPIODATADIR2 0x4
116 #define REG_GPIODATADIR3 0x5
117 #define REG_GPIODATAOUT1 0x6
118 #define REG_GPIODATAOUT2 0x7
119 #define REG_GPIODATAOUT3 0x8
120 #define REG_CLEARGPIODATAOUT1 0x9
121 #define REG_CLEARGPIODATAOUT2 0xA
122 #define REG_CLEARGPIODATAOUT3 0xB
123 #define REG_SETGPIODATAOUT1 0xC
124 #define REG_SETGPIODATAOUT2 0xD
125 #define REG_SETGPIODATAOUT3 0xE
126 #define REG_GPIO_DEBEN1 0xF
127 #define REG_GPIO_DEBEN2 0x10
128 #define REG_GPIO_DEBEN3 0x11
129 #define REG_GPIO_CTRL 0x12
130 #define REG_GPIOPUPDCTR1 0x13
131 #define REG_GPIOPUPDCTR2 0x14
132 #define REG_GPIOPUPDCTR3 0x15
133 #define REG_GPIOPUPDCTR4 0x16
134 #define REG_GPIOPUPDCTR5 0x17
135 #define REG_GPIO_ISR1A 0x19
136 #define REG_GPIO_ISR2A 0x1A
137 #define REG_GPIO_ISR3A 0x1B
138 #define REG_GPIO_IMR1A 0x1C
139 #define REG_GPIO_IMR2A 0x1D
140 #define REG_GPIO_IMR3A 0x1E
141 #define REG_GPIO_ISR1B 0x1F
142 #define REG_GPIO_ISR2B 0x20
143 #define REG_GPIO_ISR3B 0x21
144 #define REG_GPIO_IMR1B 0x22
145 #define REG_GPIO_IMR2B 0x23
146 #define REG_GPIO_IMR3B 0x24
147 #define REG_GPIO_EDR1 0x28
148 #define REG_GPIO_EDR2 0x29
149 #define REG_GPIO_EDR3 0x2A
150 #define REG_GPIO_EDR4 0x2B
151 #define REG_GPIO_EDR5 0x2C
152 #define REG_GPIO_SIH_CTRL 0x2D
154 /* Up to 18 signals are available as GPIOs, when their
155 * pins are not assigned to another use (such as ULPI/USB).
157 #define TWL4030_GPIO_MAX 18
159 /*----------------------------------------------------------------------*/
162 * Keypad register offsets (use TWL4030_MODULE_KEYPAD)
163 * ... SIH/interrupt only
166 #define TWL4030_KEYPAD_KEYP_ISR1 0x11
167 #define TWL4030_KEYPAD_KEYP_IMR1 0x12
168 #define TWL4030_KEYPAD_KEYP_ISR2 0x13
169 #define TWL4030_KEYPAD_KEYP_IMR2 0x14
170 #define TWL4030_KEYPAD_KEYP_SIR 0x15 /* test register */
171 #define TWL4030_KEYPAD_KEYP_EDR 0x16
172 #define TWL4030_KEYPAD_KEYP_SIH_CTRL 0x17
174 /*----------------------------------------------------------------------*/
177 * Multichannel ADC register offsets (use TWL4030_MODULE_MADC)
178 * ... SIH/interrupt only
181 #define TWL4030_MADC_ISR1 0x61
182 #define TWL4030_MADC_IMR1 0x62
183 #define TWL4030_MADC_ISR2 0x63
184 #define TWL4030_MADC_IMR2 0x64
185 #define TWL4030_MADC_SIR 0x65 /* test register */
186 #define TWL4030_MADC_EDR 0x66
187 #define TWL4030_MADC_SIH_CTRL 0x67
189 /*----------------------------------------------------------------------*/
192 * Battery charger register offsets (use TWL4030_MODULE_INTERRUPTS)
195 #define TWL4030_INTERRUPTS_BCIISR1A 0x0
196 #define TWL4030_INTERRUPTS_BCIISR2A 0x1
197 #define TWL4030_INTERRUPTS_BCIIMR1A 0x2
198 #define TWL4030_INTERRUPTS_BCIIMR2A 0x3
199 #define TWL4030_INTERRUPTS_BCIISR1B 0x4
200 #define TWL4030_INTERRUPTS_BCIISR2B 0x5
201 #define TWL4030_INTERRUPTS_BCIIMR1B 0x6
202 #define TWL4030_INTERRUPTS_BCIIMR2B 0x7
203 #define TWL4030_INTERRUPTS_BCISIR1 0x8 /* test register */
204 #define TWL4030_INTERRUPTS_BCISIR2 0x9 /* test register */
205 #define TWL4030_INTERRUPTS_BCIEDR1 0xa
206 #define TWL4030_INTERRUPTS_BCIEDR2 0xb
207 #define TWL4030_INTERRUPTS_BCIEDR3 0xc
208 #define TWL4030_INTERRUPTS_BCISIHCTRL 0xd
210 /*----------------------------------------------------------------------*/
213 * Power Interrupt block register offsets (use TWL4030_MODULE_INT)
216 #define TWL4030_INT_PWR_ISR1 0x0
217 #define TWL4030_INT_PWR_IMR1 0x1
218 #define TWL4030_INT_PWR_ISR2 0x2
219 #define TWL4030_INT_PWR_IMR2 0x3
220 #define TWL4030_INT_PWR_SIR 0x4 /* test register */
221 #define TWL4030_INT_PWR_EDR1 0x5
222 #define TWL4030_INT_PWR_EDR2 0x6
223 #define TWL4030_INT_PWR_SIH_CTRL 0x7
225 /*----------------------------------------------------------------------*/
228 * Accessory Interrupts
230 #define TWL5031_ACIIMR_LSB 0x05
231 #define TWL5031_ACIIMR_MSB 0x06
232 #define TWL5031_ACIIDR_LSB 0x07
233 #define TWL5031_ACIIDR_MSB 0x08
234 #define TWL5031_ACCISR1 0x0F
235 #define TWL5031_ACCIMR1 0x10
236 #define TWL5031_ACCISR2 0x11
237 #define TWL5031_ACCIMR2 0x12
238 #define TWL5031_ACCSIR 0x13
239 #define TWL5031_ACCEDR1 0x14
240 #define TWL5031_ACCSIHCTRL 0x15
242 /*----------------------------------------------------------------------*/
245 * Battery Charger Controller
248 #define TWL5031_INTERRUPTS_BCIISR1 0x0
249 #define TWL5031_INTERRUPTS_BCIIMR1 0x1
250 #define TWL5031_INTERRUPTS_BCIISR2 0x2
251 #define TWL5031_INTERRUPTS_BCIIMR2 0x3
252 #define TWL5031_INTERRUPTS_BCISIR 0x4
253 #define TWL5031_INTERRUPTS_BCIEDR1 0x5
254 #define TWL5031_INTERRUPTS_BCIEDR2 0x6
255 #define TWL5031_INTERRUPTS_BCISIHCTRL 0x7
257 /*----------------------------------------------------------------------*/
259 /* Power bus message definitions */
261 /* The TWL4030/5030 splits its power-management resources (the various
262 * regulators, clock and reset lines) into 3 processor groups - P1, P2 and
263 * P3. These groups can then be configured to transition between sleep, wait-on
264 * and active states by sending messages to the power bus. See Section 5.4.2
265 * Power Resources of TWL4030 TRM
268 /* Processor groups */
269 #define DEV_GRP_NULL 0x0
270 #define DEV_GRP_P1 0x1 /* P1: all OMAP devices */
271 #define DEV_GRP_P2 0x2 /* P2: all Modem devices */
272 #define DEV_GRP_P3 0x4 /* P3: all peripheral devices */
274 /* Resource groups */
275 #define RES_GRP_RES 0x0 /* Reserved */
276 #define RES_GRP_PP 0x1 /* Power providers */
277 #define RES_GRP_RC 0x2 /* Reset and control */
278 #define RES_GRP_PP_RC 0x3
279 #define RES_GRP_PR 0x4 /* Power references */
280 #define RES_GRP_PP_PR 0x5
281 #define RES_GRP_RC_PR 0x6
282 #define RES_GRP_ALL 0x7 /* All resource groups */
284 #define RES_TYPE2_R0 0x0
286 #define RES_TYPE_ALL 0x7
288 /* Resource states */
289 #define RES_STATE_WRST 0xF
290 #define RES_STATE_ACTIVE 0xE
291 #define RES_STATE_SLEEP 0x8
292 #define RES_STATE_OFF 0x0
294 /* Power resources */
296 /* Power providers */
307 #define RES_VINTANA1 11
308 #define RES_VINTANA2 12
309 #define RES_VINTDIG 13
313 #define RES_VUSB_1V5 17
314 #define RES_VUSB_1V8 18
315 #define RES_VUSB_3V1 19
316 #define RES_VUSBCP 20
318 /* Reset and control */
319 #define RES_NRES_PWRON 22
322 #define RES_HFCLKOUT 25
323 #define RES_32KCLKOUT 26
325 /* Power Reference */
326 #define RES_Main_Ref 28
328 #define TOTAL_RESOURCES 28
330 * Power Bus Message Format ... these can be sent individually by Linux,
331 * but are usually part of downloaded scripts that are run when various
332 * power events are triggered.
334 * Broadcast Message (16 Bits):
335 * DEV_GRP[15:13] MT[12] RES_GRP[11:9] RES_TYPE2[8:7] RES_TYPE[6:4]
338 * Singular Message (16 Bits):
339 * DEV_GRP[15:13] MT[12] RES_ID[11:4] RES_STATE[3:0]
342 #define MSG_BROADCAST(devgrp, grp, type, type2, state) \
343 ( (devgrp) << 13 | 1 << 12 | (grp) << 9 | (type2) << 7 \
344 | (type) << 4 | (state))
346 #define MSG_SINGULAR(devgrp, id, state) \
347 ((devgrp) << 13 | 0 << 12 | (id) << 4 | (state))
349 /*----------------------------------------------------------------------*/
351 struct twl4030_clock_init_data {
352 bool ck32k_lowpwr_enable;
355 struct twl4030_bci_platform_data {
356 int *battery_tmp_tbl;
357 unsigned int tblsize;
360 /* TWL4030_GPIO_MAX (18) GPIOs, with interrupts */
361 struct twl4030_gpio_platform_data {
363 unsigned irq_base, irq_end;
365 /* package the two LED signals as output-only GPIOs? */
368 /* gpio-n should control VMMC(n+1) if BIT(n) in mmc_cd is set */
371 /* if BIT(N) is set, or VMMC(n+1) is linked, debounce GPIO-N */
374 /* For gpio-N, bit (1 << N) in "pullups" is set if that pullup
375 * should be enabled. Else, if that bit is set in "pulldowns",
376 * that pulldown is enabled. Don't waste power by letting any
377 * digital inputs float...
382 int (*setup)(struct device *dev,
383 unsigned gpio, unsigned ngpio);
384 int (*teardown)(struct device *dev,
385 unsigned gpio, unsigned ngpio);
388 struct twl4030_madc_platform_data {
392 /* Boards have uniqe mappings of {row, col} --> keycode.
393 * Column and row are 8 bits each, but range only from 0..7.
394 * a PERSISTENT_KEY is "always on" and never reported.
396 #define PERSISTENT_KEY(r, c) KEY((r), (c), KEY_RESERVED)
398 struct twl4030_keypad_data {
399 const struct matrix_keymap_data *keymap_data;
405 enum twl4030_usb_mode {
406 T2_USB_MODE_ULPI = 1,
407 T2_USB_MODE_CEA2011_3PIN = 2,
410 struct twl4030_usb_data {
411 enum twl4030_usb_mode usb_mode;
419 struct twl4030_script {
420 struct twl4030_ins *script;
423 #define TWL4030_WRST_SCRIPT (1<<0)
424 #define TWL4030_WAKEUP12_SCRIPT (1<<1)
425 #define TWL4030_WAKEUP3_SCRIPT (1<<2)
426 #define TWL4030_SLEEP_SCRIPT (1<<3)
429 struct twl4030_resconfig {
431 u8 devgroup; /* Processor group that Power resource belongs to */
432 u8 type; /* Power resource addressed, 6 / broadcast message */
433 u8 type2; /* Power resource addressed, 3 / broadcast message */
434 u8 remap_off; /* off state remapping */
435 u8 remap_sleep; /* sleep state remapping */
438 struct twl4030_power_data {
439 struct twl4030_script **scripts;
441 struct twl4030_resconfig *resource_config;
442 #define TWL4030_RESCONFIG_UNDEF ((u8)-1)
445 extern void twl4030_power_init(struct twl4030_power_data *triton2_scripts);
447 struct twl4030_codec_audio_data {
448 unsigned int audio_mclk;
449 unsigned int ramp_delay_value;
450 unsigned int hs_extmute:1;
451 void (*set_hs_extmute)(int mute);
454 struct twl4030_codec_vibra_data {
455 unsigned int audio_mclk;
456 unsigned int coexist;
459 struct twl4030_codec_data {
460 unsigned int audio_mclk;
461 struct twl4030_codec_audio_data *audio;
462 struct twl4030_codec_vibra_data *vibra;
465 struct twl4030_platform_data {
466 unsigned irq_base, irq_end;
467 struct twl4030_clock_init_data *clock;
468 struct twl4030_bci_platform_data *bci;
469 struct twl4030_gpio_platform_data *gpio;
470 struct twl4030_madc_platform_data *madc;
471 struct twl4030_keypad_data *keypad;
472 struct twl4030_usb_data *usb;
473 struct twl4030_power_data *power;
474 struct twl4030_codec_data *codec;
477 struct regulator_init_data *vdac;
478 struct regulator_init_data *vpll1;
479 struct regulator_init_data *vpll2;
480 struct regulator_init_data *vmmc1;
481 struct regulator_init_data *vmmc2;
482 struct regulator_init_data *vsim;
483 struct regulator_init_data *vaux1;
484 struct regulator_init_data *vaux2;
485 struct regulator_init_data *vaux3;
486 struct regulator_init_data *vaux4;
487 struct regulator_init_data *vio;
488 struct regulator_init_data *vdd1;
489 struct regulator_init_data *vdd2;
490 struct regulator_init_data *vintana1;
491 struct regulator_init_data *vintana2;
492 struct regulator_init_data *vintdig;
495 /*----------------------------------------------------------------------*/
497 int twl4030_sih_setup(int module);
499 /* Offsets to Power Registers */
500 #define TWL4030_VDAC_DEV_GRP 0x3B
501 #define TWL4030_VDAC_DEDICATED 0x3E
502 #define TWL4030_VAUX1_DEV_GRP 0x17
503 #define TWL4030_VAUX1_DEDICATED 0x1A
504 #define TWL4030_VAUX2_DEV_GRP 0x1B
505 #define TWL4030_VAUX2_DEDICATED 0x1E
506 #define TWL4030_VAUX3_DEV_GRP 0x1F
507 #define TWL4030_VAUX3_DEDICATED 0x22
509 #if defined(CONFIG_TWL4030_BCI_BATTERY) || \
510 defined(CONFIG_TWL4030_BCI_BATTERY_MODULE)
511 extern int twl4030charger_usb_en(int enable);
513 static inline int twl4030charger_usb_en(int enable) { return 0; }
516 /*----------------------------------------------------------------------*/
518 /* Linux-specific regulator identifiers ... for now, we only support
519 * the LDOs, and leave the three buck converters alone. VDD1 and VDD2
520 * need to tie into hardware based voltage scaling (cpufreq etc), while
521 * VIO is generally fixed.
524 /* EXTERNAL dc-to-dc buck converters */
525 #define TWL4030_REG_VDD1 0
526 #define TWL4030_REG_VDD2 1
527 #define TWL4030_REG_VIO 2
530 #define TWL4030_REG_VDAC 3
531 #define TWL4030_REG_VPLL1 4
532 #define TWL4030_REG_VPLL2 5 /* not on all chips */
533 #define TWL4030_REG_VMMC1 6
534 #define TWL4030_REG_VMMC2 7 /* not on all chips */
535 #define TWL4030_REG_VSIM 8 /* not on all chips */
536 #define TWL4030_REG_VAUX1 9 /* not on all chips */
537 #define TWL4030_REG_VAUX2_4030 10 /* (twl4030-specific) */
538 #define TWL4030_REG_VAUX2 11 /* (twl5030 and newer) */
539 #define TWL4030_REG_VAUX3 12 /* not on all chips */
540 #define TWL4030_REG_VAUX4 13 /* not on all chips */
543 #define TWL4030_REG_VINTANA1 14
544 #define TWL4030_REG_VINTANA2 15
545 #define TWL4030_REG_VINTDIG 16
546 #define TWL4030_REG_VUSB1V5 17
547 #define TWL4030_REG_VUSB1V8 18
548 #define TWL4030_REG_VUSB3V1 19
550 #endif /* End of __TWL4030_H */