3 * BRIEF MODULE DESCRIPTION
4 * Include file for Alchemy Semiconductor's Au1k CPU.
6 * Copyright 2000,2001 MontaVista Software Inc.
7 * Author: MontaVista Software, Inc.
8 * ppopov@mvista.com or source@mvista.com
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
15 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
16 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
17 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
18 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
21 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
22 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 * You should have received a copy of the GNU General Public License along
27 * with this program; if not, write to the Free Software Foundation, Inc.,
28 * 675 Mass Ave, Cambridge, MA 02139, USA.
32 * some definitions add by takuzo@sm.sony.co.jp and sato@sm.sony.co.jp
38 #include <linux/config.h>
40 #ifndef _LANGUAGE_ASSEMBLY
42 #include <linux/delay.h>
45 /* cpu pipeline flush */
46 void static inline au_sync(void)
48 __asm__ volatile ("sync");
51 void static inline au_sync_udelay(int us)
53 __asm__ volatile ("sync");
57 void static inline au_sync_delay(int ms)
59 __asm__ volatile ("sync");
63 void static inline au_writeb(u8 val, unsigned long reg)
65 *(volatile u8 *)(reg) = val;
68 void static inline au_writew(u16 val, unsigned long reg)
70 *(volatile u16 *)(reg) = val;
73 void static inline au_writel(u32 val, unsigned long reg)
75 *(volatile u32 *)(reg) = val;
78 static inline u8 au_readb(unsigned long reg)
80 return (*(volatile u8 *)reg);
83 static inline u16 au_readw(unsigned long reg)
85 return (*(volatile u16 *)reg);
88 static inline u32 au_readl(unsigned long reg)
90 return (*(volatile u32 *)reg);
94 static __inline__ int au_ffz(unsigned int x)
98 return __ilog2(x & -x);
102 * ffs: find first bit set. This is defined the same way as
103 * the libc and compiler builtin ffs routines, therefore
104 * differs in spirit from the above ffz (man ffs).
106 static __inline__ int au_ffs(int x)
108 return __ilog2(x & -x) + 1;
111 /* arch/mips/au1000/common/clocks.c */
112 extern void set_au1x00_speed(unsigned int new_freq);
113 extern unsigned int get_au1x00_speed(void);
114 extern void set_au1x00_uart_baud_base(unsigned long new_baud_base);
115 extern unsigned long get_au1x00_uart_baud_base(void);
116 extern void set_au1x00_lcd_clock(void);
117 extern unsigned int get_au1x00_lcd_clock(void);
120 * Every board describes its IRQ mapping with this table.
122 typedef struct au1xxx_irqmap {
129 * init_IRQ looks for a table with this name.
131 extern au1xxx_irq_map_t au1xxx_irq_map[];
133 #endif /* !defined (_LANGUAGE_ASSEMBLY) */
136 /* no CP0 timer irq */
137 #define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4)
139 #define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5)
143 * SDRAM Register Offsets
145 #if defined(CONFIG_SOC_AU1000) || defined(CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1100)
146 #define MEM_SDMODE0 (0x0000)
147 #define MEM_SDMODE1 (0x0004)
148 #define MEM_SDMODE2 (0x0008)
149 #define MEM_SDADDR0 (0x000C)
150 #define MEM_SDADDR1 (0x0010)
151 #define MEM_SDADDR2 (0x0014)
152 #define MEM_SDREFCFG (0x0018)
153 #define MEM_SDPRECMD (0x001C)
154 #define MEM_SDAUTOREF (0x0020)
155 #define MEM_SDWRMD0 (0x0024)
156 #define MEM_SDWRMD1 (0x0028)
157 #define MEM_SDWRMD2 (0x002C)
158 #define MEM_SDSLEEP (0x0030)
159 #define MEM_SDSMCKE (0x0034)
162 * MEM_SDMODE register content definitions
164 #define MEM_SDMODE_F (1<<22)
165 #define MEM_SDMODE_SR (1<<21)
166 #define MEM_SDMODE_BS (1<<20)
167 #define MEM_SDMODE_RS (3<<18)
168 #define MEM_SDMODE_CS (7<<15)
169 #define MEM_SDMODE_TRAS (15<<11)
170 #define MEM_SDMODE_TMRD (3<<9)
171 #define MEM_SDMODE_TWR (3<<7)
172 #define MEM_SDMODE_TRP (3<<5)
173 #define MEM_SDMODE_TRCD (3<<3)
174 #define MEM_SDMODE_TCL (7<<0)
176 #define MEM_SDMODE_BS_2Bank (0<<20)
177 #define MEM_SDMODE_BS_4Bank (1<<20)
178 #define MEM_SDMODE_RS_11Row (0<<18)
179 #define MEM_SDMODE_RS_12Row (1<<18)
180 #define MEM_SDMODE_RS_13Row (2<<18)
181 #define MEM_SDMODE_RS_N(N) ((N)<<18)
182 #define MEM_SDMODE_CS_7Col (0<<15)
183 #define MEM_SDMODE_CS_8Col (1<<15)
184 #define MEM_SDMODE_CS_9Col (2<<15)
185 #define MEM_SDMODE_CS_10Col (3<<15)
186 #define MEM_SDMODE_CS_11Col (4<<15)
187 #define MEM_SDMODE_CS_N(N) ((N)<<15)
188 #define MEM_SDMODE_TRAS_N(N) ((N)<<11)
189 #define MEM_SDMODE_TMRD_N(N) ((N)<<9)
190 #define MEM_SDMODE_TWR_N(N) ((N)<<7)
191 #define MEM_SDMODE_TRP_N(N) ((N)<<5)
192 #define MEM_SDMODE_TRCD_N(N) ((N)<<3)
193 #define MEM_SDMODE_TCL_N(N) ((N)<<0)
196 * MEM_SDADDR register contents definitions
198 #define MEM_SDADDR_E (1<<20)
199 #define MEM_SDADDR_CSBA (0x03FF<<10)
200 #define MEM_SDADDR_CSMASK (0x03FF<<0)
201 #define MEM_SDADDR_CSBA_N(N) ((N)&(0x03FF<<22)>>12)
202 #define MEM_SDADDR_CSMASK_N(N) ((N)&(0x03FF<<22)>>22)
205 * MEM_SDREFCFG register content definitions
207 #define MEM_SDREFCFG_TRC (15<<28)
208 #define MEM_SDREFCFG_TRPM (3<<26)
209 #define MEM_SDREFCFG_E (1<<25)
210 #define MEM_SDREFCFG_RE (0x1ffffff<<0)
211 #define MEM_SDREFCFG_TRC_N(N) ((N)<<MEM_SDREFCFG_TRC)
212 #define MEM_SDREFCFG_TRPM_N(N) ((N)<<MEM_SDREFCFG_TRPM)
213 #define MEM_SDREFCFG_REF_N(N) (N)
216 /***********************************************************************/
219 * Au1550 SDRAM Register Offsets
222 /***********************************************************************/
224 #if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200)
225 #define MEM_SDMODE0 (0x0800)
226 #define MEM_SDMODE1 (0x0808)
227 #define MEM_SDMODE2 (0x0810)
228 #define MEM_SDADDR0 (0x0820)
229 #define MEM_SDADDR1 (0x0828)
230 #define MEM_SDADDR2 (0x0830)
231 #define MEM_SDCONFIGA (0x0840)
232 #define MEM_SDCONFIGB (0x0848)
233 #define MEM_SDSTAT (0x0850)
234 #define MEM_SDERRADDR (0x0858)
235 #define MEM_SDSTRIDE0 (0x0860)
236 #define MEM_SDSTRIDE1 (0x0868)
237 #define MEM_SDSTRIDE2 (0x0870)
238 #define MEM_SDWRMD0 (0x0880)
239 #define MEM_SDWRMD1 (0x0888)
240 #define MEM_SDWRMD2 (0x0890)
241 #define MEM_SDPRECMD (0x08C0)
242 #define MEM_SDAUTOREF (0x08C8)
243 #define MEM_SDSREF (0x08D0)
244 #define MEM_SDSLEEP MEM_SDSREF
249 * Physical base addresses for integrated peripherals
252 #ifdef CONFIG_SOC_AU1000
253 #define MEM_PHYS_ADDR 0x14000000
254 #define STATIC_MEM_PHYS_ADDR 0x14001000
255 #define DMA0_PHYS_ADDR 0x14002000
256 #define DMA1_PHYS_ADDR 0x14002100
257 #define DMA2_PHYS_ADDR 0x14002200
258 #define DMA3_PHYS_ADDR 0x14002300
259 #define DMA4_PHYS_ADDR 0x14002400
260 #define DMA5_PHYS_ADDR 0x14002500
261 #define DMA6_PHYS_ADDR 0x14002600
262 #define DMA7_PHYS_ADDR 0x14002700
263 #define IC0_PHYS_ADDR 0x10400000
264 #define IC1_PHYS_ADDR 0x11800000
265 #define AC97_PHYS_ADDR 0x10000000
266 #define USBH_PHYS_ADDR 0x10100000
267 #define USBD_PHYS_ADDR 0x10200000
268 #define IRDA_PHYS_ADDR 0x10300000
269 #define MAC0_PHYS_ADDR 0x10500000
270 #define MAC1_PHYS_ADDR 0x10510000
271 #define MACEN_PHYS_ADDR 0x10520000
272 #define MACDMA0_PHYS_ADDR 0x14004000
273 #define MACDMA1_PHYS_ADDR 0x14004200
274 #define I2S_PHYS_ADDR 0x11000000
275 #define UART0_PHYS_ADDR 0x11100000
276 #define UART1_PHYS_ADDR 0x11200000
277 #define UART2_PHYS_ADDR 0x11300000
278 #define UART3_PHYS_ADDR 0x11400000
279 #define SSI0_PHYS_ADDR 0x11600000
280 #define SSI1_PHYS_ADDR 0x11680000
281 #define SYS_PHYS_ADDR 0x11900000
282 #define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL
283 #define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL
284 #define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL
287 /********************************************************************/
289 #ifdef CONFIG_SOC_AU1500
290 #define MEM_PHYS_ADDR 0x14000000
291 #define STATIC_MEM_PHYS_ADDR 0x14001000
292 #define DMA0_PHYS_ADDR 0x14002000
293 #define DMA1_PHYS_ADDR 0x14002100
294 #define DMA2_PHYS_ADDR 0x14002200
295 #define DMA3_PHYS_ADDR 0x14002300
296 #define DMA4_PHYS_ADDR 0x14002400
297 #define DMA5_PHYS_ADDR 0x14002500
298 #define DMA6_PHYS_ADDR 0x14002600
299 #define DMA7_PHYS_ADDR 0x14002700
300 #define IC0_PHYS_ADDR 0x10400000
301 #define IC1_PHYS_ADDR 0x11800000
302 #define AC97_PHYS_ADDR 0x10000000
303 #define USBH_PHYS_ADDR 0x10100000
304 #define USBD_PHYS_ADDR 0x10200000
305 #define PCI_PHYS_ADDR 0x14005000
306 #define MAC0_PHYS_ADDR 0x11500000
307 #define MAC1_PHYS_ADDR 0x11510000
308 #define MACEN_PHYS_ADDR 0x11520000
309 #define MACDMA0_PHYS_ADDR 0x14004000
310 #define MACDMA1_PHYS_ADDR 0x14004200
311 #define I2S_PHYS_ADDR 0x11000000
312 #define UART0_PHYS_ADDR 0x11100000
313 #define UART3_PHYS_ADDR 0x11400000
314 #define GPIO2_PHYS_ADDR 0x11700000
315 #define SYS_PHYS_ADDR 0x11900000
316 #define PCI_MEM_PHYS_ADDR 0x400000000ULL
317 #define PCI_IO_PHYS_ADDR 0x500000000ULL
318 #define PCI_CONFIG0_PHYS_ADDR 0x600000000ULL
319 #define PCI_CONFIG1_PHYS_ADDR 0x680000000ULL
320 #define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL
321 #define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL
322 #define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL
325 /********************************************************************/
327 #ifdef CONFIG_SOC_AU1100
328 #define MEM_PHYS_ADDR 0x14000000
329 #define STATIC_MEM_PHYS_ADDR 0x14001000
330 #define DMA0_PHYS_ADDR 0x14002000
331 #define DMA1_PHYS_ADDR 0x14002100
332 #define DMA2_PHYS_ADDR 0x14002200
333 #define DMA3_PHYS_ADDR 0x14002300
334 #define DMA4_PHYS_ADDR 0x14002400
335 #define DMA5_PHYS_ADDR 0x14002500
336 #define DMA6_PHYS_ADDR 0x14002600
337 #define DMA7_PHYS_ADDR 0x14002700
338 #define IC0_PHYS_ADDR 0x10400000
339 #define SD0_PHYS_ADDR 0x10600000
340 #define SD1_PHYS_ADDR 0x10680000
341 #define IC1_PHYS_ADDR 0x11800000
342 #define AC97_PHYS_ADDR 0x10000000
343 #define USBH_PHYS_ADDR 0x10100000
344 #define USBD_PHYS_ADDR 0x10200000
345 #define IRDA_PHYS_ADDR 0x10300000
346 #define MAC0_PHYS_ADDR 0x10500000
347 #define MACEN_PHYS_ADDR 0x10520000
348 #define MACDMA0_PHYS_ADDR 0x14004000
349 #define MACDMA1_PHYS_ADDR 0x14004200
350 #define I2S_PHYS_ADDR 0x11000000
351 #define UART0_PHYS_ADDR 0x11100000
352 #define UART1_PHYS_ADDR 0x11200000
353 #define UART3_PHYS_ADDR 0x11400000
354 #define SSI0_PHYS_ADDR 0x11600000
355 #define SSI1_PHYS_ADDR 0x11680000
356 #define GPIO2_PHYS_ADDR 0x11700000
357 #define SYS_PHYS_ADDR 0x11900000
358 #define LCD_PHYS_ADDR 0x15000000
359 #define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL
360 #define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL
361 #define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL
364 /***********************************************************************/
366 #ifdef CONFIG_SOC_AU1550
367 #define MEM_PHYS_ADDR 0x14000000
368 #define STATIC_MEM_PHYS_ADDR 0x14001000
369 #define IC0_PHYS_ADDR 0x10400000
370 #define IC1_PHYS_ADDR 0x11800000
371 #define USBH_PHYS_ADDR 0x14020000
372 #define USBD_PHYS_ADDR 0x10200000
373 #define PCI_PHYS_ADDR 0x14005000
374 #define MAC0_PHYS_ADDR 0x10500000
375 #define MAC1_PHYS_ADDR 0x10510000
376 #define MACEN_PHYS_ADDR 0x10520000
377 #define MACDMA0_PHYS_ADDR 0x14004000
378 #define MACDMA1_PHYS_ADDR 0x14004200
379 #define UART0_PHYS_ADDR 0x11100000
380 #define UART1_PHYS_ADDR 0x11200000
381 #define UART3_PHYS_ADDR 0x11400000
382 #define GPIO2_PHYS_ADDR 0x11700000
383 #define SYS_PHYS_ADDR 0x11900000
384 #define DDMA_PHYS_ADDR 0x14002000
385 #define PE_PHYS_ADDR 0x14008000
386 #define PSC0_PHYS_ADDR 0x11A00000
387 #define PSC1_PHYS_ADDR 0x11B00000
388 #define PSC2_PHYS_ADDR 0x10A00000
389 #define PSC3_PHYS_ADDR 0x10B00000
390 #define PCI_MEM_PHYS_ADDR 0x400000000ULL
391 #define PCI_IO_PHYS_ADDR 0x500000000ULL
392 #define PCI_CONFIG0_PHYS_ADDR 0x600000000ULL
393 #define PCI_CONFIG1_PHYS_ADDR 0x680000000ULL
394 #define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL
395 #define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL
396 #define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL
399 /***********************************************************************/
401 #ifdef CONFIG_SOC_AU1200
402 #define MEM_PHYS_ADDR 0x14000000
403 #define STATIC_MEM_PHYS_ADDR 0x14001000
404 #define AES_PHYS_ADDR 0x10300000
405 #define CIM_PHYS_ADDR 0x14004000
406 #define IC0_PHYS_ADDR 0x10400000
407 #define IC1_PHYS_ADDR 0x11800000
408 #define USBM_PHYS_ADDR 0x14020000
409 #define USBH_PHYS_ADDR 0x14020100
410 #define UART0_PHYS_ADDR 0x11100000
411 #define UART1_PHYS_ADDR 0x11200000
412 #define GPIO2_PHYS_ADDR 0x11700000
413 #define SYS_PHYS_ADDR 0x11900000
414 #define DDMA_PHYS_ADDR 0x14002000
415 #define PSC0_PHYS_ADDR 0x11A00000
416 #define PSC1_PHYS_ADDR 0x11B00000
417 #define SD0_PHYS_ADDR 0x10600000
418 #define SD1_PHYS_ADDR 0x10680000
419 #define LCD_PHYS_ADDR 0x15000000
420 #define SWCNT_PHYS_ADDR 0x1110010C
421 #define MAEFE_PHYS_ADDR 0x14012000
422 #define MAEBE_PHYS_ADDR 0x14010000
423 #define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL
424 #define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL
425 #define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL
429 /* Static Bus Controller */
430 #define MEM_STCFG0 0xB4001000
431 #define MEM_STTIME0 0xB4001004
432 #define MEM_STADDR0 0xB4001008
434 #define MEM_STCFG1 0xB4001010
435 #define MEM_STTIME1 0xB4001014
436 #define MEM_STADDR1 0xB4001018
438 #define MEM_STCFG2 0xB4001020
439 #define MEM_STTIME2 0xB4001024
440 #define MEM_STADDR2 0xB4001028
442 #define MEM_STCFG3 0xB4001030
443 #define MEM_STTIME3 0xB4001034
444 #define MEM_STADDR3 0xB4001038
446 #if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200)
447 #define MEM_STNDCTL 0xB4001100
448 #define MEM_STSTAT 0xB4001104
450 #define MEM_STNAND_CMD (0x0)
451 #define MEM_STNAND_ADDR (0x4)
452 #define MEM_STNAND_DATA (0x20)
455 /* Interrupt Controller 0 */
456 #define IC0_CFG0RD 0xB0400040
457 #define IC0_CFG0SET 0xB0400040
458 #define IC0_CFG0CLR 0xB0400044
460 #define IC0_CFG1RD 0xB0400048
461 #define IC0_CFG1SET 0xB0400048
462 #define IC0_CFG1CLR 0xB040004C
464 #define IC0_CFG2RD 0xB0400050
465 #define IC0_CFG2SET 0xB0400050
466 #define IC0_CFG2CLR 0xB0400054
468 #define IC0_REQ0INT 0xB0400054
469 #define IC0_SRCRD 0xB0400058
470 #define IC0_SRCSET 0xB0400058
471 #define IC0_SRCCLR 0xB040005C
472 #define IC0_REQ1INT 0xB040005C
474 #define IC0_ASSIGNRD 0xB0400060
475 #define IC0_ASSIGNSET 0xB0400060
476 #define IC0_ASSIGNCLR 0xB0400064
478 #define IC0_WAKERD 0xB0400068
479 #define IC0_WAKESET 0xB0400068
480 #define IC0_WAKECLR 0xB040006C
482 #define IC0_MASKRD 0xB0400070
483 #define IC0_MASKSET 0xB0400070
484 #define IC0_MASKCLR 0xB0400074
486 #define IC0_RISINGRD 0xB0400078
487 #define IC0_RISINGCLR 0xB0400078
488 #define IC0_FALLINGRD 0xB040007C
489 #define IC0_FALLINGCLR 0xB040007C
491 #define IC0_TESTBIT 0xB0400080
493 /* Interrupt Controller 1 */
494 #define IC1_CFG0RD 0xB1800040
495 #define IC1_CFG0SET 0xB1800040
496 #define IC1_CFG0CLR 0xB1800044
498 #define IC1_CFG1RD 0xB1800048
499 #define IC1_CFG1SET 0xB1800048
500 #define IC1_CFG1CLR 0xB180004C
502 #define IC1_CFG2RD 0xB1800050
503 #define IC1_CFG2SET 0xB1800050
504 #define IC1_CFG2CLR 0xB1800054
506 #define IC1_REQ0INT 0xB1800054
507 #define IC1_SRCRD 0xB1800058
508 #define IC1_SRCSET 0xB1800058
509 #define IC1_SRCCLR 0xB180005C
510 #define IC1_REQ1INT 0xB180005C
512 #define IC1_ASSIGNRD 0xB1800060
513 #define IC1_ASSIGNSET 0xB1800060
514 #define IC1_ASSIGNCLR 0xB1800064
516 #define IC1_WAKERD 0xB1800068
517 #define IC1_WAKESET 0xB1800068
518 #define IC1_WAKECLR 0xB180006C
520 #define IC1_MASKRD 0xB1800070
521 #define IC1_MASKSET 0xB1800070
522 #define IC1_MASKCLR 0xB1800074
524 #define IC1_RISINGRD 0xB1800078
525 #define IC1_RISINGCLR 0xB1800078
526 #define IC1_FALLINGRD 0xB180007C
527 #define IC1_FALLINGCLR 0xB180007C
529 #define IC1_TESTBIT 0xB1800080
531 /* Interrupt Configuration Modes */
532 #define INTC_INT_DISABLED 0
533 #define INTC_INT_RISE_EDGE 0x1
534 #define INTC_INT_FALL_EDGE 0x2
535 #define INTC_INT_RISE_AND_FALL_EDGE 0x3
536 #define INTC_INT_HIGH_LEVEL 0x5
537 #define INTC_INT_LOW_LEVEL 0x6
538 #define INTC_INT_HIGH_AND_LOW_LEVEL 0x7
540 /* Interrupt Numbers */
542 #ifdef CONFIG_SOC_AU1000
543 #define AU1000_UART0_INT 0
544 #define AU1000_UART1_INT 1 /* au1000 */
545 #define AU1000_UART2_INT 2 /* au1000 */
546 #define AU1000_UART3_INT 3
547 #define AU1000_SSI0_INT 4 /* au1000 */
548 #define AU1000_SSI1_INT 5 /* au1000 */
549 #define AU1000_DMA_INT_BASE 6
550 #define AU1000_TOY_INT 14
551 #define AU1000_TOY_MATCH0_INT 15
552 #define AU1000_TOY_MATCH1_INT 16
553 #define AU1000_TOY_MATCH2_INT 17
554 #define AU1000_RTC_INT 18
555 #define AU1000_RTC_MATCH0_INT 19
556 #define AU1000_RTC_MATCH1_INT 20
557 #define AU1000_RTC_MATCH2_INT 21
558 #define AU1000_IRDA_TX_INT 22 /* au1000 */
559 #define AU1000_IRDA_RX_INT 23 /* au1000 */
560 #define AU1000_USB_DEV_REQ_INT 24
561 #define AU1000_USB_DEV_SUS_INT 25
562 #define AU1000_USB_HOST_INT 26
563 #define AU1000_ACSYNC_INT 27
564 #define AU1000_MAC0_DMA_INT 28
565 #define AU1000_MAC1_DMA_INT 29
566 #define AU1000_I2S_UO_INT 30 /* au1000 */
567 #define AU1000_AC97C_INT 31
568 #define AU1000_GPIO_0 32
569 #define AU1000_GPIO_1 33
570 #define AU1000_GPIO_2 34
571 #define AU1000_GPIO_3 35
572 #define AU1000_GPIO_4 36
573 #define AU1000_GPIO_5 37
574 #define AU1000_GPIO_6 38
575 #define AU1000_GPIO_7 39
576 #define AU1000_GPIO_8 40
577 #define AU1000_GPIO_9 41
578 #define AU1000_GPIO_10 42
579 #define AU1000_GPIO_11 43
580 #define AU1000_GPIO_12 44
581 #define AU1000_GPIO_13 45
582 #define AU1000_GPIO_14 46
583 #define AU1000_GPIO_15 47
584 #define AU1000_GPIO_16 48
585 #define AU1000_GPIO_17 49
586 #define AU1000_GPIO_18 50
587 #define AU1000_GPIO_19 51
588 #define AU1000_GPIO_20 52
589 #define AU1000_GPIO_21 53
590 #define AU1000_GPIO_22 54
591 #define AU1000_GPIO_23 55
592 #define AU1000_GPIO_24 56
593 #define AU1000_GPIO_25 57
594 #define AU1000_GPIO_26 58
595 #define AU1000_GPIO_27 59
596 #define AU1000_GPIO_28 60
597 #define AU1000_GPIO_29 61
598 #define AU1000_GPIO_30 62
599 #define AU1000_GPIO_31 63
601 #define UART0_ADDR 0xB1100000
602 #define UART1_ADDR 0xB1200000
603 #define UART2_ADDR 0xB1300000
604 #define UART3_ADDR 0xB1400000
606 #define USB_OHCI_BASE 0x10100000 // phys addr for ioremap
607 #define USB_HOST_CONFIG 0xB017fffc
609 #define AU1000_ETH0_BASE 0xB0500000
610 #define AU1000_ETH1_BASE 0xB0510000
611 #define AU1000_MAC0_ENABLE 0xB0520000
612 #define AU1000_MAC1_ENABLE 0xB0520004
613 #define NUM_ETH_INTERFACES 2
614 #endif /* CONFIG_SOC_AU1000 */
617 #ifdef CONFIG_SOC_AU1500
618 #define AU1500_UART0_INT 0
619 #define AU1000_PCI_INTA 1 /* au1500 */
620 #define AU1000_PCI_INTB 2 /* au1500 */
621 #define AU1500_UART3_INT 3
622 #define AU1000_PCI_INTC 4 /* au1500 */
623 #define AU1000_PCI_INTD 5 /* au1500 */
624 #define AU1000_DMA_INT_BASE 6
625 #define AU1000_TOY_INT 14
626 #define AU1000_TOY_MATCH0_INT 15
627 #define AU1000_TOY_MATCH1_INT 16
628 #define AU1000_TOY_MATCH2_INT 17
629 #define AU1000_RTC_INT 18
630 #define AU1000_RTC_MATCH0_INT 19
631 #define AU1000_RTC_MATCH1_INT 20
632 #define AU1000_RTC_MATCH2_INT 21
633 #define AU1500_PCI_ERR_INT 22
634 #define AU1000_USB_DEV_REQ_INT 24
635 #define AU1000_USB_DEV_SUS_INT 25
636 #define AU1000_USB_HOST_INT 26
637 #define AU1000_ACSYNC_INT 27
638 #define AU1500_MAC0_DMA_INT 28
639 #define AU1500_MAC1_DMA_INT 29
640 #define AU1000_AC97C_INT 31
641 #define AU1000_GPIO_0 32
642 #define AU1000_GPIO_1 33
643 #define AU1000_GPIO_2 34
644 #define AU1000_GPIO_3 35
645 #define AU1000_GPIO_4 36
646 #define AU1000_GPIO_5 37
647 #define AU1000_GPIO_6 38
648 #define AU1000_GPIO_7 39
649 #define AU1000_GPIO_8 40
650 #define AU1000_GPIO_9 41
651 #define AU1000_GPIO_10 42
652 #define AU1000_GPIO_11 43
653 #define AU1000_GPIO_12 44
654 #define AU1000_GPIO_13 45
655 #define AU1000_GPIO_14 46
656 #define AU1000_GPIO_15 47
657 #define AU1500_GPIO_200 48
658 #define AU1500_GPIO_201 49
659 #define AU1500_GPIO_202 50
660 #define AU1500_GPIO_203 51
661 #define AU1500_GPIO_20 52
662 #define AU1500_GPIO_204 53
663 #define AU1500_GPIO_205 54
664 #define AU1500_GPIO_23 55
665 #define AU1500_GPIO_24 56
666 #define AU1500_GPIO_25 57
667 #define AU1500_GPIO_26 58
668 #define AU1500_GPIO_27 59
669 #define AU1500_GPIO_28 60
670 #define AU1500_GPIO_206 61
671 #define AU1500_GPIO_207 62
672 #define AU1500_GPIO_208_215 63
675 #define INTA AU1000_PCI_INTA
676 #define INTB AU1000_PCI_INTB
677 #define INTC AU1000_PCI_INTC
678 #define INTD AU1000_PCI_INTD
680 #define UART0_ADDR 0xB1100000
681 #define UART3_ADDR 0xB1400000
683 #define USB_OHCI_BASE 0x10100000 // phys addr for ioremap
684 #define USB_HOST_CONFIG 0xB017fffc
686 #define AU1500_ETH0_BASE 0xB1500000
687 #define AU1500_ETH1_BASE 0xB1510000
688 #define AU1500_MAC0_ENABLE 0xB1520000
689 #define AU1500_MAC1_ENABLE 0xB1520004
690 #define NUM_ETH_INTERFACES 2
691 #endif /* CONFIG_SOC_AU1500 */
694 #ifdef CONFIG_SOC_AU1100
695 #define AU1100_UART0_INT 0
696 #define AU1100_UART1_INT 1
697 #define AU1100_SD_INT 2
698 #define AU1100_UART3_INT 3
699 #define AU1000_SSI0_INT 4
700 #define AU1000_SSI1_INT 5
701 #define AU1000_DMA_INT_BASE 6
702 #define AU1000_TOY_INT 14
703 #define AU1000_TOY_MATCH0_INT 15
704 #define AU1000_TOY_MATCH1_INT 16
705 #define AU1000_TOY_MATCH2_INT 17
706 #define AU1000_RTC_INT 18
707 #define AU1000_RTC_MATCH0_INT 19
708 #define AU1000_RTC_MATCH1_INT 20
709 #define AU1000_RTC_MATCH2_INT 21
710 #define AU1000_IRDA_TX_INT 22
711 #define AU1000_IRDA_RX_INT 23
712 #define AU1000_USB_DEV_REQ_INT 24
713 #define AU1000_USB_DEV_SUS_INT 25
714 #define AU1000_USB_HOST_INT 26
715 #define AU1000_ACSYNC_INT 27
716 #define AU1100_MAC0_DMA_INT 28
717 #define AU1100_GPIO_208_215 29
718 #define AU1100_LCD_INT 30
719 #define AU1000_AC97C_INT 31
720 #define AU1000_GPIO_0 32
721 #define AU1000_GPIO_1 33
722 #define AU1000_GPIO_2 34
723 #define AU1000_GPIO_3 35
724 #define AU1000_GPIO_4 36
725 #define AU1000_GPIO_5 37
726 #define AU1000_GPIO_6 38
727 #define AU1000_GPIO_7 39
728 #define AU1000_GPIO_8 40
729 #define AU1000_GPIO_9 41
730 #define AU1000_GPIO_10 42
731 #define AU1000_GPIO_11 43
732 #define AU1000_GPIO_12 44
733 #define AU1000_GPIO_13 45
734 #define AU1000_GPIO_14 46
735 #define AU1000_GPIO_15 47
736 #define AU1000_GPIO_16 48
737 #define AU1000_GPIO_17 49
738 #define AU1000_GPIO_18 50
739 #define AU1000_GPIO_19 51
740 #define AU1000_GPIO_20 52
741 #define AU1000_GPIO_21 53
742 #define AU1000_GPIO_22 54
743 #define AU1000_GPIO_23 55
744 #define AU1000_GPIO_24 56
745 #define AU1000_GPIO_25 57
746 #define AU1000_GPIO_26 58
747 #define AU1000_GPIO_27 59
748 #define AU1000_GPIO_28 60
749 #define AU1000_GPIO_29 61
750 #define AU1000_GPIO_30 62
751 #define AU1000_GPIO_31 63
753 #define UART0_ADDR 0xB1100000
754 #define UART1_ADDR 0xB1200000
755 #define UART3_ADDR 0xB1400000
757 #define USB_OHCI_BASE 0x10100000 // phys addr for ioremap
758 #define USB_HOST_CONFIG 0xB017fffc
760 #define AU1100_ETH0_BASE 0xB0500000
761 #define AU1100_MAC0_ENABLE 0xB0520000
762 #define NUM_ETH_INTERFACES 1
763 #endif /* CONFIG_SOC_AU1100 */
765 #ifdef CONFIG_SOC_AU1550
766 #define AU1550_UART0_INT 0
767 #define AU1550_PCI_INTA 1
768 #define AU1550_PCI_INTB 2
769 #define AU1550_DDMA_INT 3
770 #define AU1550_CRYPTO_INT 4
771 #define AU1550_PCI_INTC 5
772 #define AU1550_PCI_INTD 6
773 #define AU1550_PCI_RST_INT 7
774 #define AU1550_UART1_INT 8
775 #define AU1550_UART3_INT 9
776 #define AU1550_PSC0_INT 10
777 #define AU1550_PSC1_INT 11
778 #define AU1550_PSC2_INT 12
779 #define AU1550_PSC3_INT 13
780 #define AU1000_TOY_INT 14
781 #define AU1000_TOY_MATCH0_INT 15
782 #define AU1000_TOY_MATCH1_INT 16
783 #define AU1000_TOY_MATCH2_INT 17
784 #define AU1000_RTC_INT 18
785 #define AU1000_RTC_MATCH0_INT 19
786 #define AU1000_RTC_MATCH1_INT 20
787 #define AU1000_RTC_MATCH2_INT 21
788 #define AU1550_NAND_INT 23
789 #define AU1550_USB_DEV_REQ_INT 24
790 #define AU1550_USB_DEV_SUS_INT 25
791 #define AU1550_USB_HOST_INT 26
792 #define AU1000_USB_DEV_REQ_INT AU1550_USB_DEV_REQ_INT
793 #define AU1000_USB_DEV_SUS_INT AU1550_USB_DEV_SUS_INT
794 #define AU1000_USB_HOST_INT AU1550_USB_HOST_INT
795 #define AU1550_MAC0_DMA_INT 27
796 #define AU1550_MAC1_DMA_INT 28
797 #define AU1000_GPIO_0 32
798 #define AU1000_GPIO_1 33
799 #define AU1000_GPIO_2 34
800 #define AU1000_GPIO_3 35
801 #define AU1000_GPIO_4 36
802 #define AU1000_GPIO_5 37
803 #define AU1000_GPIO_6 38
804 #define AU1000_GPIO_7 39
805 #define AU1000_GPIO_8 40
806 #define AU1000_GPIO_9 41
807 #define AU1000_GPIO_10 42
808 #define AU1000_GPIO_11 43
809 #define AU1000_GPIO_12 44
810 #define AU1000_GPIO_13 45
811 #define AU1000_GPIO_14 46
812 #define AU1000_GPIO_15 47
813 #define AU1550_GPIO_200 48
814 #define AU1500_GPIO_201_205 49 // Logical or of GPIO201:205
815 #define AU1500_GPIO_16 50
816 #define AU1500_GPIO_17 51
817 #define AU1500_GPIO_20 52
818 #define AU1500_GPIO_21 53
819 #define AU1500_GPIO_22 54
820 #define AU1500_GPIO_23 55
821 #define AU1500_GPIO_24 56
822 #define AU1500_GPIO_25 57
823 #define AU1500_GPIO_26 58
824 #define AU1500_GPIO_27 59
825 #define AU1500_GPIO_28 60
826 #define AU1500_GPIO_206 61
827 #define AU1500_GPIO_207 62
828 #define AU1500_GPIO_208_218 63 // Logical or of GPIO208:218
831 #define INTA AU1550_PCI_INTA
832 #define INTB AU1550_PCI_INTB
833 #define INTC AU1550_PCI_INTC
834 #define INTD AU1550_PCI_INTD
836 #define UART0_ADDR 0xB1100000
837 #define UART1_ADDR 0xB1200000
838 #define UART3_ADDR 0xB1400000
840 #define USB_OHCI_BASE 0x14020000 // phys addr for ioremap
841 #define USB_OHCI_LEN 0x00060000
842 #define USB_HOST_CONFIG 0xB4027ffc
844 #define AU1550_ETH0_BASE 0xB0500000
845 #define AU1550_ETH1_BASE 0xB0510000
846 #define AU1550_MAC0_ENABLE 0xB0520000
847 #define AU1550_MAC1_ENABLE 0xB0520004
848 #define NUM_ETH_INTERFACES 2
849 #endif /* CONFIG_SOC_AU1550 */
851 #ifdef CONFIG_SOC_AU1200
852 #define AU1200_UART0_INT 0
853 #define AU1200_SWT_INT 1
854 #define AU1200_SD_INT 2
855 #define AU1200_DDMA_INT 3
856 #define AU1200_MAE_BE_INT 4
857 #define AU1200_GPIO_200 5
858 #define AU1200_GPIO_201 6
859 #define AU1200_GPIO_202 7
860 #define AU1200_UART1_INT 8
861 #define AU1200_MAE_FE_INT 9
862 #define AU1200_PSC0_INT 10
863 #define AU1200_PSC1_INT 11
864 #define AU1200_AES_INT 12
865 #define AU1200_CAMERA_INT 13
866 #define AU1000_TOY_INT 14
867 #define AU1000_TOY_MATCH0_INT 15
868 #define AU1000_TOY_MATCH1_INT 16
869 #define AU1000_TOY_MATCH2_INT 17
870 #define AU1000_RTC_INT 18
871 #define AU1000_RTC_MATCH0_INT 19
872 #define AU1000_RTC_MATCH1_INT 20
873 #define AU1000_RTC_MATCH2_INT 21
874 #define AU1200_NAND_INT 23
875 #define AU1200_GPIO_204 24
876 #define AU1200_GPIO_205 25
877 #define AU1200_GPIO_206 26
878 #define AU1200_GPIO_207 27
879 #define AU1200_GPIO_208_215 28 // Logical OR of 208:215
880 #define AU1200_USB_INT 29
881 #define AU1000_USB_HOST_INT AU1200_USB_INT
882 #define AU1200_LCD_INT 30
883 #define AU1200_MAE_BOTH_INT 31
884 #define AU1000_GPIO_0 32
885 #define AU1000_GPIO_1 33
886 #define AU1000_GPIO_2 34
887 #define AU1000_GPIO_3 35
888 #define AU1000_GPIO_4 36
889 #define AU1000_GPIO_5 37
890 #define AU1000_GPIO_6 38
891 #define AU1000_GPIO_7 39
892 #define AU1000_GPIO_8 40
893 #define AU1000_GPIO_9 41
894 #define AU1000_GPIO_10 42
895 #define AU1000_GPIO_11 43
896 #define AU1000_GPIO_12 44
897 #define AU1000_GPIO_13 45
898 #define AU1000_GPIO_14 46
899 #define AU1000_GPIO_15 47
900 #define AU1000_GPIO_16 48
901 #define AU1000_GPIO_17 49
902 #define AU1000_GPIO_18 50
903 #define AU1000_GPIO_19 51
904 #define AU1000_GPIO_20 52
905 #define AU1000_GPIO_21 53
906 #define AU1000_GPIO_22 54
907 #define AU1000_GPIO_23 55
908 #define AU1000_GPIO_24 56
909 #define AU1000_GPIO_25 57
910 #define AU1000_GPIO_26 58
911 #define AU1000_GPIO_27 59
912 #define AU1000_GPIO_28 60
913 #define AU1000_GPIO_29 61
914 #define AU1000_GPIO_30 62
915 #define AU1000_GPIO_31 63
917 #define UART0_ADDR 0xB1100000
918 #define UART1_ADDR 0xB1200000
920 #define USB_UOC_BASE 0x14020020
921 #define USB_UOC_LEN 0x20
922 #define USB_OHCI_BASE 0x14020100
923 #define USB_OHCI_LEN 0x100
924 #define USB_EHCI_BASE 0x14020200
925 #define USB_EHCI_LEN 0x100
926 #define USB_UDC_BASE 0x14022000
927 #define USB_UDC_LEN 0x2000
928 #define USB_MSR_BASE 0xB4020000
929 #define USB_MSR_MCFG 4
930 #define USBMSRMCFG_OMEMEN 0
931 #define USBMSRMCFG_OBMEN 1
932 #define USBMSRMCFG_EMEMEN 2
933 #define USBMSRMCFG_EBMEN 3
934 #define USBMSRMCFG_DMEMEN 4
935 #define USBMSRMCFG_DBMEN 5
936 #define USBMSRMCFG_GMEMEN 6
937 #define USBMSRMCFG_OHCCLKEN 16
938 #define USBMSRMCFG_EHCCLKEN 17
939 #define USBMSRMCFG_UDCCLKEN 18
940 #define USBMSRMCFG_PHYPLLEN 19
941 #define USBMSRMCFG_RDCOMB 30
942 #define USBMSRMCFG_PFEN 31
944 #endif /* CONFIG_SOC_AU1200 */
946 #define AU1000_LAST_INTC0_INT 31
947 #define AU1000_LAST_INTC1_INT 63
948 #define AU1000_MAX_INTR 63
949 #define INTX 0xFF /* not valid */
951 /* Programmable Counters 0 and 1 */
952 #define SYS_BASE 0xB1900000
953 #define SYS_COUNTER_CNTRL (SYS_BASE + 0x14)
954 #define SYS_CNTRL_E1S (1<<23)
955 #define SYS_CNTRL_T1S (1<<20)
956 #define SYS_CNTRL_M21 (1<<19)
957 #define SYS_CNTRL_M11 (1<<18)
958 #define SYS_CNTRL_M01 (1<<17)
959 #define SYS_CNTRL_C1S (1<<16)
960 #define SYS_CNTRL_BP (1<<14)
961 #define SYS_CNTRL_EN1 (1<<13)
962 #define SYS_CNTRL_BT1 (1<<12)
963 #define SYS_CNTRL_EN0 (1<<11)
964 #define SYS_CNTRL_BT0 (1<<10)
965 #define SYS_CNTRL_E0 (1<<8)
966 #define SYS_CNTRL_E0S (1<<7)
967 #define SYS_CNTRL_32S (1<<5)
968 #define SYS_CNTRL_T0S (1<<4)
969 #define SYS_CNTRL_M20 (1<<3)
970 #define SYS_CNTRL_M10 (1<<2)
971 #define SYS_CNTRL_M00 (1<<1)
972 #define SYS_CNTRL_C0S (1<<0)
974 /* Programmable Counter 0 Registers */
975 #define SYS_TOYTRIM (SYS_BASE + 0)
976 #define SYS_TOYWRITE (SYS_BASE + 4)
977 #define SYS_TOYMATCH0 (SYS_BASE + 8)
978 #define SYS_TOYMATCH1 (SYS_BASE + 0xC)
979 #define SYS_TOYMATCH2 (SYS_BASE + 0x10)
980 #define SYS_TOYREAD (SYS_BASE + 0x40)
982 /* Programmable Counter 1 Registers */
983 #define SYS_RTCTRIM (SYS_BASE + 0x44)
984 #define SYS_RTCWRITE (SYS_BASE + 0x48)
985 #define SYS_RTCMATCH0 (SYS_BASE + 0x4C)
986 #define SYS_RTCMATCH1 (SYS_BASE + 0x50)
987 #define SYS_RTCMATCH2 (SYS_BASE + 0x54)
988 #define SYS_RTCREAD (SYS_BASE + 0x58)
991 #define I2S_DATA 0xB1000000
992 #define I2S_DATA_MASK (0xffffff)
993 #define I2S_CONFIG 0xB1000004
994 #define I2S_CONFIG_XU (1<<25)
995 #define I2S_CONFIG_XO (1<<24)
996 #define I2S_CONFIG_RU (1<<23)
997 #define I2S_CONFIG_RO (1<<22)
998 #define I2S_CONFIG_TR (1<<21)
999 #define I2S_CONFIG_TE (1<<20)
1000 #define I2S_CONFIG_TF (1<<19)
1001 #define I2S_CONFIG_RR (1<<18)
1002 #define I2S_CONFIG_RE (1<<17)
1003 #define I2S_CONFIG_RF (1<<16)
1004 #define I2S_CONFIG_PD (1<<11)
1005 #define I2S_CONFIG_LB (1<<10)
1006 #define I2S_CONFIG_IC (1<<9)
1007 #define I2S_CONFIG_FM_BIT 7
1008 #define I2S_CONFIG_FM_MASK (0x3 << I2S_CONFIG_FM_BIT)
1009 #define I2S_CONFIG_FM_I2S (0x0 << I2S_CONFIG_FM_BIT)
1010 #define I2S_CONFIG_FM_LJ (0x1 << I2S_CONFIG_FM_BIT)
1011 #define I2S_CONFIG_FM_RJ (0x2 << I2S_CONFIG_FM_BIT)
1012 #define I2S_CONFIG_TN (1<<6)
1013 #define I2S_CONFIG_RN (1<<5)
1014 #define I2S_CONFIG_SZ_BIT 0
1015 #define I2S_CONFIG_SZ_MASK (0x1F << I2S_CONFIG_SZ_BIT)
1017 #define I2S_CONTROL 0xB1000008
1018 #define I2S_CONTROL_D (1<<1)
1019 #define I2S_CONTROL_CE (1<<0)
1021 /* USB Host Controller */
1022 #ifndef USB_OHCI_LEN
1023 #define USB_OHCI_LEN 0x00100000
1026 #ifndef CONFIG_SOC_AU1200
1028 /* USB Device Controller */
1029 #define USBD_EP0RD 0xB0200000
1030 #define USBD_EP0WR 0xB0200004
1031 #define USBD_EP2WR 0xB0200008
1032 #define USBD_EP3WR 0xB020000C
1033 #define USBD_EP4RD 0xB0200010
1034 #define USBD_EP5RD 0xB0200014
1035 #define USBD_INTEN 0xB0200018
1036 #define USBD_INTSTAT 0xB020001C
1037 #define USBDEV_INT_SOF (1<<12)
1038 #define USBDEV_INT_HF_BIT 6
1039 #define USBDEV_INT_HF_MASK (0x3f << USBDEV_INT_HF_BIT)
1040 #define USBDEV_INT_CMPLT_BIT 0
1041 #define USBDEV_INT_CMPLT_MASK (0x3f << USBDEV_INT_CMPLT_BIT)
1042 #define USBD_CONFIG 0xB0200020
1043 #define USBD_EP0CS 0xB0200024
1044 #define USBD_EP2CS 0xB0200028
1045 #define USBD_EP3CS 0xB020002C
1046 #define USBD_EP4CS 0xB0200030
1047 #define USBD_EP5CS 0xB0200034
1048 #define USBDEV_CS_SU (1<<14)
1049 #define USBDEV_CS_NAK (1<<13)
1050 #define USBDEV_CS_ACK (1<<12)
1051 #define USBDEV_CS_BUSY (1<<11)
1052 #define USBDEV_CS_TSIZE_BIT 1
1053 #define USBDEV_CS_TSIZE_MASK (0x3ff << USBDEV_CS_TSIZE_BIT)
1054 #define USBDEV_CS_STALL (1<<0)
1055 #define USBD_EP0RDSTAT 0xB0200040
1056 #define USBD_EP0WRSTAT 0xB0200044
1057 #define USBD_EP2WRSTAT 0xB0200048
1058 #define USBD_EP3WRSTAT 0xB020004C
1059 #define USBD_EP4RDSTAT 0xB0200050
1060 #define USBD_EP5RDSTAT 0xB0200054
1061 #define USBDEV_FSTAT_FLUSH (1<<6)
1062 #define USBDEV_FSTAT_UF (1<<5)
1063 #define USBDEV_FSTAT_OF (1<<4)
1064 #define USBDEV_FSTAT_FCNT_BIT 0
1065 #define USBDEV_FSTAT_FCNT_MASK (0x0f << USBDEV_FSTAT_FCNT_BIT)
1066 #define USBD_ENABLE 0xB0200058
1067 #define USBDEV_ENABLE (1<<1)
1068 #define USBDEV_CE (1<<0)
1070 #endif /* !CONFIG_SOC_AU1200 */
1072 /* Ethernet Controllers */
1074 /* 4 byte offsets from AU1000_ETH_BASE */
1075 #define MAC_CONTROL 0x0
1076 #define MAC_RX_ENABLE (1<<2)
1077 #define MAC_TX_ENABLE (1<<3)
1078 #define MAC_DEF_CHECK (1<<5)
1079 #define MAC_SET_BL(X) (((X)&0x3)<<6)
1080 #define MAC_AUTO_PAD (1<<8)
1081 #define MAC_DISABLE_RETRY (1<<10)
1082 #define MAC_DISABLE_BCAST (1<<11)
1083 #define MAC_LATE_COL (1<<12)
1084 #define MAC_HASH_MODE (1<<13)
1085 #define MAC_HASH_ONLY (1<<15)
1086 #define MAC_PASS_ALL (1<<16)
1087 #define MAC_INVERSE_FILTER (1<<17)
1088 #define MAC_PROMISCUOUS (1<<18)
1089 #define MAC_PASS_ALL_MULTI (1<<19)
1090 #define MAC_FULL_DUPLEX (1<<20)
1091 #define MAC_NORMAL_MODE 0
1092 #define MAC_INT_LOOPBACK (1<<21)
1093 #define MAC_EXT_LOOPBACK (1<<22)
1094 #define MAC_DISABLE_RX_OWN (1<<23)
1095 #define MAC_BIG_ENDIAN (1<<30)
1096 #define MAC_RX_ALL (1<<31)
1097 #define MAC_ADDRESS_HIGH 0x4
1098 #define MAC_ADDRESS_LOW 0x8
1099 #define MAC_MCAST_HIGH 0xC
1100 #define MAC_MCAST_LOW 0x10
1101 #define MAC_MII_CNTRL 0x14
1102 #define MAC_MII_BUSY (1<<0)
1103 #define MAC_MII_READ 0
1104 #define MAC_MII_WRITE (1<<1)
1105 #define MAC_SET_MII_SELECT_REG(X) (((X)&0x1f)<<6)
1106 #define MAC_SET_MII_SELECT_PHY(X) (((X)&0x1f)<<11)
1107 #define MAC_MII_DATA 0x18
1108 #define MAC_FLOW_CNTRL 0x1C
1109 #define MAC_FLOW_CNTRL_BUSY (1<<0)
1110 #define MAC_FLOW_CNTRL_ENABLE (1<<1)
1111 #define MAC_PASS_CONTROL (1<<2)
1112 #define MAC_SET_PAUSE(X) (((X)&0xffff)<<16)
1113 #define MAC_VLAN1_TAG 0x20
1114 #define MAC_VLAN2_TAG 0x24
1116 /* Ethernet Controller Enable */
1118 #define MAC_EN_CLOCK_ENABLE (1<<0)
1119 #define MAC_EN_RESET0 (1<<1)
1120 #define MAC_EN_TOSS (0<<2)
1121 #define MAC_EN_CACHEABLE (1<<3)
1122 #define MAC_EN_RESET1 (1<<4)
1123 #define MAC_EN_RESET2 (1<<5)
1124 #define MAC_DMA_RESET (1<<6)
1126 /* Ethernet Controller DMA Channels */
1128 #define MAC0_TX_DMA_ADDR 0xB4004000
1129 #define MAC1_TX_DMA_ADDR 0xB4004200
1130 /* offsets from MAC_TX_RING_ADDR address */
1131 #define MAC_TX_BUFF0_STATUS 0x0
1132 #define TX_FRAME_ABORTED (1<<0)
1133 #define TX_JAB_TIMEOUT (1<<1)
1134 #define TX_NO_CARRIER (1<<2)
1135 #define TX_LOSS_CARRIER (1<<3)
1136 #define TX_EXC_DEF (1<<4)
1137 #define TX_LATE_COLL_ABORT (1<<5)
1138 #define TX_EXC_COLL (1<<6)
1139 #define TX_UNDERRUN (1<<7)
1140 #define TX_DEFERRED (1<<8)
1141 #define TX_LATE_COLL (1<<9)
1142 #define TX_COLL_CNT_MASK (0xF<<10)
1143 #define TX_PKT_RETRY (1<<31)
1144 #define MAC_TX_BUFF0_ADDR 0x4
1145 #define TX_DMA_ENABLE (1<<0)
1146 #define TX_T_DONE (1<<1)
1147 #define TX_GET_DMA_BUFFER(X) (((X)>>2)&0x3)
1148 #define MAC_TX_BUFF0_LEN 0x8
1149 #define MAC_TX_BUFF1_STATUS 0x10
1150 #define MAC_TX_BUFF1_ADDR 0x14
1151 #define MAC_TX_BUFF1_LEN 0x18
1152 #define MAC_TX_BUFF2_STATUS 0x20
1153 #define MAC_TX_BUFF2_ADDR 0x24
1154 #define MAC_TX_BUFF2_LEN 0x28
1155 #define MAC_TX_BUFF3_STATUS 0x30
1156 #define MAC_TX_BUFF3_ADDR 0x34
1157 #define MAC_TX_BUFF3_LEN 0x38
1159 #define MAC0_RX_DMA_ADDR 0xB4004100
1160 #define MAC1_RX_DMA_ADDR 0xB4004300
1161 /* offsets from MAC_RX_RING_ADDR */
1162 #define MAC_RX_BUFF0_STATUS 0x0
1163 #define RX_FRAME_LEN_MASK 0x3fff
1164 #define RX_WDOG_TIMER (1<<14)
1165 #define RX_RUNT (1<<15)
1166 #define RX_OVERLEN (1<<16)
1167 #define RX_COLL (1<<17)
1168 #define RX_ETHER (1<<18)
1169 #define RX_MII_ERROR (1<<19)
1170 #define RX_DRIBBLING (1<<20)
1171 #define RX_CRC_ERROR (1<<21)
1172 #define RX_VLAN1 (1<<22)
1173 #define RX_VLAN2 (1<<23)
1174 #define RX_LEN_ERROR (1<<24)
1175 #define RX_CNTRL_FRAME (1<<25)
1176 #define RX_U_CNTRL_FRAME (1<<26)
1177 #define RX_MCAST_FRAME (1<<27)
1178 #define RX_BCAST_FRAME (1<<28)
1179 #define RX_FILTER_FAIL (1<<29)
1180 #define RX_PACKET_FILTER (1<<30)
1181 #define RX_MISSED_FRAME (1<<31)
1183 #define RX_ERROR (RX_WDOG_TIMER | RX_RUNT | RX_OVERLEN | \
1184 RX_COLL | RX_MII_ERROR | RX_CRC_ERROR | \
1185 RX_LEN_ERROR | RX_U_CNTRL_FRAME | RX_MISSED_FRAME)
1186 #define MAC_RX_BUFF0_ADDR 0x4
1187 #define RX_DMA_ENABLE (1<<0)
1188 #define RX_T_DONE (1<<1)
1189 #define RX_GET_DMA_BUFFER(X) (((X)>>2)&0x3)
1190 #define RX_SET_BUFF_ADDR(X) ((X)&0xffffffc0)
1191 #define MAC_RX_BUFF1_STATUS 0x10
1192 #define MAC_RX_BUFF1_ADDR 0x14
1193 #define MAC_RX_BUFF2_STATUS 0x20
1194 #define MAC_RX_BUFF2_ADDR 0x24
1195 #define MAC_RX_BUFF3_STATUS 0x30
1196 #define MAC_RX_BUFF3_ADDR 0x34
1200 #define UART_BASE UART0_ADDR
1201 #ifdef CONFIG_SOC_AU1200
1202 #define UART_DEBUG_BASE UART1_ADDR
1204 #define UART_DEBUG_BASE UART3_ADDR
1207 #define UART_RX 0 /* Receive buffer */
1208 #define UART_TX 4 /* Transmit buffer */
1209 #define UART_IER 8 /* Interrupt Enable Register */
1210 #define UART_IIR 0xC /* Interrupt ID Register */
1211 #define UART_FCR 0x10 /* FIFO Control Register */
1212 #define UART_LCR 0x14 /* Line Control Register */
1213 #define UART_MCR 0x18 /* Modem Control Register */
1214 #define UART_LSR 0x1C /* Line Status Register */
1215 #define UART_MSR 0x20 /* Modem Status Register */
1216 #define UART_CLK 0x28 /* Baud Rate Clock Divider */
1217 #define UART_MOD_CNTRL 0x100 /* Module Control */
1219 #define UART_FCR_ENABLE_FIFO 0x01 /* Enable the FIFO */
1220 #define UART_FCR_CLEAR_RCVR 0x02 /* Clear the RCVR FIFO */
1221 #define UART_FCR_CLEAR_XMIT 0x04 /* Clear the XMIT FIFO */
1222 #define UART_FCR_DMA_SELECT 0x08 /* For DMA applications */
1223 #define UART_FCR_TRIGGER_MASK 0xF0 /* Mask for the FIFO trigger range */
1224 #define UART_FCR_R_TRIGGER_1 0x00 /* Mask for receive trigger set at 1 */
1225 #define UART_FCR_R_TRIGGER_4 0x40 /* Mask for receive trigger set at 4 */
1226 #define UART_FCR_R_TRIGGER_8 0x80 /* Mask for receive trigger set at 8 */
1227 #define UART_FCR_R_TRIGGER_14 0xA0 /* Mask for receive trigger set at 14 */
1228 #define UART_FCR_T_TRIGGER_0 0x00 /* Mask for transmit trigger set at 0 */
1229 #define UART_FCR_T_TRIGGER_4 0x10 /* Mask for transmit trigger set at 4 */
1230 #define UART_FCR_T_TRIGGER_8 0x20 /* Mask for transmit trigger set at 8 */
1231 #define UART_FCR_T_TRIGGER_12 0x30 /* Mask for transmit trigger set at 12 */
1234 * These are the definitions for the Line Control Register
1236 #define UART_LCR_SBC 0x40 /* Set break control */
1237 #define UART_LCR_SPAR 0x20 /* Stick parity (?) */
1238 #define UART_LCR_EPAR 0x10 /* Even parity select */
1239 #define UART_LCR_PARITY 0x08 /* Parity Enable */
1240 #define UART_LCR_STOP 0x04 /* Stop bits: 0=1 stop bit, 1= 2 stop bits */
1241 #define UART_LCR_WLEN5 0x00 /* Wordlength: 5 bits */
1242 #define UART_LCR_WLEN6 0x01 /* Wordlength: 6 bits */
1243 #define UART_LCR_WLEN7 0x02 /* Wordlength: 7 bits */
1244 #define UART_LCR_WLEN8 0x03 /* Wordlength: 8 bits */
1247 * These are the definitions for the Line Status Register
1249 #define UART_LSR_TEMT 0x40 /* Transmitter empty */
1250 #define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */
1251 #define UART_LSR_BI 0x10 /* Break interrupt indicator */
1252 #define UART_LSR_FE 0x08 /* Frame error indicator */
1253 #define UART_LSR_PE 0x04 /* Parity error indicator */
1254 #define UART_LSR_OE 0x02 /* Overrun error indicator */
1255 #define UART_LSR_DR 0x01 /* Receiver data ready */
1258 * These are the definitions for the Interrupt Identification Register
1260 #define UART_IIR_NO_INT 0x01 /* No interrupts pending */
1261 #define UART_IIR_ID 0x06 /* Mask for the interrupt ID */
1262 #define UART_IIR_MSI 0x00 /* Modem status interrupt */
1263 #define UART_IIR_THRI 0x02 /* Transmitter holding register empty */
1264 #define UART_IIR_RDI 0x04 /* Receiver data interrupt */
1265 #define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */
1268 * These are the definitions for the Interrupt Enable Register
1270 #define UART_IER_MSI 0x08 /* Enable Modem status interrupt */
1271 #define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */
1272 #define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */
1273 #define UART_IER_RDI 0x01 /* Enable receiver data interrupt */
1276 * These are the definitions for the Modem Control Register
1278 #define UART_MCR_LOOP 0x10 /* Enable loopback test mode */
1279 #define UART_MCR_OUT2 0x08 /* Out2 complement */
1280 #define UART_MCR_OUT1 0x04 /* Out1 complement */
1281 #define UART_MCR_RTS 0x02 /* RTS complement */
1282 #define UART_MCR_DTR 0x01 /* DTR complement */
1285 * These are the definitions for the Modem Status Register
1287 #define UART_MSR_DCD 0x80 /* Data Carrier Detect */
1288 #define UART_MSR_RI 0x40 /* Ring Indicator */
1289 #define UART_MSR_DSR 0x20 /* Data Set Ready */
1290 #define UART_MSR_CTS 0x10 /* Clear to Send */
1291 #define UART_MSR_DDCD 0x08 /* Delta DCD */
1292 #define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */
1293 #define UART_MSR_DDSR 0x02 /* Delta DSR */
1294 #define UART_MSR_DCTS 0x01 /* Delta CTS */
1295 #define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */
1300 #define SSI0_STATUS 0xB1600000
1301 #define SSI_STATUS_BF (1<<4)
1302 #define SSI_STATUS_OF (1<<3)
1303 #define SSI_STATUS_UF (1<<2)
1304 #define SSI_STATUS_D (1<<1)
1305 #define SSI_STATUS_B (1<<0)
1306 #define SSI0_INT 0xB1600004
1307 #define SSI_INT_OI (1<<3)
1308 #define SSI_INT_UI (1<<2)
1309 #define SSI_INT_DI (1<<1)
1310 #define SSI0_INT_ENABLE 0xB1600008
1311 #define SSI_INTE_OIE (1<<3)
1312 #define SSI_INTE_UIE (1<<2)
1313 #define SSI_INTE_DIE (1<<1)
1314 #define SSI0_CONFIG 0xB1600020
1315 #define SSI_CONFIG_AO (1<<24)
1316 #define SSI_CONFIG_DO (1<<23)
1317 #define SSI_CONFIG_ALEN_BIT 20
1318 #define SSI_CONFIG_ALEN_MASK (0x7<<20)
1319 #define SSI_CONFIG_DLEN_BIT 16
1320 #define SSI_CONFIG_DLEN_MASK (0x7<<16)
1321 #define SSI_CONFIG_DD (1<<11)
1322 #define SSI_CONFIG_AD (1<<10)
1323 #define SSI_CONFIG_BM_BIT 8
1324 #define SSI_CONFIG_BM_MASK (0x3<<8)
1325 #define SSI_CONFIG_CE (1<<7)
1326 #define SSI_CONFIG_DP (1<<6)
1327 #define SSI_CONFIG_DL (1<<5)
1328 #define SSI_CONFIG_EP (1<<4)
1329 #define SSI0_ADATA 0xB1600024
1330 #define SSI_AD_D (1<<24)
1331 #define SSI_AD_ADDR_BIT 16
1332 #define SSI_AD_ADDR_MASK (0xff<<16)
1333 #define SSI_AD_DATA_BIT 0
1334 #define SSI_AD_DATA_MASK (0xfff<<0)
1335 #define SSI0_CLKDIV 0xB1600028
1336 #define SSI0_CONTROL 0xB1600100
1337 #define SSI_CONTROL_CD (1<<1)
1338 #define SSI_CONTROL_E (1<<0)
1341 #define SSI1_STATUS 0xB1680000
1342 #define SSI1_INT 0xB1680004
1343 #define SSI1_INT_ENABLE 0xB1680008
1344 #define SSI1_CONFIG 0xB1680020
1345 #define SSI1_ADATA 0xB1680024
1346 #define SSI1_CLKDIV 0xB1680028
1347 #define SSI1_ENABLE 0xB1680100
1350 * Register content definitions
1352 #define SSI_STATUS_BF (1<<4)
1353 #define SSI_STATUS_OF (1<<3)
1354 #define SSI_STATUS_UF (1<<2)
1355 #define SSI_STATUS_D (1<<1)
1356 #define SSI_STATUS_B (1<<0)
1359 #define SSI_INT_OI (1<<3)
1360 #define SSI_INT_UI (1<<2)
1361 #define SSI_INT_DI (1<<1)
1364 #define SSI_INTEN_OIE (1<<3)
1365 #define SSI_INTEN_UIE (1<<2)
1366 #define SSI_INTEN_DIE (1<<1)
1368 #define SSI_CONFIG_AO (1<<24)
1369 #define SSI_CONFIG_DO (1<<23)
1370 #define SSI_CONFIG_ALEN (7<<20)
1371 #define SSI_CONFIG_DLEN (15<<16)
1372 #define SSI_CONFIG_DD (1<<11)
1373 #define SSI_CONFIG_AD (1<<10)
1374 #define SSI_CONFIG_BM (3<<8)
1375 #define SSI_CONFIG_CE (1<<7)
1376 #define SSI_CONFIG_DP (1<<6)
1377 #define SSI_CONFIG_DL (1<<5)
1378 #define SSI_CONFIG_EP (1<<4)
1379 #define SSI_CONFIG_ALEN_N(N) ((N-1)<<20)
1380 #define SSI_CONFIG_DLEN_N(N) ((N-1)<<16)
1381 #define SSI_CONFIG_BM_HI (0<<8)
1382 #define SSI_CONFIG_BM_LO (1<<8)
1383 #define SSI_CONFIG_BM_CY (2<<8)
1385 #define SSI_ADATA_D (1<<24)
1386 #define SSI_ADATA_ADDR (0xFF<<16)
1387 #define SSI_ADATA_DATA (0x0FFF)
1388 #define SSI_ADATA_ADDR_N(N) (N<<16)
1390 #define SSI_ENABLE_CD (1<<1)
1391 #define SSI_ENABLE_E (1<<0)
1394 /* IrDA Controller */
1395 #define IRDA_BASE 0xB0300000
1396 #define IR_RING_PTR_STATUS (IRDA_BASE+0x00)
1397 #define IR_RING_BASE_ADDR_H (IRDA_BASE+0x04)
1398 #define IR_RING_BASE_ADDR_L (IRDA_BASE+0x08)
1399 #define IR_RING_SIZE (IRDA_BASE+0x0C)
1400 #define IR_RING_PROMPT (IRDA_BASE+0x10)
1401 #define IR_RING_ADDR_CMPR (IRDA_BASE+0x14)
1402 #define IR_INT_CLEAR (IRDA_BASE+0x18)
1403 #define IR_CONFIG_1 (IRDA_BASE+0x20)
1404 #define IR_RX_INVERT_LED (1<<0)
1405 #define IR_TX_INVERT_LED (1<<1)
1406 #define IR_ST (1<<2)
1407 #define IR_SF (1<<3)
1408 #define IR_SIR (1<<4)
1409 #define IR_MIR (1<<5)
1410 #define IR_FIR (1<<6)
1411 #define IR_16CRC (1<<7)
1412 #define IR_TD (1<<8)
1413 #define IR_RX_ALL (1<<9)
1414 #define IR_DMA_ENABLE (1<<10)
1415 #define IR_RX_ENABLE (1<<11)
1416 #define IR_TX_ENABLE (1<<12)
1417 #define IR_LOOPBACK (1<<14)
1418 #define IR_SIR_MODE (IR_SIR | IR_DMA_ENABLE | \
1419 IR_RX_ALL | IR_RX_ENABLE | IR_SF | IR_16CRC)
1420 #define IR_SIR_FLAGS (IRDA_BASE+0x24)
1421 #define IR_ENABLE (IRDA_BASE+0x28)
1422 #define IR_RX_STATUS (1<<9)
1423 #define IR_TX_STATUS (1<<10)
1424 #define IR_READ_PHY_CONFIG (IRDA_BASE+0x2C)
1425 #define IR_WRITE_PHY_CONFIG (IRDA_BASE+0x30)
1426 #define IR_MAX_PKT_LEN (IRDA_BASE+0x34)
1427 #define IR_RX_BYTE_CNT (IRDA_BASE+0x38)
1428 #define IR_CONFIG_2 (IRDA_BASE+0x3C)
1429 #define IR_MODE_INV (1<<0)
1430 #define IR_ONE_PIN (1<<1)
1431 #define IR_INTERFACE_CONFIG (IRDA_BASE+0x40)
1434 #define SYS_PINFUNC 0xB190002C
1435 #define SYS_PF_USB (1<<15) /* 2nd USB device/host */
1436 #define SYS_PF_U3 (1<<14) /* GPIO23/U3TXD */
1437 #define SYS_PF_U2 (1<<13) /* GPIO22/U2TXD */
1438 #define SYS_PF_U1 (1<<12) /* GPIO21/U1TXD */
1439 #define SYS_PF_SRC (1<<11) /* GPIO6/SROMCKE */
1440 #define SYS_PF_CK5 (1<<10) /* GPIO3/CLK5 */
1441 #define SYS_PF_CK4 (1<<9) /* GPIO2/CLK4 */
1442 #define SYS_PF_IRF (1<<8) /* GPIO15/IRFIRSEL */
1443 #define SYS_PF_UR3 (1<<7) /* GPIO[14:9]/UART3 */
1444 #define SYS_PF_I2D (1<<6) /* GPIO8/I2SDI */
1445 #define SYS_PF_I2S (1<<5) /* I2S/GPIO[29:31] */
1446 #define SYS_PF_NI2 (1<<4) /* NI2/GPIO[24:28] */
1447 #define SYS_PF_U0 (1<<3) /* U0TXD/GPIO20 */
1448 #define SYS_PF_RD (1<<2) /* IRTXD/GPIO19 */
1449 #define SYS_PF_A97 (1<<1) /* AC97/SSL1 */
1450 #define SYS_PF_S0 (1<<0) /* SSI_0/GPIO[16:18] */
1453 #define SYS_PF_PC (1<<18) /* PCMCIA/GPIO[207:204] */
1454 #define SYS_PF_LCD (1<<17) /* extern lcd/GPIO[203:200] */
1455 #define SYS_PF_CS (1<<16) /* EXTCLK0/32khz to gpio2 */
1456 #define SYS_PF_EX0 (1<<9) /* gpio2/clock */
1458 /* Au1550 Only. Redefines lots of pins */
1459 #define SYS_PF_PSC2_MASK (7 << 17)
1460 #define SYS_PF_PSC2_AC97 (0)
1461 #define SYS_PF_PSC2_SPI (0)
1462 #define SYS_PF_PSC2_I2S (1 << 17)
1463 #define SYS_PF_PSC2_SMBUS (3 << 17)
1464 #define SYS_PF_PSC2_GPIO (7 << 17)
1465 #define SYS_PF_PSC3_MASK (7 << 20)
1466 #define SYS_PF_PSC3_AC97 (0)
1467 #define SYS_PF_PSC3_SPI (0)
1468 #define SYS_PF_PSC3_I2S (1 << 20)
1469 #define SYS_PF_PSC3_SMBUS (3 << 20)
1470 #define SYS_PF_PSC3_GPIO (7 << 20)
1471 #define SYS_PF_PSC1_S1 (1 << 1)
1472 #define SYS_PF_MUST_BE_SET ((1 << 5) | (1 << 2))
1475 #ifdef CONFIG_SOC_AU1200
1476 #define SYS_PINFUNC_DMA (1<<31)
1477 #define SYS_PINFUNC_S0A (1<<30)
1478 #define SYS_PINFUNC_S1A (1<<29)
1479 #define SYS_PINFUNC_LP0 (1<<28)
1480 #define SYS_PINFUNC_LP1 (1<<27)
1481 #define SYS_PINFUNC_LD16 (1<<26)
1482 #define SYS_PINFUNC_LD8 (1<<25)
1483 #define SYS_PINFUNC_LD1 (1<<24)
1484 #define SYS_PINFUNC_LD0 (1<<23)
1485 #define SYS_PINFUNC_P1A (3<<21)
1486 #define SYS_PINFUNC_P1B (1<<20)
1487 #define SYS_PINFUNC_FS3 (1<<19)
1488 #define SYS_PINFUNC_P0A (3<<17)
1489 #define SYS_PINFUNC_CS (1<<16)
1490 #define SYS_PINFUNC_CIM (1<<15)
1491 #define SYS_PINFUNC_P1C (1<<14)
1492 #define SYS_PINFUNC_U1T (1<<12)
1493 #define SYS_PINFUNC_U1R (1<<11)
1494 #define SYS_PINFUNC_EX1 (1<<10)
1495 #define SYS_PINFUNC_EX0 (1<<9)
1496 #define SYS_PINFUNC_U0R (1<<8)
1497 #define SYS_PINFUNC_MC (1<<7)
1498 #define SYS_PINFUNC_S0B (1<<6)
1499 #define SYS_PINFUNC_S0C (1<<5)
1500 #define SYS_PINFUNC_P0B (1<<4)
1501 #define SYS_PINFUNC_U0T (1<<3)
1502 #define SYS_PINFUNC_S1B (1<<2)
1505 #define SYS_TRIOUTRD 0xB1900100
1506 #define SYS_TRIOUTCLR 0xB1900100
1507 #define SYS_OUTPUTRD 0xB1900108
1508 #define SYS_OUTPUTSET 0xB1900108
1509 #define SYS_OUTPUTCLR 0xB190010C
1510 #define SYS_PINSTATERD 0xB1900110
1511 #define SYS_PININPUTEN 0xB1900110
1513 /* GPIO2, Au1500, Au1550 only */
1514 #define GPIO2_BASE 0xB1700000
1515 #define GPIO2_DIR (GPIO2_BASE + 0)
1516 #define GPIO2_OUTPUT (GPIO2_BASE + 8)
1517 #define GPIO2_PINSTATE (GPIO2_BASE + 0xC)
1518 #define GPIO2_INTENABLE (GPIO2_BASE + 0x10)
1519 #define GPIO2_ENABLE (GPIO2_BASE + 0x14)
1521 /* Power Management */
1522 #define SYS_SCRATCH0 0xB1900018
1523 #define SYS_SCRATCH1 0xB190001C
1524 #define SYS_WAKEMSK 0xB1900034
1525 #define SYS_ENDIAN 0xB1900038
1526 #define SYS_POWERCTRL 0xB190003C
1527 #define SYS_WAKESRC 0xB190005C
1528 #define SYS_SLPPWR 0xB1900078
1529 #define SYS_SLEEP 0xB190007C
1531 /* Clock Controller */
1532 #define SYS_FREQCTRL0 0xB1900020
1533 #define SYS_FC_FRDIV2_BIT 22
1534 #define SYS_FC_FRDIV2_MASK (0xff << SYS_FC_FRDIV2_BIT)
1535 #define SYS_FC_FE2 (1<<21)
1536 #define SYS_FC_FS2 (1<<20)
1537 #define SYS_FC_FRDIV1_BIT 12
1538 #define SYS_FC_FRDIV1_MASK (0xff << SYS_FC_FRDIV1_BIT)
1539 #define SYS_FC_FE1 (1<<11)
1540 #define SYS_FC_FS1 (1<<10)
1541 #define SYS_FC_FRDIV0_BIT 2
1542 #define SYS_FC_FRDIV0_MASK (0xff << SYS_FC_FRDIV0_BIT)
1543 #define SYS_FC_FE0 (1<<1)
1544 #define SYS_FC_FS0 (1<<0)
1545 #define SYS_FREQCTRL1 0xB1900024
1546 #define SYS_FC_FRDIV5_BIT 22
1547 #define SYS_FC_FRDIV5_MASK (0xff << SYS_FC_FRDIV5_BIT)
1548 #define SYS_FC_FE5 (1<<21)
1549 #define SYS_FC_FS5 (1<<20)
1550 #define SYS_FC_FRDIV4_BIT 12
1551 #define SYS_FC_FRDIV4_MASK (0xff << SYS_FC_FRDIV4_BIT)
1552 #define SYS_FC_FE4 (1<<11)
1553 #define SYS_FC_FS4 (1<<10)
1554 #define SYS_FC_FRDIV3_BIT 2
1555 #define SYS_FC_FRDIV3_MASK (0xff << SYS_FC_FRDIV3_BIT)
1556 #define SYS_FC_FE3 (1<<1)
1557 #define SYS_FC_FS3 (1<<0)
1558 #define SYS_CLKSRC 0xB1900028
1559 #define SYS_CS_ME1_BIT 27
1560 #define SYS_CS_ME1_MASK (0x7<<SYS_CS_ME1_BIT)
1561 #define SYS_CS_DE1 (1<<26)
1562 #define SYS_CS_CE1 (1<<25)
1563 #define SYS_CS_ME0_BIT 22
1564 #define SYS_CS_ME0_MASK (0x7<<SYS_CS_ME0_BIT)
1565 #define SYS_CS_DE0 (1<<21)
1566 #define SYS_CS_CE0 (1<<20)
1567 #define SYS_CS_MI2_BIT 17
1568 #define SYS_CS_MI2_MASK (0x7<<SYS_CS_MI2_BIT)
1569 #define SYS_CS_DI2 (1<<16)
1570 #define SYS_CS_CI2 (1<<15)
1571 #ifdef CONFIG_SOC_AU1100
1572 #define SYS_CS_ML_BIT 7
1573 #define SYS_CS_ML_MASK (0x7<<SYS_CS_ML_BIT)
1574 #define SYS_CS_DL (1<<6)
1575 #define SYS_CS_CL (1<<5)
1577 #define SYS_CS_MUH_BIT 12
1578 #define SYS_CS_MUH_MASK (0x7<<SYS_CS_MUH_BIT)
1579 #define SYS_CS_DUH (1<<11)
1580 #define SYS_CS_CUH (1<<10)
1581 #define SYS_CS_MUD_BIT 7
1582 #define SYS_CS_MUD_MASK (0x7<<SYS_CS_MUD_BIT)
1583 #define SYS_CS_DUD (1<<6)
1584 #define SYS_CS_CUD (1<<5)
1586 #define SYS_CS_MIR_BIT 2
1587 #define SYS_CS_MIR_MASK (0x7<<SYS_CS_MIR_BIT)
1588 #define SYS_CS_DIR (1<<1)
1589 #define SYS_CS_CIR (1<<0)
1591 #define SYS_CS_MUX_AUX 0x1
1592 #define SYS_CS_MUX_FQ0 0x2
1593 #define SYS_CS_MUX_FQ1 0x3
1594 #define SYS_CS_MUX_FQ2 0x4
1595 #define SYS_CS_MUX_FQ3 0x5
1596 #define SYS_CS_MUX_FQ4 0x6
1597 #define SYS_CS_MUX_FQ5 0x7
1598 #define SYS_CPUPLL 0xB1900060
1599 #define SYS_AUXPLL 0xB1900064
1601 /* AC97 Controller */
1602 #define AC97C_CONFIG 0xB0000000
1603 #define AC97C_RECV_SLOTS_BIT 13
1604 #define AC97C_RECV_SLOTS_MASK (0x3ff << AC97C_RECV_SLOTS_BIT)
1605 #define AC97C_XMIT_SLOTS_BIT 3
1606 #define AC97C_XMIT_SLOTS_MASK (0x3ff << AC97C_XMIT_SLOTS_BIT)
1607 #define AC97C_SG (1<<2)
1608 #define AC97C_SYNC (1<<1)
1609 #define AC97C_RESET (1<<0)
1610 #define AC97C_STATUS 0xB0000004
1611 #define AC97C_XU (1<<11)
1612 #define AC97C_XO (1<<10)
1613 #define AC97C_RU (1<<9)
1614 #define AC97C_RO (1<<8)
1615 #define AC97C_READY (1<<7)
1616 #define AC97C_CP (1<<6)
1617 #define AC97C_TR (1<<5)
1618 #define AC97C_TE (1<<4)
1619 #define AC97C_TF (1<<3)
1620 #define AC97C_RR (1<<2)
1621 #define AC97C_RE (1<<1)
1622 #define AC97C_RF (1<<0)
1623 #define AC97C_DATA 0xB0000008
1624 #define AC97C_CMD 0xB000000C
1625 #define AC97C_WD_BIT 16
1626 #define AC97C_READ (1<<7)
1627 #define AC97C_INDEX_MASK 0x7f
1628 #define AC97C_CNTRL 0xB0000010
1629 #define AC97C_RS (1<<1)
1630 #define AC97C_CE (1<<0)
1633 /* Secure Digital (SD) Controller */
1634 #define SD0_XMIT_FIFO 0xB0600000
1635 #define SD0_RECV_FIFO 0xB0600004
1636 #define SD1_XMIT_FIFO 0xB0680000
1637 #define SD1_RECV_FIFO 0xB0680004
1639 #if defined (CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1550)
1640 /* Au1500 PCI Controller */
1641 #define Au1500_CFG_BASE 0xB4005000 // virtual, kseg0 addr
1642 #define Au1500_PCI_CMEM (Au1500_CFG_BASE + 0)
1643 #define Au1500_PCI_CFG (Au1500_CFG_BASE + 4)
1644 #define PCI_ERROR ((1<<22) | (1<<23) | (1<<24) | (1<<25) | (1<<26) | (1<<27))
1645 #define Au1500_PCI_B2BMASK_CCH (Au1500_CFG_BASE + 8)
1646 #define Au1500_PCI_B2B0_VID (Au1500_CFG_BASE + 0xC)
1647 #define Au1500_PCI_B2B1_ID (Au1500_CFG_BASE + 0x10)
1648 #define Au1500_PCI_MWMASK_DEV (Au1500_CFG_BASE + 0x14)
1649 #define Au1500_PCI_MWBASE_REV_CCL (Au1500_CFG_BASE + 0x18)
1650 #define Au1500_PCI_ERR_ADDR (Au1500_CFG_BASE + 0x1C)
1651 #define Au1500_PCI_SPEC_INTACK (Au1500_CFG_BASE + 0x20)
1652 #define Au1500_PCI_ID (Au1500_CFG_BASE + 0x100)
1653 #define Au1500_PCI_STATCMD (Au1500_CFG_BASE + 0x104)
1654 #define Au1500_PCI_CLASSREV (Au1500_CFG_BASE + 0x108)
1655 #define Au1500_PCI_HDRTYPE (Au1500_CFG_BASE + 0x10C)
1656 #define Au1500_PCI_MBAR (Au1500_CFG_BASE + 0x110)
1658 #define Au1500_PCI_HDR 0xB4005100 // virtual, kseg0 addr
1660 /* All of our structures, like pci resource, have 32 bit members.
1661 * Drivers are expected to do an ioremap on the PCI MEM resource, but it's
1662 * hard to store 0x4 0000 0000 in a 32 bit type. We require a small patch
1663 * to __ioremap to check for addresses between (u32)Au1500_PCI_MEM_START and
1664 * (u32)Au1500_PCI_MEM_END and change those to the full 36 bit PCI MEM
1665 * addresses. For PCI IO, it's simpler because we get to do the ioremap
1666 * ourselves and then adjust the device's resources.
1668 #define Au1500_EXT_CFG 0x600000000ULL
1669 #define Au1500_EXT_CFG_TYPE1 0x680000000ULL
1670 #define Au1500_PCI_IO_START 0x500000000ULL
1671 #define Au1500_PCI_IO_END 0x5000FFFFFULL
1672 #define Au1500_PCI_MEM_START 0x440000000ULL
1673 #define Au1500_PCI_MEM_END 0x44FFFFFFFULL
1675 #define PCI_IO_START (Au1500_PCI_IO_START + 0x1000)
1676 #define PCI_IO_END (Au1500_PCI_IO_END)
1677 #define PCI_MEM_START (Au1500_PCI_MEM_START)
1678 #define PCI_MEM_END (Au1500_PCI_MEM_END)
1679 #define PCI_FIRST_DEVFN (0<<3)
1680 #define PCI_LAST_DEVFN (19<<3)
1682 #define IOPORT_RESOURCE_START 0x00001000 /* skip legacy probing */
1683 #define IOPORT_RESOURCE_END 0xffffffff
1684 #define IOMEM_RESOURCE_START 0x10000000
1685 #define IOMEM_RESOURCE_END 0xffffffff
1688 * Borrowed from the PPC arch:
1689 * The following macro is used to lookup irqs in a standard table
1690 * format for those PPC systems that do not already have PCI
1691 * interrupts properly routed.
1693 /* FIXME - double check this from asm-ppc/pci-bridge.h */
1694 #define PCI_IRQ_TABLE_LOOKUP \
1695 ({ long _ctl_ = -1; \
1696 if (idsel >= min_idsel && idsel <= max_idsel && pin <= irqs_per_slot) \
1697 _ctl_ = pci_irq_table[idsel - min_idsel][pin-1]; \
1701 #else /* Au1000 and Au1100 and Au1200 */
1703 /* don't allow any legacy ports probing */
1704 #define IOPORT_RESOURCE_START 0x10000000
1705 #define IOPORT_RESOURCE_END 0xffffffff
1706 #define IOMEM_RESOURCE_START 0x10000000
1707 #define IOMEM_RESOURCE_END 0xffffffff
1709 #define PCI_IO_START 0
1710 #define PCI_IO_END 0
1711 #define PCI_MEM_START 0
1712 #define PCI_MEM_END 0
1713 #define PCI_FIRST_DEVFN 0
1714 #define PCI_LAST_DEVFN 0
1718 #ifndef _LANGUAGE_ASSEMBLY
1719 typedef volatile struct
1721 /* 0x0000 */ u32 toytrim;
1722 /* 0x0004 */ u32 toywrite;
1723 /* 0x0008 */ u32 toymatch0;
1724 /* 0x000C */ u32 toymatch1;
1725 /* 0x0010 */ u32 toymatch2;
1726 /* 0x0014 */ u32 cntrctrl;
1727 /* 0x0018 */ u32 scratch0;
1728 /* 0x001C */ u32 scratch1;
1729 /* 0x0020 */ u32 freqctrl0;
1730 /* 0x0024 */ u32 freqctrl1;
1731 /* 0x0028 */ u32 clksrc;
1732 /* 0x002C */ u32 pinfunc;
1733 /* 0x0030 */ u32 reserved0;
1734 /* 0x0034 */ u32 wakemsk;
1735 /* 0x0038 */ u32 endian;
1736 /* 0x003C */ u32 powerctrl;
1737 /* 0x0040 */ u32 toyread;
1738 /* 0x0044 */ u32 rtctrim;
1739 /* 0x0048 */ u32 rtcwrite;
1740 /* 0x004C */ u32 rtcmatch0;
1741 /* 0x0050 */ u32 rtcmatch1;
1742 /* 0x0054 */ u32 rtcmatch2;
1743 /* 0x0058 */ u32 rtcread;
1744 /* 0x005C */ u32 wakesrc;
1745 /* 0x0060 */ u32 cpupll;
1746 /* 0x0064 */ u32 auxpll;
1747 /* 0x0068 */ u32 reserved1;
1748 /* 0x006C */ u32 reserved2;
1749 /* 0x0070 */ u32 reserved3;
1750 /* 0x0074 */ u32 reserved4;
1751 /* 0x0078 */ u32 slppwr;
1752 /* 0x007C */ u32 sleep;
1753 /* 0x0080 */ u32 reserved5[32];
1754 /* 0x0100 */ u32 trioutrd;
1755 #define trioutclr trioutrd
1756 /* 0x0104 */ u32 reserved6;
1757 /* 0x0108 */ u32 outputrd;
1758 #define outputset outputrd
1759 /* 0x010C */ u32 outputclr;
1760 /* 0x0110 */ u32 pinstaterd;
1761 #define pininputen pinstaterd
1765 static AU1X00_SYS* const sys = (AU1X00_SYS *)SYS_BASE;
1768 /* Processor information base on prid.
1769 * Copied from PowerPC.
1771 #ifndef _LANGUAGE_ASSEMBLY
1773 /* CPU is matched via (PRID & prid_mask) == prid_value */
1774 unsigned int prid_mask;
1775 unsigned int prid_value;
1778 unsigned char cpu_od; /* Set Config[OD] */
1779 unsigned char cpu_bclk; /* Enable BCLK switching */
1782 extern struct cpu_spec cpu_specs[];
1783 extern struct cpu_spec *cur_cpu_spec[];
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