1 /************************************************************************
3 * This file is subject to the terms and conditions of the GNU Public
4 * License. See the file "COPYING" in the main directory of this archive
7 * Non-GPL License also available as part of VisualDSP++
8 * http://www.analog.com/processors/resources/crosscore/visualDspDevSoftware.html
10 * (c) Copyright 2001-2005 Analog Devices, Inc. All rights reserved
12 * This file under source code control, please send bugs or changes to:
13 * dsptools.support@analog.com
15 ************************************************************************/
17 * File: include/asm-blackfin/mach-bf533/defBF532.h
28 * Bugs: Enter bugs at http://blackfin.uclinux.org/
30 * This program is free software; you can redistribute it and/or modify
31 * it under the terms of the GNU General Public License as published by
32 * the Free Software Foundation; either version 2, or (at your option)
35 * This program is distributed in the hope that it will be useful,
36 * but WITHOUT ANY WARRANTY; without even the implied warranty of
37 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
38 * GNU General Public License for more details.
40 * You should have received a copy of the GNU General Public License
41 * along with this program; see the file COPYING.
42 * If not, write to the Free Software Foundation,
43 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
45 /* SYSTEM & MM REGISTER BIT & ADDRESS DEFINITIONS FOR ADSP-BF532 */
50 #if !defined(__ADSPLPBLACKFIN__)
51 #warning defBF532.h should only be included for 532 compatible chips
54 /* include all Core registers and bit definitions */
55 #include <asm/mach-common/def_LPBlackfin.h>
57 /*********************************************************************************** */
58 /* System MMR Register Map */
59 /*********************************************************************************** */
60 /* Clock and System Control (0xFFC00000 - 0xFFC000FF) */
62 #define PLL_CTL 0xFFC00000 /* PLL Control register (16-bit) */
63 #define PLL_DIV 0xFFC00004 /* PLL Divide Register (16-bit) */
64 #define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register (16-bit) */
65 #define PLL_STAT 0xFFC0000C /* PLL Status register (16-bit) */
66 #define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count register (16-bit) */
67 #define CHIPID 0xFFC00014 /* Chip ID Register */
68 #define SWRST 0xFFC00100 /* Software Reset Register (16-bit) */
69 #define SYSCR 0xFFC00104 /* System Configuration registe */
71 /* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */
72 #define SIC_RVECT 0xFFC00108 /* Interrupt Reset Vector Address Register */
73 #define SIC_IMASK 0xFFC0010C /* Interrupt Mask Register */
74 #define SIC_IAR0 0xFFC00110 /* Interrupt Assignment Register 0 */
75 #define SIC_IAR1 0xFFC00114 /* Interrupt Assignment Register 1 */
76 #define SIC_IAR2 0xFFC00118 /* Interrupt Assignment Register 2 */
77 #define SIC_ISR 0xFFC00120 /* Interrupt Status Register */
78 #define SIC_IWR 0xFFC00124 /* Interrupt Wakeup Register */
80 /* Watchdog Timer (0xFFC00200 - 0xFFC002FF) */
81 #define WDOG_CTL 0xFFC00200 /* Watchdog Control Register */
82 #define WDOG_CNT 0xFFC00204 /* Watchdog Count Register */
83 #define WDOG_STAT 0xFFC00208 /* Watchdog Status Register */
85 /* Real Time Clock (0xFFC00300 - 0xFFC003FF) */
86 #define RTC_STAT 0xFFC00300 /* RTC Status Register */
87 #define RTC_ICTL 0xFFC00304 /* RTC Interrupt Control Register */
88 #define RTC_ISTAT 0xFFC00308 /* RTC Interrupt Status Register */
89 #define RTC_SWCNT 0xFFC0030C /* RTC Stopwatch Count Register */
90 #define RTC_ALARM 0xFFC00310 /* RTC Alarm Time Register */
91 #define RTC_FAST 0xFFC00314 /* RTC Prescaler Enable Register */
92 #define RTC_PREN 0xFFC00314 /* RTC Prescaler Enable Register (alternate macro) */
94 /* UART Controller (0xFFC00400 - 0xFFC004FF) */
95 #define UART_THR 0xFFC00400 /* Transmit Holding register */
96 #define UART_RBR 0xFFC00400 /* Receive Buffer register */
97 #define UART_DLL 0xFFC00400 /* Divisor Latch (Low-Byte) */
98 #define UART_IER 0xFFC00404 /* Interrupt Enable Register */
99 #define UART_DLH 0xFFC00404 /* Divisor Latch (High-Byte) */
100 #define UART_IIR 0xFFC00408 /* Interrupt Identification Register */
101 #define UART_LCR 0xFFC0040C /* Line Control Register */
102 #define UART_MCR 0xFFC00410 /* Modem Control Register */
103 #define UART_LSR 0xFFC00414 /* Line Status Register */
105 #define UART_MSR 0xFFC00418 /* Modem Status Register (UNUSED in ADSP-BF532) */
107 #define UART_SCR 0xFFC0041C /* SCR Scratch Register */
108 #define UART_GCTL 0xFFC00424 /* Global Control Register */
110 /* SPI Controller (0xFFC00500 - 0xFFC005FF) */
111 #define SPI_CTL 0xFFC00500 /* SPI Control Register */
112 #define SPI_FLG 0xFFC00504 /* SPI Flag register */
113 #define SPI_STAT 0xFFC00508 /* SPI Status register */
114 #define SPI_TDBR 0xFFC0050C /* SPI Transmit Data Buffer Register */
115 #define SPI_RDBR 0xFFC00510 /* SPI Receive Data Buffer Register */
116 #define SPI_BAUD 0xFFC00514 /* SPI Baud rate Register */
117 #define SPI_SHADOW 0xFFC00518 /* SPI_RDBR Shadow Register */
119 /* TIMER 0, 1, 2 Registers (0xFFC00600 - 0xFFC006FF) */
121 #define TIMER0_CONFIG 0xFFC00600 /* Timer 0 Configuration Register */
122 #define TIMER0_COUNTER 0xFFC00604 /* Timer 0 Counter Register */
123 #define TIMER0_PERIOD 0xFFC00608 /* Timer 0 Period Register */
124 #define TIMER0_WIDTH 0xFFC0060C /* Timer 0 Width Register */
126 #define TIMER1_CONFIG 0xFFC00610 /* Timer 1 Configuration Register */
127 #define TIMER1_COUNTER 0xFFC00614 /* Timer 1 Counter Register */
128 #define TIMER1_PERIOD 0xFFC00618 /* Timer 1 Period Register */
129 #define TIMER1_WIDTH 0xFFC0061C /* Timer 1 Width Register */
131 #define TIMER2_CONFIG 0xFFC00620 /* Timer 2 Configuration Register */
132 #define TIMER2_COUNTER 0xFFC00624 /* Timer 2 Counter Register */
133 #define TIMER2_PERIOD 0xFFC00628 /* Timer 2 Period Register */
134 #define TIMER2_WIDTH 0xFFC0062C /* Timer 2 Width Register */
136 #define TIMER_ENABLE 0xFFC00640 /* Timer Enable Register */
137 #define TIMER_DISABLE 0xFFC00644 /* Timer Disable Register */
138 #define TIMER_STATUS 0xFFC00648 /* Timer Status Register */
140 /* General Purpose IO (0xFFC00700 - 0xFFC007FF) */
142 #define FIO_FLAG_D 0xFFC00700 /* Flag Mask to directly specify state of pins */
143 #define FIO_FLAG_C 0xFFC00704 /* Peripheral Interrupt Flag Register (clear) */
144 #define FIO_FLAG_S 0xFFC00708 /* Peripheral Interrupt Flag Register (set) */
145 #define FIO_FLAG_T 0xFFC0070C /* Flag Mask to directly toggle state of pins */
146 #define FIO_MASKA_D 0xFFC00710 /* Flag Mask Interrupt A Register (set directly) */
147 #define FIO_MASKA_C 0xFFC00714 /* Flag Mask Interrupt A Register (clear) */
148 #define FIO_MASKA_S 0xFFC00718 /* Flag Mask Interrupt A Register (set) */
149 #define FIO_MASKA_T 0xFFC0071C /* Flag Mask Interrupt A Register (toggle) */
150 #define FIO_MASKB_D 0xFFC00720 /* Flag Mask Interrupt B Register (set directly) */
151 #define FIO_MASKB_C 0xFFC00724 /* Flag Mask Interrupt B Register (clear) */
152 #define FIO_MASKB_S 0xFFC00728 /* Flag Mask Interrupt B Register (set) */
153 #define FIO_MASKB_T 0xFFC0072C /* Flag Mask Interrupt B Register (toggle) */
154 #define FIO_DIR 0xFFC00730 /* Peripheral Flag Direction Register */
155 #define FIO_POLAR 0xFFC00734 /* Flag Source Polarity Register */
156 #define FIO_EDGE 0xFFC00738 /* Flag Source Sensitivity Register */
157 #define FIO_BOTH 0xFFC0073C /* Flag Set on BOTH Edges Register */
158 #define FIO_INEN 0xFFC00740 /* Flag Input Enable Register */
160 /* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */
161 #define SPORT0_TCR1 0xFFC00800 /* SPORT0 Transmit Configuration 1 Register */
162 #define SPORT0_TCR2 0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */
163 #define SPORT0_TCLKDIV 0xFFC00808 /* SPORT0 Transmit Clock Divider */
164 #define SPORT0_TFSDIV 0xFFC0080C /* SPORT0 Transmit Frame Sync Divider */
165 #define SPORT0_TX 0xFFC00810 /* SPORT0 TX Data Register */
166 #define SPORT0_RX 0xFFC00818 /* SPORT0 RX Data Register */
167 #define SPORT0_RCR1 0xFFC00820 /* SPORT0 Transmit Configuration 1 Register */
168 #define SPORT0_RCR2 0xFFC00824 /* SPORT0 Transmit Configuration 2 Register */
169 #define SPORT0_RCLKDIV 0xFFC00828 /* SPORT0 Receive Clock Divider */
170 #define SPORT0_RFSDIV 0xFFC0082C /* SPORT0 Receive Frame Sync Divider */
171 #define SPORT0_STAT 0xFFC00830 /* SPORT0 Status Register */
172 #define SPORT0_CHNL 0xFFC00834 /* SPORT0 Current Channel Register */
173 #define SPORT0_MCMC1 0xFFC00838 /* SPORT0 Multi-Channel Configuration Register 1 */
174 #define SPORT0_MCMC2 0xFFC0083C /* SPORT0 Multi-Channel Configuration Register 2 */
175 #define SPORT0_MTCS0 0xFFC00840 /* SPORT0 Multi-Channel Transmit Select Register 0 */
176 #define SPORT0_MTCS1 0xFFC00844 /* SPORT0 Multi-Channel Transmit Select Register 1 */
177 #define SPORT0_MTCS2 0xFFC00848 /* SPORT0 Multi-Channel Transmit Select Register 2 */
178 #define SPORT0_MTCS3 0xFFC0084C /* SPORT0 Multi-Channel Transmit Select Register 3 */
179 #define SPORT0_MRCS0 0xFFC00850 /* SPORT0 Multi-Channel Receive Select Register 0 */
180 #define SPORT0_MRCS1 0xFFC00854 /* SPORT0 Multi-Channel Receive Select Register 1 */
181 #define SPORT0_MRCS2 0xFFC00858 /* SPORT0 Multi-Channel Receive Select Register 2 */
182 #define SPORT0_MRCS3 0xFFC0085C /* SPORT0 Multi-Channel Receive Select Register 3 */
184 /* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */
185 #define SPORT1_TCR1 0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */
186 #define SPORT1_TCR2 0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */
187 #define SPORT1_TCLKDIV 0xFFC00908 /* SPORT1 Transmit Clock Divider */
188 #define SPORT1_TFSDIV 0xFFC0090C /* SPORT1 Transmit Frame Sync Divider */
189 #define SPORT1_TX 0xFFC00910 /* SPORT1 TX Data Register */
190 #define SPORT1_RX 0xFFC00918 /* SPORT1 RX Data Register */
191 #define SPORT1_RCR1 0xFFC00920 /* SPORT1 Transmit Configuration 1 Register */
192 #define SPORT1_RCR2 0xFFC00924 /* SPORT1 Transmit Configuration 2 Register */
193 #define SPORT1_RCLKDIV 0xFFC00928 /* SPORT1 Receive Clock Divider */
194 #define SPORT1_RFSDIV 0xFFC0092C /* SPORT1 Receive Frame Sync Divider */
195 #define SPORT1_STAT 0xFFC00930 /* SPORT1 Status Register */
196 #define SPORT1_CHNL 0xFFC00934 /* SPORT1 Current Channel Register */
197 #define SPORT1_MCMC1 0xFFC00938 /* SPORT1 Multi-Channel Configuration Register 1 */
198 #define SPORT1_MCMC2 0xFFC0093C /* SPORT1 Multi-Channel Configuration Register 2 */
199 #define SPORT1_MTCS0 0xFFC00940 /* SPORT1 Multi-Channel Transmit Select Register 0 */
200 #define SPORT1_MTCS1 0xFFC00944 /* SPORT1 Multi-Channel Transmit Select Register 1 */
201 #define SPORT1_MTCS2 0xFFC00948 /* SPORT1 Multi-Channel Transmit Select Register 2 */
202 #define SPORT1_MTCS3 0xFFC0094C /* SPORT1 Multi-Channel Transmit Select Register 3 */
203 #define SPORT1_MRCS0 0xFFC00950 /* SPORT1 Multi-Channel Receive Select Register 0 */
204 #define SPORT1_MRCS1 0xFFC00954 /* SPORT1 Multi-Channel Receive Select Register 1 */
205 #define SPORT1_MRCS2 0xFFC00958 /* SPORT1 Multi-Channel Receive Select Register 2 */
206 #define SPORT1_MRCS3 0xFFC0095C /* SPORT1 Multi-Channel Receive Select Register 3 */
208 /* Asynchronous Memory Controller - External Bus Interface Unit */
209 #define EBIU_AMGCTL 0xFFC00A00 /* Asynchronous Memory Global Control Register */
210 #define EBIU_AMBCTL0 0xFFC00A04 /* Asynchronous Memory Bank Control Register 0 */
211 #define EBIU_AMBCTL1 0xFFC00A08 /* Asynchronous Memory Bank Control Register 1 */
213 /* SDRAM Controller External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */
215 #define EBIU_SDGCTL 0xFFC00A10 /* SDRAM Global Control Register */
216 #define EBIU_SDBCTL 0xFFC00A14 /* SDRAM Bank Control Register */
217 #define EBIU_SDRRC 0xFFC00A18 /* SDRAM Refresh Rate Control Register */
218 #define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */
220 /* DMA Traffic controls */
221 #define DMA_TCPER 0xFFC00B0C /* Traffic Control Periods Register */
222 #define DMA_TCCNT 0xFFC00B10 /* Traffic Control Current Counts Register */
223 #define DMA_TC_PER 0xFFC00B0C /* Traffic Control Periods Register */
224 #define DMA_TC_CNT 0xFFC00B10 /* Traffic Control Current Counts Register */
226 /* DMA Controller (0xFFC00C00 - 0xFFC00FFF) */
227 #define DMA0_CONFIG 0xFFC00C08 /* DMA Channel 0 Configuration Register */
228 #define DMA0_NEXT_DESC_PTR 0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */
229 #define DMA0_START_ADDR 0xFFC00C04 /* DMA Channel 0 Start Address Register */
230 #define DMA0_X_COUNT 0xFFC00C10 /* DMA Channel 0 X Count Register */
231 #define DMA0_Y_COUNT 0xFFC00C18 /* DMA Channel 0 Y Count Register */
232 #define DMA0_X_MODIFY 0xFFC00C14 /* DMA Channel 0 X Modify Register */
233 #define DMA0_Y_MODIFY 0xFFC00C1C /* DMA Channel 0 Y Modify Register */
234 #define DMA0_CURR_DESC_PTR 0xFFC00C20 /* DMA Channel 0 Current Descriptor Pointer Register */
235 #define DMA0_CURR_ADDR 0xFFC00C24 /* DMA Channel 0 Current Address Register */
236 #define DMA0_CURR_X_COUNT 0xFFC00C30 /* DMA Channel 0 Current X Count Register */
237 #define DMA0_CURR_Y_COUNT 0xFFC00C38 /* DMA Channel 0 Current Y Count Register */
238 #define DMA0_IRQ_STATUS 0xFFC00C28 /* DMA Channel 0 Interrupt/Status Register */
239 #define DMA0_PERIPHERAL_MAP 0xFFC00C2C /* DMA Channel 0 Peripheral Map Register */
241 #define DMA1_CONFIG 0xFFC00C48 /* DMA Channel 1 Configuration Register */
242 #define DMA1_NEXT_DESC_PTR 0xFFC00C40 /* DMA Channel 1 Next Descriptor Pointer Register */
243 #define DMA1_START_ADDR 0xFFC00C44 /* DMA Channel 1 Start Address Register */
244 #define DMA1_X_COUNT 0xFFC00C50 /* DMA Channel 1 X Count Register */
245 #define DMA1_Y_COUNT 0xFFC00C58 /* DMA Channel 1 Y Count Register */
246 #define DMA1_X_MODIFY 0xFFC00C54 /* DMA Channel 1 X Modify Register */
247 #define DMA1_Y_MODIFY 0xFFC00C5C /* DMA Channel 1 Y Modify Register */
248 #define DMA1_CURR_DESC_PTR 0xFFC00C60 /* DMA Channel 1 Current Descriptor Pointer Register */
249 #define DMA1_CURR_ADDR 0xFFC00C64 /* DMA Channel 1 Current Address Register */
250 #define DMA1_CURR_X_COUNT 0xFFC00C70 /* DMA Channel 1 Current X Count Register */
251 #define DMA1_CURR_Y_COUNT 0xFFC00C78 /* DMA Channel 1 Current Y Count Register */
252 #define DMA1_IRQ_STATUS 0xFFC00C68 /* DMA Channel 1 Interrupt/Status Register */
253 #define DMA1_PERIPHERAL_MAP 0xFFC00C6C /* DMA Channel 1 Peripheral Map Register */
255 #define DMA2_CONFIG 0xFFC00C88 /* DMA Channel 2 Configuration Register */
256 #define DMA2_NEXT_DESC_PTR 0xFFC00C80 /* DMA Channel 2 Next Descriptor Pointer Register */
257 #define DMA2_START_ADDR 0xFFC00C84 /* DMA Channel 2 Start Address Register */
258 #define DMA2_X_COUNT 0xFFC00C90 /* DMA Channel 2 X Count Register */
259 #define DMA2_Y_COUNT 0xFFC00C98 /* DMA Channel 2 Y Count Register */
260 #define DMA2_X_MODIFY 0xFFC00C94 /* DMA Channel 2 X Modify Register */
261 #define DMA2_Y_MODIFY 0xFFC00C9C /* DMA Channel 2 Y Modify Register */
262 #define DMA2_CURR_DESC_PTR 0xFFC00CA0 /* DMA Channel 2 Current Descriptor Pointer Register */
263 #define DMA2_CURR_ADDR 0xFFC00CA4 /* DMA Channel 2 Current Address Register */
264 #define DMA2_CURR_X_COUNT 0xFFC00CB0 /* DMA Channel 2 Current X Count Register */
265 #define DMA2_CURR_Y_COUNT 0xFFC00CB8 /* DMA Channel 2 Current Y Count Register */
266 #define DMA2_IRQ_STATUS 0xFFC00CA8 /* DMA Channel 2 Interrupt/Status Register */
267 #define DMA2_PERIPHERAL_MAP 0xFFC00CAC /* DMA Channel 2 Peripheral Map Register */
269 #define DMA3_CONFIG 0xFFC00CC8 /* DMA Channel 3 Configuration Register */
270 #define DMA3_NEXT_DESC_PTR 0xFFC00CC0 /* DMA Channel 3 Next Descriptor Pointer Register */
271 #define DMA3_START_ADDR 0xFFC00CC4 /* DMA Channel 3 Start Address Register */
272 #define DMA3_X_COUNT 0xFFC00CD0 /* DMA Channel 3 X Count Register */
273 #define DMA3_Y_COUNT 0xFFC00CD8 /* DMA Channel 3 Y Count Register */
274 #define DMA3_X_MODIFY 0xFFC00CD4 /* DMA Channel 3 X Modify Register */
275 #define DMA3_Y_MODIFY 0xFFC00CDC /* DMA Channel 3 Y Modify Register */
276 #define DMA3_CURR_DESC_PTR 0xFFC00CE0 /* DMA Channel 3 Current Descriptor Pointer Register */
277 #define DMA3_CURR_ADDR 0xFFC00CE4 /* DMA Channel 3 Current Address Register */
278 #define DMA3_CURR_X_COUNT 0xFFC00CF0 /* DMA Channel 3 Current X Count Register */
279 #define DMA3_CURR_Y_COUNT 0xFFC00CF8 /* DMA Channel 3 Current Y Count Register */
280 #define DMA3_IRQ_STATUS 0xFFC00CE8 /* DMA Channel 3 Interrupt/Status Register */
281 #define DMA3_PERIPHERAL_MAP 0xFFC00CEC /* DMA Channel 3 Peripheral Map Register */
283 #define DMA4_CONFIG 0xFFC00D08 /* DMA Channel 4 Configuration Register */
284 #define DMA4_NEXT_DESC_PTR 0xFFC00D00 /* DMA Channel 4 Next Descriptor Pointer Register */
285 #define DMA4_START_ADDR 0xFFC00D04 /* DMA Channel 4 Start Address Register */
286 #define DMA4_X_COUNT 0xFFC00D10 /* DMA Channel 4 X Count Register */
287 #define DMA4_Y_COUNT 0xFFC00D18 /* DMA Channel 4 Y Count Register */
288 #define DMA4_X_MODIFY 0xFFC00D14 /* DMA Channel 4 X Modify Register */
289 #define DMA4_Y_MODIFY 0xFFC00D1C /* DMA Channel 4 Y Modify Register */
290 #define DMA4_CURR_DESC_PTR 0xFFC00D20 /* DMA Channel 4 Current Descriptor Pointer Register */
291 #define DMA4_CURR_ADDR 0xFFC00D24 /* DMA Channel 4 Current Address Register */
292 #define DMA4_CURR_X_COUNT 0xFFC00D30 /* DMA Channel 4 Current X Count Register */
293 #define DMA4_CURR_Y_COUNT 0xFFC00D38 /* DMA Channel 4 Current Y Count Register */
294 #define DMA4_IRQ_STATUS 0xFFC00D28 /* DMA Channel 4 Interrupt/Status Register */
295 #define DMA4_PERIPHERAL_MAP 0xFFC00D2C /* DMA Channel 4 Peripheral Map Register */
297 #define DMA5_CONFIG 0xFFC00D48 /* DMA Channel 5 Configuration Register */
298 #define DMA5_NEXT_DESC_PTR 0xFFC00D40 /* DMA Channel 5 Next Descriptor Pointer Register */
299 #define DMA5_START_ADDR 0xFFC00D44 /* DMA Channel 5 Start Address Register */
300 #define DMA5_X_COUNT 0xFFC00D50 /* DMA Channel 5 X Count Register */
301 #define DMA5_Y_COUNT 0xFFC00D58 /* DMA Channel 5 Y Count Register */
302 #define DMA5_X_MODIFY 0xFFC00D54 /* DMA Channel 5 X Modify Register */
303 #define DMA5_Y_MODIFY 0xFFC00D5C /* DMA Channel 5 Y Modify Register */
304 #define DMA5_CURR_DESC_PTR 0xFFC00D60 /* DMA Channel 5 Current Descriptor Pointer Register */
305 #define DMA5_CURR_ADDR 0xFFC00D64 /* DMA Channel 5 Current Address Register */
306 #define DMA5_CURR_X_COUNT 0xFFC00D70 /* DMA Channel 5 Current X Count Register */
307 #define DMA5_CURR_Y_COUNT 0xFFC00D78 /* DMA Channel 5 Current Y Count Register */
308 #define DMA5_IRQ_STATUS 0xFFC00D68 /* DMA Channel 5 Interrupt/Status Register */
309 #define DMA5_PERIPHERAL_MAP 0xFFC00D6C /* DMA Channel 5 Peripheral Map Register */
311 #define DMA6_CONFIG 0xFFC00D88 /* DMA Channel 6 Configuration Register */
312 #define DMA6_NEXT_DESC_PTR 0xFFC00D80 /* DMA Channel 6 Next Descriptor Pointer Register */
313 #define DMA6_START_ADDR 0xFFC00D84 /* DMA Channel 6 Start Address Register */
314 #define DMA6_X_COUNT 0xFFC00D90 /* DMA Channel 6 X Count Register */
315 #define DMA6_Y_COUNT 0xFFC00D98 /* DMA Channel 6 Y Count Register */
316 #define DMA6_X_MODIFY 0xFFC00D94 /* DMA Channel 6 X Modify Register */
317 #define DMA6_Y_MODIFY 0xFFC00D9C /* DMA Channel 6 Y Modify Register */
318 #define DMA6_CURR_DESC_PTR 0xFFC00DA0 /* DMA Channel 6 Current Descriptor Pointer Register */
319 #define DMA6_CURR_ADDR 0xFFC00DA4 /* DMA Channel 6 Current Address Register */
320 #define DMA6_CURR_X_COUNT 0xFFC00DB0 /* DMA Channel 6 Current X Count Register */
321 #define DMA6_CURR_Y_COUNT 0xFFC00DB8 /* DMA Channel 6 Current Y Count Register */
322 #define DMA6_IRQ_STATUS 0xFFC00DA8 /* DMA Channel 6 Interrupt/Status Register */
323 #define DMA6_PERIPHERAL_MAP 0xFFC00DAC /* DMA Channel 6 Peripheral Map Register */
325 #define DMA7_CONFIG 0xFFC00DC8 /* DMA Channel 7 Configuration Register */
326 #define DMA7_NEXT_DESC_PTR 0xFFC00DC0 /* DMA Channel 7 Next Descriptor Pointer Register */
327 #define DMA7_START_ADDR 0xFFC00DC4 /* DMA Channel 7 Start Address Register */
328 #define DMA7_X_COUNT 0xFFC00DD0 /* DMA Channel 7 X Count Register */
329 #define DMA7_Y_COUNT 0xFFC00DD8 /* DMA Channel 7 Y Count Register */
330 #define DMA7_X_MODIFY 0xFFC00DD4 /* DMA Channel 7 X Modify Register */
331 #define DMA7_Y_MODIFY 0xFFC00DDC /* DMA Channel 7 Y Modify Register */
332 #define DMA7_CURR_DESC_PTR 0xFFC00DE0 /* DMA Channel 7 Current Descriptor Pointer Register */
333 #define DMA7_CURR_ADDR 0xFFC00DE4 /* DMA Channel 7 Current Address Register */
334 #define DMA7_CURR_X_COUNT 0xFFC00DF0 /* DMA Channel 7 Current X Count Register */
335 #define DMA7_CURR_Y_COUNT 0xFFC00DF8 /* DMA Channel 7 Current Y Count Register */
336 #define DMA7_IRQ_STATUS 0xFFC00DE8 /* DMA Channel 7 Interrupt/Status Register */
337 #define DMA7_PERIPHERAL_MAP 0xFFC00DEC /* DMA Channel 7 Peripheral Map Register */
339 #define MDMA_D1_CONFIG 0xFFC00E88 /* MemDMA Stream 1 Destination Configuration Register */
340 #define MDMA_D1_NEXT_DESC_PTR 0xFFC00E80 /* MemDMA Stream 1 Destination Next Descriptor Pointer Register */
341 #define MDMA_D1_START_ADDR 0xFFC00E84 /* MemDMA Stream 1 Destination Start Address Register */
342 #define MDMA_D1_X_COUNT 0xFFC00E90 /* MemDMA Stream 1 Destination X Count Register */
343 #define MDMA_D1_Y_COUNT 0xFFC00E98 /* MemDMA Stream 1 Destination Y Count Register */
344 #define MDMA_D1_X_MODIFY 0xFFC00E94 /* MemDMA Stream 1 Destination X Modify Register */
345 #define MDMA_D1_Y_MODIFY 0xFFC00E9C /* MemDMA Stream 1 Destination Y Modify Register */
346 #define MDMA_D1_CURR_DESC_PTR 0xFFC00EA0 /* MemDMA Stream 1 Destination Current Descriptor Pointer Register */
347 #define MDMA_D1_CURR_ADDR 0xFFC00EA4 /* MemDMA Stream 1 Destination Current Address Register */
348 #define MDMA_D1_CURR_X_COUNT 0xFFC00EB0 /* MemDMA Stream 1 Destination Current X Count Register */
349 #define MDMA_D1_CURR_Y_COUNT 0xFFC00EB8 /* MemDMA Stream 1 Destination Current Y Count Register */
350 #define MDMA_D1_IRQ_STATUS 0xFFC00EA8 /* MemDMA Stream 1 Destination Interrupt/Status Register */
351 #define MDMA_D1_PERIPHERAL_MAP 0xFFC00EAC /* MemDMA Stream 1 Destination Peripheral Map Register */
353 #define MDMA_S1_CONFIG 0xFFC00EC8 /* MemDMA Stream 1 Source Configuration Register */
354 #define MDMA_S1_NEXT_DESC_PTR 0xFFC00EC0 /* MemDMA Stream 1 Source Next Descriptor Pointer Register */
355 #define MDMA_S1_START_ADDR 0xFFC00EC4 /* MemDMA Stream 1 Source Start Address Register */
356 #define MDMA_S1_X_COUNT 0xFFC00ED0 /* MemDMA Stream 1 Source X Count Register */
357 #define MDMA_S1_Y_COUNT 0xFFC00ED8 /* MemDMA Stream 1 Source Y Count Register */
358 #define MDMA_S1_X_MODIFY 0xFFC00ED4 /* MemDMA Stream 1 Source X Modify Register */
359 #define MDMA_S1_Y_MODIFY 0xFFC00EDC /* MemDMA Stream 1 Source Y Modify Register */
360 #define MDMA_S1_CURR_DESC_PTR 0xFFC00EE0 /* MemDMA Stream 1 Source Current Descriptor Pointer Register */
361 #define MDMA_S1_CURR_ADDR 0xFFC00EE4 /* MemDMA Stream 1 Source Current Address Register */
362 #define MDMA_S1_CURR_X_COUNT 0xFFC00EF0 /* MemDMA Stream 1 Source Current X Count Register */
363 #define MDMA_S1_CURR_Y_COUNT 0xFFC00EF8 /* MemDMA Stream 1 Source Current Y Count Register */
364 #define MDMA_S1_IRQ_STATUS 0xFFC00EE8 /* MemDMA Stream 1 Source Interrupt/Status Register */
365 #define MDMA_S1_PERIPHERAL_MAP 0xFFC00EEC /* MemDMA Stream 1 Source Peripheral Map Register */
367 #define MDMA_D0_CONFIG 0xFFC00E08 /* MemDMA Stream 0 Destination Configuration Register */
368 #define MDMA_D0_NEXT_DESC_PTR 0xFFC00E00 /* MemDMA Stream 0 Destination Next Descriptor Pointer Register */
369 #define MDMA_D0_START_ADDR 0xFFC00E04 /* MemDMA Stream 0 Destination Start Address Register */
370 #define MDMA_D0_X_COUNT 0xFFC00E10 /* MemDMA Stream 0 Destination X Count Register */
371 #define MDMA_D0_Y_COUNT 0xFFC00E18 /* MemDMA Stream 0 Destination Y Count Register */
372 #define MDMA_D0_X_MODIFY 0xFFC00E14 /* MemDMA Stream 0 Destination X Modify Register */
373 #define MDMA_D0_Y_MODIFY 0xFFC00E1C /* MemDMA Stream 0 Destination Y Modify Register */
374 #define MDMA_D0_CURR_DESC_PTR 0xFFC00E20 /* MemDMA Stream 0 Destination Current Descriptor Pointer Register */
375 #define MDMA_D0_CURR_ADDR 0xFFC00E24 /* MemDMA Stream 0 Destination Current Address Register */
376 #define MDMA_D0_CURR_X_COUNT 0xFFC00E30 /* MemDMA Stream 0 Destination Current X Count Register */
377 #define MDMA_D0_CURR_Y_COUNT 0xFFC00E38 /* MemDMA Stream 0 Destination Current Y Count Register */
378 #define MDMA_D0_IRQ_STATUS 0xFFC00E28 /* MemDMA Stream 0 Destination Interrupt/Status Register */
379 #define MDMA_D0_PERIPHERAL_MAP 0xFFC00E2C /* MemDMA Stream 0 Destination Peripheral Map Register */
381 #define MDMA_S0_CONFIG 0xFFC00E48 /* MemDMA Stream 0 Source Configuration Register */
382 #define MDMA_S0_NEXT_DESC_PTR 0xFFC00E40 /* MemDMA Stream 0 Source Next Descriptor Pointer Register */
383 #define MDMA_S0_START_ADDR 0xFFC00E44 /* MemDMA Stream 0 Source Start Address Register */
384 #define MDMA_S0_X_COUNT 0xFFC00E50 /* MemDMA Stream 0 Source X Count Register */
385 #define MDMA_S0_Y_COUNT 0xFFC00E58 /* MemDMA Stream 0 Source Y Count Register */
386 #define MDMA_S0_X_MODIFY 0xFFC00E54 /* MemDMA Stream 0 Source X Modify Register */
387 #define MDMA_S0_Y_MODIFY 0xFFC00E5C /* MemDMA Stream 0 Source Y Modify Register */
388 #define MDMA_S0_CURR_DESC_PTR 0xFFC00E60 /* MemDMA Stream 0 Source Current Descriptor Pointer Register */
389 #define MDMA_S0_CURR_ADDR 0xFFC00E64 /* MemDMA Stream 0 Source Current Address Register */
390 #define MDMA_S0_CURR_X_COUNT 0xFFC00E70 /* MemDMA Stream 0 Source Current X Count Register */
391 #define MDMA_S0_CURR_Y_COUNT 0xFFC00E78 /* MemDMA Stream 0 Source Current Y Count Register */
392 #define MDMA_S0_IRQ_STATUS 0xFFC00E68 /* MemDMA Stream 0 Source Interrupt/Status Register */
393 #define MDMA_S0_PERIPHERAL_MAP 0xFFC00E6C /* MemDMA Stream 0 Source Peripheral Map Register */
395 /* Parallel Peripheral Interface (PPI) (0xFFC01000 - 0xFFC010FF) */
397 #define PPI_CONTROL 0xFFC01000 /* PPI Control Register */
398 #define PPI_STATUS 0xFFC01004 /* PPI Status Register */
399 #define PPI_COUNT 0xFFC01008 /* PPI Transfer Count Register */
400 #define PPI_DELAY 0xFFC0100C /* PPI Delay Count Register */
401 #define PPI_FRAME 0xFFC01010 /* PPI Frame Length Register */
403 /*********************************************************************************** */
404 /* System MMR Register Bits */
405 /******************************************************************************* */
407 /* ********************* PLL AND RESET MASKS ************************ */
410 #define PLL_CLKIN 0x00000000 /* Pass CLKIN to PLL */
411 #define PLL_CLKIN_DIV2 0x00000001 /* Pass CLKIN/2 to PLL */
412 #define PLL_OFF 0x00000002 /* Shut off PLL clocks */
413 #define STOPCK_OFF 0x00000008 /* Core clock off */
414 #define PDWN 0x00000020 /* Put the PLL in a Deep Sleep state */
415 #define BYPASS 0x00000100 /* Bypass the PLL */
419 #define SCLK_DIV(x) (x) /* SCLK = VCO / x */
421 #define CCLK_DIV1 0x00000000 /* CCLK = VCO / 1 */
422 #define CCLK_DIV2 0x00000010 /* CCLK = VCO / 2 */
423 #define CCLK_DIV4 0x00000020 /* CCLK = VCO / 4 */
424 #define CCLK_DIV8 0x00000030 /* CCLK = VCO / 8 */
427 #define ACTIVE_PLLENABLED 0x0001 /* Processor In Active Mode With PLL Enabled */
428 #define FULL_ON 0x0002 /* Processor In Full On Mode */
429 #define ACTIVE_PLLDISABLED 0x0004 /* Processor In Active Mode With PLL Disabled */
430 #define PLL_LOCKED 0x0020 /* PLL_LOCKCNT Has Been Reached */
433 #define CHIPID_VERSION 0xF0000000
434 #define CHIPID_FAMILY 0x0FFFF000
435 #define CHIPID_MANUFACTURE 0x00000FFE
438 #define SYSTEM_RESET 0x00000007 /* Initiates a system software reset */
440 /* ************* SYSTEM INTERRUPT CONTROLLER MASKS ***************** */
444 #define P0_IVG(x) ((x)-7) /* Peripheral #0 assigned IVG #x */
445 #define P1_IVG(x) ((x)-7) << 0x4 /* Peripheral #1 assigned IVG #x */
446 #define P2_IVG(x) ((x)-7) << 0x8 /* Peripheral #2 assigned IVG #x */
447 #define P3_IVG(x) ((x)-7) << 0xC /* Peripheral #3 assigned IVG #x */
448 #define P4_IVG(x) ((x)-7) << 0x10 /* Peripheral #4 assigned IVG #x */
449 #define P5_IVG(x) ((x)-7) << 0x14 /* Peripheral #5 assigned IVG #x */
450 #define P6_IVG(x) ((x)-7) << 0x18 /* Peripheral #6 assigned IVG #x */
451 #define P7_IVG(x) ((x)-7) << 0x1C /* Peripheral #7 assigned IVG #x */
455 #define P8_IVG(x) ((x)-7) /* Peripheral #8 assigned IVG #x */
456 #define P9_IVG(x) ((x)-7) << 0x4 /* Peripheral #9 assigned IVG #x */
457 #define P10_IVG(x) ((x)-7) << 0x8 /* Peripheral #10 assigned IVG #x */
458 #define P11_IVG(x) ((x)-7) << 0xC /* Peripheral #11 assigned IVG #x */
459 #define P12_IVG(x) ((x)-7) << 0x10 /* Peripheral #12 assigned IVG #x */
460 #define P13_IVG(x) ((x)-7) << 0x14 /* Peripheral #13 assigned IVG #x */
461 #define P14_IVG(x) ((x)-7) << 0x18 /* Peripheral #14 assigned IVG #x */
462 #define P15_IVG(x) ((x)-7) << 0x1C /* Peripheral #15 assigned IVG #x */
465 #define P16_IVG(x) ((x)-7) /* Peripheral #16 assigned IVG #x */
466 #define P17_IVG(x) ((x)-7) << 0x4 /* Peripheral #17 assigned IVG #x */
467 #define P18_IVG(x) ((x)-7) << 0x8 /* Peripheral #18 assigned IVG #x */
468 #define P19_IVG(x) ((x)-7) << 0xC /* Peripheral #19 assigned IVG #x */
469 #define P20_IVG(x) ((x)-7) << 0x10 /* Peripheral #20 assigned IVG #x */
470 #define P21_IVG(x) ((x)-7) << 0x14 /* Peripheral #21 assigned IVG #x */
471 #define P22_IVG(x) ((x)-7) << 0x18 /* Peripheral #22 assigned IVG #x */
472 #define P23_IVG(x) ((x)-7) << 0x1C /* Peripheral #23 assigned IVG #x */
474 /* SIC_IMASK Masks */
475 #define SIC_UNMASK_ALL 0x00000000 /* Unmask all peripheral interrupts */
476 #define SIC_MASK_ALL 0xFFFFFFFF /* Mask all peripheral interrupts */
477 #define SIC_MASK(x) (1 << (x)) /* Mask Peripheral #x interrupt */
478 #define SIC_UNMASK(x) (0xFFFFFFFF ^ (1 << (x))) /* Unmask Peripheral #x interrupt */
481 #define IWR_DISABLE_ALL 0x00000000 /* Wakeup Disable all peripherals */
482 #define IWR_ENABLE_ALL 0xFFFFFFFF /* Wakeup Enable all peripherals */
483 #define IWR_ENABLE(x) (1 << (x)) /* Wakeup Enable Peripheral #x */
484 #define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << (x))) /* Wakeup Disable Peripheral #x */
486 /* ********* WATCHDOG TIMER MASKS ********************8 */
488 /* Watchdog Timer WDOG_CTL Register */
489 #define ICTL(x) ((x<<1) & 0x0006)
490 #define ENABLE_RESET 0x00000000 /* Set Watchdog Timer to generate reset */
491 #define ENABLE_NMI 0x00000002 /* Set Watchdog Timer to generate non-maskable interrupt */
492 #define ENABLE_GPI 0x00000004 /* Set Watchdog Timer to generate general-purpose interrupt */
493 #define DISABLE_EVT 0x00000006 /* Disable Watchdog Timer interrupts */
495 #define TMR_EN 0x0000
496 #define TMR_DIS 0x0AD0
503 /* ***************************** UART CONTROLLER MASKS ********************** */
505 /* UART_LCR Register */
513 #define WLS(x) ((x-5) & 0x03)
524 /* UART_MCR Register */
525 #define LOOP_ENA 0x10
526 #define LOOP_ENA_P 0x04
528 /* UART_LSR Register */
545 /* UART_IER Register */
554 /* UART_IIR Register */
555 #define STATUS(x) ((x << 1) & 0x06)
557 #define STATUS_P1 0x02
558 #define STATUS_P0 0x01
560 #define IIR_TX_READY 0x02 /* UART_THR empty */
561 #define IIR_RX_READY 0x04 /* Receive data ready */
562 #define IIR_LINE_CHANGE 0x06 /* Receive line status */
563 #define IIR_STATUS 0x06
565 /* UART_GCTL Register */
580 /* ********** SERIAL PORT MASKS ********************** */
582 /* SPORTx_TCR1 Masks */
583 #define TSPEN 0x0001 /* TX enable */
584 #define ITCLK 0x0002 /* Internal TX Clock Select */
585 #define TDTYPE 0x000C /* TX Data Formatting Select */
586 #define TLSBIT 0x0010 /* TX Bit Order */
587 #define ITFS 0x0200 /* Internal TX Frame Sync Select */
588 #define TFSR 0x0400 /* TX Frame Sync Required Select */
589 #define DITFS 0x0800 /* Data Independent TX Frame Sync Select */
590 #define LTFS 0x1000 /* Low TX Frame Sync Select */
591 #define LATFS 0x2000 /* Late TX Frame Sync Select */
592 #define TCKFE 0x4000 /* TX Clock Falling Edge Select */
594 /* SPORTx_TCR2 Masks */
595 #define SLEN 0x001F /*TX Word Length */
596 #define TXSE 0x0100 /*TX Secondary Enable */
597 #define TSFSE 0x0200 /*TX Stereo Frame Sync Enable */
598 #define TRFST 0x0400 /*TX Right-First Data Order */
600 /* SPORTx_RCR1 Masks */
601 #define RSPEN 0x0001 /* RX enable */
602 #define IRCLK 0x0002 /* Internal RX Clock Select */
603 #define RDTYPE 0x000C /* RX Data Formatting Select */
604 #define RULAW 0x0008 /* u-Law enable */
605 #define RALAW 0x000C /* A-Law enable */
606 #define RLSBIT 0x0010 /* RX Bit Order */
607 #define IRFS 0x0200 /* Internal RX Frame Sync Select */
608 #define RFSR 0x0400 /* RX Frame Sync Required Select */
609 #define LRFS 0x1000 /* Low RX Frame Sync Select */
610 #define LARFS 0x2000 /* Late RX Frame Sync Select */
611 #define RCKFE 0x4000 /* RX Clock Falling Edge Select */
613 /* SPORTx_RCR2 Masks */
614 #define SLEN 0x001F /*RX Word Length */
615 #define RXSE 0x0100 /*RX Secondary Enable */
616 #define RSFSE 0x0200 /*RX Stereo Frame Sync Enable */
617 #define RRFST 0x0400 /*Right-First Data Order */
619 /*SPORTx_STAT Masks */
620 #define RXNE 0x0001 /*RX FIFO Not Empty Status */
621 #define RUVF 0x0002 /*RX Underflow Status */
622 #define ROVF 0x0004 /*RX Overflow Status */
623 #define TXF 0x0008 /*TX FIFO Full Status */
624 #define TUVF 0x0010 /*TX Underflow Status */
625 #define TOVF 0x0020 /*TX Overflow Status */
626 #define TXHRE 0x0040 /*TX Hold Register Empty */
628 /*SPORTx_MCMC1 Masks */
629 #define SP_WSIZE 0x0000F000 /*Multichannel Window Size Field */
630 #define SP_WOFF 0x000003FF /*Multichannel Window Offset Field */
632 /*SPORTx_MCMC2 Masks */
633 #define MCCRM 0x00000003 /*Multichannel Clock Recovery Mode */
634 #define MCDTXPE 0x00000004 /*Multichannel DMA Transmit Packing */
635 #define MCDRXPE 0x00000008 /*Multichannel DMA Receive Packing */
636 #define MCMEN 0x00000010 /*Multichannel Frame Mode Enable */
637 #define FSDR 0x00000080 /*Multichannel Frame Sync to Data Relationship */
638 #define MFD 0x0000F000 /*Multichannel Frame Delay */
640 /* ********* PARALLEL PERIPHERAL INTERFACE (PPI) MASKS **************** */
642 /* PPI_CONTROL Masks */
643 #define PORT_EN 0x00000001 /* PPI Port Enable */
644 #define PORT_DIR 0x00000002 /* PPI Port Direction */
645 #define XFR_TYPE 0x0000000C /* PPI Transfer Type */
646 #define PORT_CFG 0x00000030 /* PPI Port Configuration */
647 #define FLD_SEL 0x00000040 /* PPI Active Field Select */
648 #define PACK_EN 0x00000080 /* PPI Packing Mode */
649 #define DMA32 0x00000100 /* PPI 32-bit DMA Enable */
650 #define SKIP_EN 0x00000200 /* PPI Skip Element Enable */
651 #define SKIP_EO 0x00000400 /* PPI Skip Even/Odd Elements */
652 #define DLENGTH 0x00003800 /* PPI Data Length */
653 #define DLEN_8 0x0000 /* Data Length = 8 Bits */
654 #define DLEN_10 0x0800 /* Data Length = 10 Bits */
655 #define DLEN_11 0x1000 /* Data Length = 11 Bits */
656 #define DLEN_12 0x1800 /* Data Length = 12 Bits */
657 #define DLEN_13 0x2000 /* Data Length = 13 Bits */
658 #define DLEN_14 0x2800 /* Data Length = 14 Bits */
659 #define DLEN_15 0x3000 /* Data Length = 15 Bits */
660 #define DLEN_16 0x3800 /* Data Length = 16 Bits */
661 #define DLEN(x) (((x-9) & 0x07) << 11) /* PPI Data Length (only works for x=10-->x=16) */
662 #define POL 0x0000C000 /* PPI Signal Polarities */
664 /* PPI_STATUS Masks */
665 #define FLD 0x00000400 /* Field Indicator */
666 #define FT_ERR 0x00000800 /* Frame Track Error */
667 #define OVR 0x00001000 /* FIFO Overflow Error */
668 #define UNDR 0x00002000 /* FIFO Underrun Error */
669 #define ERR_DET 0x00004000 /* Error Detected Indicator */
670 #define ERR_NCOR 0x00008000 /* Error Not Corrected Indicator */
672 /* ********** DMA CONTROLLER MASKS *********************8 */
674 /*DMAx_CONFIG, MDMA_yy_CONFIG Masks */
675 #define DMAEN 0x00000001 /* Channel Enable */
676 #define WNR 0x00000002 /* Channel Direction (W/R*) */
677 #define WDSIZE_8 0x00000000 /* Word Size 8 bits */
678 #define WDSIZE_16 0x00000004 /* Word Size 16 bits */
679 #define WDSIZE_32 0x00000008 /* Word Size 32 bits */
680 #define DMA2D 0x00000010 /* 2D/1D* Mode */
681 #define RESTART 0x00000020 /* Restart */
682 #define DI_SEL 0x00000040 /* Data Interrupt Select */
683 #define DI_EN 0x00000080 /* Data Interrupt Enable */
684 #define NDSIZE_0 0x0000 /* Next Descriptor Size = 0 (Stop/Autobuffer) */
685 #define NDSIZE_1 0x0100 /* Next Descriptor Size = 1 */
686 #define NDSIZE_2 0x0200 /* Next Descriptor Size = 2 */
687 #define NDSIZE_3 0x0300 /* Next Descriptor Size = 3 */
688 #define NDSIZE_4 0x0400 /* Next Descriptor Size = 4 */
689 #define NDSIZE_5 0x0500 /* Next Descriptor Size = 5 */
690 #define NDSIZE_6 0x0600 /* Next Descriptor Size = 6 */
691 #define NDSIZE_7 0x0700 /* Next Descriptor Size = 7 */
692 #define NDSIZE_8 0x0800 /* Next Descriptor Size = 8 */
693 #define NDSIZE_9 0x0900 /* Next Descriptor Size = 9 */
694 #define NDSIZE 0x00000900 /* Next Descriptor Size */
695 #define DMAFLOW 0x00007000 /* Flow Control */
696 #define DMAFLOW_STOP 0x0000 /* Stop Mode */
697 #define DMAFLOW_AUTO 0x1000 /* Autobuffer Mode */
698 #define DMAFLOW_ARRAY 0x4000 /* Descriptor Array Mode */
699 #define DMAFLOW_SMALL 0x6000 /* Small Model Descriptor List Mode */
700 #define DMAFLOW_LARGE 0x7000 /* Large Model Descriptor List Mode */
702 #define DMAEN_P 0 /* Channel Enable */
703 #define WNR_P 1 /* Channel Direction (W/R*) */
704 #define DMA2D_P 4 /* 2D/1D* Mode */
705 #define RESTART_P 5 /* Restart */
706 #define DI_SEL_P 6 /* Data Interrupt Select */
707 #define DI_EN_P 7 /* Data Interrupt Enable */
709 /*DMAx_IRQ_STATUS, MDMA_yy_IRQ_STATUS Masks */
711 #define DMA_DONE 0x00000001 /* DMA Done Indicator */
712 #define DMA_ERR 0x00000002 /* DMA Error Indicator */
713 #define DFETCH 0x00000004 /* Descriptor Fetch Indicator */
714 #define DMA_RUN 0x00000008 /* DMA Running Indicator */
716 #define DMA_DONE_P 0 /* DMA Done Indicator */
717 #define DMA_ERR_P 1 /* DMA Error Indicator */
718 #define DFETCH_P 2 /* Descriptor Fetch Indicator */
719 #define DMA_RUN_P 3 /* DMA Running Indicator */
721 /*DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */
723 #define CTYPE 0x00000040 /* DMA Channel Type Indicator */
724 #define CTYPE_P 6 /* DMA Channel Type Indicator BIT POSITION */
725 #define PCAP8 0x00000080 /* DMA 8-bit Operation Indicator */
726 #define PCAP16 0x00000100 /* DMA 16-bit Operation Indicator */
727 #define PCAP32 0x00000200 /* DMA 32-bit Operation Indicator */
728 #define PCAPWR 0x00000400 /* DMA Write Operation Indicator */
729 #define PCAPRD 0x00000800 /* DMA Read Operation Indicator */
730 #define PMAP 0x00007000 /* DMA Peripheral Map Field */
732 /* ************* GENERAL PURPOSE TIMER MASKS ******************** */
734 /* PWM Timer bit definitions */
736 /* TIMER_ENABLE Register */
737 #define TIMEN0 0x0001
738 #define TIMEN1 0x0002
739 #define TIMEN2 0x0004
741 #define TIMEN0_P 0x00
742 #define TIMEN1_P 0x01
743 #define TIMEN2_P 0x02
745 /* TIMER_DISABLE Register */
746 #define TIMDIS0 0x0001
747 #define TIMDIS1 0x0002
748 #define TIMDIS2 0x0004
750 #define TIMDIS0_P 0x00
751 #define TIMDIS1_P 0x01
752 #define TIMDIS2_P 0x02
754 /* TIMER_STATUS Register */
755 #define TIMIL0 0x0001
756 #define TIMIL1 0x0002
757 #define TIMIL2 0x0004
758 #define TOVL_ERR0 0x0010
759 #define TOVL_ERR1 0x0020
760 #define TOVL_ERR2 0x0040
765 #define TIMIL0_P 0x00
766 #define TIMIL1_P 0x01
767 #define TIMIL2_P 0x02
768 #define TOVL_ERR0_P 0x04
769 #define TOVL_ERR1_P 0x05
770 #define TOVL_ERR2_P 0x06
775 /* TIMERx_CONFIG Registers */
776 #define PWM_OUT 0x0001
777 #define WDTH_CAP 0x0002
778 #define EXT_CLK 0x0003
779 #define PULSE_HI 0x0004
780 #define PERIOD_CNT 0x0008
781 #define IRQ_ENA 0x0010
782 #define TIN_SEL 0x0020
783 #define OUT_DIS 0x0040
784 #define CLK_SEL 0x0080
785 #define TOGGLE_HI 0x0100
786 #define EMU_RUN 0x0200
787 #define ERR_TYP(x) ((x & 0x03) << 14)
789 #define TMODE_P0 0x00
790 #define TMODE_P1 0x01
791 #define PULSE_HI_P 0x02
792 #define PERIOD_CNT_P 0x03
793 #define IRQ_ENA_P 0x04
794 #define TIN_SEL_P 0x05
795 #define OUT_DIS_P 0x06
796 #define CLK_SEL_P 0x07
797 #define TOGGLE_HI_P 0x08
798 #define EMU_RUN_P 0x09
799 #define ERR_TYP_P0 0x0E
800 #define ERR_TYP_P1 0x0F
802 /*/ ****************** PROGRAMMABLE FLAG MASKS ********************* */
804 /* General Purpose IO (0xFFC00700 - 0xFFC007FF) Masks */
822 /* General Purpose IO (0xFFC00700 - 0xFFC007FF) BIT POSITIONS */
840 /* *********** SERIAL PERIPHERAL INTERFACE (SPI) MASKS **************** */
843 #define TIMOD 0x00000003 /* Transfer initiation mode and interrupt generation */
844 #define SZ 0x00000004 /* Send Zero (=0) or last (=1) word when TDBR empty. */
845 #define GM 0x00000008 /* When RDBR full, get more (=1) data or discard (=0) incoming Data */
846 #define PSSE 0x00000010 /* Enable (=1) Slave-Select input for Master. */
847 #define EMISO 0x00000020 /* Enable (=1) MISO pin as an output. */
848 #define SPI_LEN 0x00000100 /* Word length (0 => 8 bits, 1 => 16 bits) */
849 #define LSBF 0x00000200 /* Data format (0 => MSB sent/received first 1 => LSB sent/received first) */
850 #define CPHA 0x00000400 /* Clock phase (0 => SPICLK starts toggling in middle of xfer, 1 => SPICLK toggles at the beginning of xfer. */
851 #define CPOL 0x00000800 /* Clock polarity (0 => active-high, 1 => active-low) */
852 #define MSTR 0x00001000 /* Configures SPI as master (=1) or slave (=0) */
853 #define WOM 0x00002000 /* Open drain (=1) data output enable (for MOSI and MISO) */
854 #define SPE 0x00004000 /* SPI module enable (=1), disable (=0) */
857 #define FLS1 0x00000002 /* Enables (=1) SPI_FLOUT1 as flag output for SPI Slave-select */
858 #define FLS2 0x00000004 /* Enables (=1) SPI_FLOUT2 as flag output for SPI Slave-select */
859 #define FLS3 0x00000008 /* Enables (=1) SPI_FLOUT3 as flag output for SPI Slave-select */
860 #define FLS4 0x00000010 /* Enables (=1) SPI_FLOUT4 as flag output for SPI Slave-select */
861 #define FLS5 0x00000020 /* Enables (=1) SPI_FLOUT5 as flag output for SPI Slave-select */
862 #define FLS6 0x00000040 /* Enables (=1) SPI_FLOUT6 as flag output for SPI Slave-select */
863 #define FLS7 0x00000080 /* Enables (=1) SPI_FLOUT7 as flag output for SPI Slave-select */
864 #define FLG1 0x00000200 /* Activates (=0) SPI_FLOUT1 as flag output for SPI Slave-select */
865 #define FLG2 0x00000400 /* Activates (=0) SPI_FLOUT2 as flag output for SPI Slave-select */
866 #define FLG3 0x00000800 /* Activates (=0) SPI_FLOUT3 as flag output for SPI Slave-select */
867 #define FLG4 0x00001000 /* Activates (=0) SPI_FLOUT4 as flag output for SPI Slave-select */
868 #define FLG5 0x00002000 /* Activates (=0) SPI_FLOUT5 as flag output for SPI Slave-select */
869 #define FLG6 0x00004000 /* Activates (=0) SPI_FLOUT6 as flag output for SPI Slave-select */
870 #define FLG7 0x00008000 /* Activates (=0) SPI_FLOUT7 as flag output for SPI Slave-select */
872 /* SPI_FLG Bit Positions */
873 #define FLS1_P 0x00000001 /* Enables (=1) SPI_FLOUT1 as flag output for SPI Slave-select */
874 #define FLS2_P 0x00000002 /* Enables (=1) SPI_FLOUT2 as flag output for SPI Slave-select */
875 #define FLS3_P 0x00000003 /* Enables (=1) SPI_FLOUT3 as flag output for SPI Slave-select */
876 #define FLS4_P 0x00000004 /* Enables (=1) SPI_FLOUT4 as flag output for SPI Slave-select */
877 #define FLS5_P 0x00000005 /* Enables (=1) SPI_FLOUT5 as flag output for SPI Slave-select */
878 #define FLS6_P 0x00000006 /* Enables (=1) SPI_FLOUT6 as flag output for SPI Slave-select */
879 #define FLS7_P 0x00000007 /* Enables (=1) SPI_FLOUT7 as flag output for SPI Slave-select */
880 #define FLG1_P 0x00000009 /* Activates (=0) SPI_FLOUT1 as flag output for SPI Slave-select */
881 #define FLG2_P 0x0000000A /* Activates (=0) SPI_FLOUT2 as flag output for SPI Slave-select */
882 #define FLG3_P 0x0000000B /* Activates (=0) SPI_FLOUT3 as flag output for SPI Slave-select */
883 #define FLG4_P 0x0000000C /* Activates (=0) SPI_FLOUT4 as flag output for SPI Slave-select */
884 #define FLG5_P 0x0000000D /* Activates (=0) SPI_FLOUT5 as flag output for SPI Slave-select */
885 #define FLG6_P 0x0000000E /* Activates (=0) SPI_FLOUT6 as flag output for SPI Slave-select */
886 #define FLG7_P 0x0000000F /* Activates (=0) SPI_FLOUT7 as flag output for SPI Slave-select */
889 #define SPIF 0x00000001 /* Set (=1) when SPI single-word transfer complete */
890 #define MODF 0x00000002 /* Set (=1) in a master device when some other device tries to become master */
891 #define TXE 0x00000004 /* Set (=1) when transmission occurs with no new data in SPI_TDBR */
892 #define TXS 0x00000008 /* SPI_TDBR Data Buffer Status (0=Empty, 1=Full) */
893 #define RBSY 0x00000010 /* Set (=1) when data is received with RDBR full */
894 #define RXS 0x00000020 /* SPI_RDBR Data Buffer Status (0=Empty, 1=Full) */
895 #define TXCOL 0x00000040 /* When set (=1), corrupt data may have been transmitted */
897 /* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS ************* */
900 #define AMCKEN 0x00000001 /* Enable CLKOUT */
901 #define AMBEN_B0 0x00000002 /* Enable Asynchronous Memory Bank 0 only */
902 #define AMBEN_B0_B1 0x00000004 /* Enable Asynchronous Memory Banks 0 & 1 only */
903 #define AMBEN_B0_B1_B2 0x00000006 /* Enable Asynchronous Memory Banks 0, 1, and 2 */
904 #define AMBEN_ALL 0x00000008 /* Enable Asynchronous Memory Banks (all) 0, 1, 2, and 3 */
906 /* AMGCTL Bit Positions */
907 #define AMCKEN_P 0x00000000 /* Enable CLKOUT */
908 #define AMBEN_P0 0x00000001 /* Asynchronous Memory Enable, 000 - banks 0-3 disabled, 001 - Bank 0 enabled */
909 #define AMBEN_P1 0x00000002 /* Asynchronous Memory Enable, 010 - banks 0&1 enabled, 011 - banks 0-3 enabled */
910 #define AMBEN_P2 0x00000003 /* Asynchronous Memory Enable, 1xx - All banks (bank 0, 1, 2, and 3) enabled */
913 #define B0RDYEN 0x00000001 /* Bank 0 RDY Enable, 0=disable, 1=enable */
914 #define B0RDYPOL 0x00000002 /* Bank 0 RDY Active high, 0=active low, 1=active high */
915 #define B0TT_1 0x00000004 /* Bank 0 Transition Time from Read to Write = 1 cycle */
916 #define B0TT_2 0x00000008 /* Bank 0 Transition Time from Read to Write = 2 cycles */
917 #define B0TT_3 0x0000000C /* Bank 0 Transition Time from Read to Write = 3 cycles */
918 #define B0TT_4 0x00000000 /* Bank 0 Transition Time from Read to Write = 4 cycles */
919 #define B0ST_1 0x00000010 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=1 cycle */
920 #define B0ST_2 0x00000020 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=2 cycles */
921 #define B0ST_3 0x00000030 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=3 cycles */
922 #define B0ST_4 0x00000000 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=4 cycles */
923 #define B0HT_1 0x00000040 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 1 cycle */
924 #define B0HT_2 0x00000080 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 2 cycles */
925 #define B0HT_3 0x000000C0 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 3 cycles */
926 #define B0HT_0 0x00000000 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 0 cycles */
927 #define B0RAT_1 0x00000100 /* Bank 0 Read Access Time = 1 cycle */
928 #define B0RAT_2 0x00000200 /* Bank 0 Read Access Time = 2 cycles */
929 #define B0RAT_3 0x00000300 /* Bank 0 Read Access Time = 3 cycles */
930 #define B0RAT_4 0x00000400 /* Bank 0 Read Access Time = 4 cycles */
931 #define B0RAT_5 0x00000500 /* Bank 0 Read Access Time = 5 cycles */
932 #define B0RAT_6 0x00000600 /* Bank 0 Read Access Time = 6 cycles */
933 #define B0RAT_7 0x00000700 /* Bank 0 Read Access Time = 7 cycles */
934 #define B0RAT_8 0x00000800 /* Bank 0 Read Access Time = 8 cycles */
935 #define B0RAT_9 0x00000900 /* Bank 0 Read Access Time = 9 cycles */
936 #define B0RAT_10 0x00000A00 /* Bank 0 Read Access Time = 10 cycles */
937 #define B0RAT_11 0x00000B00 /* Bank 0 Read Access Time = 11 cycles */
938 #define B0RAT_12 0x00000C00 /* Bank 0 Read Access Time = 12 cycles */
939 #define B0RAT_13 0x00000D00 /* Bank 0 Read Access Time = 13 cycles */
940 #define B0RAT_14 0x00000E00 /* Bank 0 Read Access Time = 14 cycles */
941 #define B0RAT_15 0x00000F00 /* Bank 0 Read Access Time = 15 cycles */
942 #define B0WAT_1 0x00001000 /* Bank 0 Write Access Time = 1 cycle */
943 #define B0WAT_2 0x00002000 /* Bank 0 Write Access Time = 2 cycles */
944 #define B0WAT_3 0x00003000 /* Bank 0 Write Access Time = 3 cycles */
945 #define B0WAT_4 0x00004000 /* Bank 0 Write Access Time = 4 cycles */
946 #define B0WAT_5 0x00005000 /* Bank 0 Write Access Time = 5 cycles */
947 #define B0WAT_6 0x00006000 /* Bank 0 Write Access Time = 6 cycles */
948 #define B0WAT_7 0x00007000 /* Bank 0 Write Access Time = 7 cycles */
949 #define B0WAT_8 0x00008000 /* Bank 0 Write Access Time = 8 cycles */
950 #define B0WAT_9 0x00009000 /* Bank 0 Write Access Time = 9 cycles */
951 #define B0WAT_10 0x0000A000 /* Bank 0 Write Access Time = 10 cycles */
952 #define B0WAT_11 0x0000B000 /* Bank 0 Write Access Time = 11 cycles */
953 #define B0WAT_12 0x0000C000 /* Bank 0 Write Access Time = 12 cycles */
954 #define B0WAT_13 0x0000D000 /* Bank 0 Write Access Time = 13 cycles */
955 #define B0WAT_14 0x0000E000 /* Bank 0 Write Access Time = 14 cycles */
956 #define B0WAT_15 0x0000F000 /* Bank 0 Write Access Time = 15 cycles */
957 #define B1RDYEN 0x00010000 /* Bank 1 RDY enable, 0=disable, 1=enable */
958 #define B1RDYPOL 0x00020000 /* Bank 1 RDY Active high, 0=active low, 1=active high */
959 #define B1TT_1 0x00040000 /* Bank 1 Transition Time from Read to Write = 1 cycle */
960 #define B1TT_2 0x00080000 /* Bank 1 Transition Time from Read to Write = 2 cycles */
961 #define B1TT_3 0x000C0000 /* Bank 1 Transition Time from Read to Write = 3 cycles */
962 #define B1TT_4 0x00000000 /* Bank 1 Transition Time from Read to Write = 4 cycles */
963 #define B1ST_1 0x00100000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
964 #define B1ST_2 0x00200000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
965 #define B1ST_3 0x00300000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
966 #define B1ST_4 0x00000000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
967 #define B1HT_1 0x00400000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
968 #define B1HT_2 0x00800000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
969 #define B1HT_3 0x00C00000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
970 #define B1HT_0 0x00000000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */
971 #define B1RAT_1 0x01000000 /* Bank 1 Read Access Time = 1 cycle */
972 #define B1RAT_2 0x02000000 /* Bank 1 Read Access Time = 2 cycles */
973 #define B1RAT_3 0x03000000 /* Bank 1 Read Access Time = 3 cycles */
974 #define B1RAT_4 0x04000000 /* Bank 1 Read Access Time = 4 cycles */
975 #define B1RAT_5 0x05000000 /* Bank 1 Read Access Time = 5 cycles */
976 #define B1RAT_6 0x06000000 /* Bank 1 Read Access Time = 6 cycles */
977 #define B1RAT_7 0x07000000 /* Bank 1 Read Access Time = 7 cycles */
978 #define B1RAT_8 0x08000000 /* Bank 1 Read Access Time = 8 cycles */
979 #define B1RAT_9 0x09000000 /* Bank 1 Read Access Time = 9 cycles */
980 #define B1RAT_10 0x0A000000 /* Bank 1 Read Access Time = 10 cycles */
981 #define B1RAT_11 0x0B000000 /* Bank 1 Read Access Time = 11 cycles */
982 #define B1RAT_12 0x0C000000 /* Bank 1 Read Access Time = 12 cycles */
983 #define B1RAT_13 0x0D000000 /* Bank 1 Read Access Time = 13 cycles */
984 #define B1RAT_14 0x0E000000 /* Bank 1 Read Access Time = 14 cycles */
985 #define B1RAT_15 0x0F000000 /* Bank 1 Read Access Time = 15 cycles */
986 #define B1WAT_1 0x10000000 /* Bank 1 Write Access Time = 1 cycle */
987 #define B1WAT_2 0x20000000 /* Bank 1 Write Access Time = 2 cycles */
988 #define B1WAT_3 0x30000000 /* Bank 1 Write Access Time = 3 cycles */
989 #define B1WAT_4 0x40000000 /* Bank 1 Write Access Time = 4 cycles */
990 #define B1WAT_5 0x50000000 /* Bank 1 Write Access Time = 5 cycles */
991 #define B1WAT_6 0x60000000 /* Bank 1 Write Access Time = 6 cycles */
992 #define B1WAT_7 0x70000000 /* Bank 1 Write Access Time = 7 cycles */
993 #define B1WAT_8 0x80000000 /* Bank 1 Write Access Time = 8 cycles */
994 #define B1WAT_9 0x90000000 /* Bank 1 Write Access Time = 9 cycles */
995 #define B1WAT_10 0xA0000000 /* Bank 1 Write Access Time = 10 cycles */
996 #define B1WAT_11 0xB0000000 /* Bank 1 Write Access Time = 11 cycles */
997 #define B1WAT_12 0xC0000000 /* Bank 1 Write Access Time = 12 cycles */
998 #define B1WAT_13 0xD0000000 /* Bank 1 Write Access Time = 13 cycles */
999 #define B1WAT_14 0xE0000000 /* Bank 1 Write Access Time = 14 cycles */
1000 #define B1WAT_15 0xF0000000 /* Bank 1 Write Access Time = 15 cycles */
1003 #define B2RDYEN 0x00000001 /* Bank 2 RDY Enable, 0=disable, 1=enable */
1004 #define B2RDYPOL 0x00000002 /* Bank 2 RDY Active high, 0=active low, 1=active high */
1005 #define B2TT_1 0x00000004 /* Bank 2 Transition Time from Read to Write = 1 cycle */
1006 #define B2TT_2 0x00000008 /* Bank 2 Transition Time from Read to Write = 2 cycles */
1007 #define B2TT_3 0x0000000C /* Bank 2 Transition Time from Read to Write = 3 cycles */
1008 #define B2TT_4 0x00000000 /* Bank 2 Transition Time from Read to Write = 4 cycles */
1009 #define B2ST_1 0x00000010 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
1010 #define B2ST_2 0x00000020 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
1011 #define B2ST_3 0x00000030 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
1012 #define B2ST_4 0x00000000 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
1013 #define B2HT_1 0x00000040 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
1014 #define B2HT_2 0x00000080 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
1015 #define B2HT_3 0x000000C0 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
1016 #define B2HT_0 0x00000000 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */
1017 #define B2RAT_1 0x00000100 /* Bank 2 Read Access Time = 1 cycle */
1018 #define B2RAT_2 0x00000200 /* Bank 2 Read Access Time = 2 cycles */
1019 #define B2RAT_3 0x00000300 /* Bank 2 Read Access Time = 3 cycles */
1020 #define B2RAT_4 0x00000400 /* Bank 2 Read Access Time = 4 cycles */
1021 #define B2RAT_5 0x00000500 /* Bank 2 Read Access Time = 5 cycles */
1022 #define B2RAT_6 0x00000600 /* Bank 2 Read Access Time = 6 cycles */
1023 #define B2RAT_7 0x00000700 /* Bank 2 Read Access Time = 7 cycles */
1024 #define B2RAT_8 0x00000800 /* Bank 2 Read Access Time = 8 cycles */
1025 #define B2RAT_9 0x00000900 /* Bank 2 Read Access Time = 9 cycles */
1026 #define B2RAT_10 0x00000A00 /* Bank 2 Read Access Time = 10 cycles */
1027 #define B2RAT_11 0x00000B00 /* Bank 2 Read Access Time = 11 cycles */
1028 #define B2RAT_12 0x00000C00 /* Bank 2 Read Access Time = 12 cycles */
1029 #define B2RAT_13 0x00000D00 /* Bank 2 Read Access Time = 13 cycles */
1030 #define B2RAT_14 0x00000E00 /* Bank 2 Read Access Time = 14 cycles */
1031 #define B2RAT_15 0x00000F00 /* Bank 2 Read Access Time = 15 cycles */
1032 #define B2WAT_1 0x00001000 /* Bank 2 Write Access Time = 1 cycle */
1033 #define B2WAT_2 0x00002000 /* Bank 2 Write Access Time = 2 cycles */
1034 #define B2WAT_3 0x00003000 /* Bank 2 Write Access Time = 3 cycles */
1035 #define B2WAT_4 0x00004000 /* Bank 2 Write Access Time = 4 cycles */
1036 #define B2WAT_5 0x00005000 /* Bank 2 Write Access Time = 5 cycles */
1037 #define B2WAT_6 0x00006000 /* Bank 2 Write Access Time = 6 cycles */
1038 #define B2WAT_7 0x00007000 /* Bank 2 Write Access Time = 7 cycles */
1039 #define B2WAT_8 0x00008000 /* Bank 2 Write Access Time = 8 cycles */
1040 #define B2WAT_9 0x00009000 /* Bank 2 Write Access Time = 9 cycles */
1041 #define B2WAT_10 0x0000A000 /* Bank 2 Write Access Time = 10 cycles */
1042 #define B2WAT_11 0x0000B000 /* Bank 2 Write Access Time = 11 cycles */
1043 #define B2WAT_12 0x0000C000 /* Bank 2 Write Access Time = 12 cycles */
1044 #define B2WAT_13 0x0000D000 /* Bank 2 Write Access Time = 13 cycles */
1045 #define B2WAT_14 0x0000E000 /* Bank 2 Write Access Time = 14 cycles */
1046 #define B2WAT_15 0x0000F000 /* Bank 2 Write Access Time = 15 cycles */
1047 #define B3RDYEN 0x00010000 /* Bank 3 RDY enable, 0=disable, 1=enable */
1048 #define B3RDYPOL 0x00020000 /* Bank 3 RDY Active high, 0=active low, 1=active high */
1049 #define B3TT_1 0x00040000 /* Bank 3 Transition Time from Read to Write = 1 cycle */
1050 #define B3TT_2 0x00080000 /* Bank 3 Transition Time from Read to Write = 2 cycles */
1051 #define B3TT_3 0x000C0000 /* Bank 3 Transition Time from Read to Write = 3 cycles */
1052 #define B3TT_4 0x00000000 /* Bank 3 Transition Time from Read to Write = 4 cycles */
1053 #define B3ST_1 0x00100000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
1054 #define B3ST_2 0x00200000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
1055 #define B3ST_3 0x00300000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
1056 #define B3ST_4 0x00000000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
1057 #define B3HT_1 0x00400000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
1058 #define B3HT_2 0x00800000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
1059 #define B3HT_3 0x00C00000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
1060 #define B3HT_0 0x00000000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */
1061 #define B3RAT_1 0x01000000 /* Bank 3 Read Access Time = 1 cycle */
1062 #define B3RAT_2 0x02000000 /* Bank 3 Read Access Time = 2 cycles */
1063 #define B3RAT_3 0x03000000 /* Bank 3 Read Access Time = 3 cycles */
1064 #define B3RAT_4 0x04000000 /* Bank 3 Read Access Time = 4 cycles */
1065 #define B3RAT_5 0x05000000 /* Bank 3 Read Access Time = 5 cycles */
1066 #define B3RAT_6 0x06000000 /* Bank 3 Read Access Time = 6 cycles */
1067 #define B3RAT_7 0x07000000 /* Bank 3 Read Access Time = 7 cycles */
1068 #define B3RAT_8 0x08000000 /* Bank 3 Read Access Time = 8 cycles */
1069 #define B3RAT_9 0x09000000 /* Bank 3 Read Access Time = 9 cycles */
1070 #define B3RAT_10 0x0A000000 /* Bank 3 Read Access Time = 10 cycles */
1071 #define B3RAT_11 0x0B000000 /* Bank 3 Read Access Time = 11 cycles */
1072 #define B3RAT_12 0x0C000000 /* Bank 3 Read Access Time = 12 cycles */
1073 #define B3RAT_13 0x0D000000 /* Bank 3 Read Access Time = 13 cycles */
1074 #define B3RAT_14 0x0E000000 /* Bank 3 Read Access Time = 14 cycles */
1075 #define B3RAT_15 0x0F000000 /* Bank 3 Read Access Time = 15 cycles */
1076 #define B3WAT_1 0x10000000 /* Bank 3 Write Access Time = 1 cycle */
1077 #define B3WAT_2 0x20000000 /* Bank 3 Write Access Time = 2 cycles */
1078 #define B3WAT_3 0x30000000 /* Bank 3 Write Access Time = 3 cycles */
1079 #define B3WAT_4 0x40000000 /* Bank 3 Write Access Time = 4 cycles */
1080 #define B3WAT_5 0x50000000 /* Bank 3 Write Access Time = 5 cycles */
1081 #define B3WAT_6 0x60000000 /* Bank 3 Write Access Time = 6 cycles */
1082 #define B3WAT_7 0x70000000 /* Bank 3 Write Access Time = 7 cycles */
1083 #define B3WAT_8 0x80000000 /* Bank 3 Write Access Time = 8 cycles */
1084 #define B3WAT_9 0x90000000 /* Bank 3 Write Access Time = 9 cycles */
1085 #define B3WAT_10 0xA0000000 /* Bank 3 Write Access Time = 10 cycles */
1086 #define B3WAT_11 0xB0000000 /* Bank 3 Write Access Time = 11 cycles */
1087 #define B3WAT_12 0xC0000000 /* Bank 3 Write Access Time = 12 cycles */
1088 #define B3WAT_13 0xD0000000 /* Bank 3 Write Access Time = 13 cycles */
1089 #define B3WAT_14 0xE0000000 /* Bank 3 Write Access Time = 14 cycles */
1090 #define B3WAT_15 0xF0000000 /* Bank 3 Write Access Time = 15 cycles */
1092 /* ********************** SDRAM CONTROLLER MASKS *************************** */
1095 #define SCTLE 0x00000001 /* Enable SCLK[0], /SRAS, /SCAS, /SWE, SDQM[3:0] */
1096 #define CL_2 0x00000008 /* SDRAM CAS latency = 2 cycles */
1097 #define CL_3 0x0000000C /* SDRAM CAS latency = 3 cycles */
1098 #define PFE 0x00000010 /* Enable SDRAM prefetch */
1099 #define PFP 0x00000020 /* Prefetch has priority over AMC requests */
1100 #define TRAS_1 0x00000040 /* SDRAM tRAS = 1 cycle */
1101 #define TRAS_2 0x00000080 /* SDRAM tRAS = 2 cycles */
1102 #define TRAS_3 0x000000C0 /* SDRAM tRAS = 3 cycles */
1103 #define TRAS_4 0x00000100 /* SDRAM tRAS = 4 cycles */
1104 #define TRAS_5 0x00000140 /* SDRAM tRAS = 5 cycles */
1105 #define TRAS_6 0x00000180 /* SDRAM tRAS = 6 cycles */
1106 #define TRAS_7 0x000001C0 /* SDRAM tRAS = 7 cycles */
1107 #define TRAS_8 0x00000200 /* SDRAM tRAS = 8 cycles */
1108 #define TRAS_9 0x00000240 /* SDRAM tRAS = 9 cycles */
1109 #define TRAS_10 0x00000280 /* SDRAM tRAS = 10 cycles */
1110 #define TRAS_11 0x000002C0 /* SDRAM tRAS = 11 cycles */
1111 #define TRAS_12 0x00000300 /* SDRAM tRAS = 12 cycles */
1112 #define TRAS_13 0x00000340 /* SDRAM tRAS = 13 cycles */
1113 #define TRAS_14 0x00000380 /* SDRAM tRAS = 14 cycles */
1114 #define TRAS_15 0x000003C0 /* SDRAM tRAS = 15 cycles */
1115 #define TRP_1 0x00000800 /* SDRAM tRP = 1 cycle */
1116 #define TRP_2 0x00001000 /* SDRAM tRP = 2 cycles */
1117 #define TRP_3 0x00001800 /* SDRAM tRP = 3 cycles */
1118 #define TRP_4 0x00002000 /* SDRAM tRP = 4 cycles */
1119 #define TRP_5 0x00002800 /* SDRAM tRP = 5 cycles */
1120 #define TRP_6 0x00003000 /* SDRAM tRP = 6 cycles */
1121 #define TRP_7 0x00003800 /* SDRAM tRP = 7 cycles */
1122 #define TRCD_1 0x00008000 /* SDRAM tRCD = 1 cycle */
1123 #define TRCD_2 0x00010000 /* SDRAM tRCD = 2 cycles */
1124 #define TRCD_3 0x00018000 /* SDRAM tRCD = 3 cycles */
1125 #define TRCD_4 0x00020000 /* SDRAM tRCD = 4 cycles */
1126 #define TRCD_5 0x00028000 /* SDRAM tRCD = 5 cycles */
1127 #define TRCD_6 0x00030000 /* SDRAM tRCD = 6 cycles */
1128 #define TRCD_7 0x00038000 /* SDRAM tRCD = 7 cycles */
1129 #define TWR_1 0x00080000 /* SDRAM tWR = 1 cycle */
1130 #define TWR_2 0x00100000 /* SDRAM tWR = 2 cycles */
1131 #define TWR_3 0x00180000 /* SDRAM tWR = 3 cycles */
1132 #define PUPSD 0x00200000 /*Power-up start delay */
1133 #define PSM 0x00400000 /* SDRAM power-up sequence = Precharge, mode register set, 8 CBR refresh cycles */
1134 #define PSS 0x00800000 /* enable SDRAM power-up sequence on next SDRAM access */
1135 #define SRFS 0x01000000 /* Start SDRAM self-refresh mode */
1136 #define EBUFE 0x02000000 /* Enable external buffering timing */
1137 #define FBBRW 0x04000000 /* Fast back-to-back read write enable */
1138 #define EMREN 0x10000000 /* Extended mode register enable */
1139 #define TCSR 0x20000000 /* Temp compensated self refresh value 85 deg C */
1140 #define CDDBG 0x40000000 /* Tristate SDRAM controls during bus grant */
1142 /* EBIU_SDBCTL Masks */
1143 #define EBE 0x00000001 /* Enable SDRAM external bank */
1144 #define EBSZ_16 0x00000000 /* SDRAM external bank size = 16MB */
1145 #define EBSZ_32 0x00000002 /* SDRAM external bank size = 32MB */
1146 #define EBSZ_64 0x00000004 /* SDRAM external bank size = 64MB */
1147 #define EBSZ_128 0x00000006 /* SDRAM external bank size = 128MB */
1148 #define EBCAW_8 0x00000000 /* SDRAM external bank column address width = 8 bits */
1149 #define EBCAW_9 0x00000010 /* SDRAM external bank column address width = 9 bits */
1150 #define EBCAW_10 0x00000020 /* SDRAM external bank column address width = 9 bits */
1151 #define EBCAW_11 0x00000030 /* SDRAM external bank column address width = 9 bits */
1153 /* EBIU_SDSTAT Masks */
1154 #define SDCI 0x00000001 /* SDRAM controller is idle */
1155 #define SDSRA 0x00000002 /* SDRAM SDRAM self refresh is active */
1156 #define SDPUA 0x00000004 /* SDRAM power up active */
1157 #define SDRS 0x00000008 /* SDRAM is in reset state */
1158 #define SDEASE 0x00000010 /* SDRAM EAB sticky error status - W1C */
1159 #define BGSTAT 0x00000020 /* Bus granted */
1167 #define VLEV_10 0xA0
1168 #define VLEV_11 0xB0
1169 #define VLEV_12 0xC0
1170 #define VLEV_13 0xD0
1171 #define VLEV_14 0xE0
1172 #define VLEV_15 0xF0
1175 #endif /* _DEF_BF532_H */
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