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   1 /*
   2  * include/asm-blackfin/cache.h
   3  */
   4 #ifndef __ARCH_BLACKFIN_CACHE_H
   5 #define __ARCH_BLACKFIN_CACHE_H
   6
   7 /*
   8  * Bytes per L1 cache line
   9  * Blackfin loads 32 bytes for cache
  10  */
  11 #define L1_CACHE_SHIFT  5
  12 #define L1_CACHE_BYTES  (1 << L1_CACHE_SHIFT)
  13 #define SMP_CACHE_BYTES L1_CACHE_BYTES
  14
  15 /*
  16  * Put cacheline_aliged data to L1 data memory
  17  */
  18 #ifdef CONFIG_CACHELINE_ALIGNED_L1
  19 #define __cacheline_aligned                             \
  20           __attribute__((__aligned__(L1_CACHE_BYTES),   \
  21                 __section__(".data_l1.cacheline_aligned")))
  22 #endif
  23
  24 /*
  25  * largest L1 which this arch supports
  26  */
  27 #define L1_CACHE_SHIFT_MAX      5
  28
  29 #endif