SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/video/via/hw.c

   1 /*
   2  * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
   3  * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
   4
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public
   7  * License as published by the Free Software Foundation;
   8  * either version 2, or (at your option) any later version.
   9
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTIES OR REPRESENTATIONS; without even
  12  * the implied warranty of MERCHANTABILITY or FITNESS FOR
  13  * A PARTICULAR PURPOSE.See the GNU General Public License
  14  * for more details.
  15
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc.,
  19  * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  20  */
  21 #include "via-core.h"
  22 #include "global.h"
  23
  24 static struct pll_map pll_value[] = {
  25         {CLK_25_175M, CLE266_PLL_25_175M, K800_PLL_25_175M,
  26          CX700_25_175M, VX855_25_175M},
  27         {CLK_29_581M, CLE266_PLL_29_581M, K800_PLL_29_581M,
  28          CX700_29_581M, VX855_29_581M},
  29         {CLK_26_880M, CLE266_PLL_26_880M, K800_PLL_26_880M,
  30          CX700_26_880M, VX855_26_880M},
  31         {CLK_31_490M, CLE266_PLL_31_490M, K800_PLL_31_490M,
  32          CX700_31_490M, VX855_31_490M},
  33         {CLK_31_500M, CLE266_PLL_31_500M, K800_PLL_31_500M,
  34          CX700_31_500M, VX855_31_500M},
  35         {CLK_31_728M, CLE266_PLL_31_728M, K800_PLL_31_728M,
  36          CX700_31_728M, VX855_31_728M},
  37         {CLK_32_668M, CLE266_PLL_32_668M, K800_PLL_32_668M,
  38          CX700_32_668M, VX855_32_668M},
  39         {CLK_36_000M, CLE266_PLL_36_000M, K800_PLL_36_000M,
  40          CX700_36_000M, VX855_36_000M},
  41         {CLK_40_000M, CLE266_PLL_40_000M, K800_PLL_40_000M,
  42          CX700_40_000M, VX855_40_000M},
  43         {CLK_41_291M, CLE266_PLL_41_291M, K800_PLL_41_291M,
  44          CX700_41_291M, VX855_41_291M},
  45         {CLK_43_163M, CLE266_PLL_43_163M, K800_PLL_43_163M,
  46          CX700_43_163M, VX855_43_163M},
  47         {CLK_45_250M, CLE266_PLL_45_250M, K800_PLL_45_250M,
  48          CX700_45_250M, VX855_45_250M},
  49         {CLK_46_000M, CLE266_PLL_46_000M, K800_PLL_46_000M,
  50          CX700_46_000M, VX855_46_000M},
  51         {CLK_46_996M, CLE266_PLL_46_996M, K800_PLL_46_996M,
  52          CX700_46_996M, VX855_46_996M},
  53         {CLK_48_000M, CLE266_PLL_48_000M, K800_PLL_48_000M,
  54          CX700_48_000M, VX855_48_000M},
  55         {CLK_48_875M, CLE266_PLL_48_875M, K800_PLL_48_875M,
  56          CX700_48_875M, VX855_48_875M},
  57         {CLK_49_500M, CLE266_PLL_49_500M, K800_PLL_49_500M,
  58          CX700_49_500M, VX855_49_500M},
  59         {CLK_52_406M, CLE266_PLL_52_406M, K800_PLL_52_406M,
  60          CX700_52_406M, VX855_52_406M},
  61         {CLK_52_977M, CLE266_PLL_52_977M, K800_PLL_52_977M,
  62          CX700_52_977M, VX855_52_977M},
  63         {CLK_56_250M, CLE266_PLL_56_250M, K800_PLL_56_250M,
  64          CX700_56_250M, VX855_56_250M},
  65         {CLK_57_275M, 0, 0, 0, VX855_57_275M},
  66         {CLK_60_466M, CLE266_PLL_60_466M, K800_PLL_60_466M,
  67          CX700_60_466M, VX855_60_466M},
  68         {CLK_61_500M, CLE266_PLL_61_500M, K800_PLL_61_500M,
  69          CX700_61_500M, VX855_61_500M},
  70         {CLK_65_000M, CLE266_PLL_65_000M, K800_PLL_65_000M,
  71          CX700_65_000M, VX855_65_000M},
  72         {CLK_65_178M, CLE266_PLL_65_178M, K800_PLL_65_178M,
  73          CX700_65_178M, VX855_65_178M},
  74         {CLK_66_750M, CLE266_PLL_66_750M, K800_PLL_66_750M,
  75          CX700_66_750M, VX855_66_750M},
  76         {CLK_68_179M, CLE266_PLL_68_179M, K800_PLL_68_179M,
  77          CX700_68_179M, VX855_68_179M},
  78         {CLK_69_924M, CLE266_PLL_69_924M, K800_PLL_69_924M,
  79          CX700_69_924M, VX855_69_924M},
  80         {CLK_70_159M, CLE266_PLL_70_159M, K800_PLL_70_159M,
  81          CX700_70_159M, VX855_70_159M},
  82         {CLK_72_000M, CLE266_PLL_72_000M, K800_PLL_72_000M,
  83          CX700_72_000M, VX855_72_000M},
  84         {CLK_78_750M, CLE266_PLL_78_750M, K800_PLL_78_750M,
  85          CX700_78_750M, VX855_78_750M},
  86         {CLK_80_136M, CLE266_PLL_80_136M, K800_PLL_80_136M,
  87          CX700_80_136M, VX855_80_136M},
  88         {CLK_83_375M, CLE266_PLL_83_375M, K800_PLL_83_375M,
  89          CX700_83_375M, VX855_83_375M},
  90         {CLK_83_950M, CLE266_PLL_83_950M, K800_PLL_83_950M,
  91          CX700_83_950M, VX855_83_950M},
  92         {CLK_84_750M, CLE266_PLL_84_750M, K800_PLL_84_750M,
  93          CX700_84_750M, VX855_84_750M},
  94         {CLK_85_860M, CLE266_PLL_85_860M, K800_PLL_85_860M,
  95          CX700_85_860M, VX855_85_860M},
  96         {CLK_88_750M, CLE266_PLL_88_750M, K800_PLL_88_750M,
  97          CX700_88_750M, VX855_88_750M},
  98         {CLK_94_500M, CLE266_PLL_94_500M, K800_PLL_94_500M,
  99          CX700_94_500M, VX855_94_500M},
 100         {CLK_97_750M, CLE266_PLL_97_750M, K800_PLL_97_750M,
 101          CX700_97_750M, VX855_97_750M},
 102         {CLK_101_000M, CLE266_PLL_101_000M, K800_PLL_101_000M,
 103          CX700_101_000M, VX855_101_000M},
 104         {CLK_106_500M, CLE266_PLL_106_500M, K800_PLL_106_500M,
 105          CX700_106_500M, VX855_106_500M},
 106         {CLK_108_000M, CLE266_PLL_108_000M, K800_PLL_108_000M,
 107          CX700_108_000M, VX855_108_000M},
 108         {CLK_113_309M, CLE266_PLL_113_309M, K800_PLL_113_309M,
 109          CX700_113_309M, VX855_113_309M},
 110         {CLK_118_840M, CLE266_PLL_118_840M, K800_PLL_118_840M,
 111          CX700_118_840M, VX855_118_840M},
 112         {CLK_119_000M, CLE266_PLL_119_000M, K800_PLL_119_000M,
 113          CX700_119_000M, VX855_119_000M},
 114         {CLK_121_750M, CLE266_PLL_121_750M, K800_PLL_121_750M,
 115          CX700_121_750M, 0},
 116         {CLK_125_104M, CLE266_PLL_125_104M, K800_PLL_125_104M,
 117          CX700_125_104M, 0},
 118         {CLK_133_308M, CLE266_PLL_133_308M, K800_PLL_133_308M,
 119          CX700_133_308M, 0},
 120         {CLK_135_000M, CLE266_PLL_135_000M, K800_PLL_135_000M,
 121          CX700_135_000M, VX855_135_000M},
 122         {CLK_136_700M, CLE266_PLL_136_700M, K800_PLL_136_700M,
 123          CX700_136_700M, VX855_136_700M},
 124         {CLK_138_400M, CLE266_PLL_138_400M, K800_PLL_138_400M,
 125          CX700_138_400M, VX855_138_400M},
 126         {CLK_146_760M, CLE266_PLL_146_760M, K800_PLL_146_760M,
 127          CX700_146_760M, VX855_146_760M},
 128         {CLK_153_920M, CLE266_PLL_153_920M, K800_PLL_153_920M,
 129          CX700_153_920M, VX855_153_920M},
 130         {CLK_156_000M, CLE266_PLL_156_000M, K800_PLL_156_000M,
 131          CX700_156_000M, VX855_156_000M},
 132         {CLK_157_500M, CLE266_PLL_157_500M, K800_PLL_157_500M,
 133          CX700_157_500M, VX855_157_500M},
 134         {CLK_162_000M, CLE266_PLL_162_000M, K800_PLL_162_000M,
 135          CX700_162_000M, VX855_162_000M},
 136         {CLK_187_000M, CLE266_PLL_187_000M, K800_PLL_187_000M,
 137          CX700_187_000M, VX855_187_000M},
 138         {CLK_193_295M, CLE266_PLL_193_295M, K800_PLL_193_295M,
 139          CX700_193_295M, VX855_193_295M},
 140         {CLK_202_500M, CLE266_PLL_202_500M, K800_PLL_202_500M,
 141          CX700_202_500M, VX855_202_500M},
 142         {CLK_204_000M, CLE266_PLL_204_000M, K800_PLL_204_000M,
 143          CX700_204_000M, VX855_204_000M},
 144         {CLK_218_500M, CLE266_PLL_218_500M, K800_PLL_218_500M,
 145          CX700_218_500M, VX855_218_500M},
 146         {CLK_234_000M, CLE266_PLL_234_000M, K800_PLL_234_000M,
 147          CX700_234_000M, VX855_234_000M},
 148         {CLK_267_250M, CLE266_PLL_267_250M, K800_PLL_267_250M,
 149          CX700_267_250M, VX855_267_250M},
 150         {CLK_297_500M, CLE266_PLL_297_500M, K800_PLL_297_500M,
 151          CX700_297_500M, VX855_297_500M},
 152         {CLK_74_481M, CLE266_PLL_74_481M, K800_PLL_74_481M,
 153          CX700_74_481M, VX855_74_481M},
 154         {CLK_172_798M, CLE266_PLL_172_798M, K800_PLL_172_798M,
 155          CX700_172_798M, VX855_172_798M},
 156         {CLK_122_614M, CLE266_PLL_122_614M, K800_PLL_122_614M,
 157          CX700_122_614M, VX855_122_614M},
 158         {CLK_74_270M, CLE266_PLL_74_270M, K800_PLL_74_270M,
 159          CX700_74_270M, 0},
 160         {CLK_148_500M, CLE266_PLL_148_500M, K800_PLL_148_500M,
 161          CX700_148_500M, VX855_148_500M}
 162 };
 163
 164 static struct fifo_depth_select display_fifo_depth_reg = {
 165         /* IGA1 FIFO Depth_Select */
 166         {IGA1_FIFO_DEPTH_SELECT_REG_NUM, {{SR17, 0, 7} } },
 167         /* IGA2 FIFO Depth_Select */
 168         {IGA2_FIFO_DEPTH_SELECT_REG_NUM,
 169          {{CR68, 4, 7}, {CR94, 7, 7}, {CR95, 7, 7} } }
 170 };
 171
 172 static struct fifo_threshold_select fifo_threshold_select_reg = {
 173         /* IGA1 FIFO Threshold Select */
 174         {IGA1_FIFO_THRESHOLD_REG_NUM, {{SR16, 0, 5}, {SR16, 7, 7} } },
 175         /* IGA2 FIFO Threshold Select */
 176         {IGA2_FIFO_THRESHOLD_REG_NUM, {{CR68, 0, 3}, {CR95, 4, 6} } }
 177 };
 178
 179 static struct fifo_high_threshold_select fifo_high_threshold_select_reg = {
 180         /* IGA1 FIFO High Threshold Select */
 181         {IGA1_FIFO_HIGH_THRESHOLD_REG_NUM, {{SR18, 0, 5}, {SR18, 7, 7} } },
 182         /* IGA2 FIFO High Threshold Select */
 183         {IGA2_FIFO_HIGH_THRESHOLD_REG_NUM, {{CR92, 0, 3}, {CR95, 0, 2} } }
 184 };
 185
 186 static struct display_queue_expire_num display_queue_expire_num_reg = {
 187         /* IGA1 Display Queue Expire Num */
 188         {IGA1_DISPLAY_QUEUE_EXPIRE_NUM_REG_NUM, {{SR22, 0, 4} } },
 189         /* IGA2 Display Queue Expire Num */
 190         {IGA2_DISPLAY_QUEUE_EXPIRE_NUM_REG_NUM, {{CR94, 0, 6} } }
 191 };
 192
 193 /* Definition Fetch Count Registers*/
 194 static struct fetch_count fetch_count_reg = {
 195         /* IGA1 Fetch Count Register */
 196         {IGA1_FETCH_COUNT_REG_NUM, {{SR1C, 0, 7}, {SR1D, 0, 1} } },
 197         /* IGA2 Fetch Count Register */
 198         {IGA2_FETCH_COUNT_REG_NUM, {{CR65, 0, 7}, {CR67, 2, 3} } }
 199 };
 200
 201 static struct iga1_crtc_timing iga1_crtc_reg = {
 202         /* IGA1 Horizontal Total */
 203         {IGA1_HOR_TOTAL_REG_NUM, {{CR00, 0, 7}, {CR36, 3, 3} } },
 204         /* IGA1 Horizontal Addressable Video */
 205         {IGA1_HOR_ADDR_REG_NUM, {{CR01, 0, 7} } },
 206         /* IGA1 Horizontal Blank Start */
 207         {IGA1_HOR_BLANK_START_REG_NUM, {{CR02, 0, 7} } },
 208         /* IGA1 Horizontal Blank End */
 209         {IGA1_HOR_BLANK_END_REG_NUM,
 210          {{CR03, 0, 4}, {CR05, 7, 7}, {CR33, 5, 5} } },
 211         /* IGA1 Horizontal Sync Start */
 212         {IGA1_HOR_SYNC_START_REG_NUM, {{CR04, 0, 7}, {CR33, 4, 4} } },
 213         /* IGA1 Horizontal Sync End */
 214         {IGA1_HOR_SYNC_END_REG_NUM, {{CR05, 0, 4} } },
 215         /* IGA1 Vertical Total */
 216         {IGA1_VER_TOTAL_REG_NUM,
 217          {{CR06, 0, 7}, {CR07, 0, 0}, {CR07, 5, 5}, {CR35, 0, 0} } },
 218         /* IGA1 Vertical Addressable Video */
 219         {IGA1_VER_ADDR_REG_NUM,
 220          {{CR12, 0, 7}, {CR07, 1, 1}, {CR07, 6, 6}, {CR35, 2, 2} } },
 221         /* IGA1 Vertical Blank Start */
 222         {IGA1_VER_BLANK_START_REG_NUM,
 223          {{CR15, 0, 7}, {CR07, 3, 3}, {CR09, 5, 5}, {CR35, 3, 3} } },
 224         /* IGA1 Vertical Blank End */
 225         {IGA1_VER_BLANK_END_REG_NUM, {{CR16, 0, 7} } },
 226         /* IGA1 Vertical Sync Start */
 227         {IGA1_VER_SYNC_START_REG_NUM,
 228          {{CR10, 0, 7}, {CR07, 2, 2}, {CR07, 7, 7}, {CR35, 1, 1} } },
 229         /* IGA1 Vertical Sync End */
 230         {IGA1_VER_SYNC_END_REG_NUM, {{CR11, 0, 3} } }
 231 };
 232
 233 static struct iga2_crtc_timing iga2_crtc_reg = {
 234         /* IGA2 Horizontal Total */
 235         {IGA2_HOR_TOTAL_REG_NUM, {{CR50, 0, 7}, {CR55, 0, 3} } },
 236         /* IGA2 Horizontal Addressable Video */
 237         {IGA2_HOR_ADDR_REG_NUM, {{CR51, 0, 7}, {CR55, 4, 6} } },
 238         /* IGA2 Horizontal Blank Start */
 239         {IGA2_HOR_BLANK_START_REG_NUM, {{CR52, 0, 7}, {CR54, 0, 2} } },
 240         /* IGA2 Horizontal Blank End */
 241         {IGA2_HOR_BLANK_END_REG_NUM,
 242          {{CR53, 0, 7}, {CR54, 3, 5}, {CR5D, 6, 6} } },
 243         /* IGA2 Horizontal Sync Start */
 244         {IGA2_HOR_SYNC_START_REG_NUM,
 245          {{CR56, 0, 7}, {CR54, 6, 7}, {CR5C, 7, 7}, {CR5D, 7, 7} } },
 246         /* IGA2 Horizontal Sync End */
 247         {IGA2_HOR_SYNC_END_REG_NUM, {{CR57, 0, 7}, {CR5C, 6, 6} } },
 248         /* IGA2 Vertical Total */
 249         {IGA2_VER_TOTAL_REG_NUM, {{CR58, 0, 7}, {CR5D, 0, 2} } },
 250         /* IGA2 Vertical Addressable Video */
 251         {IGA2_VER_ADDR_REG_NUM, {{CR59, 0, 7}, {CR5D, 3, 5} } },
 252         /* IGA2 Vertical Blank Start */
 253         {IGA2_VER_BLANK_START_REG_NUM, {{CR5A, 0, 7}, {CR5C, 0, 2} } },
 254         /* IGA2 Vertical Blank End */
 255         {IGA2_VER_BLANK_END_REG_NUM, {{CR5B, 0, 7}, {CR5C, 3, 5} } },
 256         /* IGA2 Vertical Sync Start */
 257         {IGA2_VER_SYNC_START_REG_NUM, {{CR5E, 0, 7}, {CR5F, 5, 7} } },
 258         /* IGA2 Vertical Sync End */
 259         {IGA2_VER_SYNC_END_REG_NUM, {{CR5F, 0, 4} } }
 260 };
 261
 262 static struct rgbLUT palLUT_table[] = {
 263         /* {R,G,B} */
 264         /* Index 0x00~0x03 */
 265         {0x00, 0x00, 0x00}, {0x00, 0x00, 0x2A}, {0x00, 0x2A, 0x00}, {0x00,
 266                                                                      0x2A,
 267                                                                      0x2A},
 268         /* Index 0x04~0x07 */
 269         {0x2A, 0x00, 0x00}, {0x2A, 0x00, 0x2A}, {0x2A, 0x15, 0x00}, {0x2A,
 270                                                                      0x2A,
 271                                                                      0x2A},
 272         /* Index 0x08~0x0B */
 273         {0x15, 0x15, 0x15}, {0x15, 0x15, 0x3F}, {0x15, 0x3F, 0x15}, {0x15,
 274                                                                      0x3F,
 275                                                                      0x3F},
 276         /* Index 0x0C~0x0F */
 277         {0x3F, 0x15, 0x15}, {0x3F, 0x15, 0x3F}, {0x3F, 0x3F, 0x15}, {0x3F,
 278                                                                      0x3F,
 279                                                                      0x3F},
 280         /* Index 0x10~0x13 */
 281         {0x00, 0x00, 0x00}, {0x05, 0x05, 0x05}, {0x08, 0x08, 0x08}, {0x0B,
 282                                                                      0x0B,
 283                                                                      0x0B},
 284         /* Index 0x14~0x17 */
 285         {0x0E, 0x0E, 0x0E}, {0x11, 0x11, 0x11}, {0x14, 0x14, 0x14}, {0x18,
 286                                                                      0x18,
 287                                                                      0x18},
 288         /* Index 0x18~0x1B */
 289         {0x1C, 0x1C, 0x1C}, {0x20, 0x20, 0x20}, {0x24, 0x24, 0x24}, {0x28,
 290                                                                      0x28,
 291                                                                      0x28},
 292         /* Index 0x1C~0x1F */
 293         {0x2D, 0x2D, 0x2D}, {0x32, 0x32, 0x32}, {0x38, 0x38, 0x38}, {0x3F,
 294                                                                      0x3F,
 295                                                                      0x3F},
 296         /* Index 0x20~0x23 */
 297         {0x00, 0x00, 0x3F}, {0x10, 0x00, 0x3F}, {0x1F, 0x00, 0x3F}, {0x2F,
 298                                                                      0x00,
 299                                                                      0x3F},
 300         /* Index 0x24~0x27 */
 301         {0x3F, 0x00, 0x3F}, {0x3F, 0x00, 0x2F}, {0x3F, 0x00, 0x1F}, {0x3F,
 302                                                                      0x00,
 303                                                                      0x10},
 304         /* Index 0x28~0x2B */
 305         {0x3F, 0x00, 0x00}, {0x3F, 0x10, 0x00}, {0x3F, 0x1F, 0x00}, {0x3F,
 306                                                                      0x2F,
 307                                                                      0x00},
 308         /* Index 0x2C~0x2F */
 309         {0x3F, 0x3F, 0x00}, {0x2F, 0x3F, 0x00}, {0x1F, 0x3F, 0x00}, {0x10,
 310                                                                      0x3F,
 311                                                                      0x00},
 312         /* Index 0x30~0x33 */
 313         {0x00, 0x3F, 0x00}, {0x00, 0x3F, 0x10}, {0x00, 0x3F, 0x1F}, {0x00,
 314                                                                      0x3F,
 315                                                                      0x2F},
 316         /* Index 0x34~0x37 */
 317         {0x00, 0x3F, 0x3F}, {0x00, 0x2F, 0x3F}, {0x00, 0x1F, 0x3F}, {0x00,
 318                                                                      0x10,
 319                                                                      0x3F},
 320         /* Index 0x38~0x3B */
 321         {0x1F, 0x1F, 0x3F}, {0x27, 0x1F, 0x3F}, {0x2F, 0x1F, 0x3F}, {0x37,
 322                                                                      0x1F,
 323                                                                      0x3F},
 324         /* Index 0x3C~0x3F */
 325         {0x3F, 0x1F, 0x3F}, {0x3F, 0x1F, 0x37}, {0x3F, 0x1F, 0x2F}, {0x3F,
 326                                                                      0x1F,
 327                                                                      0x27},
 328         /* Index 0x40~0x43 */
 329         {0x3F, 0x1F, 0x1F}, {0x3F, 0x27, 0x1F}, {0x3F, 0x2F, 0x1F}, {0x3F,
 330                                                                      0x3F,
 331                                                                      0x1F},
 332         /* Index 0x44~0x47 */
 333         {0x3F, 0x3F, 0x1F}, {0x37, 0x3F, 0x1F}, {0x2F, 0x3F, 0x1F}, {0x27,
 334                                                                      0x3F,
 335                                                                      0x1F},
 336         /* Index 0x48~0x4B */
 337         {0x1F, 0x3F, 0x1F}, {0x1F, 0x3F, 0x27}, {0x1F, 0x3F, 0x2F}, {0x1F,
 338                                                                      0x3F,
 339                                                                      0x37},
 340         /* Index 0x4C~0x4F */
 341         {0x1F, 0x3F, 0x3F}, {0x1F, 0x37, 0x3F}, {0x1F, 0x2F, 0x3F}, {0x1F,
 342                                                                      0x27,
 343                                                                      0x3F},
 344         /* Index 0x50~0x53 */
 345         {0x2D, 0x2D, 0x3F}, {0x31, 0x2D, 0x3F}, {0x36, 0x2D, 0x3F}, {0x3A,
 346                                                                      0x2D,
 347                                                                      0x3F},
 348         /* Index 0x54~0x57 */
 349         {0x3F, 0x2D, 0x3F}, {0x3F, 0x2D, 0x3A}, {0x3F, 0x2D, 0x36}, {0x3F,
 350                                                                      0x2D,
 351                                                                      0x31},
 352         /* Index 0x58~0x5B */
 353         {0x3F, 0x2D, 0x2D}, {0x3F, 0x31, 0x2D}, {0x3F, 0x36, 0x2D}, {0x3F,
 354                                                                      0x3A,
 355                                                                      0x2D},
 356         /* Index 0x5C~0x5F */
 357         {0x3F, 0x3F, 0x2D}, {0x3A, 0x3F, 0x2D}, {0x36, 0x3F, 0x2D}, {0x31,
 358                                                                      0x3F,
 359                                                                      0x2D},
 360         /* Index 0x60~0x63 */
 361         {0x2D, 0x3F, 0x2D}, {0x2D, 0x3F, 0x31}, {0x2D, 0x3F, 0x36}, {0x2D,
 362                                                                      0x3F,
 363                                                                      0x3A},
 364         /* Index 0x64~0x67 */
 365         {0x2D, 0x3F, 0x3F}, {0x2D, 0x3A, 0x3F}, {0x2D, 0x36, 0x3F}, {0x2D,
 366                                                                      0x31,
 367                                                                      0x3F},
 368         /* Index 0x68~0x6B */
 369         {0x00, 0x00, 0x1C}, {0x07, 0x00, 0x1C}, {0x0E, 0x00, 0x1C}, {0x15,
 370                                                                      0x00,
 371                                                                      0x1C},
 372         /* Index 0x6C~0x6F */
 373         {0x1C, 0x00, 0x1C}, {0x1C, 0x00, 0x15}, {0x1C, 0x00, 0x0E}, {0x1C,
 374                                                                      0x00,
 375                                                                      0x07},
 376         /* Index 0x70~0x73 */
 377         {0x1C, 0x00, 0x00}, {0x1C, 0x07, 0x00}, {0x1C, 0x0E, 0x00}, {0x1C,
 378                                                                      0x15,
 379                                                                      0x00},
 380         /* Index 0x74~0x77 */
 381         {0x1C, 0x1C, 0x00}, {0x15, 0x1C, 0x00}, {0x0E, 0x1C, 0x00}, {0x07,
 382                                                                      0x1C,
 383                                                                      0x00},
 384         /* Index 0x78~0x7B */
 385         {0x00, 0x1C, 0x00}, {0x00, 0x1C, 0x07}, {0x00, 0x1C, 0x0E}, {0x00,
 386                                                                      0x1C,
 387                                                                      0x15},
 388         /* Index 0x7C~0x7F */
 389         {0x00, 0x1C, 0x1C}, {0x00, 0x15, 0x1C}, {0x00, 0x0E, 0x1C}, {0x00,
 390                                                                      0x07,
 391                                                                      0x1C},
 392         /* Index 0x80~0x83 */
 393         {0x0E, 0x0E, 0x1C}, {0x11, 0x0E, 0x1C}, {0x15, 0x0E, 0x1C}, {0x18,
 394                                                                      0x0E,
 395                                                                      0x1C},
 396         /* Index 0x84~0x87 */
 397         {0x1C, 0x0E, 0x1C}, {0x1C, 0x0E, 0x18}, {0x1C, 0x0E, 0x15}, {0x1C,
 398                                                                      0x0E,
 399                                                                      0x11},
 400         /* Index 0x88~0x8B */
 401         {0x1C, 0x0E, 0x0E}, {0x1C, 0x11, 0x0E}, {0x1C, 0x15, 0x0E}, {0x1C,
 402                                                                      0x18,
 403                                                                      0x0E},
 404         /* Index 0x8C~0x8F */
 405         {0x1C, 0x1C, 0x0E}, {0x18, 0x1C, 0x0E}, {0x15, 0x1C, 0x0E}, {0x11,
 406                                                                      0x1C,
 407                                                                      0x0E},
 408         /* Index 0x90~0x93 */
 409         {0x0E, 0x1C, 0x0E}, {0x0E, 0x1C, 0x11}, {0x0E, 0x1C, 0x15}, {0x0E,
 410                                                                      0x1C,
 411                                                                      0x18},
 412         /* Index 0x94~0x97 */
 413         {0x0E, 0x1C, 0x1C}, {0x0E, 0x18, 0x1C}, {0x0E, 0x15, 0x1C}, {0x0E,
 414                                                                      0x11,
 415                                                                      0x1C},
 416         /* Index 0x98~0x9B */
 417         {0x14, 0x14, 0x1C}, {0x16, 0x14, 0x1C}, {0x18, 0x14, 0x1C}, {0x1A,
 418                                                                      0x14,
 419                                                                      0x1C},
 420         /* Index 0x9C~0x9F */
 421         {0x1C, 0x14, 0x1C}, {0x1C, 0x14, 0x1A}, {0x1C, 0x14, 0x18}, {0x1C,
 422                                                                      0x14,
 423                                                                      0x16},
 424         /* Index 0xA0~0xA3 */
 425         {0x1C, 0x14, 0x14}, {0x1C, 0x16, 0x14}, {0x1C, 0x18, 0x14}, {0x1C,
 426                                                                      0x1A,
 427                                                                      0x14},
 428         /* Index 0xA4~0xA7 */
 429         {0x1C, 0x1C, 0x14}, {0x1A, 0x1C, 0x14}, {0x18, 0x1C, 0x14}, {0x16,
 430                                                                      0x1C,
 431                                                                      0x14},
 432         /* Index 0xA8~0xAB */
 433         {0x14, 0x1C, 0x14}, {0x14, 0x1C, 0x16}, {0x14, 0x1C, 0x18}, {0x14,
 434                                                                      0x1C,
 435                                                                      0x1A},
 436         /* Index 0xAC~0xAF */
 437         {0x14, 0x1C, 0x1C}, {0x14, 0x1A, 0x1C}, {0x14, 0x18, 0x1C}, {0x14,
 438                                                                      0x16,
 439                                                                      0x1C},
 440         /* Index 0xB0~0xB3 */
 441         {0x00, 0x00, 0x10}, {0x04, 0x00, 0x10}, {0x08, 0x00, 0x10}, {0x0C,
 442                                                                      0x00,
 443                                                                      0x10},
 444         /* Index 0xB4~0xB7 */
 445         {0x10, 0x00, 0x10}, {0x10, 0x00, 0x0C}, {0x10, 0x00, 0x08}, {0x10,
 446                                                                      0x00,
 447                                                                      0x04},
 448         /* Index 0xB8~0xBB */
 449         {0x10, 0x00, 0x00}, {0x10, 0x04, 0x00}, {0x10, 0x08, 0x00}, {0x10,
 450                                                                      0x0C,
 451                                                                      0x00},
 452         /* Index 0xBC~0xBF */
 453         {0x10, 0x10, 0x00}, {0x0C, 0x10, 0x00}, {0x08, 0x10, 0x00}, {0x04,
 454                                                                      0x10,
 455                                                                      0x00},
 456         /* Index 0xC0~0xC3 */
 457         {0x00, 0x10, 0x00}, {0x00, 0x10, 0x04}, {0x00, 0x10, 0x08}, {0x00,
 458                                                                      0x10,
 459                                                                      0x0C},
 460         /* Index 0xC4~0xC7 */
 461         {0x00, 0x10, 0x10}, {0x00, 0x0C, 0x10}, {0x00, 0x08, 0x10}, {0x00,
 462                                                                      0x04,
 463                                                                      0x10},
 464         /* Index 0xC8~0xCB */
 465         {0x08, 0x08, 0x10}, {0x0A, 0x08, 0x10}, {0x0C, 0x08, 0x10}, {0x0E,
 466                                                                      0x08,
 467                                                                      0x10},
 468         /* Index 0xCC~0xCF */
 469         {0x10, 0x08, 0x10}, {0x10, 0x08, 0x0E}, {0x10, 0x08, 0x0C}, {0x10,
 470                                                                      0x08,
 471                                                                      0x0A},
 472         /* Index 0xD0~0xD3 */
 473         {0x10, 0x08, 0x08}, {0x10, 0x0A, 0x08}, {0x10, 0x0C, 0x08}, {0x10,
 474                                                                      0x0E,
 475                                                                      0x08},
 476         /* Index 0xD4~0xD7 */
 477         {0x10, 0x10, 0x08}, {0x0E, 0x10, 0x08}, {0x0C, 0x10, 0x08}, {0x0A,
 478                                                                      0x10,
 479                                                                      0x08},
 480         /* Index 0xD8~0xDB */
 481         {0x08, 0x10, 0x08}, {0x08, 0x10, 0x0A}, {0x08, 0x10, 0x0C}, {0x08,
 482                                                                      0x10,
 483                                                                      0x0E},
 484         /* Index 0xDC~0xDF */
 485         {0x08, 0x10, 0x10}, {0x08, 0x0E, 0x10}, {0x08, 0x0C, 0x10}, {0x08,
 486                                                                      0x0A,
 487                                                                      0x10},
 488         /* Index 0xE0~0xE3 */
 489         {0x0B, 0x0B, 0x10}, {0x0C, 0x0B, 0x10}, {0x0D, 0x0B, 0x10}, {0x0F,
 490                                                                      0x0B,
 491                                                                      0x10},
 492         /* Index 0xE4~0xE7 */
 493         {0x10, 0x0B, 0x10}, {0x10, 0x0B, 0x0F}, {0x10, 0x0B, 0x0D}, {0x10,
 494                                                                      0x0B,
 495                                                                      0x0C},
 496         /* Index 0xE8~0xEB */
 497         {0x10, 0x0B, 0x0B}, {0x10, 0x0C, 0x0B}, {0x10, 0x0D, 0x0B}, {0x10,
 498                                                                      0x0F,
 499                                                                      0x0B},
 500         /* Index 0xEC~0xEF */
 501         {0x10, 0x10, 0x0B}, {0x0F, 0x10, 0x0B}, {0x0D, 0x10, 0x0B}, {0x0C,
 502                                                                      0x10,
 503                                                                      0x0B},
 504         /* Index 0xF0~0xF3 */
 505         {0x0B, 0x10, 0x0B}, {0x0B, 0x10, 0x0C}, {0x0B, 0x10, 0x0D}, {0x0B,
 506                                                                      0x10,
 507                                                                      0x0F},
 508         /* Index 0xF4~0xF7 */
 509         {0x0B, 0x10, 0x10}, {0x0B, 0x0F, 0x10}, {0x0B, 0x0D, 0x10}, {0x0B,
 510                                                                      0x0C,
 511                                                                      0x10},
 512         /* Index 0xF8~0xFB */
 513         {0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}, {0x00,
 514                                                                      0x00,
 515                                                                      0x00},
 516         /* Index 0xFC~0xFF */
 517         {0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}, {0x00,
 518                                                                      0x00,
 519                                                                      0x00}
 520 };
 521
 522 static void set_crt_output_path(int set_iga);
 523 static void dvi_patch_skew_dvp0(void);
 524 static void dvi_patch_skew_dvp1(void);
 525 static void dvi_patch_skew_dvp_low(void);
 526 static void set_dvi_output_path(int set_iga, int output_interface);
 527 static void set_lcd_output_path(int set_iga, int output_interface);
 528 static void load_fix_bit_crtc_reg(void);
 529 static void init_gfx_chip_info(int chip_type);
 530 static void init_tmds_chip_info(void);
 531 static void init_lvds_chip_info(void);
 532 static void device_screen_off(void);
 533 static void device_screen_on(void);
 534 static void set_display_channel(void);
 535 static void device_off(void);
 536 static void device_on(void);
 537 static void enable_second_display_channel(void);
 538 static void disable_second_display_channel(void);
 539
 540 void viafb_lock_crt(void)
 541 {
 542         viafb_write_reg_mask(CR11, VIACR, BIT7, BIT7);
 543 }
 544
 545 void viafb_unlock_crt(void)
 546 {
 547         viafb_write_reg_mask(CR11, VIACR, 0, BIT7);
 548         viafb_write_reg_mask(CR47, VIACR, 0, BIT0);
 549 }
 550
 551 void write_dac_reg(u8 index, u8 r, u8 g, u8 b)
 552 {
 553         outb(index, LUT_INDEX_WRITE);
 554         outb(r, LUT_DATA);
 555         outb(g, LUT_DATA);
 556         outb(b, LUT_DATA);
 557 }
 558
 559 /*Set IGA path for each device*/
 560 void viafb_set_iga_path(void)
 561 {
 562
 563         if (viafb_SAMM_ON == 1) {
 564                 if (viafb_CRT_ON) {
 565                         if (viafb_primary_dev == CRT_Device)
 566                                 viaparinfo->crt_setting_info->iga_path = IGA1;
 567                         else
 568                                 viaparinfo->crt_setting_info->iga_path = IGA2;
 569                 }
 570
 571                 if (viafb_DVI_ON) {
 572                         if (viafb_primary_dev == DVI_Device)
 573                                 viaparinfo->tmds_setting_info->iga_path = IGA1;
 574                         else
 575                                 viaparinfo->tmds_setting_info->iga_path = IGA2;
 576                 }
 577
 578                 if (viafb_LCD_ON) {
 579                         if (viafb_primary_dev == LCD_Device) {
 580                                 if (viafb_dual_fb &&
 581                                         (viaparinfo->chip_info->gfx_chip_name ==
 582                                         UNICHROME_CLE266)) {
 583                                         viaparinfo->
 584                                         lvds_setting_info->iga_path = IGA2;
 585                                         viaparinfo->
 586                                         crt_setting_info->iga_path = IGA1;
 587                                         viaparinfo->
 588                                         tmds_setting_info->iga_path = IGA1;
 589                                 } else
 590                                         viaparinfo->
 591                                         lvds_setting_info->iga_path = IGA1;
 592                         } else {
 593                                 viaparinfo->lvds_setting_info->iga_path = IGA2;
 594                         }
 595                 }
 596                 if (viafb_LCD2_ON) {
 597                         if (LCD2_Device == viafb_primary_dev)
 598                                 viaparinfo->lvds_setting_info2->iga_path = IGA1;
 599                         else
 600                                 viaparinfo->lvds_setting_info2->iga_path = IGA2;
 601                 }
 602         } else {
 603                 viafb_SAMM_ON = 0;
 604
 605                 if (viafb_CRT_ON && viafb_LCD_ON) {
 606                         viaparinfo->crt_setting_info->iga_path = IGA1;
 607                         viaparinfo->lvds_setting_info->iga_path = IGA2;
 608                 } else if (viafb_CRT_ON && viafb_DVI_ON) {
 609                         viaparinfo->crt_setting_info->iga_path = IGA1;
 610                         viaparinfo->tmds_setting_info->iga_path = IGA2;
 611                 } else if (viafb_LCD_ON && viafb_DVI_ON) {
 612                         viaparinfo->tmds_setting_info->iga_path = IGA1;
 613                         viaparinfo->lvds_setting_info->iga_path = IGA2;
 614                 } else if (viafb_LCD_ON && viafb_LCD2_ON) {
 615                         viaparinfo->lvds_setting_info->iga_path = IGA2;
 616                         viaparinfo->lvds_setting_info2->iga_path = IGA2;
 617                 } else if (viafb_CRT_ON) {
 618                         viaparinfo->crt_setting_info->iga_path = IGA1;
 619                 } else if (viafb_LCD_ON) {
 620                         viaparinfo->lvds_setting_info->iga_path = IGA2;
 621                 } else if (viafb_DVI_ON) {
 622                         viaparinfo->tmds_setting_info->iga_path = IGA1;
 623                 }
 624         }
 625 }
 626
 627 static void set_color_register(u8 index, u8 red, u8 green, u8 blue)
 628 {
 629         outb(0xFF, 0x3C6); /* bit mask of palette */
 630         outb(index, 0x3C8);
 631         outb(red, 0x3C9);
 632         outb(green, 0x3C9);
 633         outb(blue, 0x3C9);
 634 }
 635
 636 void viafb_set_primary_color_register(u8 index, u8 red, u8 green, u8 blue)
 637 {
 638         viafb_write_reg_mask(0x1A, VIASR, 0x00, 0x01);
 639         set_color_register(index, red, green, blue);
 640 }
 641
 642 void viafb_set_secondary_color_register(u8 index, u8 red, u8 green, u8 blue)
 643 {
 644         viafb_write_reg_mask(0x1A, VIASR, 0x01, 0x01);
 645         set_color_register(index, red, green, blue);
 646 }
 647
 648 void viafb_set_output_path(int device, int set_iga, int output_interface)
 649 {
 650         switch (device) {
 651         case DEVICE_CRT:
 652                 set_crt_output_path(set_iga);
 653                 break;
 654         case DEVICE_DVI:
 655                 set_dvi_output_path(set_iga, output_interface);
 656                 break;
 657         case DEVICE_LCD:
 658                 set_lcd_output_path(set_iga, output_interface);
 659                 break;
 660         }
 661 }
 662
 663 static void set_crt_output_path(int set_iga)
 664 {
 665         viafb_write_reg_mask(CR36, VIACR, 0x00, BIT4 + BIT5);
 666
 667         switch (set_iga) {
 668         case IGA1:
 669                 viafb_write_reg_mask(SR16, VIASR, 0x00, BIT6);
 670                 break;
 671         case IGA2:
 672                 viafb_write_reg_mask(CR6A, VIACR, 0xC0, BIT6 + BIT7);
 673                 viafb_write_reg_mask(SR16, VIASR, 0x40, BIT6);
 674                 break;
 675         }
 676 }
 677
 678 static void dvi_patch_skew_dvp0(void)
 679 {
 680         /* Reset data driving first: */
 681         viafb_write_reg_mask(SR1B, VIASR, 0, BIT1);
 682         viafb_write_reg_mask(SR2A, VIASR, 0, BIT4);
 683
 684         switch (viaparinfo->chip_info->gfx_chip_name) {
 685         case UNICHROME_P4M890:
 686                 {
 687                         if ((viaparinfo->tmds_setting_info->h_active == 1600) &&
 688                                 (viaparinfo->tmds_setting_info->v_active ==
 689                                 1200))
 690                                 viafb_write_reg_mask(CR96, VIACR, 0x03,
 691                                                BIT0 + BIT1 + BIT2);
 692                         else
 693                                 viafb_write_reg_mask(CR96, VIACR, 0x07,
 694                                                BIT0 + BIT1 + BIT2);
 695                         break;
 696                 }
 697
 698         case UNICHROME_P4M900:
 699                 {
 700                         viafb_write_reg_mask(CR96, VIACR, 0x07,
 701                                        BIT0 + BIT1 + BIT2 + BIT3);
 702                         viafb_write_reg_mask(SR1B, VIASR, 0x02, BIT1);
 703                         viafb_write_reg_mask(SR2A, VIASR, 0x10, BIT4);
 704                         break;
 705                 }
 706
 707         default:
 708                 {
 709                         break;
 710                 }
 711         }
 712 }
 713
 714 static void dvi_patch_skew_dvp1(void)
 715 {
 716         switch (viaparinfo->chip_info->gfx_chip_name) {
 717         case UNICHROME_CX700:
 718                 {
 719                         break;
 720                 }
 721
 722         default:
 723                 {
 724                         break;
 725                 }
 726         }
 727 }
 728
 729 static void dvi_patch_skew_dvp_low(void)
 730 {
 731         switch (viaparinfo->chip_info->gfx_chip_name) {
 732         case UNICHROME_K8M890:
 733                 {
 734                         viafb_write_reg_mask(CR99, VIACR, 0x03, BIT0 + BIT1);
 735                         break;
 736                 }
 737
 738         case UNICHROME_P4M900:
 739                 {
 740                         viafb_write_reg_mask(CR99, VIACR, 0x08,
 741                                        BIT0 + BIT1 + BIT2 + BIT3);
 742                         break;
 743                 }
 744
 745         case UNICHROME_P4M890:
 746                 {
 747                         viafb_write_reg_mask(CR99, VIACR, 0x0F,
 748                                        BIT0 + BIT1 + BIT2 + BIT3);
 749                         break;
 750                 }
 751
 752         default:
 753                 {
 754                         break;
 755                 }
 756         }
 757 }
 758
 759 static void set_dvi_output_path(int set_iga, int output_interface)
 760 {
 761         switch (output_interface) {
 762         case INTERFACE_DVP0:
 763                 viafb_write_reg_mask(CR6B, VIACR, 0x01, BIT0);
 764
 765                 if (set_iga == IGA1) {
 766                         viafb_write_reg_mask(CR96, VIACR, 0x00, BIT4);
 767                         viafb_write_reg_mask(CR6C, VIACR, 0x21, BIT0 +
 768                                 BIT5 + BIT7);
 769                 } else {
 770                         viafb_write_reg_mask(CR96, VIACR, 0x10, BIT4);
 771                         viafb_write_reg_mask(CR6C, VIACR, 0xA1, BIT0 +
 772                                 BIT5 + BIT7);
 773                 }
 774
 775                 viafb_write_reg_mask(SR1E, VIASR, 0xC0, BIT7 + BIT6);
 776
 777                 dvi_patch_skew_dvp0();
 778                 break;
 779
 780         case INTERFACE_DVP1:
 781                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266) {
 782                         if (set_iga == IGA1)
 783                                 viafb_write_reg_mask(CR93, VIACR, 0x21,
 784                                                BIT0 + BIT5 + BIT7);
 785                         else
 786                                 viafb_write_reg_mask(CR93, VIACR, 0xA1,
 787                                                BIT0 + BIT5 + BIT7);
 788                 } else {
 789                         if (set_iga == IGA1)
 790                                 viafb_write_reg_mask(CR9B, VIACR, 0x00, BIT4);
 791                         else
 792                                 viafb_write_reg_mask(CR9B, VIACR, 0x10, BIT4);
 793                 }
 794
 795                 viafb_write_reg_mask(SR1E, VIASR, 0x30, BIT4 + BIT5);
 796                 dvi_patch_skew_dvp1();
 797                 break;
 798         case INTERFACE_DFP_HIGH:
 799                 if (viaparinfo->chip_info->gfx_chip_name != UNICHROME_CLE266) {
 800                         if (set_iga == IGA1) {
 801                                 viafb_write_reg_mask(CR96, VIACR, 0x00, BIT4);
 802                                 viafb_write_reg_mask(CR97, VIACR, 0x03,
 803                                                BIT0 + BIT1 + BIT4);
 804                         } else {
 805                                 viafb_write_reg_mask(CR96, VIACR, 0x10, BIT4);
 806                                 viafb_write_reg_mask(CR97, VIACR, 0x13,
 807                                                BIT0 + BIT1 + BIT4);
 808                         }
 809                 }
 810                 viafb_write_reg_mask(SR2A, VIASR, 0x0C, BIT2 + BIT3);
 811                 break;
 812
 813         case INTERFACE_DFP_LOW:
 814                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266)
 815                         break;
 816
 817                 if (set_iga == IGA1) {
 818                         viafb_write_reg_mask(CR99, VIACR, 0x00, BIT4);
 819                         viafb_write_reg_mask(CR9B, VIACR, 0x00, BIT4);
 820                 } else {
 821                         viafb_write_reg_mask(CR99, VIACR, 0x10, BIT4);
 822                         viafb_write_reg_mask(CR9B, VIACR, 0x10, BIT4);
 823                 }
 824
 825                 viafb_write_reg_mask(SR2A, VIASR, 0x03, BIT0 + BIT1);
 826                 dvi_patch_skew_dvp_low();
 827                 break;
 828
 829         case INTERFACE_TMDS:
 830                 if (set_iga == IGA1)
 831                         viafb_write_reg_mask(CR99, VIACR, 0x00, BIT4);
 832                 else
 833                         viafb_write_reg_mask(CR99, VIACR, 0x10, BIT4);
 834                 break;
 835         }
 836
 837         if (set_iga == IGA2) {
 838                 enable_second_display_channel();
 839                 /* Disable LCD Scaling */
 840                 viafb_write_reg_mask(CR79, VIACR, 0x00, BIT0);
 841         }
 842 }
 843
 844 static void set_lcd_output_path(int set_iga, int output_interface)
 845 {
 846         DEBUG_MSG(KERN_INFO
 847                   "set_lcd_output_path, iga:%d,out_interface:%d\n",
 848                   set_iga, output_interface);
 849         switch (set_iga) {
 850         case IGA1:
 851                 viafb_write_reg_mask(CR6B, VIACR, 0x00, BIT3);
 852                 viafb_write_reg_mask(CR6A, VIACR, 0x08, BIT3);
 853
 854                 disable_second_display_channel();
 855                 break;
 856
 857         case IGA2:
 858                 viafb_write_reg_mask(CR6B, VIACR, 0x00, BIT3);
 859                 viafb_write_reg_mask(CR6A, VIACR, 0x08, BIT3);
 860
 861                 enable_second_display_channel();
 862                 break;
 863         }
 864
 865         switch (output_interface) {
 866         case INTERFACE_DVP0:
 867                 if (set_iga == IGA1) {
 868                         viafb_write_reg_mask(CR96, VIACR, 0x00, BIT4);
 869                 } else {
 870                         viafb_write_reg(CR91, VIACR, 0x00);
 871                         viafb_write_reg_mask(CR96, VIACR, 0x10, BIT4);
 872                 }
 873                 break;
 874
 875         case INTERFACE_DVP1:
 876                 if (set_iga == IGA1)
 877                         viafb_write_reg_mask(CR9B, VIACR, 0x00, BIT4);
 878                 else {
 879                         viafb_write_reg(CR91, VIACR, 0x00);
 880                         viafb_write_reg_mask(CR9B, VIACR, 0x10, BIT4);
 881                 }
 882                 break;
 883
 884         case INTERFACE_DFP_HIGH:
 885                 if (set_iga == IGA1)
 886                         viafb_write_reg_mask(CR97, VIACR, 0x00, BIT4);
 887                 else {
 888                         viafb_write_reg(CR91, VIACR, 0x00);
 889                         viafb_write_reg_mask(CR97, VIACR, 0x10, BIT4);
 890                         viafb_write_reg_mask(CR96, VIACR, 0x10, BIT4);
 891                 }
 892                 break;
 893
 894         case INTERFACE_DFP_LOW:
 895                 if (set_iga == IGA1)
 896                         viafb_write_reg_mask(CR99, VIACR, 0x00, BIT4);
 897                 else {
 898                         viafb_write_reg(CR91, VIACR, 0x00);
 899                         viafb_write_reg_mask(CR99, VIACR, 0x10, BIT4);
 900                         viafb_write_reg_mask(CR9B, VIACR, 0x10, BIT4);
 901                 }
 902
 903                 break;
 904
 905         case INTERFACE_DFP:
 906                 if ((UNICHROME_K8M890 == viaparinfo->chip_info->gfx_chip_name)
 907                     || (UNICHROME_P4M890 ==
 908                     viaparinfo->chip_info->gfx_chip_name))
 909                         viafb_write_reg_mask(CR97, VIACR, 0x84,
 910                                        BIT7 + BIT2 + BIT1 + BIT0);
 911                 if (set_iga == IGA1) {
 912                         viafb_write_reg_mask(CR97, VIACR, 0x00, BIT4);
 913                         viafb_write_reg_mask(CR99, VIACR, 0x00, BIT4);
 914                 } else {
 915                         viafb_write_reg(CR91, VIACR, 0x00);
 916                         viafb_write_reg_mask(CR97, VIACR, 0x10, BIT4);
 917                         viafb_write_reg_mask(CR99, VIACR, 0x10, BIT4);
 918                 }
 919                 break;
 920
 921         case INTERFACE_LVDS0:
 922         case INTERFACE_LVDS0LVDS1:
 923                 if (set_iga == IGA1)
 924                         viafb_write_reg_mask(CR99, VIACR, 0x00, BIT4);
 925                 else
 926                         viafb_write_reg_mask(CR99, VIACR, 0x10, BIT4);
 927
 928                 break;
 929
 930         case INTERFACE_LVDS1:
 931                 if (set_iga == IGA1)
 932                         viafb_write_reg_mask(CR97, VIACR, 0x00, BIT4);
 933                 else
 934                         viafb_write_reg_mask(CR97, VIACR, 0x10, BIT4);
 935                 break;
 936         }
 937 }
 938
 939 static void load_fix_bit_crtc_reg(void)
 940 {
 941         /* always set to 1 */
 942         viafb_write_reg_mask(CR03, VIACR, 0x80, BIT7);
 943         /* line compare should set all bits = 1 (extend modes) */
 944         viafb_write_reg(CR18, VIACR, 0xff);
 945         /* line compare should set all bits = 1 (extend modes) */
 946         viafb_write_reg_mask(CR07, VIACR, 0x10, BIT4);
 947         /* line compare should set all bits = 1 (extend modes) */
 948         viafb_write_reg_mask(CR09, VIACR, 0x40, BIT6);
 949         /* line compare should set all bits = 1 (extend modes) */
 950         viafb_write_reg_mask(CR35, VIACR, 0x10, BIT4);
 951         /* line compare should set all bits = 1 (extend modes) */
 952         viafb_write_reg_mask(CR33, VIACR, 0x06, BIT0 + BIT1 + BIT2);
 953         /*viafb_write_reg_mask(CR32, VIACR, 0x01, BIT0); */
 954         /* extend mode always set to e3h */
 955         viafb_write_reg(CR17, VIACR, 0xe3);
 956         /* extend mode always set to 0h */
 957         viafb_write_reg(CR08, VIACR, 0x00);
 958         /* extend mode always set to 0h */
 959         viafb_write_reg(CR14, VIACR, 0x00);
 960
 961         /* If K8M800, enable Prefetch Mode. */
 962         if ((viaparinfo->chip_info->gfx_chip_name == UNICHROME_K800)
 963                 || (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K8M890))
 964                 viafb_write_reg_mask(CR33, VIACR, 0x08, BIT3);
 965         if ((viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266)
 966             && (viaparinfo->chip_info->gfx_chip_revision == CLE266_REVISION_AX))
 967                 viafb_write_reg_mask(SR1A, VIASR, 0x02, BIT1);
 968
 969 }
 970
 971 void viafb_load_reg(int timing_value, int viafb_load_reg_num,
 972         struct io_register *reg,
 973               int io_type)
 974 {
 975         int reg_mask;
 976         int bit_num = 0;
 977         int data;
 978         int i, j;
 979         int shift_next_reg;
 980         int start_index, end_index, cr_index;
 981         u16 get_bit;
 982
 983         for (i = 0; i < viafb_load_reg_num; i++) {
 984                 reg_mask = 0;
 985                 data = 0;
 986                 start_index = reg[i].start_bit;
 987                 end_index = reg[i].end_bit;
 988                 cr_index = reg[i].io_addr;
 989
 990                 shift_next_reg = bit_num;
 991                 for (j = start_index; j <= end_index; j++) {
 992                         /*if (bit_num==8) timing_value = timing_value >>8; */
 993                         reg_mask = reg_mask | (BIT0 << j);
 994                         get_bit = (timing_value & (BIT0 << bit_num));
 995                         data =
 996                             data | ((get_bit >> shift_next_reg) << start_index);
 997                         bit_num++;
 998                 }
 999                 if (io_type == VIACR)
1000                         viafb_write_reg_mask(cr_index, VIACR, data, reg_mask);
1001                 else
1002                         viafb_write_reg_mask(cr_index, VIASR, data, reg_mask);
1003         }
1004
1005 }
1006
1007 /* Write Registers */
1008 void viafb_write_regx(struct io_reg RegTable[], int ItemNum)
1009 {
1010         int i;
1011
1012         /*DEBUG_MSG(KERN_INFO "Table Size : %x!!\n",ItemNum ); */
1013
1014         for (i = 0; i < ItemNum; i++)
1015                 via_write_reg_mask(RegTable[i].port, RegTable[i].index,
1016                         RegTable[i].value, RegTable[i].mask);
1017 }
1018
1019 void viafb_load_fetch_count_reg(int h_addr, int bpp_byte, int set_iga)
1020 {
1021         int reg_value;
1022         int viafb_load_reg_num;
1023         struct io_register *reg = NULL;
1024
1025         switch (set_iga) {
1026         case IGA1:
1027                 reg_value = IGA1_FETCH_COUNT_FORMULA(h_addr, bpp_byte);
1028                 viafb_load_reg_num = fetch_count_reg.
1029                         iga1_fetch_count_reg.reg_num;
1030                 reg = fetch_count_reg.iga1_fetch_count_reg.reg;
1031                 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR);
1032                 break;
1033         case IGA2:
1034                 reg_value = IGA2_FETCH_COUNT_FORMULA(h_addr, bpp_byte);
1035                 viafb_load_reg_num = fetch_count_reg.
1036                         iga2_fetch_count_reg.reg_num;
1037                 reg = fetch_count_reg.iga2_fetch_count_reg.reg;
1038                 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR);
1039                 break;
1040         }
1041
1042 }
1043
1044 void viafb_load_FIFO_reg(int set_iga, int hor_active, int ver_active)
1045 {
1046         int reg_value;
1047         int viafb_load_reg_num;
1048         struct io_register *reg = NULL;
1049         int iga1_fifo_max_depth = 0, iga1_fifo_threshold =
1050             0, iga1_fifo_high_threshold = 0, iga1_display_queue_expire_num = 0;
1051         int iga2_fifo_max_depth = 0, iga2_fifo_threshold =
1052             0, iga2_fifo_high_threshold = 0, iga2_display_queue_expire_num = 0;
1053
1054         if (set_iga == IGA1) {
1055                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K800) {
1056                         iga1_fifo_max_depth = K800_IGA1_FIFO_MAX_DEPTH;
1057                         iga1_fifo_threshold = K800_IGA1_FIFO_THRESHOLD;
1058                         iga1_fifo_high_threshold =
1059                             K800_IGA1_FIFO_HIGH_THRESHOLD;
1060                         /* If resolution > 1280x1024, expire length = 64, else
1061                            expire length = 128 */
1062                         if ((hor_active > 1280) && (ver_active > 1024))
1063                                 iga1_display_queue_expire_num = 16;
1064                         else
1065                                 iga1_display_queue_expire_num =
1066                                     K800_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1067
1068                 }
1069
1070                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_PM800) {
1071                         iga1_fifo_max_depth = P880_IGA1_FIFO_MAX_DEPTH;
1072                         iga1_fifo_threshold = P880_IGA1_FIFO_THRESHOLD;
1073                         iga1_fifo_high_threshold =
1074                             P880_IGA1_FIFO_HIGH_THRESHOLD;
1075                         iga1_display_queue_expire_num =
1076                             P880_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1077
1078                         /* If resolution > 1280x1024, expire length = 64, else
1079                            expire length = 128 */
1080                         if ((hor_active > 1280) && (ver_active > 1024))
1081                                 iga1_display_queue_expire_num = 16;
1082                         else
1083                                 iga1_display_queue_expire_num =
1084                                     P880_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1085                 }
1086
1087                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CN700) {
1088                         iga1_fifo_max_depth = CN700_IGA1_FIFO_MAX_DEPTH;
1089                         iga1_fifo_threshold = CN700_IGA1_FIFO_THRESHOLD;
1090                         iga1_fifo_high_threshold =
1091                             CN700_IGA1_FIFO_HIGH_THRESHOLD;
1092
1093                         /* If resolution > 1280x1024, expire length = 64,
1094                            else expire length = 128 */
1095                         if ((hor_active > 1280) && (ver_active > 1024))
1096                                 iga1_display_queue_expire_num = 16;
1097                         else
1098                                 iga1_display_queue_expire_num =
1099                                     CN700_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1100                 }
1101
1102                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CX700) {
1103                         iga1_fifo_max_depth = CX700_IGA1_FIFO_MAX_DEPTH;
1104                         iga1_fifo_threshold = CX700_IGA1_FIFO_THRESHOLD;
1105                         iga1_fifo_high_threshold =
1106                             CX700_IGA1_FIFO_HIGH_THRESHOLD;
1107                         iga1_display_queue_expire_num =
1108                             CX700_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1109                 }
1110
1111                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K8M890) {
1112                         iga1_fifo_max_depth = K8M890_IGA1_FIFO_MAX_DEPTH;
1113                         iga1_fifo_threshold = K8M890_IGA1_FIFO_THRESHOLD;
1114                         iga1_fifo_high_threshold =
1115                             K8M890_IGA1_FIFO_HIGH_THRESHOLD;
1116                         iga1_display_queue_expire_num =
1117                             K8M890_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1118                 }
1119
1120                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_P4M890) {
1121                         iga1_fifo_max_depth = P4M890_IGA1_FIFO_MAX_DEPTH;
1122                         iga1_fifo_threshold = P4M890_IGA1_FIFO_THRESHOLD;
1123                         iga1_fifo_high_threshold =
1124                             P4M890_IGA1_FIFO_HIGH_THRESHOLD;
1125                         iga1_display_queue_expire_num =
1126                             P4M890_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1127                 }
1128
1129                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_P4M900) {
1130                         iga1_fifo_max_depth = P4M900_IGA1_FIFO_MAX_DEPTH;
1131                         iga1_fifo_threshold = P4M900_IGA1_FIFO_THRESHOLD;
1132                         iga1_fifo_high_threshold =
1133                             P4M900_IGA1_FIFO_HIGH_THRESHOLD;
1134                         iga1_display_queue_expire_num =
1135                             P4M900_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1136                 }
1137
1138                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_VX800) {
1139                         iga1_fifo_max_depth = VX800_IGA1_FIFO_MAX_DEPTH;
1140                         iga1_fifo_threshold = VX800_IGA1_FIFO_THRESHOLD;
1141                         iga1_fifo_high_threshold =
1142                             VX800_IGA1_FIFO_HIGH_THRESHOLD;
1143                         iga1_display_queue_expire_num =
1144                             VX800_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1145                 }
1146
1147                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_VX855) {
1148                         iga1_fifo_max_depth = VX855_IGA1_FIFO_MAX_DEPTH;
1149                         iga1_fifo_threshold = VX855_IGA1_FIFO_THRESHOLD;
1150                         iga1_fifo_high_threshold =
1151                             VX855_IGA1_FIFO_HIGH_THRESHOLD;
1152                         iga1_display_queue_expire_num =
1153                             VX855_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1154                 }
1155
1156                 /* Set Display FIFO Depath Select */
1157                 reg_value = IGA1_FIFO_DEPTH_SELECT_FORMULA(iga1_fifo_max_depth);
1158                 viafb_load_reg_num =
1159                     display_fifo_depth_reg.iga1_fifo_depth_select_reg.reg_num;
1160                 reg = display_fifo_depth_reg.iga1_fifo_depth_select_reg.reg;
1161                 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR);
1162
1163                 /* Set Display FIFO Threshold Select */
1164                 reg_value = IGA1_FIFO_THRESHOLD_FORMULA(iga1_fifo_threshold);
1165                 viafb_load_reg_num =
1166                     fifo_threshold_select_reg.
1167                     iga1_fifo_threshold_select_reg.reg_num;
1168                 reg =
1169                     fifo_threshold_select_reg.
1170                     iga1_fifo_threshold_select_reg.reg;
1171                 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR);
1172
1173                 /* Set FIFO High Threshold Select */
1174                 reg_value =
1175                     IGA1_FIFO_HIGH_THRESHOLD_FORMULA(iga1_fifo_high_threshold);
1176                 viafb_load_reg_num =
1177                     fifo_high_threshold_select_reg.
1178                     iga1_fifo_high_threshold_select_reg.reg_num;
1179                 reg =
1180                     fifo_high_threshold_select_reg.
1181                     iga1_fifo_high_threshold_select_reg.reg;
1182                 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR);
1183
1184                 /* Set Display Queue Expire Num */
1185                 reg_value =
1186                     IGA1_DISPLAY_QUEUE_EXPIRE_NUM_FORMULA
1187                     (iga1_display_queue_expire_num);
1188                 viafb_load_reg_num =
1189                     display_queue_expire_num_reg.
1190                     iga1_display_queue_expire_num_reg.reg_num;
1191                 reg =
1192                     display_queue_expire_num_reg.
1193                     iga1_display_queue_expire_num_reg.reg;
1194                 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR);
1195
1196         } else {
1197                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K800) {
1198                         iga2_fifo_max_depth = K800_IGA2_FIFO_MAX_DEPTH;
1199                         iga2_fifo_threshold = K800_IGA2_FIFO_THRESHOLD;
1200                         iga2_fifo_high_threshold =
1201                             K800_IGA2_FIFO_HIGH_THRESHOLD;
1202
1203                         /* If resolution > 1280x1024, expire length = 64,
1204                            else  expire length = 128 */
1205                         if ((hor_active > 1280) && (ver_active > 1024))
1206                                 iga2_display_queue_expire_num = 16;
1207                         else
1208                                 iga2_display_queue_expire_num =
1209                                     K800_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1210                 }
1211
1212                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_PM800) {
1213                         iga2_fifo_max_depth = P880_IGA2_FIFO_MAX_DEPTH;
1214                         iga2_fifo_threshold = P880_IGA2_FIFO_THRESHOLD;
1215                         iga2_fifo_high_threshold =
1216                             P880_IGA2_FIFO_HIGH_THRESHOLD;
1217
1218                         /* If resolution > 1280x1024, expire length = 64,
1219                            else  expire length = 128 */
1220                         if ((hor_active > 1280) && (ver_active > 1024))
1221                                 iga2_display_queue_expire_num = 16;
1222                         else
1223                                 iga2_display_queue_expire_num =
1224                                     P880_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1225                 }
1226
1227                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CN700) {
1228                         iga2_fifo_max_depth = CN700_IGA2_FIFO_MAX_DEPTH;
1229                         iga2_fifo_threshold = CN700_IGA2_FIFO_THRESHOLD;
1230                         iga2_fifo_high_threshold =
1231                             CN700_IGA2_FIFO_HIGH_THRESHOLD;
1232
1233                         /* If resolution > 1280x1024, expire length = 64,
1234                            else expire length = 128 */
1235                         if ((hor_active > 1280) && (ver_active > 1024))
1236                                 iga2_display_queue_expire_num = 16;
1237                         else
1238                                 iga2_display_queue_expire_num =
1239                                     CN700_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1240                 }
1241
1242                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CX700) {
1243                         iga2_fifo_max_depth = CX700_IGA2_FIFO_MAX_DEPTH;
1244                         iga2_fifo_threshold = CX700_IGA2_FIFO_THRESHOLD;
1245                         iga2_fifo_high_threshold =
1246                             CX700_IGA2_FIFO_HIGH_THRESHOLD;
1247                         iga2_display_queue_expire_num =
1248                             CX700_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1249                 }
1250
1251                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K8M890) {
1252                         iga2_fifo_max_depth = K8M890_IGA2_FIFO_MAX_DEPTH;
1253                         iga2_fifo_threshold = K8M890_IGA2_FIFO_THRESHOLD;
1254                         iga2_fifo_high_threshold =
1255                             K8M890_IGA2_FIFO_HIGH_THRESHOLD;
1256                         iga2_display_queue_expire_num =
1257                             K8M890_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1258                 }
1259
1260                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_P4M890) {
1261                         iga2_fifo_max_depth = P4M890_IGA2_FIFO_MAX_DEPTH;
1262                         iga2_fifo_threshold = P4M890_IGA2_FIFO_THRESHOLD;
1263                         iga2_fifo_high_threshold =
1264                             P4M890_IGA2_FIFO_HIGH_THRESHOLD;
1265                         iga2_display_queue_expire_num =
1266                             P4M890_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1267                 }
1268
1269                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_P4M900) {
1270                         iga2_fifo_max_depth = P4M900_IGA2_FIFO_MAX_DEPTH;
1271                         iga2_fifo_threshold = P4M900_IGA2_FIFO_THRESHOLD;
1272                         iga2_fifo_high_threshold =
1273                             P4M900_IGA2_FIFO_HIGH_THRESHOLD;
1274                         iga2_display_queue_expire_num =
1275                             P4M900_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1276                 }
1277
1278                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_VX800) {
1279                         iga2_fifo_max_depth = VX800_IGA2_FIFO_MAX_DEPTH;
1280                         iga2_fifo_threshold = VX800_IGA2_FIFO_THRESHOLD;
1281                         iga2_fifo_high_threshold =
1282                             VX800_IGA2_FIFO_HIGH_THRESHOLD;
1283                         iga2_display_queue_expire_num =
1284                             VX800_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1285                 }
1286
1287                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_VX855) {
1288                         iga2_fifo_max_depth = VX855_IGA2_FIFO_MAX_DEPTH;
1289                         iga2_fifo_threshold = VX855_IGA2_FIFO_THRESHOLD;
1290                         iga2_fifo_high_threshold =
1291                             VX855_IGA2_FIFO_HIGH_THRESHOLD;
1292                         iga2_display_queue_expire_num =
1293                             VX855_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1294                 }
1295
1296                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K800) {
1297                         /* Set Display FIFO Depath Select */
1298                         reg_value =
1299                             IGA2_FIFO_DEPTH_SELECT_FORMULA(iga2_fifo_max_depth)
1300                             - 1;
1301                         /* Patch LCD in IGA2 case */
1302                         viafb_load_reg_num =
1303                             display_fifo_depth_reg.
1304                             iga2_fifo_depth_select_reg.reg_num;
1305                         reg =
1306                             display_fifo_depth_reg.
1307                             iga2_fifo_depth_select_reg.reg;
1308                         viafb_load_reg(reg_value,
1309                                 viafb_load_reg_num, reg, VIACR);
1310                 } else {
1311
1312                         /* Set Display FIFO Depath Select */
1313                         reg_value =
1314                             IGA2_FIFO_DEPTH_SELECT_FORMULA(iga2_fifo_max_depth);
1315                         viafb_load_reg_num =
1316                             display_fifo_depth_reg.
1317                             iga2_fifo_depth_select_reg.reg_num;
1318                         reg =
1319                             display_fifo_depth_reg.
1320                             iga2_fifo_depth_select_reg.reg;
1321                         viafb_load_reg(reg_value,
1322                                 viafb_load_reg_num, reg, VIACR);
1323                 }
1324
1325                 /* Set Display FIFO Threshold Select */
1326                 reg_value = IGA2_FIFO_THRESHOLD_FORMULA(iga2_fifo_threshold);
1327                 viafb_load_reg_num =
1328                     fifo_threshold_select_reg.
1329                     iga2_fifo_threshold_select_reg.reg_num;
1330                 reg =
1331                     fifo_threshold_select_reg.
1332                     iga2_fifo_threshold_select_reg.reg;
1333                 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR);
1334
1335                 /* Set FIFO High Threshold Select */
1336                 reg_value =
1337                     IGA2_FIFO_HIGH_THRESHOLD_FORMULA(iga2_fifo_high_threshold);
1338                 viafb_load_reg_num =
1339                     fifo_high_threshold_select_reg.
1340                     iga2_fifo_high_threshold_select_reg.reg_num;
1341                 reg =
1342                     fifo_high_threshold_select_reg.
1343                     iga2_fifo_high_threshold_select_reg.reg;
1344                 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR);
1345
1346                 /* Set Display Queue Expire Num */
1347                 reg_value =
1348                     IGA2_DISPLAY_QUEUE_EXPIRE_NUM_FORMULA
1349                     (iga2_display_queue_expire_num);
1350                 viafb_load_reg_num =
1351                     display_queue_expire_num_reg.
1352                     iga2_display_queue_expire_num_reg.reg_num;
1353                 reg =
1354                     display_queue_expire_num_reg.
1355                     iga2_display_queue_expire_num_reg.reg;
1356                 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR);
1357
1358         }
1359
1360 }
1361
1362 u32 viafb_get_clk_value(int clk)
1363 {
1364         int i;
1365
1366         for (i = 0; i < NUM_TOTAL_PLL_TABLE; i++) {
1367                 if (clk == pll_value[i].clk) {
1368                         switch (viaparinfo->chip_info->gfx_chip_name) {
1369                         case UNICHROME_CLE266:
1370                         case UNICHROME_K400:
1371                                 return pll_value[i].cle266_pll;
1372
1373                         case UNICHROME_K800:
1374                         case UNICHROME_PM800:
1375                         case UNICHROME_CN700:
1376                                 return pll_value[i].k800_pll;
1377
1378                         case UNICHROME_CX700:
1379                         case UNICHROME_K8M890:
1380                         case UNICHROME_P4M890:
1381                         case UNICHROME_P4M900:
1382                         case UNICHROME_VX800:
1383                                 return pll_value[i].cx700_pll;
1384                         case UNICHROME_VX855:
1385                                 return pll_value[i].vx855_pll;
1386                         }
1387                 }
1388         }
1389
1390         DEBUG_MSG(KERN_INFO "Can't find match PLL value\n\n");
1391         return 0;
1392 }
1393
1394 /* Set VCLK*/
1395 void viafb_set_vclock(u32 CLK, int set_iga)
1396 {
1397         /* H.W. Reset : ON */
1398         viafb_write_reg_mask(CR17, VIACR, 0x00, BIT7);
1399
1400         if (set_iga == IGA1) {
1401                 /* Change D,N FOR VCLK */
1402                 switch (viaparinfo->chip_info->gfx_chip_name) {
1403                 case UNICHROME_CLE266:
1404                 case UNICHROME_K400:
1405                         viafb_write_reg(SR46, VIASR, CLK / 0x100);
1406                         viafb_write_reg(SR47, VIASR, CLK % 0x100);
1407                         break;
1408
1409                 case UNICHROME_K800:
1410                 case UNICHROME_PM800:
1411                 case UNICHROME_CN700:
1412                 case UNICHROME_CX700:
1413                 case UNICHROME_K8M890:
1414                 case UNICHROME_P4M890:
1415                 case UNICHROME_P4M900:
1416                 case UNICHROME_VX800:
1417                 case UNICHROME_VX855:
1418                         viafb_write_reg(SR44, VIASR, CLK / 0x10000);
1419                         DEBUG_MSG(KERN_INFO "\nSR44=%x", CLK / 0x10000);
1420                         viafb_write_reg(SR45, VIASR, (CLK & 0xFFFF) / 0x100);
1421                         DEBUG_MSG(KERN_INFO "\nSR45=%x",
1422                                   (CLK & 0xFFFF) / 0x100);
1423                         viafb_write_reg(SR46, VIASR, CLK % 0x100);
1424                         DEBUG_MSG(KERN_INFO "\nSR46=%x", CLK % 0x100);
1425                         break;
1426                 }
1427         }
1428
1429         if (set_iga == IGA2) {
1430                 /* Change D,N FOR LCK */
1431                 switch (viaparinfo->chip_info->gfx_chip_name) {
1432                 case UNICHROME_CLE266:
1433                 case UNICHROME_K400:
1434                         viafb_write_reg(SR44, VIASR, CLK / 0x100);
1435                         viafb_write_reg(SR45, VIASR, CLK % 0x100);
1436                         break;
1437
1438                 case UNICHROME_K800:
1439                 case UNICHROME_PM800:
1440                 case UNICHROME_CN700:
1441                 case UNICHROME_CX700:
1442                 case UNICHROME_K8M890:
1443                 case UNICHROME_P4M890:
1444                 case UNICHROME_P4M900:
1445                 case UNICHROME_VX800:
1446                 case UNICHROME_VX855:
1447                         viafb_write_reg(SR4A, VIASR, CLK / 0x10000);
1448                         viafb_write_reg(SR4B, VIASR, (CLK & 0xFFFF) / 0x100);
1449                         viafb_write_reg(SR4C, VIASR, CLK % 0x100);
1450                         break;
1451                 }
1452         }
1453
1454         /* H.W. Reset : OFF */
1455         viafb_write_reg_mask(CR17, VIACR, 0x80, BIT7);
1456
1457         /* Reset PLL */
1458         if (set_iga == IGA1) {
1459                 viafb_write_reg_mask(SR40, VIASR, 0x02, BIT1);
1460                 viafb_write_reg_mask(SR40, VIASR, 0x00, BIT1);
1461         }
1462
1463         if (set_iga == IGA2) {
1464                 viafb_write_reg_mask(SR40, VIASR, 0x01, BIT0);
1465                 viafb_write_reg_mask(SR40, VIASR, 0x00, BIT0);
1466         }
1467
1468         /* Fire! */
1469         via_write_misc_reg_mask(0x0C, 0x0C); /* select external clock */
1470 }
1471
1472 void viafb_load_crtc_timing(struct display_timing device_timing,
1473         int set_iga)
1474 {
1475         int i;
1476         int viafb_load_reg_num = 0;
1477         int reg_value = 0;
1478         struct io_register *reg = NULL;
1479
1480         viafb_unlock_crt();
1481
1482         for (i = 0; i < 12; i++) {
1483                 if (set_iga == IGA1) {
1484                         switch (i) {
1485                         case H_TOTAL_INDEX:
1486                                 reg_value =
1487                                     IGA1_HOR_TOTAL_FORMULA(device_timing.
1488                                                            hor_total);
1489                                 viafb_load_reg_num =
1490                                         iga1_crtc_reg.hor_total.reg_num;
1491                                 reg = iga1_crtc_reg.hor_total.reg;
1492                                 break;
1493                         case H_ADDR_INDEX:
1494                                 reg_value =
1495                                     IGA1_HOR_ADDR_FORMULA(device_timing.
1496                                                           hor_addr);
1497                                 viafb_load_reg_num =
1498                                         iga1_crtc_reg.hor_addr.reg_num;
1499                                 reg = iga1_crtc_reg.hor_addr.reg;
1500                                 break;
1501                         case H_BLANK_START_INDEX:
1502                                 reg_value =
1503                                     IGA1_HOR_BLANK_START_FORMULA
1504                                     (device_timing.hor_blank_start);
1505                                 viafb_load_reg_num =
1506                                     iga1_crtc_reg.hor_blank_start.reg_num;
1507                                 reg = iga1_crtc_reg.hor_blank_start.reg;
1508                                 break;
1509                         case H_BLANK_END_INDEX:
1510                                 reg_value =
1511                                     IGA1_HOR_BLANK_END_FORMULA
1512                                     (device_timing.hor_blank_start,
1513                                      device_timing.hor_blank_end);
1514                                 viafb_load_reg_num =
1515                                     iga1_crtc_reg.hor_blank_end.reg_num;
1516                                 reg = iga1_crtc_reg.hor_blank_end.reg;
1517                                 break;
1518                         case H_SYNC_START_INDEX:
1519                                 reg_value =
1520                                     IGA1_HOR_SYNC_START_FORMULA
1521                                     (device_timing.hor_sync_start);
1522                                 viafb_load_reg_num =
1523                                     iga1_crtc_reg.hor_sync_start.reg_num;
1524                                 reg = iga1_crtc_reg.hor_sync_start.reg;
1525                                 break;
1526                         case H_SYNC_END_INDEX:
1527                                 reg_value =
1528                                     IGA1_HOR_SYNC_END_FORMULA
1529                                     (device_timing.hor_sync_start,
1530                                      device_timing.hor_sync_end);
1531                                 viafb_load_reg_num =
1532                                     iga1_crtc_reg.hor_sync_end.reg_num;
1533                                 reg = iga1_crtc_reg.hor_sync_end.reg;
1534                                 break;
1535                         case V_TOTAL_INDEX:
1536                                 reg_value =
1537                                     IGA1_VER_TOTAL_FORMULA(device_timing.
1538                                                            ver_total);
1539                                 viafb_load_reg_num =
1540                                         iga1_crtc_reg.ver_total.reg_num;
1541                                 reg = iga1_crtc_reg.ver_total.reg;
1542                                 break;
1543                         case V_ADDR_INDEX:
1544                                 reg_value =
1545                                     IGA1_VER_ADDR_FORMULA(device_timing.
1546                                                           ver_addr);
1547                                 viafb_load_reg_num =
1548                                         iga1_crtc_reg.ver_addr.reg_num;
1549                                 reg = iga1_crtc_reg.ver_addr.reg;
1550                                 break;
1551                         case V_BLANK_START_INDEX:
1552                                 reg_value =
1553                                     IGA1_VER_BLANK_START_FORMULA
1554                                     (device_timing.ver_blank_start);
1555                                 viafb_load_reg_num =
1556                                     iga1_crtc_reg.ver_blank_start.reg_num;
1557                                 reg = iga1_crtc_reg.ver_blank_start.reg;
1558                                 break;
1559                         case V_BLANK_END_INDEX:
1560                                 reg_value =
1561                                     IGA1_VER_BLANK_END_FORMULA
1562                                     (device_timing.ver_blank_start,
1563                                      device_timing.ver_blank_end);
1564                                 viafb_load_reg_num =
1565                                     iga1_crtc_reg.ver_blank_end.reg_num;
1566                                 reg = iga1_crtc_reg.ver_blank_end.reg;
1567                                 break;
1568                         case V_SYNC_START_INDEX:
1569                                 reg_value =
1570                                     IGA1_VER_SYNC_START_FORMULA
1571                                     (device_timing.ver_sync_start);
1572                                 viafb_load_reg_num =
1573                                     iga1_crtc_reg.ver_sync_start.reg_num;
1574                                 reg = iga1_crtc_reg.ver_sync_start.reg;
1575                                 break;
1576                         case V_SYNC_END_INDEX:
1577                                 reg_value =
1578                                     IGA1_VER_SYNC_END_FORMULA
1579                                     (device_timing.ver_sync_start,
1580                                      device_timing.ver_sync_end);
1581                                 viafb_load_reg_num =
1582                                     iga1_crtc_reg.ver_sync_end.reg_num;
1583                                 reg = iga1_crtc_reg.ver_sync_end.reg;
1584                                 break;
1585
1586                         }
1587                 }
1588
1589                 if (set_iga == IGA2) {
1590                         switch (i) {
1591                         case H_TOTAL_INDEX:
1592                                 reg_value =
1593                                     IGA2_HOR_TOTAL_FORMULA(device_timing.
1594                                                            hor_total);
1595                                 viafb_load_reg_num =
1596                                         iga2_crtc_reg.hor_total.reg_num;
1597                                 reg = iga2_crtc_reg.hor_total.reg;
1598                                 break;
1599                         case H_ADDR_INDEX:
1600                                 reg_value =
1601                                     IGA2_HOR_ADDR_FORMULA(device_timing.
1602                                                           hor_addr);
1603                                 viafb_load_reg_num =
1604                                         iga2_crtc_reg.hor_addr.reg_num;
1605                                 reg = iga2_crtc_reg.hor_addr.reg;
1606                                 break;
1607                         case H_BLANK_START_INDEX:
1608                                 reg_value =
1609                                     IGA2_HOR_BLANK_START_FORMULA
1610                                     (device_timing.hor_blank_start);
1611                                 viafb_load_reg_num =
1612                                     iga2_crtc_reg.hor_blank_start.reg_num;
1613                                 reg = iga2_crtc_reg.hor_blank_start.reg;
1614                                 break;
1615                         case H_BLANK_END_INDEX:
1616                                 reg_value =
1617                                     IGA2_HOR_BLANK_END_FORMULA
1618                                     (device_timing.hor_blank_start,
1619                                      device_timing.hor_blank_end);
1620                                 viafb_load_reg_num =
1621                                     iga2_crtc_reg.hor_blank_end.reg_num;
1622                                 reg = iga2_crtc_reg.hor_blank_end.reg;
1623                                 break;
1624                         case H_SYNC_START_INDEX:
1625                                 reg_value =
1626                                     IGA2_HOR_SYNC_START_FORMULA
1627                                     (device_timing.hor_sync_start);
1628                                 if (UNICHROME_CN700 <=
1629                                         viaparinfo->chip_info->gfx_chip_name)
1630                                         viafb_load_reg_num =
1631                                             iga2_crtc_reg.hor_sync_start.
1632                                             reg_num;
1633                                 else
1634                                         viafb_load_reg_num = 3;
1635                                 reg = iga2_crtc_reg.hor_sync_start.reg;
1636                                 break;
1637                         case H_SYNC_END_INDEX:
1638                                 reg_value =
1639                                     IGA2_HOR_SYNC_END_FORMULA
1640                                     (device_timing.hor_sync_start,
1641                                      device_timing.hor_sync_end);
1642                                 viafb_load_reg_num =
1643                                     iga2_crtc_reg.hor_sync_end.reg_num;
1644                                 reg = iga2_crtc_reg.hor_sync_end.reg;
1645                                 break;
1646                         case V_TOTAL_INDEX:
1647                                 reg_value =
1648                                     IGA2_VER_TOTAL_FORMULA(device_timing.
1649                                                            ver_total);
1650                                 viafb_load_reg_num =
1651                                         iga2_crtc_reg.ver_total.reg_num;
1652                                 reg = iga2_crtc_reg.ver_total.reg;
1653                                 break;
1654                         case V_ADDR_INDEX:
1655                                 reg_value =
1656                                     IGA2_VER_ADDR_FORMULA(device_timing.
1657                                                           ver_addr);
1658                                 viafb_load_reg_num =
1659                                         iga2_crtc_reg.ver_addr.reg_num;
1660                                 reg = iga2_crtc_reg.ver_addr.reg;
1661                                 break;
1662                         case V_BLANK_START_INDEX:
1663                                 reg_value =
1664                                     IGA2_VER_BLANK_START_FORMULA
1665                                     (device_timing.ver_blank_start);
1666                                 viafb_load_reg_num =
1667                                     iga2_crtc_reg.ver_blank_start.reg_num;
1668                                 reg = iga2_crtc_reg.ver_blank_start.reg;
1669                                 break;
1670                         case V_BLANK_END_INDEX:
1671                                 reg_value =
1672                                     IGA2_VER_BLANK_END_FORMULA
1673                                     (device_timing.ver_blank_start,
1674                                      device_timing.ver_blank_end);
1675                                 viafb_load_reg_num =
1676                                     iga2_crtc_reg.ver_blank_end.reg_num;
1677                                 reg = iga2_crtc_reg.ver_blank_end.reg;
1678                                 break;
1679                         case V_SYNC_START_INDEX:
1680                                 reg_value =
1681                                     IGA2_VER_SYNC_START_FORMULA
1682                                     (device_timing.ver_sync_start);
1683                                 viafb_load_reg_num =
1684                                     iga2_crtc_reg.ver_sync_start.reg_num;
1685                                 reg = iga2_crtc_reg.ver_sync_start.reg;
1686                                 break;
1687                         case V_SYNC_END_INDEX:
1688                                 reg_value =
1689                                     IGA2_VER_SYNC_END_FORMULA
1690                                     (device_timing.ver_sync_start,
1691                                      device_timing.ver_sync_end);
1692                                 viafb_load_reg_num =
1693                                     iga2_crtc_reg.ver_sync_end.reg_num;
1694                                 reg = iga2_crtc_reg.ver_sync_end.reg;
1695                                 break;
1696
1697                         }
1698                 }
1699                 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR);
1700         }
1701
1702         viafb_lock_crt();
1703 }
1704
1705 void viafb_fill_crtc_timing(struct crt_mode_table *crt_table,
1706         struct VideoModeTable *video_mode, int bpp_byte, int set_iga)
1707 {
1708         struct display_timing crt_reg;
1709         int i;
1710         int index = 0;
1711         int h_addr, v_addr;
1712         u32 pll_D_N;
1713         u8 polarity = 0;
1714
1715         for (i = 0; i < video_mode->mode_array; i++) {
1716                 index = i;
1717
1718                 if (crt_table[i].refresh_rate == viaparinfo->
1719                         crt_setting_info->refresh_rate)
1720                         break;
1721         }
1722
1723         crt_reg = crt_table[index].crtc;
1724
1725         /* Mode 640x480 has border, but LCD/DFP didn't have border. */
1726         /* So we would delete border. */
1727         if ((viafb_LCD_ON | viafb_DVI_ON)
1728             && video_mode->crtc[0].crtc.hor_addr == 640
1729             && video_mode->crtc[0].crtc.ver_addr == 480
1730             && viaparinfo->crt_setting_info->refresh_rate == 60) {
1731                 /* The border is 8 pixels. */
1732                 crt_reg.hor_blank_start = crt_reg.hor_blank_start - 8;
1733
1734                 /* Blanking time should add left and right borders. */
1735                 crt_reg.hor_blank_end = crt_reg.hor_blank_end + 16;
1736         }
1737
1738         h_addr = crt_reg.hor_addr;
1739         v_addr = crt_reg.ver_addr;
1740
1741         /* update polarity for CRT timing */
1742         if (crt_table[index].h_sync_polarity == NEGATIVE)
1743                 polarity |= BIT6;
1744         if (crt_table[index].v_sync_polarity == NEGATIVE)
1745                 polarity |= BIT7;
1746         via_write_misc_reg_mask(polarity, BIT6 | BIT7);
1747
1748         if (set_iga == IGA1) {
1749                 viafb_unlock_crt();
1750                 viafb_write_reg(CR09, VIACR, 0x00);     /*initial CR09=0 */
1751                 viafb_write_reg_mask(CR11, VIACR, 0x00, BIT4 + BIT5 + BIT6);
1752                 viafb_write_reg_mask(CR17, VIACR, 0x00, BIT7);
1753         }
1754
1755         switch (set_iga) {
1756         case IGA1:
1757                 viafb_load_crtc_timing(crt_reg, IGA1);
1758                 break;
1759         case IGA2:
1760                 viafb_load_crtc_timing(crt_reg, IGA2);
1761                 break;
1762         }
1763
1764         load_fix_bit_crtc_reg();
1765         viafb_lock_crt();
1766         viafb_write_reg_mask(CR17, VIACR, 0x80, BIT7);
1767         viafb_load_fetch_count_reg(h_addr, bpp_byte, set_iga);
1768
1769         /* load FIFO */
1770         if ((viaparinfo->chip_info->gfx_chip_name != UNICHROME_CLE266)
1771             && (viaparinfo->chip_info->gfx_chip_name != UNICHROME_K400))
1772                 viafb_load_FIFO_reg(set_iga, h_addr, v_addr);
1773
1774         pll_D_N = viafb_get_clk_value(crt_table[index].clk);
1775         DEBUG_MSG(KERN_INFO "PLL=%x", pll_D_N);
1776         viafb_set_vclock(pll_D_N, set_iga);
1777
1778 }
1779
1780 void viafb_init_chip_info(int chip_type)
1781 {
1782         init_gfx_chip_info(chip_type);
1783         init_tmds_chip_info();
1784         init_lvds_chip_info();
1785
1786         viaparinfo->crt_setting_info->iga_path = IGA1;
1787         viaparinfo->crt_setting_info->refresh_rate = viafb_refresh;
1788
1789         /*Set IGA path for each device */
1790         viafb_set_iga_path();
1791
1792         viaparinfo->lvds_setting_info->display_method = viafb_lcd_dsp_method;
1793         viaparinfo->lvds_setting_info->get_lcd_size_method =
1794                 GET_LCD_SIZE_BY_USER_SETTING;
1795         viaparinfo->lvds_setting_info->lcd_mode = viafb_lcd_mode;
1796         viaparinfo->lvds_setting_info2->display_method =
1797                 viaparinfo->lvds_setting_info->display_method;
1798         viaparinfo->lvds_setting_info2->lcd_mode =
1799                 viaparinfo->lvds_setting_info->lcd_mode;
1800 }
1801
1802 void viafb_update_device_setting(int hres, int vres,
1803         int bpp, int vmode_refresh, int flag)
1804 {
1805         if (flag == 0) {
1806                 viaparinfo->crt_setting_info->h_active = hres;
1807                 viaparinfo->crt_setting_info->v_active = vres;
1808                 viaparinfo->crt_setting_info->bpp = bpp;
1809                 viaparinfo->crt_setting_info->refresh_rate =
1810                         vmode_refresh;
1811
1812                 viaparinfo->tmds_setting_info->h_active = hres;
1813                 viaparinfo->tmds_setting_info->v_active = vres;
1814
1815                 viaparinfo->lvds_setting_info->h_active = hres;
1816                 viaparinfo->lvds_setting_info->v_active = vres;
1817                 viaparinfo->lvds_setting_info->bpp = bpp;
1818                 viaparinfo->lvds_setting_info->refresh_rate =
1819                         vmode_refresh;
1820                 viaparinfo->lvds_setting_info2->h_active = hres;
1821                 viaparinfo->lvds_setting_info2->v_active = vres;
1822                 viaparinfo->lvds_setting_info2->bpp = bpp;
1823                 viaparinfo->lvds_setting_info2->refresh_rate =
1824                         vmode_refresh;
1825         } else {
1826
1827                 if (viaparinfo->tmds_setting_info->iga_path == IGA2) {
1828                         viaparinfo->tmds_setting_info->h_active = hres;
1829                         viaparinfo->tmds_setting_info->v_active = vres;
1830                 }
1831
1832                 if (viaparinfo->lvds_setting_info->iga_path == IGA2) {
1833                         viaparinfo->lvds_setting_info->h_active = hres;
1834                         viaparinfo->lvds_setting_info->v_active = vres;
1835                         viaparinfo->lvds_setting_info->bpp = bpp;
1836                         viaparinfo->lvds_setting_info->refresh_rate =
1837                                 vmode_refresh;
1838                 }
1839                 if (IGA2 == viaparinfo->lvds_setting_info2->iga_path) {
1840                         viaparinfo->lvds_setting_info2->h_active = hres;
1841                         viaparinfo->lvds_setting_info2->v_active = vres;
1842                         viaparinfo->lvds_setting_info2->bpp = bpp;
1843                         viaparinfo->lvds_setting_info2->refresh_rate =
1844                                 vmode_refresh;
1845                 }
1846         }
1847 }
1848
1849 static void init_gfx_chip_info(int chip_type)
1850 {
1851         u8 tmp;
1852
1853         viaparinfo->chip_info->gfx_chip_name = chip_type;
1854
1855         /* Check revision of CLE266 Chip */
1856         if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266) {
1857                 /* CR4F only define in CLE266.CX chip */
1858                 tmp = viafb_read_reg(VIACR, CR4F);
1859                 viafb_write_reg(CR4F, VIACR, 0x55);
1860                 if (viafb_read_reg(VIACR, CR4F) != 0x55)
1861                         viaparinfo->chip_info->gfx_chip_revision =
1862                         CLE266_REVISION_AX;
1863                 else
1864                         viaparinfo->chip_info->gfx_chip_revision =
1865                         CLE266_REVISION_CX;
1866                 /* restore orignal CR4F value */
1867                 viafb_write_reg(CR4F, VIACR, tmp);
1868         }
1869
1870         if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CX700) {
1871                 tmp = viafb_read_reg(VIASR, SR43);
1872                 DEBUG_MSG(KERN_INFO "SR43:%X\n", tmp);
1873                 if (tmp & 0x02) {
1874                         viaparinfo->chip_info->gfx_chip_revision =
1875                                 CX700_REVISION_700M2;
1876                 } else if (tmp & 0x40) {
1877                         viaparinfo->chip_info->gfx_chip_revision =
1878                                 CX700_REVISION_700M;
1879                 } else {
1880                         viaparinfo->chip_info->gfx_chip_revision =
1881                                 CX700_REVISION_700;
1882                 }
1883         }
1884
1885         /* Determine which 2D engine we have */
1886         switch (viaparinfo->chip_info->gfx_chip_name) {
1887         case UNICHROME_VX800:
1888         case UNICHROME_VX855:
1889                 viaparinfo->chip_info->twod_engine = VIA_2D_ENG_M1;
1890                 break;
1891         case UNICHROME_K8M890:
1892         case UNICHROME_P4M900:
1893                 viaparinfo->chip_info->twod_engine = VIA_2D_ENG_H5;
1894                 break;
1895         default:
1896                 viaparinfo->chip_info->twod_engine = VIA_2D_ENG_H2;
1897                 break;
1898         }
1899 }
1900
1901 static void init_tmds_chip_info(void)
1902 {
1903         viafb_tmds_trasmitter_identify();
1904
1905         if (INTERFACE_NONE == viaparinfo->chip_info->tmds_chip_info.
1906                 output_interface) {
1907                 switch (viaparinfo->chip_info->gfx_chip_name) {
1908                 case UNICHROME_CX700:
1909                         {
1910                                 /* we should check support by hardware layout.*/
1911                                 if ((viafb_display_hardware_layout ==
1912                                      HW_LAYOUT_DVI_ONLY)
1913                                     || (viafb_display_hardware_layout ==
1914                                         HW_LAYOUT_LCD_DVI)) {
1915                                         viaparinfo->chip_info->tmds_chip_info.
1916                                             output_interface = INTERFACE_TMDS;
1917                                 } else {
1918                                         viaparinfo->chip_info->tmds_chip_info.
1919                                                 output_interface =
1920                                                 INTERFACE_NONE;
1921                                 }
1922                                 break;
1923                         }
1924                 case UNICHROME_K8M890:
1925                 case UNICHROME_P4M900:
1926                 case UNICHROME_P4M890:
1927                         /* TMDS on PCIE, we set DFPLOW as default. */
1928                         viaparinfo->chip_info->tmds_chip_info.output_interface =
1929                             INTERFACE_DFP_LOW;
1930                         break;
1931                 default:
1932                         {
1933                                 /* set DVP1 default for DVI */
1934                                 viaparinfo->chip_info->tmds_chip_info
1935                                 .output_interface = INTERFACE_DVP1;
1936                         }
1937                 }
1938         }
1939
1940         DEBUG_MSG(KERN_INFO "TMDS Chip = %d\n",
1941                   viaparinfo->chip_info->tmds_chip_info.tmds_chip_name);
1942         viafb_init_dvi_size(&viaparinfo->shared->chip_info.tmds_chip_info,
1943                 &viaparinfo->shared->tmds_setting_info);
1944 }
1945
1946 static void init_lvds_chip_info(void)
1947 {
1948         if (viafb_lcd_panel_id > LCD_PANEL_ID_MAXIMUM)
1949                 viaparinfo->lvds_setting_info->get_lcd_size_method =
1950                     GET_LCD_SIZE_BY_VGA_BIOS;
1951         else
1952                 viaparinfo->lvds_setting_info->get_lcd_size_method =
1953                     GET_LCD_SIZE_BY_USER_SETTING;
1954
1955         viafb_lvds_trasmitter_identify();
1956         viafb_init_lcd_size();
1957         viafb_init_lvds_output_interface(&viaparinfo->chip_info->lvds_chip_info,
1958                                    viaparinfo->lvds_setting_info);
1959         if (viaparinfo->chip_info->lvds_chip_info2.lvds_chip_name) {
1960                 viafb_init_lvds_output_interface(&viaparinfo->chip_info->
1961                         lvds_chip_info2, viaparinfo->lvds_setting_info2);
1962         }
1963         /*If CX700,two singel LCD, we need to reassign
1964            LCD interface to different LVDS port */
1965         if ((UNICHROME_CX700 == viaparinfo->chip_info->gfx_chip_name)
1966             && (HW_LAYOUT_LCD1_LCD2 == viafb_display_hardware_layout)) {
1967                 if ((INTEGRATED_LVDS == viaparinfo->chip_info->lvds_chip_info.
1968                         lvds_chip_name) && (INTEGRATED_LVDS ==
1969                         viaparinfo->chip_info->
1970                         lvds_chip_info2.lvds_chip_name)) {
1971                         viaparinfo->chip_info->lvds_chip_info.output_interface =
1972                                 INTERFACE_LVDS0;
1973                         viaparinfo->chip_info->lvds_chip_info2.
1974                                 output_interface =
1975                             INTERFACE_LVDS1;
1976                 }
1977         }
1978
1979         DEBUG_MSG(KERN_INFO "LVDS Chip = %d\n",
1980                   viaparinfo->chip_info->lvds_chip_info.lvds_chip_name);
1981         DEBUG_MSG(KERN_INFO "LVDS1 output_interface = %d\n",
1982                   viaparinfo->chip_info->lvds_chip_info.output_interface);
1983         DEBUG_MSG(KERN_INFO "LVDS2 output_interface = %d\n",
1984                   viaparinfo->chip_info->lvds_chip_info.output_interface);
1985 }
1986
1987 void viafb_init_dac(int set_iga)
1988 {
1989         int i;
1990         u8 tmp;
1991
1992         if (set_iga == IGA1) {
1993                 /* access Primary Display's LUT */
1994                 viafb_write_reg_mask(SR1A, VIASR, 0x00, BIT0);
1995                 /* turn off LCK */
1996                 viafb_write_reg_mask(SR1B, VIASR, 0x00, BIT7 + BIT6);
1997                 for (i = 0; i < 256; i++) {
1998                         write_dac_reg(i, palLUT_table[i].red,
1999                                       palLUT_table[i].green,
2000                                       palLUT_table[i].blue);
2001                 }
2002                 /* turn on LCK */
2003                 viafb_write_reg_mask(SR1B, VIASR, 0xC0, BIT7 + BIT6);
2004         } else {
2005                 tmp = viafb_read_reg(VIACR, CR6A);
2006                 /* access Secondary Display's LUT */
2007                 viafb_write_reg_mask(CR6A, VIACR, 0x40, BIT6);
2008                 viafb_write_reg_mask(SR1A, VIASR, 0x01, BIT0);
2009                 for (i = 0; i < 256; i++) {
2010                         write_dac_reg(i, palLUT_table[i].red,
2011                                       palLUT_table[i].green,
2012                                       palLUT_table[i].blue);
2013                 }
2014                 /* set IGA1 DAC for default */
2015                 viafb_write_reg_mask(SR1A, VIASR, 0x00, BIT0);
2016                 viafb_write_reg(CR6A, VIACR, tmp);
2017         }
2018 }
2019
2020 static void device_screen_off(void)
2021 {
2022         /* turn off CRT screen (IGA1) */
2023         viafb_write_reg_mask(SR01, VIASR, 0x20, BIT5);
2024 }
2025
2026 static void device_screen_on(void)
2027 {
2028         /* turn on CRT screen (IGA1) */
2029         viafb_write_reg_mask(SR01, VIASR, 0x00, BIT5);
2030 }
2031
2032 static void set_display_channel(void)
2033 {
2034         /*If viafb_LCD2_ON, on cx700, internal lvds's information
2035         is keeped on lvds_setting_info2 */
2036         if (viafb_LCD2_ON &&
2037                 viaparinfo->lvds_setting_info2->device_lcd_dualedge) {
2038                 /* For dual channel LCD: */
2039                 /* Set to Dual LVDS channel. */
2040                 viafb_write_reg_mask(CRD2, VIACR, 0x20, BIT4 + BIT5);
2041         } else if (viafb_LCD_ON && viafb_DVI_ON) {
2042                 /* For LCD+DFP: */
2043                 /* Set to LVDS1 + TMDS channel. */
2044                 viafb_write_reg_mask(CRD2, VIACR, 0x10, BIT4 + BIT5);
2045         } else if (viafb_DVI_ON) {
2046                 /* Set to single TMDS channel. */
2047                 viafb_write_reg_mask(CRD2, VIACR, 0x30, BIT4 + BIT5);
2048         } else if (viafb_LCD_ON) {
2049                 if (viaparinfo->lvds_setting_info->device_lcd_dualedge) {
2050                         /* For dual channel LCD: */
2051                         /* Set to Dual LVDS channel. */
2052                         viafb_write_reg_mask(CRD2, VIACR, 0x20, BIT4 + BIT5);
2053                 } else {
2054                         /* Set to LVDS0 + LVDS1 channel. */
2055                         viafb_write_reg_mask(CRD2, VIACR, 0x00, BIT4 + BIT5);
2056                 }
2057         }
2058 }
2059
2060 int viafb_setmode(struct VideoModeTable *vmode_tbl, int video_bpp,
2061         struct VideoModeTable *vmode_tbl1, int video_bpp1)
2062 {
2063         int i, j;
2064         int port;
2065         u8 value, index, mask;
2066         struct crt_mode_table *crt_timing;
2067         struct crt_mode_table *crt_timing1 = NULL;
2068
2069         device_screen_off();
2070         crt_timing = vmode_tbl->crtc;
2071
2072         if (viafb_SAMM_ON == 1) {
2073                 crt_timing1 = vmode_tbl1->crtc;
2074         }
2075
2076         inb(VIAStatus);
2077         outb(0x00, VIAAR);
2078
2079         /* Write Common Setting for Video Mode */
2080         switch (viaparinfo->chip_info->gfx_chip_name) {
2081         case UNICHROME_CLE266:
2082                 viafb_write_regx(CLE266_ModeXregs, NUM_TOTAL_CLE266_ModeXregs);
2083                 break;
2084
2085         case UNICHROME_K400:
2086                 viafb_write_regx(KM400_ModeXregs, NUM_TOTAL_KM400_ModeXregs);
2087                 break;
2088
2089         case UNICHROME_K800:
2090         case UNICHROME_PM800:
2091                 viafb_write_regx(CN400_ModeXregs, NUM_TOTAL_CN400_ModeXregs);
2092                 break;
2093
2094         case UNICHROME_CN700:
2095         case UNICHROME_K8M890:
2096         case UNICHROME_P4M890:
2097         case UNICHROME_P4M900:
2098                 viafb_write_regx(CN700_ModeXregs, NUM_TOTAL_CN700_ModeXregs);
2099                 break;
2100
2101         case UNICHROME_CX700:
2102         case UNICHROME_VX800:
2103                 viafb_write_regx(CX700_ModeXregs, NUM_TOTAL_CX700_ModeXregs);
2104                 break;
2105
2106         case UNICHROME_VX855:
2107                 viafb_write_regx(VX855_ModeXregs, NUM_TOTAL_VX855_ModeXregs);
2108                 break;
2109         }
2110
2111         device_off();
2112
2113         /* Fill VPIT Parameters */
2114         /* Write Misc Register */
2115         outb(VPIT.Misc, VIA_MISC_REG_WRITE);
2116
2117         /* Write Sequencer */
2118         for (i = 1; i <= StdSR; i++)
2119                 via_write_reg(VIASR, i, VPIT.SR[i - 1]);
2120
2121         viafb_write_reg_mask(0x15, VIASR, 0xA2, 0xA2);
2122         viafb_set_iga_path();
2123
2124         /* Write CRTC */
2125         viafb_fill_crtc_timing(crt_timing, vmode_tbl, video_bpp / 8, IGA1);
2126
2127         /* Write Graphic Controller */
2128         for (i = 0; i < StdGR; i++)
2129                 via_write_reg(VIAGR, i, VPIT.GR[i]);
2130
2131         /* Write Attribute Controller */
2132         for (i = 0; i < StdAR; i++) {
2133                 inb(VIAStatus);
2134                 outb(i, VIAAR);
2135                 outb(VPIT.AR[i], VIAAR);
2136         }
2137
2138         inb(VIAStatus);
2139         outb(0x20, VIAAR);
2140
2141         /* Update Patch Register */
2142
2143         if ((viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266
2144             || viaparinfo->chip_info->gfx_chip_name == UNICHROME_K400)
2145             && vmode_tbl->crtc[0].crtc.hor_addr == 1024
2146             && vmode_tbl->crtc[0].crtc.ver_addr == 768) {
2147                 for (j = 0; j < res_patch_table[0].table_length; j++) {
2148                         index = res_patch_table[0].io_reg_table[j].index;
2149                         port = res_patch_table[0].io_reg_table[j].port;
2150                         value = res_patch_table[0].io_reg_table[j].value;
2151                         mask = res_patch_table[0].io_reg_table[j].mask;
2152                         viafb_write_reg_mask(index, port, value, mask);
2153                 }
2154         }
2155
2156         via_set_primary_pitch(viafbinfo->fix.line_length);
2157         via_set_secondary_pitch(viafb_dual_fb ? viafbinfo1->fix.line_length
2158                 : viafbinfo->fix.line_length);
2159         via_set_primary_color_depth(viaparinfo->depth);
2160         via_set_secondary_color_depth(viafb_dual_fb ? viaparinfo1->depth
2161                 : viaparinfo->depth);
2162         /* Update Refresh Rate Setting */
2163
2164         /* Clear On Screen */
2165
2166         /* CRT set mode */
2167         if (viafb_CRT_ON) {
2168                 if (viafb_SAMM_ON && (viaparinfo->crt_setting_info->iga_path ==
2169                         IGA2)) {
2170                         viafb_fill_crtc_timing(crt_timing1, vmode_tbl1,
2171                                 video_bpp1 / 8,
2172                                 viaparinfo->crt_setting_info->iga_path);
2173                 } else {
2174                         viafb_fill_crtc_timing(crt_timing, vmode_tbl,
2175                                 video_bpp / 8,
2176                                 viaparinfo->crt_setting_info->iga_path);
2177                 }
2178
2179                 set_crt_output_path(viaparinfo->crt_setting_info->iga_path);
2180
2181                 /* Patch if set_hres is not 8 alignment (1366) to viafb_setmode
2182                 to 8 alignment (1368),there is several pixels (2 pixels)
2183                 on right side of screen. */
2184                 if (vmode_tbl->crtc[0].crtc.hor_addr % 8) {
2185                         viafb_unlock_crt();
2186                         viafb_write_reg(CR02, VIACR,
2187                                 viafb_read_reg(VIACR, CR02) - 1);
2188                         viafb_lock_crt();
2189                 }
2190         }
2191
2192         if (viafb_DVI_ON) {
2193                 if (viafb_SAMM_ON &&
2194                         (viaparinfo->tmds_setting_info->iga_path == IGA2)) {
2195                         viafb_dvi_set_mode(viafb_get_mode
2196                                      (viaparinfo->tmds_setting_info->h_active,
2197                                       viaparinfo->tmds_setting_info->
2198                                       v_active),
2199                                      video_bpp1, viaparinfo->
2200                                      tmds_setting_info->iga_path);
2201                 } else {
2202                         viafb_dvi_set_mode(viafb_get_mode
2203                                      (viaparinfo->tmds_setting_info->h_active,
2204                                       viaparinfo->
2205                                       tmds_setting_info->v_active),
2206                                      video_bpp, viaparinfo->
2207                                      tmds_setting_info->iga_path);
2208                 }
2209         }
2210
2211         if (viafb_LCD_ON) {
2212                 if (viafb_SAMM_ON &&
2213                         (viaparinfo->lvds_setting_info->iga_path == IGA2)) {
2214                         viaparinfo->lvds_setting_info->bpp = video_bpp1;
2215                         viafb_lcd_set_mode(crt_timing1, viaparinfo->
2216                                 lvds_setting_info,
2217                                      &viaparinfo->chip_info->lvds_chip_info);
2218                 } else {
2219                         /* IGA1 doesn't have LCD scaling, so set it center. */
2220                         if (viaparinfo->lvds_setting_info->iga_path == IGA1) {
2221                                 viaparinfo->lvds_setting_info->display_method =
2222                                     LCD_CENTERING;
2223                         }
2224                         viaparinfo->lvds_setting_info->bpp = video_bpp;
2225                         viafb_lcd_set_mode(crt_timing, viaparinfo->
2226                                 lvds_setting_info,
2227                                      &viaparinfo->chip_info->lvds_chip_info);
2228                 }
2229         }
2230         if (viafb_LCD2_ON) {
2231                 if (viafb_SAMM_ON &&
2232                         (viaparinfo->lvds_setting_info2->iga_path == IGA2)) {
2233                         viaparinfo->lvds_setting_info2->bpp = video_bpp1;
2234                         viafb_lcd_set_mode(crt_timing1, viaparinfo->
2235                                 lvds_setting_info2,
2236                                      &viaparinfo->chip_info->lvds_chip_info2);
2237                 } else {
2238                         /* IGA1 doesn't have LCD scaling, so set it center. */
2239                         if (viaparinfo->lvds_setting_info2->iga_path == IGA1) {
2240                                 viaparinfo->lvds_setting_info2->display_method =
2241                                     LCD_CENTERING;
2242                         }
2243                         viaparinfo->lvds_setting_info2->bpp = video_bpp;
2244                         viafb_lcd_set_mode(crt_timing, viaparinfo->
2245                                 lvds_setting_info2,
2246                                      &viaparinfo->chip_info->lvds_chip_info2);
2247                 }
2248         }
2249
2250         if ((viaparinfo->chip_info->gfx_chip_name == UNICHROME_CX700)
2251             && (viafb_LCD_ON || viafb_DVI_ON))
2252                 set_display_channel();
2253
2254         /* If set mode normally, save resolution information for hot-plug . */
2255         if (!viafb_hotplug) {
2256                 viafb_hotplug_Xres = vmode_tbl->crtc[0].crtc.hor_addr;
2257                 viafb_hotplug_Yres = vmode_tbl->crtc[0].crtc.ver_addr;
2258                 viafb_hotplug_bpp = video_bpp;
2259                 viafb_hotplug_refresh = viafb_refresh;
2260
2261                 if (viafb_DVI_ON)
2262                         viafb_DeviceStatus = DVI_Device;
2263                 else
2264                         viafb_DeviceStatus = CRT_Device;
2265         }
2266         device_on();
2267
2268         if (viafb_SAMM_ON == 1)
2269                 viafb_write_reg_mask(CR6A, VIACR, 0xC0, BIT6 + BIT7);
2270
2271         device_screen_on();
2272         return 1;
2273 }
2274
2275 int viafb_get_pixclock(int hres, int vres, int vmode_refresh)
2276 {
2277         int i;
2278
2279         for (i = 0; i < NUM_TOTAL_RES_MAP_REFRESH; i++) {
2280                 if ((hres == res_map_refresh_tbl[i].hres)
2281                     && (vres == res_map_refresh_tbl[i].vres)
2282                     && (vmode_refresh == res_map_refresh_tbl[i].vmode_refresh))
2283                         return res_map_refresh_tbl[i].pixclock;
2284         }
2285         return RES_640X480_60HZ_PIXCLOCK;
2286
2287 }
2288
2289 int viafb_get_refresh(int hres, int vres, u32 long_refresh)
2290 {
2291 #define REFRESH_TOLERANCE 3
2292         int i, nearest = -1, diff = REFRESH_TOLERANCE;
2293         for (i = 0; i < NUM_TOTAL_RES_MAP_REFRESH; i++) {
2294                 if ((hres == res_map_refresh_tbl[i].hres)
2295                     && (vres == res_map_refresh_tbl[i].vres)
2296                     && (diff > (abs(long_refresh -
2297                     res_map_refresh_tbl[i].vmode_refresh)))) {
2298                         diff = abs(long_refresh - res_map_refresh_tbl[i].
2299                                 vmode_refresh);
2300                         nearest = i;
2301                 }
2302         }
2303 #undef REFRESH_TOLERANCE
2304         if (nearest > 0)
2305                 return res_map_refresh_tbl[nearest].vmode_refresh;
2306         return 60;
2307 }
2308
2309 static void device_off(void)
2310 {
2311         viafb_crt_disable();
2312         viafb_dvi_disable();
2313         viafb_lcd_disable();
2314 }
2315
2316 static void device_on(void)
2317 {
2318         if (viafb_CRT_ON == 1)
2319                 viafb_crt_enable();
2320         if (viafb_DVI_ON == 1)
2321                 viafb_dvi_enable();
2322         if (viafb_LCD_ON == 1)
2323                 viafb_lcd_enable();
2324 }
2325
2326 void viafb_crt_disable(void)
2327 {
2328         viafb_write_reg_mask(CR36, VIACR, BIT5 + BIT4, BIT5 + BIT4);
2329 }
2330
2331 void viafb_crt_enable(void)
2332 {
2333         viafb_write_reg_mask(CR36, VIACR, 0x0, BIT5 + BIT4);
2334 }
2335
2336 static void enable_second_display_channel(void)
2337 {
2338         /* to enable second display channel. */
2339         viafb_write_reg_mask(CR6A, VIACR, 0x00, BIT6);
2340         viafb_write_reg_mask(CR6A, VIACR, BIT7, BIT7);
2341         viafb_write_reg_mask(CR6A, VIACR, BIT6, BIT6);
2342 }
2343
2344 static void disable_second_display_channel(void)
2345 {
2346         /* to disable second display channel. */
2347         viafb_write_reg_mask(CR6A, VIACR, 0x00, BIT6);
2348         viafb_write_reg_mask(CR6A, VIACR, 0x00, BIT7);
2349         viafb_write_reg_mask(CR6A, VIACR, BIT6, BIT6);
2350 }
2351
2352
2353 void viafb_set_dpa_gfx(int output_interface, struct GFX_DPA_SETTING\
2354                                         *p_gfx_dpa_setting)
2355 {
2356         switch (output_interface) {
2357         case INTERFACE_DVP0:
2358                 {
2359                         /* DVP0 Clock Polarity and Adjust: */
2360                         viafb_write_reg_mask(CR96, VIACR,
2361                                        p_gfx_dpa_setting->DVP0, 0x0F);
2362
2363                         /* DVP0 Clock and Data Pads Driving: */
2364                         viafb_write_reg_mask(SR1E, VIASR,
2365                                        p_gfx_dpa_setting->DVP0ClockDri_S, BIT2);
2366                         viafb_write_reg_mask(SR2A, VIASR,
2367                                        p_gfx_dpa_setting->DVP0ClockDri_S1,
2368                                        BIT4);
2369                         viafb_write_reg_mask(SR1B, VIASR,
2370                                        p_gfx_dpa_setting->DVP0DataDri_S, BIT1);
2371                         viafb_write_reg_mask(SR2A, VIASR,
2372                                        p_gfx_dpa_setting->DVP0DataDri_S1, BIT5);
2373                         break;
2374                 }
2375
2376         case INTERFACE_DVP1:
2377                 {
2378                         /* DVP1 Clock Polarity and Adjust: */
2379                         viafb_write_reg_mask(CR9B, VIACR,
2380                                        p_gfx_dpa_setting->DVP1, 0x0F);
2381
2382                         /* DVP1 Clock and Data Pads Driving: */
2383                         viafb_write_reg_mask(SR65, VIASR,
2384                                        p_gfx_dpa_setting->DVP1Driving, 0x0F);
2385                         break;
2386                 }
2387
2388         case INTERFACE_DFP_HIGH:
2389                 {
2390                         viafb_write_reg_mask(CR97, VIACR,
2391                                        p_gfx_dpa_setting->DFPHigh, 0x0F);
2392                         break;
2393                 }
2394
2395         case INTERFACE_DFP_LOW:
2396                 {
2397                         viafb_write_reg_mask(CR99, VIACR,
2398                                        p_gfx_dpa_setting->DFPLow, 0x0F);
2399                         break;
2400                 }
2401
2402         case INTERFACE_DFP:
2403                 {
2404                         viafb_write_reg_mask(CR97, VIACR,
2405                                        p_gfx_dpa_setting->DFPHigh, 0x0F);
2406                         viafb_write_reg_mask(CR99, VIACR,
2407                                        p_gfx_dpa_setting->DFPLow, 0x0F);
2408                         break;
2409                 }
2410         }
2411 }
2412
2413 /*According var's xres, yres fill var's other timing information*/
2414 void viafb_fill_var_timing_info(struct fb_var_screeninfo *var, int refresh,
2415         struct VideoModeTable *vmode_tbl)
2416 {
2417         struct crt_mode_table *crt_timing = NULL;
2418         struct display_timing crt_reg;
2419         int i = 0, index = 0;
2420         crt_timing = vmode_tbl->crtc;
2421         for (i = 0; i < vmode_tbl->mode_array; i++) {
2422                 index = i;
2423                 if (crt_timing[i].refresh_rate == refresh)
2424                         break;
2425         }
2426
2427         crt_reg = crt_timing[index].crtc;
2428         var->pixclock = viafb_get_pixclock(var->xres, var->yres, refresh);
2429         var->left_margin =
2430             crt_reg.hor_total - (crt_reg.hor_sync_start + crt_reg.hor_sync_end);
2431         var->right_margin = crt_reg.hor_sync_start - crt_reg.hor_addr;
2432         var->hsync_len = crt_reg.hor_sync_end;
2433         var->upper_margin =
2434             crt_reg.ver_total - (crt_reg.ver_sync_start + crt_reg.ver_sync_end);
2435         var->lower_margin = crt_reg.ver_sync_start - crt_reg.ver_addr;
2436         var->vsync_len = crt_reg.ver_sync_end;
2437 }