2 * SuperH Mobile LCDC Framebuffer
4 * Copyright (c) 2008 Magnus Damm
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
11 #include <linux/kernel.h>
12 #include <linux/init.h>
13 #include <linux/delay.h>
16 #include <linux/clk.h>
17 #include <linux/platform_device.h>
18 #include <linux/dma-mapping.h>
19 #include <video/sh_mobile_lcdc.h>
23 struct sh_mobile_lcdc_priv;
24 struct sh_mobile_lcdc_chan {
25 struct sh_mobile_lcdc_priv *lcdc;
26 unsigned long *reg_offs;
27 unsigned long ldmt1r_value;
28 unsigned long enabled; /* ME and SE in LDCNT2R */
29 struct sh_mobile_lcdc_chan_cfg cfg;
30 u32 pseudo_palette[PALETTE_NR];
32 dma_addr_t dma_handle;
35 struct sh_mobile_lcdc_priv {
37 #ifdef CONFIG_HAVE_CLK
41 struct sh_mobile_lcdc_chan ch[2];
44 /* shared registers */
46 #define _LDDCKSTPR 0x414
49 #define _LDCNT1R 0x470
50 #define _LDCNT2R 0x474
52 #define _LDDWD0R 0x800
57 /* per-channel registers */
58 enum { LDDCKPAT1R, LDDCKPAT2R, LDMT1R, LDMT2R, LDMT3R, LDDFR, LDSM1R,
59 LDSA1R, LDMLSR, LDHCNR, LDHSYNR, LDVLNR, LDVSYNR, LDPMR };
61 static unsigned long lcdc_offs_mainlcd[] = {
78 static unsigned long lcdc_offs_sublcd[] = {
95 #define START_LCDC 0x00000001
96 #define LCDC_RESET 0x00000100
97 #define DISPLAY_BEU 0x00000008
98 #define LCDC_ENABLE 0x00000001
100 static void lcdc_write_chan(struct sh_mobile_lcdc_chan *chan,
101 int reg_nr, unsigned long data)
103 iowrite32(data, chan->lcdc->base + chan->reg_offs[reg_nr]);
106 static unsigned long lcdc_read_chan(struct sh_mobile_lcdc_chan *chan,
109 return ioread32(chan->lcdc->base + chan->reg_offs[reg_nr]);
112 static void lcdc_write(struct sh_mobile_lcdc_priv *priv,
113 unsigned long reg_offs, unsigned long data)
115 iowrite32(data, priv->base + reg_offs);
118 static unsigned long lcdc_read(struct sh_mobile_lcdc_priv *priv,
119 unsigned long reg_offs)
121 return ioread32(priv->base + reg_offs);
124 static void lcdc_wait_bit(struct sh_mobile_lcdc_priv *priv,
125 unsigned long reg_offs,
126 unsigned long mask, unsigned long until)
128 while ((lcdc_read(priv, reg_offs) & mask) != until)
132 static int lcdc_chan_is_sublcd(struct sh_mobile_lcdc_chan *chan)
134 return chan->cfg.chan == LCDC_CHAN_SUBLCD;
137 static void lcdc_sys_write_index(void *handle, unsigned long data)
139 struct sh_mobile_lcdc_chan *ch = handle;
141 lcdc_write(ch->lcdc, _LDDWD0R, data | 0x10000000);
142 lcdc_wait_bit(ch->lcdc, _LDSR, 2, 0);
143 lcdc_write(ch->lcdc, _LDDWAR, 1 | (lcdc_chan_is_sublcd(ch) ? 2 : 0));
146 static void lcdc_sys_write_data(void *handle, unsigned long data)
148 struct sh_mobile_lcdc_chan *ch = handle;
150 lcdc_write(ch->lcdc, _LDDWD0R, data | 0x11000000);
151 lcdc_wait_bit(ch->lcdc, _LDSR, 2, 0);
152 lcdc_write(ch->lcdc, _LDDWAR, 1 | (lcdc_chan_is_sublcd(ch) ? 2 : 0));
155 static unsigned long lcdc_sys_read_data(void *handle)
157 struct sh_mobile_lcdc_chan *ch = handle;
159 lcdc_write(ch->lcdc, _LDDRDR, 0x01000000);
160 lcdc_wait_bit(ch->lcdc, _LDSR, 2, 0);
161 lcdc_write(ch->lcdc, _LDDRAR, 1 | (lcdc_chan_is_sublcd(ch) ? 2 : 0));
164 return lcdc_read(ch->lcdc, _LDDRDR) & 0xffff;
167 struct sh_mobile_lcdc_sys_bus_ops sh_mobile_lcdc_sys_bus_ops = {
168 lcdc_sys_write_index,
173 static void sh_mobile_lcdc_start_stop(struct sh_mobile_lcdc_priv *priv,
176 unsigned long tmp = lcdc_read(priv, _LDCNT2R);
179 /* start or stop the lcdc */
181 lcdc_write(priv, _LDCNT2R, tmp | START_LCDC);
183 lcdc_write(priv, _LDCNT2R, tmp & ~START_LCDC);
185 /* wait until power is applied/stopped on all channels */
186 for (k = 0; k < ARRAY_SIZE(priv->ch); k++)
187 if (lcdc_read(priv, _LDCNT2R) & priv->ch[k].enabled)
189 tmp = lcdc_read_chan(&priv->ch[k], LDPMR) & 3;
190 if (start && tmp == 3)
192 if (!start && tmp == 0)
198 lcdc_write(priv, _LDDCKSTPR, 1); /* stop dotclock */
201 static int sh_mobile_lcdc_start(struct sh_mobile_lcdc_priv *priv)
203 struct sh_mobile_lcdc_chan *ch;
204 struct fb_videomode *lcd_cfg;
205 struct sh_mobile_lcdc_board_cfg *board_cfg;
211 lcdc_write(priv, _LDCNT2R, lcdc_read(priv, _LDCNT2R) | LCDC_RESET);
212 lcdc_wait_bit(priv, _LDCNT2R, LCDC_RESET, 0);
214 /* enable LCDC channels */
215 tmp = lcdc_read(priv, _LDCNT2R);
216 tmp |= priv->ch[0].enabled;
217 tmp |= priv->ch[1].enabled;
218 lcdc_write(priv, _LDCNT2R, tmp);
220 /* read data from external memory, avoid using the BEU for now */
221 lcdc_write(priv, _LDCNT2R, lcdc_read(priv, _LDCNT2R) & ~DISPLAY_BEU);
223 /* stop the lcdc first */
224 sh_mobile_lcdc_start_stop(priv, 0);
226 /* configure clocks */
228 for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
231 if (!priv->ch[k].enabled)
234 m = ch->cfg.clock_divider;
240 tmp |= m << (lcdc_chan_is_sublcd(ch) ? 8 : 0);
242 lcdc_write_chan(ch, LDDCKPAT1R, 0x00000000);
243 lcdc_write_chan(ch, LDDCKPAT2R, (1 << (m/2)) - 1);
246 lcdc_write(priv, _LDDCKR, tmp);
248 /* start dotclock again */
249 lcdc_write(priv, _LDDCKSTPR, 0);
250 lcdc_wait_bit(priv, _LDDCKSTPR, ~0, 0);
252 /* interrupts are disabled */
253 lcdc_write(priv, _LDINTR, 0);
255 for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
257 lcd_cfg = &ch->cfg.lcd_cfg;
262 tmp = ch->ldmt1r_value;
263 tmp |= (lcd_cfg->sync & FB_SYNC_VERT_HIGH_ACT) ? 0 : 1 << 28;
264 tmp |= (lcd_cfg->sync & FB_SYNC_HOR_HIGH_ACT) ? 0 : 1 << 27;
265 lcdc_write_chan(ch, LDMT1R, tmp);
268 lcdc_write_chan(ch, LDMT2R, ch->cfg.sys_bus_cfg.ldmt2r);
269 lcdc_write_chan(ch, LDMT3R, ch->cfg.sys_bus_cfg.ldmt3r);
271 /* horizontal configuration */
272 tmp = lcd_cfg->xres + lcd_cfg->hsync_len;
273 tmp += lcd_cfg->left_margin;
274 tmp += lcd_cfg->right_margin;
276 tmp |= (lcd_cfg->xres / 8) << 16; /* HDCN */
277 lcdc_write_chan(ch, LDHCNR, tmp);
280 tmp += lcd_cfg->right_margin;
281 tmp /= 8; /* HSYNP */
282 tmp |= (lcd_cfg->hsync_len / 8) << 16; /* HSYNW */
283 lcdc_write_chan(ch, LDHSYNR, tmp);
286 lcdc_write_chan(ch, LDPMR, 0);
288 /* vertical configuration */
289 tmp = lcd_cfg->yres + lcd_cfg->vsync_len;
290 tmp += lcd_cfg->upper_margin;
291 tmp += lcd_cfg->lower_margin; /* VTLN */
292 tmp |= lcd_cfg->yres << 16; /* VDLN */
293 lcdc_write_chan(ch, LDVLNR, tmp);
296 tmp += lcd_cfg->lower_margin; /* VSYNP */
297 tmp |= lcd_cfg->vsync_len << 16; /* VSYNW */
298 lcdc_write_chan(ch, LDVSYNR, tmp);
300 board_cfg = &ch->cfg.board_cfg;
301 if (board_cfg->setup_sys)
302 ret = board_cfg->setup_sys(board_cfg->board_data, ch,
303 &sh_mobile_lcdc_sys_bus_ops);
308 /* --- display_lcdc_data() --- */
309 lcdc_write(priv, _LDINTR, 0x00000f00);
311 /* word and long word swap */
312 lcdc_write(priv, _LDDDSR, lcdc_read(priv, _LDDDSR) | 6);
314 for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
317 if (!priv->ch[k].enabled)
320 /* set bpp format in PKF[4:0] */
321 tmp = lcdc_read_chan(ch, LDDFR);
322 tmp &= ~(0x0001001f);
323 tmp |= (priv->ch[k].info.var.bits_per_pixel == 16) ? 3 : 0;
324 lcdc_write_chan(ch, LDDFR, tmp);
326 /* point out our frame buffer */
327 lcdc_write_chan(ch, LDSA1R, ch->info.fix.smem_start);
330 lcdc_write_chan(ch, LDMLSR, ch->info.fix.line_length);
332 /* continuous read mode */
333 lcdc_write_chan(ch, LDSM1R, 0);
337 lcdc_write(priv, _LDCNT1R, LCDC_ENABLE);
340 sh_mobile_lcdc_start_stop(priv, 1);
342 /* tell the board code to enable the panel */
343 for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
345 board_cfg = &ch->cfg.board_cfg;
346 if (board_cfg->display_on)
347 board_cfg->display_on(board_cfg->board_data);
353 static void sh_mobile_lcdc_stop(struct sh_mobile_lcdc_priv *priv)
355 struct sh_mobile_lcdc_chan *ch;
356 struct sh_mobile_lcdc_board_cfg *board_cfg;
359 /* tell the board code to disable the panel */
360 for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
362 board_cfg = &ch->cfg.board_cfg;
363 if (board_cfg->display_off)
364 board_cfg->display_off(board_cfg->board_data);
368 sh_mobile_lcdc_start_stop(priv, 0);
371 static int sh_mobile_lcdc_check_interface(struct sh_mobile_lcdc_chan *ch)
375 switch (ch->cfg.interface_type) {
376 case RGB8: ifm = 0; miftyp = 0; break;
377 case RGB9: ifm = 0; miftyp = 4; break;
378 case RGB12A: ifm = 0; miftyp = 5; break;
379 case RGB12B: ifm = 0; miftyp = 6; break;
380 case RGB16: ifm = 0; miftyp = 7; break;
381 case RGB18: ifm = 0; miftyp = 10; break;
382 case RGB24: ifm = 0; miftyp = 11; break;
383 case SYS8A: ifm = 1; miftyp = 0; break;
384 case SYS8B: ifm = 1; miftyp = 1; break;
385 case SYS8C: ifm = 1; miftyp = 2; break;
386 case SYS8D: ifm = 1; miftyp = 3; break;
387 case SYS9: ifm = 1; miftyp = 4; break;
388 case SYS12: ifm = 1; miftyp = 5; break;
389 case SYS16A: ifm = 1; miftyp = 7; break;
390 case SYS16B: ifm = 1; miftyp = 8; break;
391 case SYS16C: ifm = 1; miftyp = 9; break;
392 case SYS18: ifm = 1; miftyp = 10; break;
393 case SYS24: ifm = 1; miftyp = 11; break;
397 /* SUBLCD only supports SYS interface */
398 if (lcdc_chan_is_sublcd(ch)) {
405 ch->ldmt1r_value = (ifm << 12) | miftyp;
411 static int sh_mobile_lcdc_setup_clocks(struct device *dev, int clock_source,
412 struct sh_mobile_lcdc_priv *priv)
417 switch (clock_source) {
418 case LCDC_CLK_BUS: str = "bus_clk"; icksel = 0; break;
419 case LCDC_CLK_PERIPHERAL: str = "peripheral_clk"; icksel = 1; break;
420 case LCDC_CLK_EXTERNAL: str = NULL; icksel = 2; break;
425 priv->lddckr = icksel << 16;
427 #ifdef CONFIG_HAVE_CLK
429 priv->clk = clk_get(dev, str);
430 if (IS_ERR(priv->clk)) {
431 dev_err(dev, "cannot get clock %s\n", str);
432 return PTR_ERR(priv->clk);
435 clk_enable(priv->clk);
442 static int sh_mobile_lcdc_setcolreg(u_int regno,
443 u_int red, u_int green, u_int blue,
444 u_int transp, struct fb_info *info)
446 u32 *palette = info->pseudo_palette;
448 if (regno >= PALETTE_NR)
451 /* only FB_VISUAL_TRUECOLOR supported */
453 red >>= 16 - info->var.red.length;
454 green >>= 16 - info->var.green.length;
455 blue >>= 16 - info->var.blue.length;
456 transp >>= 16 - info->var.transp.length;
458 palette[regno] = (red << info->var.red.offset) |
459 (green << info->var.green.offset) |
460 (blue << info->var.blue.offset) |
461 (transp << info->var.transp.offset);
466 static struct fb_fix_screeninfo sh_mobile_lcdc_fix = {
467 .id = "SH Mobile LCDC",
468 .type = FB_TYPE_PACKED_PIXELS,
469 .visual = FB_VISUAL_TRUECOLOR,
470 .accel = FB_ACCEL_NONE,
473 static struct fb_ops sh_mobile_lcdc_ops = {
474 .fb_setcolreg = sh_mobile_lcdc_setcolreg,
475 .fb_fillrect = cfb_fillrect,
476 .fb_copyarea = cfb_copyarea,
477 .fb_imageblit = cfb_imageblit,
480 static int sh_mobile_lcdc_set_bpp(struct fb_var_screeninfo *var, int bpp)
483 case 16: /* PKF[4:0] = 00011 - RGB 565 */
484 var->red.offset = 11;
486 var->green.offset = 5;
487 var->green.length = 6;
488 var->blue.offset = 0;
489 var->blue.length = 5;
490 var->transp.offset = 0;
491 var->transp.length = 0;
494 case 32: /* PKF[4:0] = 00000 - RGB 888
495 * sh7722 pdf says 00RRGGBB but reality is GGBB00RR
496 * this may be because LDDDSR has word swap enabled..
500 var->green.offset = 24;
501 var->green.length = 8;
502 var->blue.offset = 16;
503 var->blue.length = 8;
504 var->transp.offset = 0;
505 var->transp.length = 0;
510 var->bits_per_pixel = bpp;
511 var->red.msb_right = 0;
512 var->green.msb_right = 0;
513 var->blue.msb_right = 0;
514 var->transp.msb_right = 0;
518 static int sh_mobile_lcdc_remove(struct platform_device *pdev);
520 static int __init sh_mobile_lcdc_probe(struct platform_device *pdev)
522 struct fb_info *info;
523 struct sh_mobile_lcdc_priv *priv;
524 struct sh_mobile_lcdc_info *pdata;
525 struct sh_mobile_lcdc_chan_cfg *cfg;
526 struct resource *res;
531 if (!pdev->dev.platform_data) {
532 dev_err(&pdev->dev, "no platform data defined\n");
537 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
539 dev_err(&pdev->dev, "cannot find IO resource\n");
544 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
546 dev_err(&pdev->dev, "cannot allocate device data\n");
551 platform_set_drvdata(pdev, priv);
552 pdata = pdev->dev.platform_data;
555 for (i = 0; i < ARRAY_SIZE(pdata->ch); i++) {
556 priv->ch[j].lcdc = priv;
557 memcpy(&priv->ch[j].cfg, &pdata->ch[i], sizeof(pdata->ch[i]));
559 error = sh_mobile_lcdc_check_interface(&priv->ch[i]);
561 dev_err(&pdev->dev, "unsupported interface type\n");
565 switch (pdata->ch[i].chan) {
566 case LCDC_CHAN_MAINLCD:
567 priv->ch[j].enabled = 1 << 1;
568 priv->ch[j].reg_offs = lcdc_offs_mainlcd;
571 case LCDC_CHAN_SUBLCD:
572 priv->ch[j].enabled = 1 << 2;
573 priv->ch[j].reg_offs = lcdc_offs_sublcd;
580 dev_err(&pdev->dev, "no channels defined\n");
585 error = sh_mobile_lcdc_setup_clocks(&pdev->dev,
586 pdata->clock_source, priv);
588 dev_err(&pdev->dev, "unable to setup clocks\n");
592 priv->lddckr = pdata->lddckr;
593 priv->base = ioremap_nocache(res->start, (res->end - res->start) + 1);
595 for (i = 0; i < j; i++) {
596 info = &priv->ch[i].info;
597 cfg = &priv->ch[i].cfg;
599 info->fbops = &sh_mobile_lcdc_ops;
600 info->var.xres = info->var.xres_virtual = cfg->lcd_cfg.xres;
601 info->var.yres = info->var.yres_virtual = cfg->lcd_cfg.yres;
602 info->var.width = cfg->lcd_size_cfg.width;
603 info->var.height = cfg->lcd_size_cfg.height;
604 info->var.activate = FB_ACTIVATE_NOW;
605 error = sh_mobile_lcdc_set_bpp(&info->var, cfg->bpp);
609 info->fix = sh_mobile_lcdc_fix;
610 info->fix.line_length = cfg->lcd_cfg.xres * (cfg->bpp / 8);
611 info->fix.smem_len = info->fix.line_length * cfg->lcd_cfg.yres;
613 buf = dma_alloc_coherent(&pdev->dev, info->fix.smem_len,
614 &priv->ch[i].dma_handle, GFP_KERNEL);
616 dev_err(&pdev->dev, "unable to allocate buffer\n");
621 info->pseudo_palette = &priv->ch[i].pseudo_palette;
622 info->flags = FBINFO_FLAG_DEFAULT;
624 error = fb_alloc_cmap(&info->cmap, PALETTE_NR, 0);
626 dev_err(&pdev->dev, "unable to allocate cmap\n");
627 dma_free_coherent(&pdev->dev, info->fix.smem_len,
628 buf, priv->ch[i].dma_handle);
632 memset(buf, 0, info->fix.smem_len);
633 info->fix.smem_start = priv->ch[i].dma_handle;
634 info->screen_base = buf;
635 info->device = &pdev->dev;
641 error = sh_mobile_lcdc_start(priv);
643 dev_err(&pdev->dev, "unable to start hardware\n");
647 for (i = 0; i < j; i++) {
648 error = register_framebuffer(&priv->ch[i].info);
653 for (i = 0; i < j; i++) {
654 info = &priv->ch[i].info;
656 "registered %s/%s as %dx%d %dbpp.\n",
658 (priv->ch[i].cfg.chan == LCDC_CHAN_MAINLCD) ?
659 "mainlcd" : "sublcd",
660 (int) priv->ch[i].cfg.lcd_cfg.xres,
661 (int) priv->ch[i].cfg.lcd_cfg.yres,
662 priv->ch[i].cfg.bpp);
667 sh_mobile_lcdc_remove(pdev);
672 static int sh_mobile_lcdc_remove(struct platform_device *pdev)
674 struct sh_mobile_lcdc_priv *priv = platform_get_drvdata(pdev);
675 struct fb_info *info;
678 for (i = 0; i < ARRAY_SIZE(priv->ch); i++)
679 if (priv->ch[i].info.dev)
680 unregister_framebuffer(&priv->ch[i].info);
682 sh_mobile_lcdc_stop(priv);
684 for (i = 0; i < ARRAY_SIZE(priv->ch); i++) {
685 info = &priv->ch[i].info;
690 dma_free_coherent(&pdev->dev, info->fix.smem_len,
691 info->screen_base, priv->ch[i].dma_handle);
692 fb_dealloc_cmap(&info->cmap);
695 #ifdef CONFIG_HAVE_CLK
697 clk_disable(priv->clk);
709 static struct platform_driver sh_mobile_lcdc_driver = {
711 .name = "sh_mobile_lcdc_fb",
712 .owner = THIS_MODULE,
714 .probe = sh_mobile_lcdc_probe,
715 .remove = sh_mobile_lcdc_remove,
718 static int __init sh_mobile_lcdc_init(void)
720 return platform_driver_register(&sh_mobile_lcdc_driver);
723 static void __exit sh_mobile_lcdc_exit(void)
725 platform_driver_unregister(&sh_mobile_lcdc_driver);
728 module_init(sh_mobile_lcdc_init);
729 module_exit(sh_mobile_lcdc_exit);
731 MODULE_DESCRIPTION("SuperH Mobile LCDC Framebuffer driver");
732 MODULE_AUTHOR("Magnus Damm <damm@opensource.se>");
733 MODULE_LICENSE("GPL v2");