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   1 /*
   2  * linux/drivers/video/s3c2410fb.c
   3  *      Copyright (c) Arnaud Patard, Ben Dooks
   4  *
   5  * This file is subject to the terms and conditions of the GNU General Public
   6  * License.  See the file COPYING in the main directory of this archive for
   7  * more details.
   8  *
   9  *          S3C2410 LCD Controller Frame Buffer Driver
  10  *          based on skeletonfb.c, sa1100fb.c and others
  11  *
  12  * ChangeLog
  13  * 2005-04-07: Arnaud Patard <arnaud.patard@rtp-net.org>
  14  *      - u32 state -> pm_message_t state
  15  *      - S3C2410_{VA,SZ}_LCD -> S3C24XX
  16  *
  17  * 2005-03-15: Arnaud Patard <arnaud.patard@rtp-net.org>
  18  *      - Removed the ioctl
  19  *      - use readl/writel instead of __raw_writel/__raw_readl
  20  *
  21  * 2004-12-04: Arnaud Patard <arnaud.patard@rtp-net.org>
  22  *      - Added the possibility to set on or off the
  23  *      debugging mesaages
  24  *      - Replaced 0 and 1 by on or off when reading the
  25  *      /sys files
  26  *
  27  * 2005-03-23: Ben Dooks <ben-linux@fluff.org>
  28  *      - added non 16bpp modes
  29  *      - updated platform information for range of x/y/bpp
  30  *      - add code to ensure palette is written correctly
  31  *      - add pixel clock divisor control
  32  *
  33  * 2004-11-11: Arnaud Patard <arnaud.patard@rtp-net.org>
  34  *      - Removed the use of currcon as it no more exist
  35  *      - Added LCD power sysfs interface
  36  *
  37  * 2004-11-03: Ben Dooks <ben-linux@fluff.org>
  38  *      - minor cleanups
  39  *      - add suspend/resume support
  40  *      - s3c2410fb_setcolreg() not valid in >8bpp modes
  41  *      - removed last CONFIG_FB_S3C2410_FIXED
  42  *      - ensure lcd controller stopped before cleanup
  43  *      - added sysfs interface for backlight power
  44  *      - added mask for gpio configuration
  45  *      - ensured IRQs disabled during GPIO configuration
  46  *      - disable TPAL before enabling video
  47  *
  48  * 2004-09-20: Arnaud Patard <arnaud.patard@rtp-net.org>
  49  *      - Suppress command line options
  50  *
  51  * 2004-09-15: Arnaud Patard <arnaud.patard@rtp-net.org>
  52  *      - code cleanup
  53  *
  54  * 2004-09-07: Arnaud Patard <arnaud.patard@rtp-net.org>
  55  *      - Renamed from h1940fb.c to s3c2410fb.c
  56  *      - Add support for different devices
  57  *      - Backlight support
  58  *
  59  * 2004-09-05: Herbert Pötzl <herbert@13thfloor.at>
  60  *      - added clock (de-)allocation code
  61  *      - added fixem fbmem option
  62  *
  63  * 2004-07-27: Arnaud Patard <arnaud.patard@rtp-net.org>
  64  *      - code cleanup
  65  *      - added a forgotten return in h1940fb_init
  66  *
  67  * 2004-07-19: Herbert Pötzl <herbert@13thfloor.at>
  68  *      - code cleanup and extended debugging
  69  *
  70  * 2004-07-15: Arnaud Patard <arnaud.patard@rtp-net.org>
  71  *      - First version
  72  */
  73
  74 #include <linux/module.h>
  75 #include <linux/kernel.h>
  76 #include <linux/errno.h>
  77 #include <linux/string.h>
  78 #include <linux/mm.h>
  79 #include <linux/slab.h>
  80 #include <linux/delay.h>
  81 #include <linux/fb.h>
  82 #include <linux/init.h>
  83 #include <linux/dma-mapping.h>
  84 #include <linux/interrupt.h>
  85 #include <linux/workqueue.h>
  86 #include <linux/wait.h>
  87 #include <linux/platform_device.h>
  88 #include <linux/clk.h>
  89
  90 #include <asm/io.h>
  91 #include <asm/uaccess.h>
  92 #include <asm/div64.h>
  93
  94 #include <asm/mach/map.h>
  95 #include <asm/arch/regs-lcd.h>
  96 #include <asm/arch/regs-gpio.h>
  97 #include <asm/arch/fb.h>
  98
  99 #ifdef CONFIG_PM
 100 #include <linux/pm.h>
 101 #endif
 102
 103 #include "s3c2410fb.h"
 104
 105 static struct s3c2410fb_mach_info *mach_info;
 106
 107 /* Debugging stuff */
 108 #ifdef CONFIG_FB_S3C2410_DEBUG
 109 static int debug        = 1;
 110 #else
 111 static int debug        = 0;
 112 #endif
 113
 114 #define dprintk(msg...) if (debug) { printk(KERN_DEBUG "s3c2410fb: " msg); }
 115
 116 /* useful functions */
 117
 118 /* s3c2410fb_set_lcdaddr
 119  *
 120  * initialise lcd controller address pointers
 121  */
 122 static void s3c2410fb_set_lcdaddr(struct s3c2410fb_info *fbi)
 123 {
 124         struct fb_var_screeninfo *var = &fbi->fb->var;
 125         unsigned long saddr1, saddr2, saddr3;
 126         int line_length = var->xres * var->bits_per_pixel;
 127
 128         saddr1  = fbi->fb->fix.smem_start >> 1;
 129         saddr2  = fbi->fb->fix.smem_start;
 130         saddr2 += (line_length * var->yres) / 8;
 131         saddr2 >>= 1;
 132
 133         saddr3 = S3C2410_OFFSIZE(0) |
 134                  S3C2410_PAGEWIDTH((line_length / 16) & 0x3ff);
 135
 136         dprintk("LCDSADDR1 = 0x%08lx\n", saddr1);
 137         dprintk("LCDSADDR2 = 0x%08lx\n", saddr2);
 138         dprintk("LCDSADDR3 = 0x%08lx\n", saddr3);
 139
 140         writel(saddr1, S3C2410_LCDSADDR1);
 141         writel(saddr2, S3C2410_LCDSADDR2);
 142         writel(saddr3, S3C2410_LCDSADDR3);
 143 }
 144
 145 /* s3c2410fb_calc_pixclk()
 146  *
 147  * calculate divisor for clk->pixclk
 148  */
 149 static unsigned int s3c2410fb_calc_pixclk(struct s3c2410fb_info *fbi,
 150                                           unsigned long pixclk)
 151 {
 152         unsigned long clk = clk_get_rate(fbi->clk);
 153         unsigned long long div;
 154
 155         /* pixclk is in picoseoncds, our clock is in Hz
 156          *
 157          * Hz -> picoseconds is / 10^-12
 158          */
 159
 160         div = (unsigned long long)clk * pixclk;
 161         do_div(div, 1000000UL);
 162         do_div(div, 1000000UL);
 163
 164         dprintk("pixclk %ld, divisor is %ld\n", pixclk, (long)div);
 165         return div;
 166 }
 167
 168 /*
 169  *      s3c2410fb_check_var():
 170  *      Get the video params out of 'var'. If a value doesn't fit, round it up,
 171  *      if it's too big, return -EINVAL.
 172  *
 173  */
 174 static int s3c2410fb_check_var(struct fb_var_screeninfo *var,
 175                                struct fb_info *info)
 176 {
 177         struct s3c2410fb_info *fbi = info->par;
 178
 179         dprintk("check_var(var=%p, info=%p)\n", var, info);
 180
 181         /* validate x/y resolution */
 182
 183         if (var->yres > fbi->mach_info->yres.max)
 184                 var->yres = fbi->mach_info->yres.max;
 185         else if (var->yres < fbi->mach_info->yres.min)
 186                 var->yres = fbi->mach_info->yres.min;
 187
 188         if (var->xres > fbi->mach_info->xres.max)
 189                 var->yres = fbi->mach_info->xres.max;
 190         else if (var->xres < fbi->mach_info->xres.min)
 191                 var->xres = fbi->mach_info->xres.min;
 192
 193         /* validate bpp */
 194
 195         if (var->bits_per_pixel > fbi->mach_info->bpp.max)
 196                 var->bits_per_pixel = fbi->mach_info->bpp.max;
 197         else if (var->bits_per_pixel < fbi->mach_info->bpp.min)
 198                 var->bits_per_pixel = fbi->mach_info->bpp.min;
 199
 200         var->transp.offset = 0;
 201         var->transp.length = 0;
 202         /* set r/g/b positions */
 203         switch (var->bits_per_pixel) {
 204         case 1:
 205         case 2:
 206         case 4:
 207                 var->red.offset = 0;
 208                 var->red.length = var->bits_per_pixel;
 209                 var->green      = var->red;
 210                 var->blue       = var->red;
 211                 break;
 212         case 8:
 213                 if (fbi->mach_info->type != S3C2410_LCDCON1_TFT) {
 214                         /* 8 bpp 332 */
 215                         var->red.length         = 3;
 216                         var->red.offset         = 5;
 217                         var->green.length       = 3;
 218                         var->green.offset       = 2;
 219                         var->blue.length        = 2;
 220                         var->blue.offset        = 0;
 221                 } else {
 222                         var->red.offset         = 0;
 223                         var->red.length         = 8;
 224                         var->green              = var->red;
 225                         var->blue               = var->red;
 226                 }
 227                 break;
 228         case 12:
 229                 /* 12 bpp 444 */
 230                 var->red.length         = 4;
 231                 var->red.offset         = 8;
 232                 var->green.length       = 4;
 233                 var->green.offset       = 4;
 234                 var->blue.length        = 4;
 235                 var->blue.offset        = 0;
 236                 break;
 237
 238         default:
 239         case 16:
 240                 if (fbi->regs.lcdcon5 & S3C2410_LCDCON5_FRM565) {
 241                         /* 16 bpp, 565 format */
 242                         var->red.offset         = 11;
 243                         var->green.offset       = 5;
 244                         var->blue.offset        = 0;
 245                         var->red.length         = 5;
 246                         var->green.length       = 6;
 247                         var->blue.length        = 5;
 248                 } else {
 249                         /* 16 bpp, 5551 format */
 250                         var->red.offset         = 11;
 251                         var->green.offset       = 6;
 252                         var->blue.offset        = 1;
 253                         var->red.length         = 5;
 254                         var->green.length       = 5;
 255                         var->blue.length        = 5;
 256                 }
 257                 break;
 258         case 24:
 259                 /* 24 bpp 888 */
 260                 var->red.length         = 8;
 261                 var->red.offset         = 16;
 262                 var->green.length       = 8;
 263                 var->green.offset       = 8;
 264                 var->blue.length        = 8;
 265                 var->blue.offset        = 0;
 266                 break;
 267
 268
 269         }
 270         return 0;
 271 }
 272
 273 /* s3c2410fb_activate_var
 274  *
 275  * activate (set) the controller from the given framebuffer
 276  * information
 277  */
 278 static void s3c2410fb_activate_var(struct s3c2410fb_info *fbi,
 279                                    struct fb_var_screeninfo *var)
 280 {
 281         int hs;
 282
 283         fbi->regs.lcdcon1 &= ~S3C2410_LCDCON1_MODEMASK;
 284         fbi->regs.lcdcon1 &= ~S3C2410_LCDCON1_TFT;
 285
 286         dprintk("%s: var->xres  = %d\n", __FUNCTION__, var->xres);
 287         dprintk("%s: var->yres  = %d\n", __FUNCTION__, var->yres);
 288         dprintk("%s: var->bpp   = %d\n", __FUNCTION__, var->bits_per_pixel);
 289
 290         fbi->regs.lcdcon1 |= fbi->mach_info->type;
 291
 292         if (fbi->mach_info->type == S3C2410_LCDCON1_TFT)
 293                 switch (var->bits_per_pixel) {
 294                 case 1:
 295                         fbi->regs.lcdcon1 |= S3C2410_LCDCON1_TFT1BPP;
 296                         break;
 297                 case 2:
 298                         fbi->regs.lcdcon1 |= S3C2410_LCDCON1_TFT2BPP;
 299                         break;
 300                 case 4:
 301                         fbi->regs.lcdcon1 |= S3C2410_LCDCON1_TFT4BPP;
 302                         break;
 303                 case 8:
 304                         fbi->regs.lcdcon1 |= S3C2410_LCDCON1_TFT8BPP;
 305                         break;
 306                 case 16:
 307                         fbi->regs.lcdcon1 |= S3C2410_LCDCON1_TFT16BPP;
 308                         break;
 309
 310                 default:
 311                         /* invalid pixel depth */
 312                         dev_err(fbi->dev, "invalid bpp %d\n",
 313                                 var->bits_per_pixel);
 314                 }
 315         else
 316                 switch (var->bits_per_pixel) {
 317                 case 1:
 318                         fbi->regs.lcdcon1 |= S3C2410_LCDCON1_STN1BPP;
 319                         break;
 320                 case 2:
 321                         fbi->regs.lcdcon1 |= S3C2410_LCDCON1_STN2GREY;
 322                         break;
 323                 case 4:
 324                         fbi->regs.lcdcon1 |= S3C2410_LCDCON1_STN4GREY;
 325                         break;
 326                 case 8:
 327                         fbi->regs.lcdcon1 |= S3C2410_LCDCON1_STN8BPP;
 328                         break;
 329                 case 12:
 330                         fbi->regs.lcdcon1 |= S3C2410_LCDCON1_STN12BPP;
 331                         break;
 332
 333                 default:
 334                         /* invalid pixel depth */
 335                         dev_err(fbi->dev, "invalid bpp %d\n",
 336                                 var->bits_per_pixel);
 337                 }
 338
 339         /* check to see if we need to update sync/borders */
 340
 341         if (!fbi->mach_info->fixed_syncs) {
 342                 dprintk("setting vert: up=%d, low=%d, sync=%d\n",
 343                         var->upper_margin, var->lower_margin, var->vsync_len);
 344
 345                 dprintk("setting horz: lft=%d, rt=%d, sync=%d\n",
 346                         var->left_margin, var->right_margin, var->hsync_len);
 347
 348                 fbi->regs.lcdcon2 =
 349                         S3C2410_LCDCON2_VBPD(var->upper_margin - 1) |
 350                         S3C2410_LCDCON2_VFPD(var->lower_margin - 1) |
 351                         S3C2410_LCDCON2_VSPW(var->vsync_len - 1);
 352
 353                 fbi->regs.lcdcon3 =
 354                         S3C2410_LCDCON3_HBPD(var->right_margin - 1) |
 355                         S3C2410_LCDCON3_HFPD(var->left_margin - 1);
 356
 357                 fbi->regs.lcdcon4 &= ~S3C2410_LCDCON4_HSPW(0xff);
 358                 fbi->regs.lcdcon4 |=  S3C2410_LCDCON4_HSPW(var->hsync_len - 1);
 359         }
 360
 361         /* update X/Y info */
 362
 363         fbi->regs.lcdcon2 &= ~S3C2410_LCDCON2_LINEVAL(0x3ff);
 364         fbi->regs.lcdcon2 |=  S3C2410_LCDCON2_LINEVAL(var->yres - 1);
 365
 366         switch (fbi->mach_info->type) {
 367         case S3C2410_LCDCON1_DSCAN4:
 368         case S3C2410_LCDCON1_STN8:
 369                 hs = var->xres / 8;
 370                 break;
 371         case S3C2410_LCDCON1_STN4:
 372                 hs = var->xres / 4;
 373                 break;
 374         default:
 375         case S3C2410_LCDCON1_TFT:
 376                 hs = var->xres;
 377                 break;
 378         }
 379
 380         /* Special cases : STN color displays */
 381         if (((fbi->regs.lcdcon1 & S3C2410_LCDCON1_MODEMASK) == S3C2410_LCDCON1_STN8BPP) ||
 382             ((fbi->regs.lcdcon1 & S3C2410_LCDCON1_MODEMASK) == S3C2410_LCDCON1_STN12BPP))
 383                 hs = hs * 3;
 384
 385         fbi->regs.lcdcon3 &= ~S3C2410_LCDCON3_HOZVAL(0x7ff);
 386         fbi->regs.lcdcon3 |=  S3C2410_LCDCON3_HOZVAL(hs - 1);
 387
 388         if (var->pixclock > 0) {
 389                 int clkdiv = s3c2410fb_calc_pixclk(fbi, var->pixclock);
 390
 391                 if (fbi->mach_info->type == S3C2410_LCDCON1_TFT) {
 392                         clkdiv = (clkdiv / 2) - 1;
 393                         if (clkdiv < 0)
 394                                 clkdiv = 0;
 395                 } else {
 396                         clkdiv = (clkdiv / 2);
 397                         if (clkdiv < 2)
 398                                 clkdiv = 2;
 399                 }
 400
 401                 fbi->regs.lcdcon1 &= ~S3C2410_LCDCON1_CLKVAL(0x3ff);
 402                 fbi->regs.lcdcon1 |=  S3C2410_LCDCON1_CLKVAL(clkdiv);
 403         }
 404
 405         /* write new registers */
 406
 407         dprintk("new register set:\n");
 408         dprintk("lcdcon[1] = 0x%08lx\n", fbi->regs.lcdcon1);
 409         dprintk("lcdcon[2] = 0x%08lx\n", fbi->regs.lcdcon2);
 410         dprintk("lcdcon[3] = 0x%08lx\n", fbi->regs.lcdcon3);
 411         dprintk("lcdcon[4] = 0x%08lx\n", fbi->regs.lcdcon4);
 412         dprintk("lcdcon[5] = 0x%08lx\n", fbi->regs.lcdcon5);
 413
 414         writel(fbi->regs.lcdcon1 & ~S3C2410_LCDCON1_ENVID, S3C2410_LCDCON1);
 415         writel(fbi->regs.lcdcon2, S3C2410_LCDCON2);
 416         writel(fbi->regs.lcdcon3, S3C2410_LCDCON3);
 417         writel(fbi->regs.lcdcon4, S3C2410_LCDCON4);
 418         writel(fbi->regs.lcdcon5, S3C2410_LCDCON5);
 419
 420         /* set lcd address pointers */
 421         s3c2410fb_set_lcdaddr(fbi);
 422
 423         writel(fbi->regs.lcdcon1, S3C2410_LCDCON1);
 424 }
 425
 426 /*
 427  *      s3c2410fb_set_par - Alters the hardware state.
 428  *      @info: frame buffer structure that represents a single frame buffer
 429  *
 430  */
 431 static int s3c2410fb_set_par(struct fb_info *info)
 432 {
 433         struct s3c2410fb_info *fbi = info->par;
 434         struct fb_var_screeninfo *var = &info->var;
 435
 436         switch (var->bits_per_pixel) {
 437         case 16:
 438                 info->fix.visual = FB_VISUAL_TRUECOLOR;
 439                 break;
 440         case 1:
 441                 info->fix.visual = FB_VISUAL_MONO01;
 442                 break;
 443         default:
 444                 info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
 445                 break;
 446         }
 447
 448         info->fix.line_length = (var->width * var->bits_per_pixel) / 8;
 449
 450         /* activate this new configuration */
 451
 452         s3c2410fb_activate_var(fbi, var);
 453         return 0;
 454 }
 455
 456 static void schedule_palette_update(struct s3c2410fb_info *fbi,
 457                                     unsigned int regno, unsigned int val)
 458 {
 459         unsigned long flags;
 460         unsigned long irqen;
 461         void __iomem *regs = fbi->io;
 462
 463         local_irq_save(flags);
 464
 465         fbi->palette_buffer[regno] = val;
 466
 467         if (!fbi->palette_ready) {
 468                 fbi->palette_ready = 1;
 469
 470                 /* enable IRQ */
 471                 irqen = readl(regs + S3C2410_LCDINTMSK);
 472                 irqen &= ~S3C2410_LCDINT_FRSYNC;
 473                 writel(irqen, regs + S3C2410_LCDINTMSK);
 474         }
 475
 476         local_irq_restore(flags);
 477 }
 478
 479 /* from pxafb.c */
 480 static inline unsigned int chan_to_field(unsigned int chan,
 481                                          struct fb_bitfield *bf)
 482 {
 483         chan &= 0xffff;
 484         chan >>= 16 - bf->length;
 485         return chan << bf->offset;
 486 }
 487
 488 static int s3c2410fb_setcolreg(unsigned regno,
 489                                unsigned red, unsigned green, unsigned blue,
 490                                unsigned transp, struct fb_info *info)
 491 {
 492         struct s3c2410fb_info *fbi = info->par;
 493         unsigned int val;
 494
 495         /* dprintk("setcol: regno=%d, rgb=%d,%d,%d\n",
 496                    regno, red, green, blue); */
 497
 498         switch (info->fix.visual) {
 499         case FB_VISUAL_TRUECOLOR:
 500                 /* true-colour, use pseudo-palette */
 501
 502                 if (regno < 16) {
 503                         u32 *pal = info->pseudo_palette;
 504
 505                         val  = chan_to_field(red,   &info->var.red);
 506                         val |= chan_to_field(green, &info->var.green);
 507                         val |= chan_to_field(blue,  &info->var.blue);
 508
 509                         pal[regno] = val;
 510                 }
 511                 break;
 512
 513         case FB_VISUAL_PSEUDOCOLOR:
 514                 if (regno < 256) {
 515                         /* currently assume RGB 5-6-5 mode */
 516
 517                         val  = ((red   >>  0) & 0xf800);
 518                         val |= ((green >>  5) & 0x07e0);
 519                         val |= ((blue  >> 11) & 0x001f);
 520
 521                         writel(val, S3C2410_TFTPAL(regno));
 522                         schedule_palette_update(fbi, regno, val);
 523                 }
 524
 525                 break;
 526
 527         default:
 528                 return 1;       /* unknown type */
 529         }
 530
 531         return 0;
 532 }
 533
 534 /*
 535  *      s3c2410fb_blank
 536  *      @blank_mode: the blank mode we want.
 537  *      @info: frame buffer structure that represents a single frame buffer
 538  *
 539  *      Blank the screen if blank_mode != 0, else unblank. Return 0 if
 540  *      blanking succeeded, != 0 if un-/blanking failed due to e.g. a
 541  *      video mode which doesn't support it. Implements VESA suspend
 542  *      and powerdown modes on hardware that supports disabling hsync/vsync:
 543  *      blank_mode == 2: suspend vsync
 544  *      blank_mode == 3: suspend hsync
 545  *      blank_mode == 4: powerdown
 546  *
 547  *      Returns negative errno on error, or zero on success.
 548  *
 549  */
 550 static int s3c2410fb_blank(int blank_mode, struct fb_info *info)
 551 {
 552         dprintk("blank(mode=%d, info=%p)\n", blank_mode, info);
 553
 554         if (mach_info == NULL)
 555                 return -EINVAL;
 556
 557         if (blank_mode == FB_BLANK_UNBLANK)
 558                 writel(0x0, S3C2410_TPAL);
 559         else {
 560                 dprintk("setting TPAL to output 0x000000\n");
 561                 writel(S3C2410_TPAL_EN, S3C2410_TPAL);
 562         }
 563
 564         return 0;
 565 }
 566
 567 static int s3c2410fb_debug_show(struct device *dev,
 568                                 struct device_attribute *attr, char *buf)
 569 {
 570         return snprintf(buf, PAGE_SIZE, "%s\n", debug ? "on" : "off");
 571 }
 572 static int s3c2410fb_debug_store(struct device *dev,
 573                                  struct device_attribute *attr,
 574                                  const char *buf, size_t len)
 575 {
 576         if (mach_info == NULL)
 577                 return -EINVAL;
 578
 579         if (len < 1)
 580                 return -EINVAL;
 581
 582         if (strnicmp(buf, "on", 2) == 0 ||
 583             strnicmp(buf, "1", 1) == 0) {
 584                 debug = 1;
 585                 printk(KERN_DEBUG "s3c2410fb: Debug On");
 586         } else if (strnicmp(buf, "off", 3) == 0 ||
 587                    strnicmp(buf, "0", 1) == 0) {
 588                 debug = 0;
 589                 printk(KERN_DEBUG "s3c2410fb: Debug Off");
 590         } else {
 591                 return -EINVAL;
 592         }
 593
 594         return len;
 595 }
 596
 597 static DEVICE_ATTR(debug, 0666, s3c2410fb_debug_show, s3c2410fb_debug_store);
 598
 599 static struct fb_ops s3c2410fb_ops = {
 600         .owner          = THIS_MODULE,
 601         .fb_check_var   = s3c2410fb_check_var,
 602         .fb_set_par     = s3c2410fb_set_par,
 603         .fb_blank       = s3c2410fb_blank,
 604         .fb_setcolreg   = s3c2410fb_setcolreg,
 605         .fb_fillrect    = cfb_fillrect,
 606         .fb_copyarea    = cfb_copyarea,
 607         .fb_imageblit   = cfb_imageblit,
 608 };
 609
 610 /*
 611  * s3c2410fb_map_video_memory():
 612  *      Allocates the DRAM memory for the frame buffer.  This buffer is
 613  *      remapped into a non-cached, non-buffered, memory region to
 614  *      allow palette and pixel writes to occur without flushing the
 615  *      cache.  Once this area is remapped, all virtual memory
 616  *      access to the video memory should occur at the new region.
 617  */
 618 static int __init s3c2410fb_map_video_memory(struct s3c2410fb_info *fbi)
 619 {
 620         dprintk("map_video_memory(fbi=%p)\n", fbi);
 621
 622         fbi->map_size = PAGE_ALIGN(fbi->fb->fix.smem_len + PAGE_SIZE);
 623         fbi->map_cpu  = dma_alloc_writecombine(fbi->dev, fbi->map_size,
 624                                                &fbi->map_dma, GFP_KERNEL);
 625
 626         fbi->map_size = fbi->fb->fix.smem_len;
 627
 628         if (fbi->map_cpu) {
 629                 /* prevent initial garbage on screen */
 630                 dprintk("map_video_memory: clear %p:%08x\n",
 631                         fbi->map_cpu, fbi->map_size);
 632                 memset(fbi->map_cpu, 0xf0, fbi->map_size);
 633
 634                 fbi->screen_dma         = fbi->map_dma;
 635                 fbi->fb->screen_base    = fbi->map_cpu;
 636                 fbi->fb->fix.smem_start  = fbi->screen_dma;
 637
 638                 dprintk("map_video_memory: dma=%08x cpu=%p size=%08x\n",
 639                         fbi->map_dma, fbi->map_cpu, fbi->fb->fix.smem_len);
 640         }
 641
 642         return fbi->map_cpu ? 0 : -ENOMEM;
 643 }
 644
 645 static inline void s3c2410fb_unmap_video_memory(struct s3c2410fb_info *fbi)
 646 {
 647         dma_free_writecombine(fbi->dev, fbi->map_size, fbi->map_cpu,
 648                               fbi->map_dma);
 649 }
 650
 651 static inline void modify_gpio(void __iomem *reg,
 652                                unsigned long set, unsigned long mask)
 653 {
 654         unsigned long tmp;
 655
 656         tmp = readl(reg) & ~mask;
 657         writel(tmp | set, reg);
 658 }
 659
 660 /*
 661  * s3c2410fb_init_registers - Initialise all LCD-related registers
 662  */
 663 static int s3c2410fb_init_registers(struct s3c2410fb_info *fbi)
 664 {
 665         unsigned long flags;
 666         void __iomem *regs = fbi->io;
 667
 668         /* Initialise LCD with values from haret */
 669
 670         local_irq_save(flags);
 671
 672         /* modify the gpio(s) with interrupts set (bjd) */
 673
 674         modify_gpio(S3C2410_GPCUP,  mach_info->gpcup,  mach_info->gpcup_mask);
 675         modify_gpio(S3C2410_GPCCON, mach_info->gpccon, mach_info->gpccon_mask);
 676         modify_gpio(S3C2410_GPDUP,  mach_info->gpdup,  mach_info->gpdup_mask);
 677         modify_gpio(S3C2410_GPDCON, mach_info->gpdcon, mach_info->gpdcon_mask);
 678
 679         local_irq_restore(flags);
 680
 681         writel(fbi->regs.lcdcon1, regs + S3C2410_LCDCON1);
 682         writel(fbi->regs.lcdcon2, regs + S3C2410_LCDCON2);
 683         writel(fbi->regs.lcdcon3, regs + S3C2410_LCDCON3);
 684         writel(fbi->regs.lcdcon4, regs + S3C2410_LCDCON4);
 685         writel(fbi->regs.lcdcon5, regs + S3C2410_LCDCON5);
 686
 687         s3c2410fb_set_lcdaddr(fbi);
 688
 689         dprintk("LPCSEL    = 0x%08lx\n", mach_info->lpcsel);
 690         writel(mach_info->lpcsel, regs + S3C2410_LPCSEL);
 691
 692         dprintk("replacing TPAL %08x\n", readl(regs + S3C2410_TPAL));
 693
 694         /* ensure temporary palette disabled */
 695         writel(0x00, regs + S3C2410_TPAL);
 696
 697         /* Enable video by setting the ENVID bit to 1 */
 698         fbi->regs.lcdcon1 |= S3C2410_LCDCON1_ENVID;
 699         writel(fbi->regs.lcdcon1, regs + S3C2410_LCDCON1);
 700         return 0;
 701 }
 702
 703 static void s3c2410fb_write_palette(struct s3c2410fb_info *fbi)
 704 {
 705         unsigned int i;
 706         void __iomem *regs = fbi->io;
 707
 708         fbi->palette_ready = 0;
 709
 710         for (i = 0; i < 256; i++) {
 711                 unsigned long ent = fbi->palette_buffer[i];
 712                 if (ent == PALETTE_BUFF_CLEAR)
 713                         continue;
 714
 715                 writel(ent, regs + S3C2410_TFTPAL(i));
 716
 717                 /* it seems the only way to know exactly
 718                  * if the palette wrote ok, is to check
 719                  * to see if the value verifies ok
 720                  */
 721
 722                 if (readw(regs + S3C2410_TFTPAL(i)) == ent)
 723                         fbi->palette_buffer[i] = PALETTE_BUFF_CLEAR;
 724                 else
 725                         fbi->palette_ready = 1;   /* retry */
 726         }
 727 }
 728
 729 static irqreturn_t s3c2410fb_irq(int irq, void *dev_id)
 730 {
 731         struct s3c2410fb_info *fbi = dev_id;
 732         void __iomem *regs = fbi->io;
 733         unsigned long lcdirq = readl(regs + S3C2410_LCDINTPND);
 734
 735         if (lcdirq & S3C2410_LCDINT_FRSYNC) {
 736                 if (fbi->palette_ready)
 737                         s3c2410fb_write_palette(fbi);
 738
 739                 writel(S3C2410_LCDINT_FRSYNC, regs + S3C2410_LCDINTPND);
 740                 writel(S3C2410_LCDINT_FRSYNC, regs + S3C2410_LCDSRCPND);
 741         }
 742
 743         return IRQ_HANDLED;
 744 }
 745
 746 static char driver_name[] = "s3c2410fb";
 747
 748 static int __init s3c2410fb_probe(struct platform_device *pdev)
 749 {
 750         struct s3c2410fb_info *info;
 751         struct fb_info *fbinfo;
 752         struct s3c2410fb_hw *mregs;
 753         struct resource *res;
 754         int ret;
 755         int irq;
 756         int i;
 757         int size;
 758         u32 lcdcon1;
 759
 760         mach_info = pdev->dev.platform_data;
 761         if (mach_info == NULL) {
 762                 dev_err(&pdev->dev,
 763                         "no platform data for lcd, cannot attach\n");
 764                 return -EINVAL;
 765         }
 766
 767         mregs = &mach_info->regs;
 768
 769         irq = platform_get_irq(pdev, 0);
 770         if (irq < 0) {
 771                 dev_err(&pdev->dev, "no irq for device\n");
 772                 return -ENOENT;
 773         }
 774
 775         fbinfo = framebuffer_alloc(sizeof(struct s3c2410fb_info), &pdev->dev);
 776         if (!fbinfo)
 777                 return -ENOMEM;
 778
 779         info = fbinfo->par;
 780         info->fb = fbinfo;
 781         info->dev = &pdev->dev;
 782
 783         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 784         if (res == NULL) {
 785                 dev_err(&pdev->dev, "failed to get memory registers\n");
 786                 ret = -ENXIO;
 787                 goto dealloc_fb;
 788         }
 789
 790         size = (res->end - res->start) + 1;
 791         info->mem = request_mem_region(res->start, size, pdev->name);
 792         if (info->mem == NULL) {
 793                 dev_err(&pdev->dev, "failed to get memory region\n");
 794                 ret = -ENOENT;
 795                 goto dealloc_fb;
 796         }
 797
 798         info->io = ioremap(res->start, size);
 799         if (info->io == NULL) {
 800                 dev_err(&pdev->dev, "ioremap() of registers failed\n");
 801                 ret = -ENXIO;
 802                 goto release_mem;
 803         }
 804
 805         platform_set_drvdata(pdev, fbinfo);
 806
 807         dprintk("devinit\n");
 808
 809         strcpy(fbinfo->fix.id, driver_name);
 810
 811         memcpy(&info->regs, &mach_info->regs, sizeof(info->regs));
 812
 813         /* Stop the video and unset ENVID if set */
 814         info->regs.lcdcon1 &= ~S3C2410_LCDCON1_ENVID;
 815         lcdcon1 = readl(info->io + S3C2410_LCDCON1);
 816         writel(lcdcon1 & ~S3C2410_LCDCON1_ENVID, info->io + S3C2410_LCDCON1);
 817
 818         info->mach_info             = pdev->dev.platform_data;
 819
 820         fbinfo->fix.type            = FB_TYPE_PACKED_PIXELS;
 821         fbinfo->fix.type_aux        = 0;
 822         fbinfo->fix.xpanstep        = 0;
 823         fbinfo->fix.ypanstep        = 0;
 824         fbinfo->fix.ywrapstep       = 0;
 825         fbinfo->fix.accel           = FB_ACCEL_NONE;
 826
 827         fbinfo->var.nonstd          = 0;
 828         fbinfo->var.activate        = FB_ACTIVATE_NOW;
 829         fbinfo->var.height          = mach_info->height;
 830         fbinfo->var.width           = mach_info->width;
 831         fbinfo->var.accel_flags     = 0;
 832         fbinfo->var.vmode           = FB_VMODE_NONINTERLACED;
 833
 834         fbinfo->fbops               = &s3c2410fb_ops;
 835         fbinfo->flags               = FBINFO_FLAG_DEFAULT;
 836         fbinfo->pseudo_palette      = &info->pseudo_pal;
 837
 838         fbinfo->var.xres            = mach_info->xres.defval;
 839         fbinfo->var.xres_virtual    = mach_info->xres.defval;
 840         fbinfo->var.yres            = mach_info->yres.defval;
 841         fbinfo->var.yres_virtual    = mach_info->yres.defval;
 842         fbinfo->var.bits_per_pixel  = mach_info->bpp.defval;
 843
 844         fbinfo->var.upper_margin    =
 845                                 S3C2410_LCDCON2_GET_VBPD(mregs->lcdcon2) + 1;
 846         fbinfo->var.lower_margin    =
 847                                 S3C2410_LCDCON2_GET_VFPD(mregs->lcdcon2) + 1;
 848         fbinfo->var.vsync_len       =
 849                                 S3C2410_LCDCON2_GET_VSPW(mregs->lcdcon2) + 1;
 850
 851         fbinfo->var.left_margin     =
 852                                 S3C2410_LCDCON3_GET_HFPD(mregs->lcdcon3) + 1;
 853         fbinfo->var.right_margin    =
 854                                 S3C2410_LCDCON3_GET_HBPD(mregs->lcdcon3) + 1;
 855         fbinfo->var.hsync_len       =
 856                                 S3C2410_LCDCON4_GET_HSPW(mregs->lcdcon4) + 1;
 857
 858         fbinfo->var.red.offset      = 11;
 859         fbinfo->var.green.offset    = 5;
 860         fbinfo->var.blue.offset     = 0;
 861         fbinfo->var.transp.offset   = 0;
 862         fbinfo->var.red.length      = 5;
 863         fbinfo->var.green.length    = 6;
 864         fbinfo->var.blue.length     = 5;
 865         fbinfo->var.transp.length   = 0;
 866         fbinfo->fix.smem_len        =   mach_info->xres.max *
 867                                         mach_info->yres.max *
 868                                         mach_info->bpp.max / 8;
 869
 870         for (i = 0; i < 256; i++)
 871                 info->palette_buffer[i] = PALETTE_BUFF_CLEAR;
 872
 873         ret = request_irq(irq, s3c2410fb_irq, IRQF_DISABLED, pdev->name, info);
 874         if (ret) {
 875                 dev_err(&pdev->dev, "cannot get irq %d - err %d\n", irq, ret);
 876                 ret = -EBUSY;
 877                 goto release_regs;
 878         }
 879
 880         info->clk = clk_get(NULL, "lcd");
 881         if (!info->clk || IS_ERR(info->clk)) {
 882                 printk(KERN_ERR "failed to get lcd clock source\n");
 883                 ret = -ENOENT;
 884                 goto release_irq;
 885         }
 886
 887         clk_enable(info->clk);
 888         dprintk("got and enabled clock\n");
 889
 890         msleep(1);
 891
 892         /* Initialize video memory */
 893         ret = s3c2410fb_map_video_memory(info);
 894         if (ret) {
 895                 printk(KERN_ERR "Failed to allocate video RAM: %d\n", ret);
 896                 ret = -ENOMEM;
 897                 goto release_clock;
 898         }
 899
 900         dprintk("got video memory\n");
 901
 902         s3c2410fb_init_registers(info);
 903
 904         s3c2410fb_check_var(&fbinfo->var, fbinfo);
 905
 906         ret = register_framebuffer(fbinfo);
 907         if (ret < 0) {
 908                 printk(KERN_ERR "Failed to register framebuffer device: %d\n",
 909                         ret);
 910                 goto free_video_memory;
 911         }
 912
 913         /* create device files */
 914         device_create_file(&pdev->dev, &dev_attr_debug);
 915
 916         printk(KERN_INFO "fb%d: %s frame buffer device\n",
 917                 fbinfo->node, fbinfo->fix.id);
 918
 919         return 0;
 920
 921 free_video_memory:
 922         s3c2410fb_unmap_video_memory(info);
 923 release_clock:
 924         clk_disable(info->clk);
 925         clk_put(info->clk);
 926 release_irq:
 927         free_irq(irq, info);
 928 release_regs:
 929         iounmap(info->io);
 930 release_mem:
 931         release_resource(info->mem);
 932         kfree(info->mem);
 933 dealloc_fb:
 934         framebuffer_release(fbinfo);
 935         return ret;
 936 }
 937
 938 /* s3c2410fb_stop_lcd
 939  *
 940  * shutdown the lcd controller
 941  */
 942 static void s3c2410fb_stop_lcd(struct s3c2410fb_info *fbi)
 943 {
 944         unsigned long flags;
 945
 946         local_irq_save(flags);
 947
 948         fbi->regs.lcdcon1 &= ~S3C2410_LCDCON1_ENVID;
 949         writel(fbi->regs.lcdcon1, fbi->io + S3C2410_LCDCON1);
 950
 951         local_irq_restore(flags);
 952 }
 953
 954 /*
 955  *  Cleanup
 956  */
 957 static int s3c2410fb_remove(struct platform_device *pdev)
 958 {
 959         struct fb_info *fbinfo = platform_get_drvdata(pdev);
 960         struct s3c2410fb_info *info = fbinfo->par;
 961         int irq;
 962
 963         s3c2410fb_stop_lcd(info);
 964         msleep(1);
 965
 966         s3c2410fb_unmap_video_memory(info);
 967
 968         if (info->clk) {
 969                 clk_disable(info->clk);
 970                 clk_put(info->clk);
 971                 info->clk = NULL;
 972         }
 973
 974         irq = platform_get_irq(pdev, 0);
 975         free_irq(irq, info);
 976
 977         release_resource(info->mem);
 978         kfree(info->mem);
 979         iounmap(info->io);
 980         unregister_framebuffer(fbinfo);
 981
 982         return 0;
 983 }
 984
 985 #ifdef CONFIG_PM
 986
 987 /* suspend and resume support for the lcd controller */
 988 static int s3c2410fb_suspend(struct platform_device *dev, pm_message_t state)
 989 {
 990         struct fb_info     *fbinfo = platform_get_drvdata(dev);
 991         struct s3c2410fb_info *info = fbinfo->par;
 992
 993         s3c2410fb_stop_lcd(info);
 994
 995         /* sleep before disabling the clock, we need to ensure
 996          * the LCD DMA engine is not going to get back on the bus
 997          * before the clock goes off again (bjd) */
 998
 999         msleep(1);
1000         clk_disable(info->clk);
1001
1002         return 0;
1003 }
1004
1005 static int s3c2410fb_resume(struct platform_device *dev)
1006 {
1007         struct fb_info     *fbinfo = platform_get_drvdata(dev);
1008         struct s3c2410fb_info *info = fbinfo->par;
1009
1010         clk_enable(info->clk);
1011         msleep(1);
1012
1013         s3c2410fb_init_registers(info);
1014
1015         return 0;
1016 }
1017
1018 #else
1019 #define s3c2410fb_suspend NULL
1020 #define s3c2410fb_resume  NULL
1021 #endif
1022
1023 static struct platform_driver s3c2410fb_driver = {
1024         .probe          = s3c2410fb_probe,
1025         .remove         = s3c2410fb_remove,
1026         .suspend        = s3c2410fb_suspend,
1027         .resume         = s3c2410fb_resume,
1028         .driver         = {
1029                 .name   = "s3c2410-lcd",
1030                 .owner  = THIS_MODULE,
1031         },
1032 };
1033
1034 int __devinit s3c2410fb_init(void)
1035 {
1036         return platform_driver_register(&s3c2410fb_driver);
1037 }
1038
1039 static void __exit s3c2410fb_cleanup(void)
1040 {
1041         platform_driver_unregister(&s3c2410fb_driver);
1042 }
1043
1044 module_init(s3c2410fb_init);
1045 module_exit(s3c2410fb_cleanup);
1046
1047 MODULE_AUTHOR("Arnaud Patard <arnaud.patard@rtp-net.org>, "
1048               "Ben Dooks <ben-linux@fluff.org>");
1049 MODULE_DESCRIPTION("Framebuffer driver for the s3c2410");
1050 MODULE_LICENSE("GPL");