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   1 /* linux/drivers/video/s3c2410fb.c
   2  *      Copyright (c) 2004,2005 Arnaud Patard
   3  *      Copyright (c) 2004-2008 Ben Dooks
   4  *
   5  * S3C2410 LCD Framebuffer Driver
   6  *
   7  * This file is subject to the terms and conditions of the GNU General Public
   8  * License.  See the file COPYING in the main directory of this archive for
   9  * more details.
  10  *
  11  * Driver based on skeletonfb.c, sa1100fb.c and others.
  12 */
  13
  14 #include <linux/module.h>
  15 #include <linux/kernel.h>
  16 #include <linux/errno.h>
  17 #include <linux/string.h>
  18 #include <linux/mm.h>
  19 #include <linux/slab.h>
  20 #include <linux/delay.h>
  21 #include <linux/fb.h>
  22 #include <linux/init.h>
  23 #include <linux/dma-mapping.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/clk.h>
  27 #include <linux/cpufreq.h>
  28
  29 #include <asm/io.h>
  30 #include <asm/div64.h>
  31
  32 #include <asm/mach/map.h>
  33 #include <mach/regs-lcd.h>
  34 #include <mach/regs-gpio.h>
  35 #include <mach/fb.h>
  36
  37 #ifdef CONFIG_PM
  38 #include <linux/pm.h>
  39 #endif
  40
  41 #include "s3c2410fb.h"
  42
  43 /* Debugging stuff */
  44 #ifdef CONFIG_FB_S3C2410_DEBUG
  45 static int debug        = 1;
  46 #else
  47 static int debug        = 0;
  48 #endif
  49
  50 #define dprintk(msg...) if (debug) { printk(KERN_DEBUG "s3c2410fb: " msg); }
  51
  52 /* useful functions */
  53
  54 static int is_s3c2412(struct s3c2410fb_info *fbi)
  55 {
  56         return (fbi->drv_type == DRV_S3C2412);
  57 }
  58
  59 /* s3c2410fb_set_lcdaddr
  60  *
  61  * initialise lcd controller address pointers
  62  */
  63 static void s3c2410fb_set_lcdaddr(struct fb_info *info)
  64 {
  65         unsigned long saddr1, saddr2, saddr3;
  66         struct s3c2410fb_info *fbi = info->par;
  67         void __iomem *regs = fbi->io;
  68
  69         saddr1  = info->fix.smem_start >> 1;
  70         saddr2  = info->fix.smem_start;
  71         saddr2 += info->fix.line_length * info->var.yres;
  72         saddr2 >>= 1;
  73
  74         saddr3 = S3C2410_OFFSIZE(0) |
  75                  S3C2410_PAGEWIDTH((info->fix.line_length / 2) & 0x3ff);
  76
  77         dprintk("LCDSADDR1 = 0x%08lx\n", saddr1);
  78         dprintk("LCDSADDR2 = 0x%08lx\n", saddr2);
  79         dprintk("LCDSADDR3 = 0x%08lx\n", saddr3);
  80
  81         writel(saddr1, regs + S3C2410_LCDSADDR1);
  82         writel(saddr2, regs + S3C2410_LCDSADDR2);
  83         writel(saddr3, regs + S3C2410_LCDSADDR3);
  84 }
  85
  86 /* s3c2410fb_calc_pixclk()
  87  *
  88  * calculate divisor for clk->pixclk
  89  */
  90 static unsigned int s3c2410fb_calc_pixclk(struct s3c2410fb_info *fbi,
  91                                           unsigned long pixclk)
  92 {
  93         unsigned long clk = fbi->clk_rate;
  94         unsigned long long div;
  95
  96         /* pixclk is in picoseconds, our clock is in Hz
  97          *
  98          * Hz -> picoseconds is / 10^-12
  99          */
 100
 101         div = (unsigned long long)clk * pixclk;
 102         div >>= 12;                     /* div / 2^12 */
 103         do_div(div, 625 * 625UL * 625); /* div / 5^12 */
 104
 105         dprintk("pixclk %ld, divisor is %ld\n", pixclk, (long)div);
 106         return div;
 107 }
 108
 109 /*
 110  *      s3c2410fb_check_var():
 111  *      Get the video params out of 'var'. If a value doesn't fit, round it up,
 112  *      if it's too big, return -EINVAL.
 113  *
 114  */
 115 static int s3c2410fb_check_var(struct fb_var_screeninfo *var,
 116                                struct fb_info *info)
 117 {
 118         struct s3c2410fb_info *fbi = info->par;
 119         struct s3c2410fb_mach_info *mach_info = fbi->dev->platform_data;
 120         struct s3c2410fb_display *display = NULL;
 121         struct s3c2410fb_display *default_display = mach_info->displays +
 122                                                     mach_info->default_display;
 123         int type = default_display->type;
 124         unsigned i;
 125
 126         dprintk("check_var(var=%p, info=%p)\n", var, info);
 127
 128         /* validate x/y resolution */
 129         /* choose default mode if possible */
 130         if (var->yres == default_display->yres &&
 131             var->xres == default_display->xres &&
 132             var->bits_per_pixel == default_display->bpp)
 133                 display = default_display;
 134         else
 135                 for (i = 0; i < mach_info->num_displays; i++)
 136                         if (type == mach_info->displays[i].type &&
 137                             var->yres == mach_info->displays[i].yres &&
 138                             var->xres == mach_info->displays[i].xres &&
 139                             var->bits_per_pixel == mach_info->displays[i].bpp) {
 140                                 display = mach_info->displays + i;
 141                                 break;
 142                         }
 143
 144         if (!display) {
 145                 dprintk("wrong resolution or depth %dx%d at %d bpp\n",
 146                         var->xres, var->yres, var->bits_per_pixel);
 147                 return -EINVAL;
 148         }
 149
 150         /* it is always the size as the display */
 151         var->xres_virtual = display->xres;
 152         var->yres_virtual = display->yres;
 153         var->height = display->height;
 154         var->width = display->width;
 155
 156         /* copy lcd settings */
 157         var->pixclock = display->pixclock;
 158         var->left_margin = display->left_margin;
 159         var->right_margin = display->right_margin;
 160         var->upper_margin = display->upper_margin;
 161         var->lower_margin = display->lower_margin;
 162         var->vsync_len = display->vsync_len;
 163         var->hsync_len = display->hsync_len;
 164
 165         fbi->regs.lcdcon5 = display->lcdcon5;
 166         /* set display type */
 167         fbi->regs.lcdcon1 = display->type;
 168
 169         var->transp.offset = 0;
 170         var->transp.length = 0;
 171         /* set r/g/b positions */
 172         switch (var->bits_per_pixel) {
 173         case 1:
 174         case 2:
 175         case 4:
 176                 var->red.offset = 0;
 177                 var->red.length = var->bits_per_pixel;
 178                 var->green      = var->red;
 179                 var->blue       = var->red;
 180                 break;
 181         case 8:
 182                 if (display->type != S3C2410_LCDCON1_TFT) {
 183                         /* 8 bpp 332 */
 184                         var->red.length         = 3;
 185                         var->red.offset         = 5;
 186                         var->green.length       = 3;
 187                         var->green.offset       = 2;
 188                         var->blue.length        = 2;
 189                         var->blue.offset        = 0;
 190                 } else {
 191                         var->red.offset         = 0;
 192                         var->red.length         = 8;
 193                         var->green              = var->red;
 194                         var->blue               = var->red;
 195                 }
 196                 break;
 197         case 12:
 198                 /* 12 bpp 444 */
 199                 var->red.length         = 4;
 200                 var->red.offset         = 8;
 201                 var->green.length       = 4;
 202                 var->green.offset       = 4;
 203                 var->blue.length        = 4;
 204                 var->blue.offset        = 0;
 205                 break;
 206
 207         default:
 208         case 16:
 209                 if (display->lcdcon5 & S3C2410_LCDCON5_FRM565) {
 210                         /* 16 bpp, 565 format */
 211                         var->red.offset         = 11;
 212                         var->green.offset       = 5;
 213                         var->blue.offset        = 0;
 214                         var->red.length         = 5;
 215                         var->green.length       = 6;
 216                         var->blue.length        = 5;
 217                 } else {
 218                         /* 16 bpp, 5551 format */
 219                         var->red.offset         = 11;
 220                         var->green.offset       = 6;
 221                         var->blue.offset        = 1;
 222                         var->red.length         = 5;
 223                         var->green.length       = 5;
 224                         var->blue.length        = 5;
 225                 }
 226                 break;
 227         case 32:
 228                 /* 24 bpp 888 and 8 dummy */
 229                 var->red.length         = 8;
 230                 var->red.offset         = 16;
 231                 var->green.length       = 8;
 232                 var->green.offset       = 8;
 233                 var->blue.length        = 8;
 234                 var->blue.offset        = 0;
 235                 break;
 236         }
 237         return 0;
 238 }
 239
 240 /* s3c2410fb_calculate_stn_lcd_regs
 241  *
 242  * calculate register values from var settings
 243  */
 244 static void s3c2410fb_calculate_stn_lcd_regs(const struct fb_info *info,
 245                                              struct s3c2410fb_hw *regs)
 246 {
 247         const struct s3c2410fb_info *fbi = info->par;
 248         const struct fb_var_screeninfo *var = &info->var;
 249         int type = regs->lcdcon1 & ~S3C2410_LCDCON1_TFT;
 250         int hs = var->xres >> 2;
 251         unsigned wdly = (var->left_margin >> 4) - 1;
 252         unsigned wlh = (var->hsync_len >> 4) - 1;
 253
 254         if (type != S3C2410_LCDCON1_STN4)
 255                 hs >>= 1;
 256
 257         switch (var->bits_per_pixel) {
 258         case 1:
 259                 regs->lcdcon1 |= S3C2410_LCDCON1_STN1BPP;
 260                 break;
 261         case 2:
 262                 regs->lcdcon1 |= S3C2410_LCDCON1_STN2GREY;
 263                 break;
 264         case 4:
 265                 regs->lcdcon1 |= S3C2410_LCDCON1_STN4GREY;
 266                 break;
 267         case 8:
 268                 regs->lcdcon1 |= S3C2410_LCDCON1_STN8BPP;
 269                 hs *= 3;
 270                 break;
 271         case 12:
 272                 regs->lcdcon1 |= S3C2410_LCDCON1_STN12BPP;
 273                 hs *= 3;
 274                 break;
 275
 276         default:
 277                 /* invalid pixel depth */
 278                 dev_err(fbi->dev, "invalid bpp %d\n",
 279                         var->bits_per_pixel);
 280         }
 281         /* update X/Y info */
 282         dprintk("setting horz: lft=%d, rt=%d, sync=%d\n",
 283                 var->left_margin, var->right_margin, var->hsync_len);
 284
 285         regs->lcdcon2 = S3C2410_LCDCON2_LINEVAL(var->yres - 1);
 286
 287         if (wdly > 3)
 288                 wdly = 3;
 289
 290         if (wlh > 3)
 291                 wlh = 3;
 292
 293         regs->lcdcon3 = S3C2410_LCDCON3_WDLY(wdly) |
 294                         S3C2410_LCDCON3_LINEBLANK(var->right_margin / 8) |
 295                         S3C2410_LCDCON3_HOZVAL(hs - 1);
 296
 297         regs->lcdcon4 = S3C2410_LCDCON4_WLH(wlh);
 298 }
 299
 300 /* s3c2410fb_calculate_tft_lcd_regs
 301  *
 302  * calculate register values from var settings
 303  */
 304 static void s3c2410fb_calculate_tft_lcd_regs(const struct fb_info *info,
 305                                              struct s3c2410fb_hw *regs)
 306 {
 307         const struct s3c2410fb_info *fbi = info->par;
 308         const struct fb_var_screeninfo *var = &info->var;
 309
 310         switch (var->bits_per_pixel) {
 311         case 1:
 312                 regs->lcdcon1 |= S3C2410_LCDCON1_TFT1BPP;
 313                 break;
 314         case 2:
 315                 regs->lcdcon1 |= S3C2410_LCDCON1_TFT2BPP;
 316                 break;
 317         case 4:
 318                 regs->lcdcon1 |= S3C2410_LCDCON1_TFT4BPP;
 319                 break;
 320         case 8:
 321                 regs->lcdcon1 |= S3C2410_LCDCON1_TFT8BPP;
 322                 regs->lcdcon5 |= S3C2410_LCDCON5_BSWP |
 323                                  S3C2410_LCDCON5_FRM565;
 324                 regs->lcdcon5 &= ~S3C2410_LCDCON5_HWSWP;
 325                 break;
 326         case 16:
 327                 regs->lcdcon1 |= S3C2410_LCDCON1_TFT16BPP;
 328                 regs->lcdcon5 &= ~S3C2410_LCDCON5_BSWP;
 329                 regs->lcdcon5 |= S3C2410_LCDCON5_HWSWP;
 330                 break;
 331         case 32:
 332                 regs->lcdcon1 |= S3C2410_LCDCON1_TFT24BPP;
 333                 regs->lcdcon5 &= ~(S3C2410_LCDCON5_BSWP |
 334                                    S3C2410_LCDCON5_HWSWP |
 335                                    S3C2410_LCDCON5_BPP24BL);
 336                 break;
 337         default:
 338                 /* invalid pixel depth */
 339                 dev_err(fbi->dev, "invalid bpp %d\n",
 340                         var->bits_per_pixel);
 341         }
 342         /* update X/Y info */
 343         dprintk("setting vert: up=%d, low=%d, sync=%d\n",
 344                 var->upper_margin, var->lower_margin, var->vsync_len);
 345
 346         dprintk("setting horz: lft=%d, rt=%d, sync=%d\n",
 347                 var->left_margin, var->right_margin, var->hsync_len);
 348
 349         regs->lcdcon2 = S3C2410_LCDCON2_LINEVAL(var->yres - 1) |
 350                         S3C2410_LCDCON2_VBPD(var->upper_margin - 1) |
 351                         S3C2410_LCDCON2_VFPD(var->lower_margin - 1) |
 352                         S3C2410_LCDCON2_VSPW(var->vsync_len - 1);
 353
 354         regs->lcdcon3 = S3C2410_LCDCON3_HBPD(var->right_margin - 1) |
 355                         S3C2410_LCDCON3_HFPD(var->left_margin - 1) |
 356                         S3C2410_LCDCON3_HOZVAL(var->xres - 1);
 357
 358         regs->lcdcon4 = S3C2410_LCDCON4_HSPW(var->hsync_len - 1);
 359 }
 360
 361 /* s3c2410fb_activate_var
 362  *
 363  * activate (set) the controller from the given framebuffer
 364  * information
 365  */
 366 static void s3c2410fb_activate_var(struct fb_info *info)
 367 {
 368         struct s3c2410fb_info *fbi = info->par;
 369         void __iomem *regs = fbi->io;
 370         int type = fbi->regs.lcdcon1 & S3C2410_LCDCON1_TFT;
 371         struct fb_var_screeninfo *var = &info->var;
 372         int clkdiv = s3c2410fb_calc_pixclk(fbi, var->pixclock) / 2;
 373
 374         dprintk("%s: var->xres  = %d\n", __func__, var->xres);
 375         dprintk("%s: var->yres  = %d\n", __func__, var->yres);
 376         dprintk("%s: var->bpp   = %d\n", __func__, var->bits_per_pixel);
 377
 378         if (type == S3C2410_LCDCON1_TFT) {
 379                 s3c2410fb_calculate_tft_lcd_regs(info, &fbi->regs);
 380                 --clkdiv;
 381                 if (clkdiv < 0)
 382                         clkdiv = 0;
 383         } else {
 384                 s3c2410fb_calculate_stn_lcd_regs(info, &fbi->regs);
 385                 if (clkdiv < 2)
 386                         clkdiv = 2;
 387         }
 388
 389         fbi->regs.lcdcon1 |=  S3C2410_LCDCON1_CLKVAL(clkdiv);
 390
 391         /* write new registers */
 392
 393         dprintk("new register set:\n");
 394         dprintk("lcdcon[1] = 0x%08lx\n", fbi->regs.lcdcon1);
 395         dprintk("lcdcon[2] = 0x%08lx\n", fbi->regs.lcdcon2);
 396         dprintk("lcdcon[3] = 0x%08lx\n", fbi->regs.lcdcon3);
 397         dprintk("lcdcon[4] = 0x%08lx\n", fbi->regs.lcdcon4);
 398         dprintk("lcdcon[5] = 0x%08lx\n", fbi->regs.lcdcon5);
 399
 400         writel(fbi->regs.lcdcon1 & ~S3C2410_LCDCON1_ENVID,
 401                 regs + S3C2410_LCDCON1);
 402         writel(fbi->regs.lcdcon2, regs + S3C2410_LCDCON2);
 403         writel(fbi->regs.lcdcon3, regs + S3C2410_LCDCON3);
 404         writel(fbi->regs.lcdcon4, regs + S3C2410_LCDCON4);
 405         writel(fbi->regs.lcdcon5, regs + S3C2410_LCDCON5);
 406
 407         /* set lcd address pointers */
 408         s3c2410fb_set_lcdaddr(info);
 409
 410         fbi->regs.lcdcon1 |= S3C2410_LCDCON1_ENVID,
 411         writel(fbi->regs.lcdcon1, regs + S3C2410_LCDCON1);
 412 }
 413
 414 /*
 415  *      s3c2410fb_set_par - Alters the hardware state.
 416  *      @info: frame buffer structure that represents a single frame buffer
 417  *
 418  */
 419 static int s3c2410fb_set_par(struct fb_info *info)
 420 {
 421         struct fb_var_screeninfo *var = &info->var;
 422
 423         switch (var->bits_per_pixel) {
 424         case 32:
 425         case 16:
 426         case 12:
 427                 info->fix.visual = FB_VISUAL_TRUECOLOR;
 428                 break;
 429         case 1:
 430                 info->fix.visual = FB_VISUAL_MONO01;
 431                 break;
 432         default:
 433                 info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
 434                 break;
 435         }
 436
 437         info->fix.line_length = (var->xres_virtual * var->bits_per_pixel) / 8;
 438
 439         /* activate this new configuration */
 440
 441         s3c2410fb_activate_var(info);
 442         return 0;
 443 }
 444
 445 static void schedule_palette_update(struct s3c2410fb_info *fbi,
 446                                     unsigned int regno, unsigned int val)
 447 {
 448         unsigned long flags;
 449         unsigned long irqen;
 450         void __iomem *irq_base = fbi->irq_base;
 451
 452         local_irq_save(flags);
 453
 454         fbi->palette_buffer[regno] = val;
 455
 456         if (!fbi->palette_ready) {
 457                 fbi->palette_ready = 1;
 458
 459                 /* enable IRQ */
 460                 irqen = readl(irq_base + S3C24XX_LCDINTMSK);
 461                 irqen &= ~S3C2410_LCDINT_FRSYNC;
 462                 writel(irqen, irq_base + S3C24XX_LCDINTMSK);
 463         }
 464
 465         local_irq_restore(flags);
 466 }
 467
 468 /* from pxafb.c */
 469 static inline unsigned int chan_to_field(unsigned int chan,
 470                                          struct fb_bitfield *bf)
 471 {
 472         chan &= 0xffff;
 473         chan >>= 16 - bf->length;
 474         return chan << bf->offset;
 475 }
 476
 477 static int s3c2410fb_setcolreg(unsigned regno,
 478                                unsigned red, unsigned green, unsigned blue,
 479                                unsigned transp, struct fb_info *info)
 480 {
 481         struct s3c2410fb_info *fbi = info->par;
 482         void __iomem *regs = fbi->io;
 483         unsigned int val;
 484
 485         /* dprintk("setcol: regno=%d, rgb=%d,%d,%d\n",
 486                    regno, red, green, blue); */
 487
 488         switch (info->fix.visual) {
 489         case FB_VISUAL_TRUECOLOR:
 490                 /* true-colour, use pseudo-palette */
 491
 492                 if (regno < 16) {
 493                         u32 *pal = info->pseudo_palette;
 494
 495                         val  = chan_to_field(red,   &info->var.red);
 496                         val |= chan_to_field(green, &info->var.green);
 497                         val |= chan_to_field(blue,  &info->var.blue);
 498
 499                         pal[regno] = val;
 500                 }
 501                 break;
 502
 503         case FB_VISUAL_PSEUDOCOLOR:
 504                 if (regno < 256) {
 505                         /* currently assume RGB 5-6-5 mode */
 506
 507                         val  = (red   >>  0) & 0xf800;
 508                         val |= (green >>  5) & 0x07e0;
 509                         val |= (blue  >> 11) & 0x001f;
 510
 511                         writel(val, regs + S3C2410_TFTPAL(regno));
 512                         schedule_palette_update(fbi, regno, val);
 513                 }
 514
 515                 break;
 516
 517         default:
 518                 return 1;       /* unknown type */
 519         }
 520
 521         return 0;
 522 }
 523
 524 /* s3c2410fb_lcd_enable
 525  *
 526  * shutdown the lcd controller
 527  */
 528 static void s3c2410fb_lcd_enable(struct s3c2410fb_info *fbi, int enable)
 529 {
 530         unsigned long flags;
 531
 532         local_irq_save(flags);
 533
 534         if (enable)
 535                 fbi->regs.lcdcon1 |= S3C2410_LCDCON1_ENVID;
 536         else
 537                 fbi->regs.lcdcon1 &= ~S3C2410_LCDCON1_ENVID;
 538
 539         writel(fbi->regs.lcdcon1, fbi->io + S3C2410_LCDCON1);
 540
 541         local_irq_restore(flags);
 542 }
 543
 544
 545 /*
 546  *      s3c2410fb_blank
 547  *      @blank_mode: the blank mode we want.
 548  *      @info: frame buffer structure that represents a single frame buffer
 549  *
 550  *      Blank the screen if blank_mode != 0, else unblank. Return 0 if
 551  *      blanking succeeded, != 0 if un-/blanking failed due to e.g. a
 552  *      video mode which doesn't support it. Implements VESA suspend
 553  *      and powerdown modes on hardware that supports disabling hsync/vsync:
 554  *
 555  *      Returns negative errno on error, or zero on success.
 556  *
 557  */
 558 static int s3c2410fb_blank(int blank_mode, struct fb_info *info)
 559 {
 560         struct s3c2410fb_info *fbi = info->par;
 561         void __iomem *tpal_reg = fbi->io;
 562
 563         dprintk("blank(mode=%d, info=%p)\n", blank_mode, info);
 564
 565         tpal_reg += is_s3c2412(fbi) ? S3C2412_TPAL : S3C2410_TPAL;
 566
 567         if (blank_mode == FB_BLANK_POWERDOWN) {
 568                 s3c2410fb_lcd_enable(fbi, 0);
 569         } else {
 570                 s3c2410fb_lcd_enable(fbi, 1);
 571         }
 572
 573         if (blank_mode == FB_BLANK_UNBLANK)
 574                 writel(0x0, tpal_reg);
 575         else {
 576                 dprintk("setting TPAL to output 0x000000\n");
 577                 writel(S3C2410_TPAL_EN, tpal_reg);
 578         }
 579
 580         return 0;
 581 }
 582
 583 static int s3c2410fb_debug_show(struct device *dev,
 584                                 struct device_attribute *attr, char *buf)
 585 {
 586         return snprintf(buf, PAGE_SIZE, "%s\n", debug ? "on" : "off");
 587 }
 588
 589 static int s3c2410fb_debug_store(struct device *dev,
 590                                  struct device_attribute *attr,
 591                                  const char *buf, size_t len)
 592 {
 593         if (len < 1)
 594                 return -EINVAL;
 595
 596         if (strnicmp(buf, "on", 2) == 0 ||
 597             strnicmp(buf, "1", 1) == 0) {
 598                 debug = 1;
 599                 printk(KERN_DEBUG "s3c2410fb: Debug On");
 600         } else if (strnicmp(buf, "off", 3) == 0 ||
 601                    strnicmp(buf, "0", 1) == 0) {
 602                 debug = 0;
 603                 printk(KERN_DEBUG "s3c2410fb: Debug Off");
 604         } else {
 605                 return -EINVAL;
 606         }
 607
 608         return len;
 609 }
 610
 611 static DEVICE_ATTR(debug, 0666, s3c2410fb_debug_show, s3c2410fb_debug_store);
 612
 613 static struct fb_ops s3c2410fb_ops = {
 614         .owner          = THIS_MODULE,
 615         .fb_check_var   = s3c2410fb_check_var,
 616         .fb_set_par     = s3c2410fb_set_par,
 617         .fb_blank       = s3c2410fb_blank,
 618         .fb_setcolreg   = s3c2410fb_setcolreg,
 619         .fb_fillrect    = cfb_fillrect,
 620         .fb_copyarea    = cfb_copyarea,
 621         .fb_imageblit   = cfb_imageblit,
 622 };
 623
 624 /*
 625  * s3c2410fb_map_video_memory():
 626  *      Allocates the DRAM memory for the frame buffer.  This buffer is
 627  *      remapped into a non-cached, non-buffered, memory region to
 628  *      allow palette and pixel writes to occur without flushing the
 629  *      cache.  Once this area is remapped, all virtual memory
 630  *      access to the video memory should occur at the new region.
 631  */
 632 static int __init s3c2410fb_map_video_memory(struct fb_info *info)
 633 {
 634         struct s3c2410fb_info *fbi = info->par;
 635         dma_addr_t map_dma;
 636         unsigned map_size = PAGE_ALIGN(info->fix.smem_len);
 637
 638         dprintk("map_video_memory(fbi=%p) map_size %u\n", fbi, map_size);
 639
 640         info->screen_base = dma_alloc_writecombine(fbi->dev, map_size,
 641                                                    &map_dma, GFP_KERNEL);
 642
 643         if (info->screen_base) {
 644                 /* prevent initial garbage on screen */
 645                 dprintk("map_video_memory: clear %p:%08x\n",
 646                         info->screen_base, map_size);
 647                 memset(info->screen_base, 0x00, map_size);
 648
 649                 info->fix.smem_start = map_dma;
 650
 651                 dprintk("map_video_memory: dma=%08lx cpu=%p size=%08x\n",
 652                         info->fix.smem_start, info->screen_base, map_size);
 653         }
 654
 655         return info->screen_base ? 0 : -ENOMEM;
 656 }
 657
 658 static inline void s3c2410fb_unmap_video_memory(struct fb_info *info)
 659 {
 660         struct s3c2410fb_info *fbi = info->par;
 661
 662         dma_free_writecombine(fbi->dev, PAGE_ALIGN(info->fix.smem_len),
 663                               info->screen_base, info->fix.smem_start);
 664 }
 665
 666 static inline void modify_gpio(void __iomem *reg,
 667                                unsigned long set, unsigned long mask)
 668 {
 669         unsigned long tmp;
 670
 671         tmp = readl(reg) & ~mask;
 672         writel(tmp | set, reg);
 673 }
 674
 675 /*
 676  * s3c2410fb_init_registers - Initialise all LCD-related registers
 677  */
 678 static int s3c2410fb_init_registers(struct fb_info *info)
 679 {
 680         struct s3c2410fb_info *fbi = info->par;
 681         struct s3c2410fb_mach_info *mach_info = fbi->dev->platform_data;
 682         unsigned long flags;
 683         void __iomem *regs = fbi->io;
 684         void __iomem *tpal;
 685         void __iomem *lpcsel;
 686
 687         if (is_s3c2412(fbi)) {
 688                 tpal = regs + S3C2412_TPAL;
 689                 lpcsel = regs + S3C2412_TCONSEL;
 690         } else {
 691                 tpal = regs + S3C2410_TPAL;
 692                 lpcsel = regs + S3C2410_LPCSEL;
 693         }
 694
 695         /* Initialise LCD with values from haret */
 696
 697         local_irq_save(flags);
 698
 699         /* modify the gpio(s) with interrupts set (bjd) */
 700
 701         modify_gpio(S3C2410_GPCUP,  mach_info->gpcup,  mach_info->gpcup_mask);
 702         modify_gpio(S3C2410_GPCCON, mach_info->gpccon, mach_info->gpccon_mask);
 703         modify_gpio(S3C2410_GPDUP,  mach_info->gpdup,  mach_info->gpdup_mask);
 704         modify_gpio(S3C2410_GPDCON, mach_info->gpdcon, mach_info->gpdcon_mask);
 705
 706         local_irq_restore(flags);
 707
 708         dprintk("LPCSEL    = 0x%08lx\n", mach_info->lpcsel);
 709         writel(mach_info->lpcsel, lpcsel);
 710
 711         dprintk("replacing TPAL %08x\n", readl(tpal));
 712
 713         /* ensure temporary palette disabled */
 714         writel(0x00, tpal);
 715
 716         return 0;
 717 }
 718
 719 static void s3c2410fb_write_palette(struct s3c2410fb_info *fbi)
 720 {
 721         unsigned int i;
 722         void __iomem *regs = fbi->io;
 723
 724         fbi->palette_ready = 0;
 725
 726         for (i = 0; i < 256; i++) {
 727                 unsigned long ent = fbi->palette_buffer[i];
 728                 if (ent == PALETTE_BUFF_CLEAR)
 729                         continue;
 730
 731                 writel(ent, regs + S3C2410_TFTPAL(i));
 732
 733                 /* it seems the only way to know exactly
 734                  * if the palette wrote ok, is to check
 735                  * to see if the value verifies ok
 736                  */
 737
 738                 if (readw(regs + S3C2410_TFTPAL(i)) == ent)
 739                         fbi->palette_buffer[i] = PALETTE_BUFF_CLEAR;
 740                 else
 741                         fbi->palette_ready = 1;   /* retry */
 742         }
 743 }
 744
 745 static irqreturn_t s3c2410fb_irq(int irq, void *dev_id)
 746 {
 747         struct s3c2410fb_info *fbi = dev_id;
 748         void __iomem *irq_base = fbi->irq_base;
 749         unsigned long lcdirq = readl(irq_base + S3C24XX_LCDINTPND);
 750
 751         if (lcdirq & S3C2410_LCDINT_FRSYNC) {
 752                 if (fbi->palette_ready)
 753                         s3c2410fb_write_palette(fbi);
 754
 755                 writel(S3C2410_LCDINT_FRSYNC, irq_base + S3C24XX_LCDINTPND);
 756                 writel(S3C2410_LCDINT_FRSYNC, irq_base + S3C24XX_LCDSRCPND);
 757         }
 758
 759         return IRQ_HANDLED;
 760 }
 761
 762 #ifdef CONFIG_CPU_FREQ
 763
 764 static int s3c2410fb_cpufreq_transition(struct notifier_block *nb,
 765                                         unsigned long val, void *data)
 766 {
 767         struct cpufreq_freqs *freqs = data;
 768         struct s3c2410fb_info *info;
 769         struct fb_info *fbinfo;
 770         long delta_f;
 771
 772         info = container_of(nb, struct s3c2410fb_info, freq_transition);
 773         fbinfo = platform_get_drvdata(to_platform_device(info->dev));
 774
 775         /* work out change, <0 for speed-up */
 776         delta_f = info->clk_rate - clk_get_rate(info->clk);
 777
 778         if ((val == CPUFREQ_POSTCHANGE && delta_f > 0) ||
 779             (val == CPUFREQ_PRECHANGE && delta_f < 0)) {
 780                 info->clk_rate = clk_get_rate(info->clk);
 781                 s3c2410fb_activate_var(fbinfo);
 782         }
 783
 784         return 0;
 785 }
 786
 787 static inline int s3c2410fb_cpufreq_register(struct s3c2410fb_info *info)
 788 {
 789         info->freq_transition.notifier_call = s3c2410fb_cpufreq_transition;
 790
 791         return cpufreq_register_notifier(&info->freq_transition,
 792                                          CPUFREQ_TRANSITION_NOTIFIER);
 793 }
 794
 795 static inline void s3c2410fb_cpufreq_deregister(struct s3c2410fb_info *info)
 796 {
 797         cpufreq_unregister_notifier(&info->freq_transition,
 798                                     CPUFREQ_TRANSITION_NOTIFIER);
 799 }
 800
 801 #else
 802 static inline int s3c2410fb_cpufreq_register(struct s3c2410fb_info *info)
 803 {
 804         return 0;
 805 }
 806
 807 static inline void s3c2410fb_cpufreq_deregister(struct s3c2410fb_info *info)
 808 {
 809 }
 810 #endif
 811
 812
 813 static char driver_name[] = "s3c2410fb";
 814
 815 static int __init s3c24xxfb_probe(struct platform_device *pdev,
 816                                   enum s3c_drv_type drv_type)
 817 {
 818         struct s3c2410fb_info *info;
 819         struct s3c2410fb_display *display;
 820         struct fb_info *fbinfo;
 821         struct s3c2410fb_mach_info *mach_info;
 822         struct resource *res;
 823         int ret;
 824         int irq;
 825         int i;
 826         int size;
 827         u32 lcdcon1;
 828
 829         mach_info = pdev->dev.platform_data;
 830         if (mach_info == NULL) {
 831                 dev_err(&pdev->dev,
 832                         "no platform data for lcd, cannot attach\n");
 833                 return -EINVAL;
 834         }
 835
 836         if (mach_info->default_display >= mach_info->num_displays) {
 837                 dev_err(&pdev->dev, "default is %d but only %d displays\n",
 838                         mach_info->default_display, mach_info->num_displays);
 839                 return -EINVAL;
 840         }
 841
 842         display = mach_info->displays + mach_info->default_display;
 843
 844         irq = platform_get_irq(pdev, 0);
 845         if (irq < 0) {
 846                 dev_err(&pdev->dev, "no irq for device\n");
 847                 return -ENOENT;
 848         }
 849
 850         fbinfo = framebuffer_alloc(sizeof(struct s3c2410fb_info), &pdev->dev);
 851         if (!fbinfo)
 852                 return -ENOMEM;
 853
 854         platform_set_drvdata(pdev, fbinfo);
 855
 856         info = fbinfo->par;
 857         info->dev = &pdev->dev;
 858         info->drv_type = drv_type;
 859
 860         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 861         if (res == NULL) {
 862                 dev_err(&pdev->dev, "failed to get memory registers\n");
 863                 ret = -ENXIO;
 864                 goto dealloc_fb;
 865         }
 866
 867         size = (res->end - res->start) + 1;
 868         info->mem = request_mem_region(res->start, size, pdev->name);
 869         if (info->mem == NULL) {
 870                 dev_err(&pdev->dev, "failed to get memory region\n");
 871                 ret = -ENOENT;
 872                 goto dealloc_fb;
 873         }
 874
 875         info->io = ioremap(res->start, size);
 876         if (info->io == NULL) {
 877                 dev_err(&pdev->dev, "ioremap() of registers failed\n");
 878                 ret = -ENXIO;
 879                 goto release_mem;
 880         }
 881
 882         info->irq_base = info->io + ((drv_type == DRV_S3C2412) ? S3C2412_LCDINTBASE : S3C2410_LCDINTBASE);
 883
 884         dprintk("devinit\n");
 885
 886         strcpy(fbinfo->fix.id, driver_name);
 887
 888         /* Stop the video */
 889         lcdcon1 = readl(info->io + S3C2410_LCDCON1);
 890         writel(lcdcon1 & ~S3C2410_LCDCON1_ENVID, info->io + S3C2410_LCDCON1);
 891
 892         fbinfo->fix.type            = FB_TYPE_PACKED_PIXELS;
 893         fbinfo->fix.type_aux        = 0;
 894         fbinfo->fix.xpanstep        = 0;
 895         fbinfo->fix.ypanstep        = 0;
 896         fbinfo->fix.ywrapstep       = 0;
 897         fbinfo->fix.accel           = FB_ACCEL_NONE;
 898
 899         fbinfo->var.nonstd          = 0;
 900         fbinfo->var.activate        = FB_ACTIVATE_NOW;
 901         fbinfo->var.accel_flags     = 0;
 902         fbinfo->var.vmode           = FB_VMODE_NONINTERLACED;
 903
 904         fbinfo->fbops               = &s3c2410fb_ops;
 905         fbinfo->flags               = FBINFO_FLAG_DEFAULT;
 906         fbinfo->pseudo_palette      = &info->pseudo_pal;
 907
 908         for (i = 0; i < 256; i++)
 909                 info->palette_buffer[i] = PALETTE_BUFF_CLEAR;
 910
 911         ret = request_irq(irq, s3c2410fb_irq, IRQF_DISABLED, pdev->name, info);
 912         if (ret) {
 913                 dev_err(&pdev->dev, "cannot get irq %d - err %d\n", irq, ret);
 914                 ret = -EBUSY;
 915                 goto release_regs;
 916         }
 917
 918         info->clk = clk_get(NULL, "lcd");
 919         if (!info->clk || IS_ERR(info->clk)) {
 920                 printk(KERN_ERR "failed to get lcd clock source\n");
 921                 ret = -ENOENT;
 922                 goto release_irq;
 923         }
 924
 925         clk_enable(info->clk);
 926         dprintk("got and enabled clock\n");
 927
 928         msleep(1);
 929
 930         info->clk_rate = clk_get_rate(info->clk);
 931
 932         /* find maximum required memory size for display */
 933         for (i = 0; i < mach_info->num_displays; i++) {
 934                 unsigned long smem_len = mach_info->displays[i].xres;
 935
 936                 smem_len *= mach_info->displays[i].yres;
 937                 smem_len *= mach_info->displays[i].bpp;
 938                 smem_len >>= 3;
 939                 if (fbinfo->fix.smem_len < smem_len)
 940                         fbinfo->fix.smem_len = smem_len;
 941         }
 942
 943         /* Initialize video memory */
 944         ret = s3c2410fb_map_video_memory(fbinfo);
 945         if (ret) {
 946                 printk(KERN_ERR "Failed to allocate video RAM: %d\n", ret);
 947                 ret = -ENOMEM;
 948                 goto release_clock;
 949         }
 950
 951         dprintk("got video memory\n");
 952
 953         fbinfo->var.xres = display->xres;
 954         fbinfo->var.yres = display->yres;
 955         fbinfo->var.bits_per_pixel = display->bpp;
 956
 957         s3c2410fb_init_registers(fbinfo);
 958
 959         s3c2410fb_check_var(&fbinfo->var, fbinfo);
 960
 961         ret = s3c2410fb_cpufreq_register(info);
 962         if (ret < 0) {
 963                 dev_err(&pdev->dev, "Failed to register cpufreq\n");
 964                 goto free_video_memory;
 965         }
 966
 967         ret = register_framebuffer(fbinfo);
 968         if (ret < 0) {
 969                 printk(KERN_ERR "Failed to register framebuffer device: %d\n",
 970                         ret);
 971                 goto free_cpufreq;
 972         }
 973
 974         /* create device files */
 975         ret = device_create_file(&pdev->dev, &dev_attr_debug);
 976         if (ret) {
 977                 printk(KERN_ERR "failed to add debug attribute\n");
 978         }
 979
 980         printk(KERN_INFO "fb%d: %s frame buffer device\n",
 981                 fbinfo->node, fbinfo->fix.id);
 982
 983         return 0;
 984
 985  free_cpufreq:
 986         s3c2410fb_cpufreq_deregister(info);
 987 free_video_memory:
 988         s3c2410fb_unmap_video_memory(fbinfo);
 989 release_clock:
 990         clk_disable(info->clk);
 991         clk_put(info->clk);
 992 release_irq:
 993         free_irq(irq, info);
 994 release_regs:
 995         iounmap(info->io);
 996 release_mem:
 997         release_resource(info->mem);
 998         kfree(info->mem);
 999 dealloc_fb:
1000         platform_set_drvdata(pdev, NULL);
1001         framebuffer_release(fbinfo);
1002         return ret;
1003 }
1004
1005 static int __init s3c2410fb_probe(struct platform_device *pdev)
1006 {
1007         return s3c24xxfb_probe(pdev, DRV_S3C2410);
1008 }
1009
1010 static int __init s3c2412fb_probe(struct platform_device *pdev)
1011 {
1012         return s3c24xxfb_probe(pdev, DRV_S3C2412);
1013 }
1014
1015
1016 /*
1017  *  Cleanup
1018  */
1019 static int s3c2410fb_remove(struct platform_device *pdev)
1020 {
1021         struct fb_info *fbinfo = platform_get_drvdata(pdev);
1022         struct s3c2410fb_info *info = fbinfo->par;
1023         int irq;
1024
1025         unregister_framebuffer(fbinfo);
1026         s3c2410fb_cpufreq_deregister(info);
1027
1028         s3c2410fb_lcd_enable(info, 0);
1029         msleep(1);
1030
1031         s3c2410fb_unmap_video_memory(fbinfo);
1032
1033         if (info->clk) {
1034                 clk_disable(info->clk);
1035                 clk_put(info->clk);
1036                 info->clk = NULL;
1037         }
1038
1039         irq = platform_get_irq(pdev, 0);
1040         free_irq(irq, info);
1041
1042         iounmap(info->io);
1043
1044         release_resource(info->mem);
1045         kfree(info->mem);
1046
1047         platform_set_drvdata(pdev, NULL);
1048         framebuffer_release(fbinfo);
1049
1050         return 0;
1051 }
1052
1053 #ifdef CONFIG_PM
1054
1055 /* suspend and resume support for the lcd controller */
1056 static int s3c2410fb_suspend(struct platform_device *dev, pm_message_t state)
1057 {
1058         struct fb_info     *fbinfo = platform_get_drvdata(dev);
1059         struct s3c2410fb_info *info = fbinfo->par;
1060
1061         s3c2410fb_lcd_enable(info, 0);
1062
1063         /* sleep before disabling the clock, we need to ensure
1064          * the LCD DMA engine is not going to get back on the bus
1065          * before the clock goes off again (bjd) */
1066
1067         msleep(1);
1068         clk_disable(info->clk);
1069
1070         return 0;
1071 }
1072
1073 static int s3c2410fb_resume(struct platform_device *dev)
1074 {
1075         struct fb_info     *fbinfo = platform_get_drvdata(dev);
1076         struct s3c2410fb_info *info = fbinfo->par;
1077
1078         clk_enable(info->clk);
1079         msleep(1);
1080
1081         s3c2410fb_init_registers(fbinfo);
1082
1083         /* re-activate our display after resume */
1084         s3c2410fb_activate_var(fbinfo);
1085         s3c2410fb_blank(FB_BLANK_UNBLANK, fbinfo);
1086
1087         return 0;
1088 }
1089
1090 #else
1091 #define s3c2410fb_suspend NULL
1092 #define s3c2410fb_resume  NULL
1093 #endif
1094
1095 static struct platform_driver s3c2410fb_driver = {
1096         .probe          = s3c2410fb_probe,
1097         .remove         = s3c2410fb_remove,
1098         .suspend        = s3c2410fb_suspend,
1099         .resume         = s3c2410fb_resume,
1100         .driver         = {
1101                 .name   = "s3c2410-lcd",
1102                 .owner  = THIS_MODULE,
1103         },
1104 };
1105
1106 static struct platform_driver s3c2412fb_driver = {
1107         .probe          = s3c2412fb_probe,
1108         .remove         = s3c2410fb_remove,
1109         .suspend        = s3c2410fb_suspend,
1110         .resume         = s3c2410fb_resume,
1111         .driver         = {
1112                 .name   = "s3c2412-lcd",
1113                 .owner  = THIS_MODULE,
1114         },
1115 };
1116
1117 int __init s3c2410fb_init(void)
1118 {
1119         int ret = platform_driver_register(&s3c2410fb_driver);
1120
1121         if (ret == 0)
1122                 ret = platform_driver_register(&s3c2412fb_driver);
1123
1124         return ret;
1125 }
1126
1127 static void __exit s3c2410fb_cleanup(void)
1128 {
1129         platform_driver_unregister(&s3c2410fb_driver);
1130         platform_driver_unregister(&s3c2412fb_driver);
1131 }
1132
1133 module_init(s3c2410fb_init);
1134 module_exit(s3c2410fb_cleanup);
1135
1136 MODULE_AUTHOR("Arnaud Patard <arnaud.patard@rtp-net.org>, "
1137               "Ben Dooks <ben-linux@fluff.org>");
1138 MODULE_DESCRIPTION("Framebuffer driver for the s3c2410");
1139 MODULE_LICENSE("GPL");
1140 MODULE_ALIAS("platform:s3c2410-lcd");
1141 MODULE_ALIAS("platform:s3c2412-lcd");