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   1 /*
   2  * linux/drivers/video/s3c2410fb.c
   3  *      Copyright (c) Arnaud Patard, Ben Dooks
   4  *
   5  * This file is subject to the terms and conditions of the GNU General Public
   6  * License.  See the file COPYING in the main directory of this archive for
   7  * more details.
   8  *
   9  *          S3C2410 LCD Controller Frame Buffer Driver
  10  *          based on skeletonfb.c, sa1100fb.c and others
  11  *
  12  * ChangeLog
  13  * 2005-04-07: Arnaud Patard <arnaud.patard@rtp-net.org>
  14  *      - u32 state -> pm_message_t state
  15  *      - S3C2410_{VA,SZ}_LCD -> S3C24XX
  16  *
  17  * 2005-03-15: Arnaud Patard <arnaud.patard@rtp-net.org>
  18  *      - Removed the ioctl
  19  *      - use readl/writel instead of __raw_writel/__raw_readl
  20  *
  21  * 2004-12-04: Arnaud Patard <arnaud.patard@rtp-net.org>
  22  *      - Added the possibility to set on or off the
  23  *      debugging mesaages
  24  *      - Replaced 0 and 1 by on or off when reading the
  25  *      /sys files
  26  *
  27  * 2005-03-23: Ben Dooks <ben-linux@fluff.org>
  28  *      - added non 16bpp modes
  29  *      - updated platform information for range of x/y/bpp
  30  *      - add code to ensure palette is written correctly
  31  *      - add pixel clock divisor control
  32  *
  33  * 2004-11-11: Arnaud Patard <arnaud.patard@rtp-net.org>
  34  *      - Removed the use of currcon as it no more exist
  35  *      - Added LCD power sysfs interface
  36  *
  37  * 2004-11-03: Ben Dooks <ben-linux@fluff.org>
  38  *      - minor cleanups
  39  *      - add suspend/resume support
  40  *      - s3c2410fb_setcolreg() not valid in >8bpp modes
  41  *      - removed last CONFIG_FB_S3C2410_FIXED
  42  *      - ensure lcd controller stopped before cleanup
  43  *      - added sysfs interface for backlight power
  44  *      - added mask for gpio configuration
  45  *      - ensured IRQs disabled during GPIO configuration
  46  *      - disable TPAL before enabling video
  47  *
  48  * 2004-09-20: Arnaud Patard <arnaud.patard@rtp-net.org>
  49  *      - Suppress command line options
  50  *
  51  * 2004-09-15: Arnaud Patard <arnaud.patard@rtp-net.org>
  52  *      - code cleanup
  53  *
  54  * 2004-09-07: Arnaud Patard <arnaud.patard@rtp-net.org>
  55  *      - Renamed from h1940fb.c to s3c2410fb.c
  56  *      - Add support for different devices
  57  *      - Backlight support
  58  *
  59  * 2004-09-05: Herbert Pötzl <herbert@13thfloor.at>
  60  *      - added clock (de-)allocation code
  61  *      - added fixem fbmem option
  62  *
  63  * 2004-07-27: Arnaud Patard <arnaud.patard@rtp-net.org>
  64  *      - code cleanup
  65  *      - added a forgotten return in h1940fb_init
  66  *
  67  * 2004-07-19: Herbert Pötzl <herbert@13thfloor.at>
  68  *      - code cleanup and extended debugging
  69  *
  70  * 2004-07-15: Arnaud Patard <arnaud.patard@rtp-net.org>
  71  *      - First version
  72  */
  73
  74 #include <linux/module.h>
  75 #include <linux/kernel.h>
  76 #include <linux/errno.h>
  77 #include <linux/string.h>
  78 #include <linux/mm.h>
  79 #include <linux/slab.h>
  80 #include <linux/delay.h>
  81 #include <linux/fb.h>
  82 #include <linux/init.h>
  83 #include <linux/dma-mapping.h>
  84 #include <linux/interrupt.h>
  85 #include <linux/workqueue.h>
  86 #include <linux/wait.h>
  87 #include <linux/platform_device.h>
  88 #include <linux/clk.h>
  89
  90 #include <asm/io.h>
  91 #include <asm/uaccess.h>
  92 #include <asm/div64.h>
  93
  94 #include <asm/mach/map.h>
  95 #include <asm/arch/regs-lcd.h>
  96 #include <asm/arch/regs-gpio.h>
  97 #include <asm/arch/fb.h>
  98
  99 #ifdef CONFIG_PM
 100 #include <linux/pm.h>
 101 #endif
 102
 103 #include "s3c2410fb.h"
 104
 105 static struct s3c2410fb_mach_info *mach_info;
 106
 107 /* Debugging stuff */
 108 #ifdef CONFIG_FB_S3C2410_DEBUG
 109 static int debug        = 1;
 110 #else
 111 static int debug        = 0;
 112 #endif
 113
 114 #define dprintk(msg...) if (debug) { printk(KERN_DEBUG "s3c2410fb: " msg); }
 115
 116 /* useful functions */
 117
 118 /* s3c2410fb_set_lcdaddr
 119  *
 120  * initialise lcd controller address pointers
 121  */
 122 static void s3c2410fb_set_lcdaddr(struct fb_info *info)
 123 {
 124         unsigned long saddr1, saddr2, saddr3;
 125         int line_length = info->var.xres * info->var.bits_per_pixel;
 126         struct s3c2410fb_info *fbi = info->par;
 127         void __iomem *regs = fbi->io;
 128
 129         saddr1  = info->fix.smem_start >> 1;
 130         saddr2  = info->fix.smem_start;
 131         saddr2 += (line_length * info->var.yres) / 8;
 132         saddr2 >>= 1;
 133
 134         saddr3 = S3C2410_OFFSIZE(0) |
 135                  S3C2410_PAGEWIDTH((line_length / 16) & 0x3ff);
 136
 137         dprintk("LCDSADDR1 = 0x%08lx\n", saddr1);
 138         dprintk("LCDSADDR2 = 0x%08lx\n", saddr2);
 139         dprintk("LCDSADDR3 = 0x%08lx\n", saddr3);
 140
 141         writel(saddr1, regs + S3C2410_LCDSADDR1);
 142         writel(saddr2, regs + S3C2410_LCDSADDR2);
 143         writel(saddr3, regs + S3C2410_LCDSADDR3);
 144 }
 145
 146 /* s3c2410fb_calc_pixclk()
 147  *
 148  * calculate divisor for clk->pixclk
 149  */
 150 static unsigned int s3c2410fb_calc_pixclk(struct s3c2410fb_info *fbi,
 151                                           unsigned long pixclk)
 152 {
 153         unsigned long clk = clk_get_rate(fbi->clk);
 154         unsigned long long div;
 155
 156         /* pixclk is in picoseoncds, our clock is in Hz
 157          *
 158          * Hz -> picoseconds is / 10^-12
 159          */
 160
 161         div = (unsigned long long)clk * pixclk;
 162         do_div(div, 1000000UL);
 163         do_div(div, 1000000UL);
 164
 165         dprintk("pixclk %ld, divisor is %ld\n", pixclk, (long)div);
 166         return div;
 167 }
 168
 169 /*
 170  *      s3c2410fb_check_var():
 171  *      Get the video params out of 'var'. If a value doesn't fit, round it up,
 172  *      if it's too big, return -EINVAL.
 173  *
 174  */
 175 static int s3c2410fb_check_var(struct fb_var_screeninfo *var,
 176                                struct fb_info *info)
 177 {
 178         struct s3c2410fb_info *fbi = info->par;
 179         struct s3c2410fb_mach_info *mach_info = fbi->mach_info;
 180         struct s3c2410fb_display *display = NULL;
 181         unsigned i;
 182
 183         dprintk("check_var(var=%p, info=%p)\n", var, info);
 184
 185         /* validate x/y resolution */
 186
 187         for (i = 0; i < mach_info->num_displays; i++)
 188                 if (var->yres == mach_info->displays[i].yres &&
 189                     var->xres == mach_info->displays[i].xres &&
 190                     var->bits_per_pixel == mach_info->displays[i].bpp) {
 191                         display = mach_info->displays + i;
 192                         fbi->current_display = i;
 193                         break;
 194                 }
 195
 196         if (!display) {
 197                 dprintk("wrong resolution or depth %dx%d at %d bpp\n",
 198                         var->xres, var->yres, var->bits_per_pixel);
 199                 return -EINVAL;
 200         }
 201
 202         /* it is always the size as the display */
 203         var->xres_virtual = display->xres;
 204         var->yres_virtual = display->yres;
 205
 206         /* copy lcd settings */
 207         var->left_margin = display->left_margin;
 208         var->right_margin = display->right_margin;
 209
 210         var->transp.offset = 0;
 211         var->transp.length = 0;
 212         /* set r/g/b positions */
 213         switch (var->bits_per_pixel) {
 214         case 1:
 215         case 2:
 216         case 4:
 217                 var->red.offset = 0;
 218                 var->red.length = var->bits_per_pixel;
 219                 var->green      = var->red;
 220                 var->blue       = var->red;
 221                 break;
 222         case 8:
 223                 if (display->type != S3C2410_LCDCON1_TFT) {
 224                         /* 8 bpp 332 */
 225                         var->red.length         = 3;
 226                         var->red.offset         = 5;
 227                         var->green.length       = 3;
 228                         var->green.offset       = 2;
 229                         var->blue.length        = 2;
 230                         var->blue.offset        = 0;
 231                 } else {
 232                         var->red.offset         = 0;
 233                         var->red.length         = 8;
 234                         var->green              = var->red;
 235                         var->blue               = var->red;
 236                 }
 237                 break;
 238         case 12:
 239                 /* 12 bpp 444 */
 240                 var->red.length         = 4;
 241                 var->red.offset         = 8;
 242                 var->green.length       = 4;
 243                 var->green.offset       = 4;
 244                 var->blue.length        = 4;
 245                 var->blue.offset        = 0;
 246                 break;
 247
 248         default:
 249         case 16:
 250                 if (display->lcdcon5 & S3C2410_LCDCON5_FRM565) {
 251                         /* 16 bpp, 565 format */
 252                         var->red.offset         = 11;
 253                         var->green.offset       = 5;
 254                         var->blue.offset        = 0;
 255                         var->red.length         = 5;
 256                         var->green.length       = 6;
 257                         var->blue.length        = 5;
 258                 } else {
 259                         /* 16 bpp, 5551 format */
 260                         var->red.offset         = 11;
 261                         var->green.offset       = 6;
 262                         var->blue.offset        = 1;
 263                         var->red.length         = 5;
 264                         var->green.length       = 5;
 265                         var->blue.length        = 5;
 266                 }
 267                 break;
 268         case 32:
 269                 /* 24 bpp 888 and 8 dummy */
 270                 var->red.length         = 8;
 271                 var->red.offset         = 16;
 272                 var->green.length       = 8;
 273                 var->green.offset       = 8;
 274                 var->blue.length        = 8;
 275                 var->blue.offset        = 0;
 276                 break;
 277         }
 278         return 0;
 279 }
 280
 281 /* s3c2410fb_calculate_stn_lcd_regs
 282  *
 283  * calculate register values from var settings
 284  */
 285 static void s3c2410fb_calculate_stn_lcd_regs(const struct fb_info *info,
 286                                              struct s3c2410fb_hw *regs)
 287 {
 288         const struct s3c2410fb_info *fbi = info->par;
 289         const struct fb_var_screeninfo *var = &info->var;
 290         int type = regs->lcdcon1 & ~S3C2410_LCDCON1_TFT;
 291         int hs = var->xres >> 2;
 292         unsigned wdly = (var->left_margin >> 4) - 1;
 293         unsigned wlh = (var->hsync_len >> 4) - 1;
 294
 295         dprintk("%s: var->xres  = %d\n", __FUNCTION__, var->xres);
 296         dprintk("%s: var->yres  = %d\n", __FUNCTION__, var->yres);
 297         dprintk("%s: var->bpp   = %d\n", __FUNCTION__, var->bits_per_pixel);
 298
 299         if (type != S3C2410_LCDCON1_STN4)
 300                 hs >>= 1;
 301
 302         regs->lcdcon1 &= ~S3C2410_LCDCON1_MODEMASK;
 303
 304         switch (var->bits_per_pixel) {
 305         case 1:
 306                 regs->lcdcon1 |= S3C2410_LCDCON1_STN1BPP;
 307                 break;
 308         case 2:
 309                 regs->lcdcon1 |= S3C2410_LCDCON1_STN2GREY;
 310                 break;
 311         case 4:
 312                 regs->lcdcon1 |= S3C2410_LCDCON1_STN4GREY;
 313                 break;
 314         case 8:
 315                 regs->lcdcon1 |= S3C2410_LCDCON1_STN8BPP;
 316                 hs *= 3;
 317                 break;
 318         case 12:
 319                 regs->lcdcon1 |= S3C2410_LCDCON1_STN12BPP;
 320                 hs *= 3;
 321                 break;
 322
 323         default:
 324                 /* invalid pixel depth */
 325                 dev_err(fbi->dev, "invalid bpp %d\n",
 326                         var->bits_per_pixel);
 327         }
 328         /* update X/Y info */
 329         dprintk("setting horz: lft=%d, rt=%d, sync=%d\n",
 330                 var->left_margin, var->right_margin, var->hsync_len);
 331
 332         regs->lcdcon2 = S3C2410_LCDCON2_LINEVAL(var->yres - 1);
 333
 334         if (wdly > 3)
 335                 wdly = 3;
 336
 337         if (wlh > 3)
 338                 wlh = 3;
 339
 340         regs->lcdcon3 = S3C2410_LCDCON3_WDLY(wdly) |
 341                         S3C2410_LCDCON3_LINEBLANK(var->right_margin / 8) |
 342                         S3C2410_LCDCON3_HOZVAL(hs - 1);
 343
 344         regs->lcdcon4 = S3C2410_LCDCON4_WLH(wlh);
 345 }
 346
 347 /* s3c2410fb_calculate_tft_lcd_regs
 348  *
 349  * calculate register values from var settings
 350  */
 351 static void s3c2410fb_calculate_tft_lcd_regs(const struct fb_info *info,
 352                                              struct s3c2410fb_hw *regs)
 353 {
 354         const struct s3c2410fb_info *fbi = info->par;
 355         const struct fb_var_screeninfo *var = &info->var;
 356
 357         dprintk("%s: var->xres  = %d\n", __FUNCTION__, var->xres);
 358         dprintk("%s: var->yres  = %d\n", __FUNCTION__, var->yres);
 359         dprintk("%s: var->bpp   = %d\n", __FUNCTION__, var->bits_per_pixel);
 360
 361         regs->lcdcon1 &= ~S3C2410_LCDCON1_MODEMASK;
 362
 363         switch (var->bits_per_pixel) {
 364         case 1:
 365                 regs->lcdcon1 |= S3C2410_LCDCON1_TFT1BPP;
 366                 break;
 367         case 2:
 368                 regs->lcdcon1 |= S3C2410_LCDCON1_TFT2BPP;
 369                 break;
 370         case 4:
 371                 regs->lcdcon1 |= S3C2410_LCDCON1_TFT4BPP;
 372                 break;
 373         case 8:
 374                 regs->lcdcon1 |= S3C2410_LCDCON1_TFT8BPP;
 375                 regs->lcdcon5 |= S3C2410_LCDCON5_BSWP |
 376                                  S3C2410_LCDCON5_FRM565;
 377                 regs->lcdcon5 &= ~S3C2410_LCDCON5_HWSWP;
 378                 break;
 379         case 16:
 380                 regs->lcdcon1 |= S3C2410_LCDCON1_TFT16BPP;
 381                 regs->lcdcon5 &= ~S3C2410_LCDCON5_BSWP;
 382                 regs->lcdcon5 |= S3C2410_LCDCON5_HWSWP;
 383                 break;
 384         case 32:
 385                 regs->lcdcon1 |= S3C2410_LCDCON1_TFT24BPP;
 386                 regs->lcdcon5 &= ~(S3C2410_LCDCON5_BSWP |
 387                                    S3C2410_LCDCON5_HWSWP |
 388                                    S3C2410_LCDCON5_BPP24BL);
 389                 break;
 390         default:
 391                 /* invalid pixel depth */
 392                 dev_err(fbi->dev, "invalid bpp %d\n",
 393                         var->bits_per_pixel);
 394         }
 395         /* update X/Y info */
 396         dprintk("setting vert: up=%d, low=%d, sync=%d\n",
 397                 var->upper_margin, var->lower_margin, var->vsync_len);
 398
 399         dprintk("setting horz: lft=%d, rt=%d, sync=%d\n",
 400                 var->left_margin, var->right_margin, var->hsync_len);
 401
 402         regs->lcdcon2 = S3C2410_LCDCON2_LINEVAL(var->yres - 1) |
 403                         S3C2410_LCDCON2_VBPD(var->upper_margin - 1) |
 404                         S3C2410_LCDCON2_VFPD(var->lower_margin - 1) |
 405                         S3C2410_LCDCON2_VSPW(var->vsync_len - 1);
 406
 407         regs->lcdcon3 = S3C2410_LCDCON3_HBPD(var->right_margin - 1) |
 408                         S3C2410_LCDCON3_HFPD(var->left_margin - 1) |
 409                         S3C2410_LCDCON3_HOZVAL(var->xres - 1);
 410
 411         regs->lcdcon4 = S3C2410_LCDCON4_HSPW(var->hsync_len - 1);
 412 }
 413
 414 /* s3c2410fb_activate_var
 415  *
 416  * activate (set) the controller from the given framebuffer
 417  * information
 418  */
 419 static void s3c2410fb_activate_var(struct fb_info *info)
 420 {
 421         struct s3c2410fb_info *fbi = info->par;
 422         void __iomem *regs = fbi->io;
 423         struct fb_var_screeninfo *var = &info->var;
 424         struct s3c2410fb_mach_info *mach_info = fbi->mach_info;
 425         struct s3c2410fb_display *display = mach_info->displays +
 426                                             fbi->current_display;
 427
 428         /* set display type */
 429         fbi->regs.lcdcon1 &= ~S3C2410_LCDCON1_TFT;
 430         fbi->regs.lcdcon1 |= display->type;
 431
 432         if (var->pixclock > 0) {
 433                 int clkdiv = s3c2410fb_calc_pixclk(fbi, var->pixclock);
 434
 435                 if (display->type == S3C2410_LCDCON1_TFT) {
 436                         clkdiv = (clkdiv / 2) - 1;
 437                         if (clkdiv < 0)
 438                                 clkdiv = 0;
 439                 } else {
 440                         clkdiv = (clkdiv / 2);
 441                         if (clkdiv < 2)
 442                                 clkdiv = 2;
 443                 }
 444
 445                 fbi->regs.lcdcon1 &= ~S3C2410_LCDCON1_CLKVAL(0x3ff);
 446                 fbi->regs.lcdcon1 |=  S3C2410_LCDCON1_CLKVAL(clkdiv);
 447         }
 448
 449         if (display->type == S3C2410_LCDCON1_TFT)
 450                 s3c2410fb_calculate_tft_lcd_regs(info, &fbi->regs);
 451         else
 452                 s3c2410fb_calculate_stn_lcd_regs(info, &fbi->regs);
 453
 454         /* write new registers */
 455
 456         dprintk("new register set:\n");
 457         dprintk("lcdcon[1] = 0x%08lx\n", fbi->regs.lcdcon1);
 458         dprintk("lcdcon[2] = 0x%08lx\n", fbi->regs.lcdcon2);
 459         dprintk("lcdcon[3] = 0x%08lx\n", fbi->regs.lcdcon3);
 460         dprintk("lcdcon[4] = 0x%08lx\n", fbi->regs.lcdcon4);
 461         dprintk("lcdcon[5] = 0x%08lx\n", fbi->regs.lcdcon5);
 462
 463         writel(fbi->regs.lcdcon1 & ~S3C2410_LCDCON1_ENVID,
 464                 regs + S3C2410_LCDCON1);
 465         writel(fbi->regs.lcdcon2, regs + S3C2410_LCDCON2);
 466         writel(fbi->regs.lcdcon3, regs + S3C2410_LCDCON3);
 467         writel(fbi->regs.lcdcon4, regs + S3C2410_LCDCON4);
 468         writel(fbi->regs.lcdcon5, regs + S3C2410_LCDCON5);
 469
 470         /* set lcd address pointers */
 471         s3c2410fb_set_lcdaddr(info);
 472
 473         writel(fbi->regs.lcdcon1, regs + S3C2410_LCDCON1);
 474 }
 475
 476 /*
 477  *      s3c2410fb_set_par - Alters the hardware state.
 478  *      @info: frame buffer structure that represents a single frame buffer
 479  *
 480  */
 481 static int s3c2410fb_set_par(struct fb_info *info)
 482 {
 483         struct fb_var_screeninfo *var = &info->var;
 484
 485         switch (var->bits_per_pixel) {
 486         case 32:
 487         case 16:
 488         case 12:
 489                 info->fix.visual = FB_VISUAL_TRUECOLOR;
 490                 break;
 491         case 1:
 492                 info->fix.visual = FB_VISUAL_MONO01;
 493                 break;
 494         default:
 495                 info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
 496                 break;
 497         }
 498
 499         info->fix.line_length = (var->width * var->bits_per_pixel) / 8;
 500
 501         /* activate this new configuration */
 502
 503         s3c2410fb_activate_var(info);
 504         return 0;
 505 }
 506
 507 static void schedule_palette_update(struct s3c2410fb_info *fbi,
 508                                     unsigned int regno, unsigned int val)
 509 {
 510         unsigned long flags;
 511         unsigned long irqen;
 512         void __iomem *regs = fbi->io;
 513
 514         local_irq_save(flags);
 515
 516         fbi->palette_buffer[regno] = val;
 517
 518         if (!fbi->palette_ready) {
 519                 fbi->palette_ready = 1;
 520
 521                 /* enable IRQ */
 522                 irqen = readl(regs + S3C2410_LCDINTMSK);
 523                 irqen &= ~S3C2410_LCDINT_FRSYNC;
 524                 writel(irqen, regs + S3C2410_LCDINTMSK);
 525         }
 526
 527         local_irq_restore(flags);
 528 }
 529
 530 /* from pxafb.c */
 531 static inline unsigned int chan_to_field(unsigned int chan,
 532                                          struct fb_bitfield *bf)
 533 {
 534         chan &= 0xffff;
 535         chan >>= 16 - bf->length;
 536         return chan << bf->offset;
 537 }
 538
 539 static int s3c2410fb_setcolreg(unsigned regno,
 540                                unsigned red, unsigned green, unsigned blue,
 541                                unsigned transp, struct fb_info *info)
 542 {
 543         struct s3c2410fb_info *fbi = info->par;
 544         void __iomem *regs = fbi->io;
 545         unsigned int val;
 546
 547         /* dprintk("setcol: regno=%d, rgb=%d,%d,%d\n",
 548                    regno, red, green, blue); */
 549
 550         switch (info->fix.visual) {
 551         case FB_VISUAL_TRUECOLOR:
 552                 /* true-colour, use pseudo-palette */
 553
 554                 if (regno < 16) {
 555                         u32 *pal = info->pseudo_palette;
 556
 557                         val  = chan_to_field(red,   &info->var.red);
 558                         val |= chan_to_field(green, &info->var.green);
 559                         val |= chan_to_field(blue,  &info->var.blue);
 560
 561                         pal[regno] = val;
 562                 }
 563                 break;
 564
 565         case FB_VISUAL_PSEUDOCOLOR:
 566                 if (regno < 256) {
 567                         /* currently assume RGB 5-6-5 mode */
 568
 569                         val  = ((red   >>  0) & 0xf800);
 570                         val |= ((green >>  5) & 0x07e0);
 571                         val |= ((blue  >> 11) & 0x001f);
 572
 573                         writel(val, regs + S3C2410_TFTPAL(regno));
 574                         schedule_palette_update(fbi, regno, val);
 575                 }
 576
 577                 break;
 578
 579         default:
 580                 return 1;       /* unknown type */
 581         }
 582
 583         return 0;
 584 }
 585
 586 /*
 587  *      s3c2410fb_blank
 588  *      @blank_mode: the blank mode we want.
 589  *      @info: frame buffer structure that represents a single frame buffer
 590  *
 591  *      Blank the screen if blank_mode != 0, else unblank. Return 0 if
 592  *      blanking succeeded, != 0 if un-/blanking failed due to e.g. a
 593  *      video mode which doesn't support it. Implements VESA suspend
 594  *      and powerdown modes on hardware that supports disabling hsync/vsync:
 595  *      blank_mode == 2: suspend vsync
 596  *      blank_mode == 3: suspend hsync
 597  *      blank_mode == 4: powerdown
 598  *
 599  *      Returns negative errno on error, or zero on success.
 600  *
 601  */
 602 static int s3c2410fb_blank(int blank_mode, struct fb_info *info)
 603 {
 604         struct s3c2410fb_info *fbi = info->par;
 605         void __iomem *regs = fbi->io;
 606
 607         dprintk("blank(mode=%d, info=%p)\n", blank_mode, info);
 608
 609         if (mach_info == NULL)
 610                 return -EINVAL;
 611
 612         if (blank_mode == FB_BLANK_UNBLANK)
 613                 writel(0x0, regs + S3C2410_TPAL);
 614         else {
 615                 dprintk("setting TPAL to output 0x000000\n");
 616                 writel(S3C2410_TPAL_EN, regs + S3C2410_TPAL);
 617         }
 618
 619         return 0;
 620 }
 621
 622 static int s3c2410fb_debug_show(struct device *dev,
 623                                 struct device_attribute *attr, char *buf)
 624 {
 625         return snprintf(buf, PAGE_SIZE, "%s\n", debug ? "on" : "off");
 626 }
 627 static int s3c2410fb_debug_store(struct device *dev,
 628                                  struct device_attribute *attr,
 629                                  const char *buf, size_t len)
 630 {
 631         if (mach_info == NULL)
 632                 return -EINVAL;
 633
 634         if (len < 1)
 635                 return -EINVAL;
 636
 637         if (strnicmp(buf, "on", 2) == 0 ||
 638             strnicmp(buf, "1", 1) == 0) {
 639                 debug = 1;
 640                 printk(KERN_DEBUG "s3c2410fb: Debug On");
 641         } else if (strnicmp(buf, "off", 3) == 0 ||
 642                    strnicmp(buf, "0", 1) == 0) {
 643                 debug = 0;
 644                 printk(KERN_DEBUG "s3c2410fb: Debug Off");
 645         } else {
 646                 return -EINVAL;
 647         }
 648
 649         return len;
 650 }
 651
 652 static DEVICE_ATTR(debug, 0666, s3c2410fb_debug_show, s3c2410fb_debug_store);
 653
 654 static struct fb_ops s3c2410fb_ops = {
 655         .owner          = THIS_MODULE,
 656         .fb_check_var   = s3c2410fb_check_var,
 657         .fb_set_par     = s3c2410fb_set_par,
 658         .fb_blank       = s3c2410fb_blank,
 659         .fb_setcolreg   = s3c2410fb_setcolreg,
 660         .fb_fillrect    = cfb_fillrect,
 661         .fb_copyarea    = cfb_copyarea,
 662         .fb_imageblit   = cfb_imageblit,
 663 };
 664
 665 /*
 666  * s3c2410fb_map_video_memory():
 667  *      Allocates the DRAM memory for the frame buffer.  This buffer is
 668  *      remapped into a non-cached, non-buffered, memory region to
 669  *      allow palette and pixel writes to occur without flushing the
 670  *      cache.  Once this area is remapped, all virtual memory
 671  *      access to the video memory should occur at the new region.
 672  */
 673 static int __init s3c2410fb_map_video_memory(struct fb_info *info)
 674 {
 675         struct s3c2410fb_info *fbi = info->par;
 676
 677         dprintk("map_video_memory(fbi=%p)\n", fbi);
 678
 679         fbi->map_size = PAGE_ALIGN(info->fix.smem_len + PAGE_SIZE);
 680         fbi->map_cpu  = dma_alloc_writecombine(fbi->dev, fbi->map_size,
 681                                                &fbi->map_dma, GFP_KERNEL);
 682
 683         fbi->map_size = info->fix.smem_len;
 684
 685         if (fbi->map_cpu) {
 686                 /* prevent initial garbage on screen */
 687                 dprintk("map_video_memory: clear %p:%08x\n",
 688                         fbi->map_cpu, fbi->map_size);
 689                 memset(fbi->map_cpu, 0xf0, fbi->map_size);
 690
 691                 fbi->screen_dma         = fbi->map_dma;
 692                 info->screen_base       = fbi->map_cpu;
 693                 info->fix.smem_start    = fbi->screen_dma;
 694
 695                 dprintk("map_video_memory: dma=%08x cpu=%p size=%08x\n",
 696                         fbi->map_dma, fbi->map_cpu, info->fix.smem_len);
 697         }
 698
 699         return fbi->map_cpu ? 0 : -ENOMEM;
 700 }
 701
 702 static inline void s3c2410fb_unmap_video_memory(struct s3c2410fb_info *fbi)
 703 {
 704         dma_free_writecombine(fbi->dev, fbi->map_size, fbi->map_cpu,
 705                               fbi->map_dma);
 706 }
 707
 708 static inline void modify_gpio(void __iomem *reg,
 709                                unsigned long set, unsigned long mask)
 710 {
 711         unsigned long tmp;
 712
 713         tmp = readl(reg) & ~mask;
 714         writel(tmp | set, reg);
 715 }
 716
 717 /*
 718  * s3c2410fb_init_registers - Initialise all LCD-related registers
 719  */
 720 static int s3c2410fb_init_registers(struct fb_info *info)
 721 {
 722         struct s3c2410fb_info *fbi = info->par;
 723         unsigned long flags;
 724         void __iomem *regs = fbi->io;
 725
 726         /* Initialise LCD with values from haret */
 727
 728         local_irq_save(flags);
 729
 730         /* modify the gpio(s) with interrupts set (bjd) */
 731
 732         modify_gpio(S3C2410_GPCUP,  mach_info->gpcup,  mach_info->gpcup_mask);
 733         modify_gpio(S3C2410_GPCCON, mach_info->gpccon, mach_info->gpccon_mask);
 734         modify_gpio(S3C2410_GPDUP,  mach_info->gpdup,  mach_info->gpdup_mask);
 735         modify_gpio(S3C2410_GPDCON, mach_info->gpdcon, mach_info->gpdcon_mask);
 736
 737         local_irq_restore(flags);
 738
 739         writel(fbi->regs.lcdcon1, regs + S3C2410_LCDCON1);
 740         writel(fbi->regs.lcdcon2, regs + S3C2410_LCDCON2);
 741         writel(fbi->regs.lcdcon3, regs + S3C2410_LCDCON3);
 742         writel(fbi->regs.lcdcon4, regs + S3C2410_LCDCON4);
 743         writel(fbi->regs.lcdcon5, regs + S3C2410_LCDCON5);
 744
 745         s3c2410fb_set_lcdaddr(info);
 746
 747         dprintk("LPCSEL    = 0x%08lx\n", mach_info->lpcsel);
 748         writel(mach_info->lpcsel, regs + S3C2410_LPCSEL);
 749
 750         dprintk("replacing TPAL %08x\n", readl(regs + S3C2410_TPAL));
 751
 752         /* ensure temporary palette disabled */
 753         writel(0x00, regs + S3C2410_TPAL);
 754
 755         /* Enable video by setting the ENVID bit to 1 */
 756         fbi->regs.lcdcon1 |= S3C2410_LCDCON1_ENVID;
 757         writel(fbi->regs.lcdcon1, regs + S3C2410_LCDCON1);
 758         return 0;
 759 }
 760
 761 static void s3c2410fb_write_palette(struct s3c2410fb_info *fbi)
 762 {
 763         unsigned int i;
 764         void __iomem *regs = fbi->io;
 765
 766         fbi->palette_ready = 0;
 767
 768         for (i = 0; i < 256; i++) {
 769                 unsigned long ent = fbi->palette_buffer[i];
 770                 if (ent == PALETTE_BUFF_CLEAR)
 771                         continue;
 772
 773                 writel(ent, regs + S3C2410_TFTPAL(i));
 774
 775                 /* it seems the only way to know exactly
 776                  * if the palette wrote ok, is to check
 777                  * to see if the value verifies ok
 778                  */
 779
 780                 if (readw(regs + S3C2410_TFTPAL(i)) == ent)
 781                         fbi->palette_buffer[i] = PALETTE_BUFF_CLEAR;
 782                 else
 783                         fbi->palette_ready = 1;   /* retry */
 784         }
 785 }
 786
 787 static irqreturn_t s3c2410fb_irq(int irq, void *dev_id)
 788 {
 789         struct s3c2410fb_info *fbi = dev_id;
 790         void __iomem *regs = fbi->io;
 791         unsigned long lcdirq = readl(regs + S3C2410_LCDINTPND);
 792
 793         if (lcdirq & S3C2410_LCDINT_FRSYNC) {
 794                 if (fbi->palette_ready)
 795                         s3c2410fb_write_palette(fbi);
 796
 797                 writel(S3C2410_LCDINT_FRSYNC, regs + S3C2410_LCDINTPND);
 798                 writel(S3C2410_LCDINT_FRSYNC, regs + S3C2410_LCDSRCPND);
 799         }
 800
 801         return IRQ_HANDLED;
 802 }
 803
 804 static char driver_name[] = "s3c2410fb";
 805
 806 static int __init s3c2410fb_probe(struct platform_device *pdev)
 807 {
 808         struct s3c2410fb_info *info;
 809         struct s3c2410fb_display *display;
 810         struct fb_info *fbinfo;
 811         struct resource *res;
 812         int ret;
 813         int irq;
 814         int i;
 815         int size;
 816         u32 lcdcon1;
 817
 818         mach_info = pdev->dev.platform_data;
 819         if (mach_info == NULL) {
 820                 dev_err(&pdev->dev,
 821                         "no platform data for lcd, cannot attach\n");
 822                 return -EINVAL;
 823         }
 824
 825         display = mach_info->displays + mach_info->default_display;
 826
 827         irq = platform_get_irq(pdev, 0);
 828         if (irq < 0) {
 829                 dev_err(&pdev->dev, "no irq for device\n");
 830                 return -ENOENT;
 831         }
 832
 833         fbinfo = framebuffer_alloc(sizeof(struct s3c2410fb_info), &pdev->dev);
 834         if (!fbinfo)
 835                 return -ENOMEM;
 836
 837         info = fbinfo->par;
 838         info->dev = &pdev->dev;
 839
 840         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 841         if (res == NULL) {
 842                 dev_err(&pdev->dev, "failed to get memory registers\n");
 843                 ret = -ENXIO;
 844                 goto dealloc_fb;
 845         }
 846
 847         size = (res->end - res->start) + 1;
 848         info->mem = request_mem_region(res->start, size, pdev->name);
 849         if (info->mem == NULL) {
 850                 dev_err(&pdev->dev, "failed to get memory region\n");
 851                 ret = -ENOENT;
 852                 goto dealloc_fb;
 853         }
 854
 855         info->io = ioremap(res->start, size);
 856         if (info->io == NULL) {
 857                 dev_err(&pdev->dev, "ioremap() of registers failed\n");
 858                 ret = -ENXIO;
 859                 goto release_mem;
 860         }
 861
 862         platform_set_drvdata(pdev, fbinfo);
 863
 864         dprintk("devinit\n");
 865
 866         strcpy(fbinfo->fix.id, driver_name);
 867
 868         info->regs.lcdcon1 = display->lcdcon1;
 869         info->regs.lcdcon5 = display->lcdcon5;
 870
 871         /* Stop the video and unset ENVID if set */
 872         info->regs.lcdcon1 &= ~S3C2410_LCDCON1_ENVID;
 873         lcdcon1 = readl(info->io + S3C2410_LCDCON1);
 874         writel(lcdcon1 & ~S3C2410_LCDCON1_ENVID, info->io + S3C2410_LCDCON1);
 875
 876         info->mach_info             = pdev->dev.platform_data;
 877         info->current_display       = mach_info->default_display;
 878
 879         fbinfo->fix.type            = FB_TYPE_PACKED_PIXELS;
 880         fbinfo->fix.type_aux        = 0;
 881         fbinfo->fix.xpanstep        = 0;
 882         fbinfo->fix.ypanstep        = 0;
 883         fbinfo->fix.ywrapstep       = 0;
 884         fbinfo->fix.accel           = FB_ACCEL_NONE;
 885
 886         fbinfo->var.nonstd          = 0;
 887         fbinfo->var.activate        = FB_ACTIVATE_NOW;
 888         fbinfo->var.height          = display->height;
 889         fbinfo->var.width           = display->width;
 890         fbinfo->var.accel_flags     = 0;
 891         fbinfo->var.vmode           = FB_VMODE_NONINTERLACED;
 892
 893         fbinfo->fbops               = &s3c2410fb_ops;
 894         fbinfo->flags               = FBINFO_FLAG_DEFAULT;
 895         fbinfo->pseudo_palette      = &info->pseudo_pal;
 896
 897         fbinfo->var.xres            = display->xres;
 898         fbinfo->var.xres_virtual    = display->xres;
 899         fbinfo->var.yres            = display->yres;
 900         fbinfo->var.yres_virtual    = display->yres;
 901         fbinfo->var.bits_per_pixel  = display->bpp;
 902         fbinfo->var.left_margin     = display->left_margin;
 903         fbinfo->var.right_margin    = display->right_margin;
 904
 905         fbinfo->var.upper_margin    = display->upper_margin;
 906         fbinfo->var.lower_margin    = display->lower_margin;
 907         fbinfo->var.vsync_len       = display->vsync_len;
 908         fbinfo->var.hsync_len       = display->hsync_len;
 909
 910         fbinfo->var.red.offset      = 11;
 911         fbinfo->var.green.offset    = 5;
 912         fbinfo->var.blue.offset     = 0;
 913         fbinfo->var.transp.offset   = 0;
 914         fbinfo->var.red.length      = 5;
 915         fbinfo->var.green.length    = 6;
 916         fbinfo->var.blue.length     = 5;
 917         fbinfo->var.transp.length   = 0;
 918
 919         /* find maximum required memory size for display */
 920         for (i = 0; i < mach_info->num_displays; i++) {
 921                 unsigned long smem_len = mach_info->displays[i].xres;
 922
 923                 smem_len *= mach_info->displays[i].yres;
 924                 smem_len *= mach_info->displays[i].bpp;
 925                 smem_len >>= 3;
 926                 if (fbinfo->fix.smem_len < smem_len)
 927                         fbinfo->fix.smem_len = smem_len;
 928         }
 929
 930         for (i = 0; i < 256; i++)
 931                 info->palette_buffer[i] = PALETTE_BUFF_CLEAR;
 932
 933         ret = request_irq(irq, s3c2410fb_irq, IRQF_DISABLED, pdev->name, info);
 934         if (ret) {
 935                 dev_err(&pdev->dev, "cannot get irq %d - err %d\n", irq, ret);
 936                 ret = -EBUSY;
 937                 goto release_regs;
 938         }
 939
 940         info->clk = clk_get(NULL, "lcd");
 941         if (!info->clk || IS_ERR(info->clk)) {
 942                 printk(KERN_ERR "failed to get lcd clock source\n");
 943                 ret = -ENOENT;
 944                 goto release_irq;
 945         }
 946
 947         clk_enable(info->clk);
 948         dprintk("got and enabled clock\n");
 949
 950         msleep(1);
 951
 952         /* Initialize video memory */
 953         ret = s3c2410fb_map_video_memory(fbinfo);
 954         if (ret) {
 955                 printk(KERN_ERR "Failed to allocate video RAM: %d\n", ret);
 956                 ret = -ENOMEM;
 957                 goto release_clock;
 958         }
 959
 960         dprintk("got video memory\n");
 961
 962         s3c2410fb_init_registers(fbinfo);
 963
 964         s3c2410fb_check_var(&fbinfo->var, fbinfo);
 965
 966         ret = register_framebuffer(fbinfo);
 967         if (ret < 0) {
 968                 printk(KERN_ERR "Failed to register framebuffer device: %d\n",
 969                         ret);
 970                 goto free_video_memory;
 971         }
 972
 973         /* create device files */
 974         device_create_file(&pdev->dev, &dev_attr_debug);
 975
 976         printk(KERN_INFO "fb%d: %s frame buffer device\n",
 977                 fbinfo->node, fbinfo->fix.id);
 978
 979         return 0;
 980
 981 free_video_memory:
 982         s3c2410fb_unmap_video_memory(info);
 983 release_clock:
 984         clk_disable(info->clk);
 985         clk_put(info->clk);
 986 release_irq:
 987         free_irq(irq, info);
 988 release_regs:
 989         iounmap(info->io);
 990 release_mem:
 991         release_resource(info->mem);
 992         kfree(info->mem);
 993 dealloc_fb:
 994         framebuffer_release(fbinfo);
 995         return ret;
 996 }
 997
 998 /* s3c2410fb_stop_lcd
 999  *
1000  * shutdown the lcd controller
1001  */
1002 static void s3c2410fb_stop_lcd(struct s3c2410fb_info *fbi)
1003 {
1004         unsigned long flags;
1005
1006         local_irq_save(flags);
1007
1008         fbi->regs.lcdcon1 &= ~S3C2410_LCDCON1_ENVID;
1009         writel(fbi->regs.lcdcon1, fbi->io + S3C2410_LCDCON1);
1010
1011         local_irq_restore(flags);
1012 }
1013
1014 /*
1015  *  Cleanup
1016  */
1017 static int s3c2410fb_remove(struct platform_device *pdev)
1018 {
1019         struct fb_info *fbinfo = platform_get_drvdata(pdev);
1020         struct s3c2410fb_info *info = fbinfo->par;
1021         int irq;
1022
1023         s3c2410fb_stop_lcd(info);
1024         msleep(1);
1025
1026         s3c2410fb_unmap_video_memory(info);
1027
1028         if (info->clk) {
1029                 clk_disable(info->clk);
1030                 clk_put(info->clk);
1031                 info->clk = NULL;
1032         }
1033
1034         irq = platform_get_irq(pdev, 0);
1035         free_irq(irq, info);
1036
1037         release_resource(info->mem);
1038         kfree(info->mem);
1039         iounmap(info->io);
1040         unregister_framebuffer(fbinfo);
1041
1042         return 0;
1043 }
1044
1045 #ifdef CONFIG_PM
1046
1047 /* suspend and resume support for the lcd controller */
1048 static int s3c2410fb_suspend(struct platform_device *dev, pm_message_t state)
1049 {
1050         struct fb_info     *fbinfo = platform_get_drvdata(dev);
1051         struct s3c2410fb_info *info = fbinfo->par;
1052
1053         s3c2410fb_stop_lcd(info);
1054
1055         /* sleep before disabling the clock, we need to ensure
1056          * the LCD DMA engine is not going to get back on the bus
1057          * before the clock goes off again (bjd) */
1058
1059         msleep(1);
1060         clk_disable(info->clk);
1061
1062         return 0;
1063 }
1064
1065 static int s3c2410fb_resume(struct platform_device *dev)
1066 {
1067         struct fb_info     *fbinfo = platform_get_drvdata(dev);
1068         struct s3c2410fb_info *info = fbinfo->par;
1069
1070         clk_enable(info->clk);
1071         msleep(1);
1072
1073         s3c2410fb_init_registers(info);
1074
1075         return 0;
1076 }
1077
1078 #else
1079 #define s3c2410fb_suspend NULL
1080 #define s3c2410fb_resume  NULL
1081 #endif
1082
1083 static struct platform_driver s3c2410fb_driver = {
1084         .probe          = s3c2410fb_probe,
1085         .remove         = s3c2410fb_remove,
1086         .suspend        = s3c2410fb_suspend,
1087         .resume         = s3c2410fb_resume,
1088         .driver         = {
1089                 .name   = "s3c2410-lcd",
1090                 .owner  = THIS_MODULE,
1091         },
1092 };
1093
1094 int __devinit s3c2410fb_init(void)
1095 {
1096         return platform_driver_register(&s3c2410fb_driver);
1097 }
1098
1099 static void __exit s3c2410fb_cleanup(void)
1100 {
1101         platform_driver_unregister(&s3c2410fb_driver);
1102 }
1103
1104 module_init(s3c2410fb_init);
1105 module_exit(s3c2410fb_cleanup);
1106
1107 MODULE_AUTHOR("Arnaud Patard <arnaud.patard@rtp-net.org>, "
1108               "Ben Dooks <ben-linux@fluff.org>");
1109 MODULE_DESCRIPTION("Framebuffer driver for the s3c2410");
1110 MODULE_LICENSE("GPL");