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   1 /*
   2  * linux/drivers/video/s3c2410fb.c
   3  *      Copyright (c) Arnaud Patard, Ben Dooks
   4  *
   5  * This file is subject to the terms and conditions of the GNU General Public
   6  * License.  See the file COPYING in the main directory of this archive for
   7  * more details.
   8  *
   9  *          S3C2410 LCD Controller Frame Buffer Driver
  10  *          based on skeletonfb.c, sa1100fb.c and others
  11  *
  12  * ChangeLog
  13  * 2005-04-07: Arnaud Patard <arnaud.patard@rtp-net.org>
  14  *      - u32 state -> pm_message_t state
  15  *      - S3C2410_{VA,SZ}_LCD -> S3C24XX
  16  *
  17  * 2005-03-15: Arnaud Patard <arnaud.patard@rtp-net.org>
  18  *      - Removed the ioctl
  19  *      - use readl/writel instead of __raw_writel/__raw_readl
  20  *
  21  * 2004-12-04: Arnaud Patard <arnaud.patard@rtp-net.org>
  22  *      - Added the possibility to set on or off the
  23  *      debugging messages
  24  *      - Replaced 0 and 1 by on or off when reading the
  25  *      /sys files
  26  *
  27  * 2005-03-23: Ben Dooks <ben-linux@fluff.org>
  28  *      - added non 16bpp modes
  29  *      - updated platform information for range of x/y/bpp
  30  *      - add code to ensure palette is written correctly
  31  *      - add pixel clock divisor control
  32  *
  33  * 2004-11-11: Arnaud Patard <arnaud.patard@rtp-net.org>
  34  *      - Removed the use of currcon as it no more exists
  35  *      - Added LCD power sysfs interface
  36  *
  37  * 2004-11-03: Ben Dooks <ben-linux@fluff.org>
  38  *      - minor cleanups
  39  *      - add suspend/resume support
  40  *      - s3c2410fb_setcolreg() not valid in >8bpp modes
  41  *      - removed last CONFIG_FB_S3C2410_FIXED
  42  *      - ensure lcd controller stopped before cleanup
  43  *      - added sysfs interface for backlight power
  44  *      - added mask for gpio configuration
  45  *      - ensured IRQs disabled during GPIO configuration
  46  *      - disable TPAL before enabling video
  47  *
  48  * 2004-09-20: Arnaud Patard <arnaud.patard@rtp-net.org>
  49  *      - Suppress command line options
  50  *
  51  * 2004-09-15: Arnaud Patard <arnaud.patard@rtp-net.org>
  52  *      - code cleanup
  53  *
  54  * 2004-09-07: Arnaud Patard <arnaud.patard@rtp-net.org>
  55  *      - Renamed from h1940fb.c to s3c2410fb.c
  56  *      - Add support for different devices
  57  *      - Backlight support
  58  *
  59  * 2004-09-05: Herbert Pötzl <herbert@13thfloor.at>
  60  *      - added clock (de-)allocation code
  61  *      - added fixem fbmem option
  62  *
  63  * 2004-07-27: Arnaud Patard <arnaud.patard@rtp-net.org>
  64  *      - code cleanup
  65  *      - added a forgotten return in h1940fb_init
  66  *
  67  * 2004-07-19: Herbert Pötzl <herbert@13thfloor.at>
  68  *      - code cleanup and extended debugging
  69  *
  70  * 2004-07-15: Arnaud Patard <arnaud.patard@rtp-net.org>
  71  *      - First version
  72  */
  73
  74 #include <linux/module.h>
  75 #include <linux/kernel.h>
  76 #include <linux/errno.h>
  77 #include <linux/string.h>
  78 #include <linux/mm.h>
  79 #include <linux/slab.h>
  80 #include <linux/delay.h>
  81 #include <linux/fb.h>
  82 #include <linux/init.h>
  83 #include <linux/dma-mapping.h>
  84 #include <linux/interrupt.h>
  85 #include <linux/platform_device.h>
  86 #include <linux/clk.h>
  87
  88 #include <asm/io.h>
  89 #include <asm/div64.h>
  90
  91 #include <asm/mach/map.h>
  92 #include <asm/arch/regs-lcd.h>
  93 #include <asm/arch/regs-gpio.h>
  94 #include <asm/arch/fb.h>
  95
  96 #ifdef CONFIG_PM
  97 #include <linux/pm.h>
  98 #endif
  99
 100 #include "s3c2410fb.h"
 101
 102 /* Debugging stuff */
 103 #ifdef CONFIG_FB_S3C2410_DEBUG
 104 static int debug        = 1;
 105 #else
 106 static int debug        = 0;
 107 #endif
 108
 109 #define dprintk(msg...) if (debug) { printk(KERN_DEBUG "s3c2410fb: " msg); }
 110
 111 /* useful functions */
 112
 113 /* s3c2410fb_set_lcdaddr
 114  *
 115  * initialise lcd controller address pointers
 116  */
 117 static void s3c2410fb_set_lcdaddr(struct fb_info *info)
 118 {
 119         unsigned long saddr1, saddr2, saddr3;
 120         struct s3c2410fb_info *fbi = info->par;
 121         void __iomem *regs = fbi->io;
 122
 123         saddr1  = info->fix.smem_start >> 1;
 124         saddr2  = info->fix.smem_start;
 125         saddr2 += info->fix.line_length * info->var.yres;
 126         saddr2 >>= 1;
 127
 128         saddr3 = S3C2410_OFFSIZE(0) |
 129                  S3C2410_PAGEWIDTH((info->fix.line_length / 2) & 0x3ff);
 130
 131         dprintk("LCDSADDR1 = 0x%08lx\n", saddr1);
 132         dprintk("LCDSADDR2 = 0x%08lx\n", saddr2);
 133         dprintk("LCDSADDR3 = 0x%08lx\n", saddr3);
 134
 135         writel(saddr1, regs + S3C2410_LCDSADDR1);
 136         writel(saddr2, regs + S3C2410_LCDSADDR2);
 137         writel(saddr3, regs + S3C2410_LCDSADDR3);
 138 }
 139
 140 /* s3c2410fb_calc_pixclk()
 141  *
 142  * calculate divisor for clk->pixclk
 143  */
 144 static unsigned int s3c2410fb_calc_pixclk(struct s3c2410fb_info *fbi,
 145                                           unsigned long pixclk)
 146 {
 147         unsigned long clk = clk_get_rate(fbi->clk);
 148         unsigned long long div;
 149
 150         /* pixclk is in picoseconds, our clock is in Hz
 151          *
 152          * Hz -> picoseconds is / 10^-12
 153          */
 154
 155         div = (unsigned long long)clk * pixclk;
 156         div >>= 12;                     /* div / 2^12 */
 157         do_div(div, 625 * 625UL * 625); /* div / 5^12 */
 158
 159         dprintk("pixclk %ld, divisor is %ld\n", pixclk, (long)div);
 160         return div;
 161 }
 162
 163 /*
 164  *      s3c2410fb_check_var():
 165  *      Get the video params out of 'var'. If a value doesn't fit, round it up,
 166  *      if it's too big, return -EINVAL.
 167  *
 168  */
 169 static int s3c2410fb_check_var(struct fb_var_screeninfo *var,
 170                                struct fb_info *info)
 171 {
 172         struct s3c2410fb_info *fbi = info->par;
 173         struct s3c2410fb_mach_info *mach_info = fbi->dev->platform_data;
 174         struct s3c2410fb_display *display = NULL;
 175         unsigned i;
 176
 177         dprintk("check_var(var=%p, info=%p)\n", var, info);
 178
 179         /* validate x/y resolution */
 180
 181         for (i = 0; i < mach_info->num_displays; i++)
 182                 if (var->yres == mach_info->displays[i].yres &&
 183                     var->xres == mach_info->displays[i].xres &&
 184                     var->bits_per_pixel == mach_info->displays[i].bpp) {
 185                         display = mach_info->displays + i;
 186                         break;
 187                 }
 188
 189         if (!display) {
 190                 dprintk("wrong resolution or depth %dx%d at %d bpp\n",
 191                         var->xres, var->yres, var->bits_per_pixel);
 192                 return -EINVAL;
 193         }
 194
 195         /* it is always the size as the display */
 196         var->xres_virtual = display->xres;
 197         var->yres_virtual = display->yres;
 198         var->height = display->height;
 199         var->width = display->width;
 200
 201         /* copy lcd settings */
 202         var->pixclock = display->pixclock;
 203         var->left_margin = display->left_margin;
 204         var->right_margin = display->right_margin;
 205         var->upper_margin = display->upper_margin;
 206         var->lower_margin = display->lower_margin;
 207         var->vsync_len = display->vsync_len;
 208         var->hsync_len = display->hsync_len;
 209
 210         fbi->regs.lcdcon1 = display->lcdcon1;
 211         fbi->regs.lcdcon5 = display->lcdcon5;
 212         /* set display type */
 213         fbi->regs.lcdcon1 &= ~S3C2410_LCDCON1_TFT;
 214         fbi->regs.lcdcon1 |= display->type;
 215
 216         var->transp.offset = 0;
 217         var->transp.length = 0;
 218         /* set r/g/b positions */
 219         switch (var->bits_per_pixel) {
 220         case 1:
 221         case 2:
 222         case 4:
 223                 var->red.offset = 0;
 224                 var->red.length = var->bits_per_pixel;
 225                 var->green      = var->red;
 226                 var->blue       = var->red;
 227                 break;
 228         case 8:
 229                 if (display->type != S3C2410_LCDCON1_TFT) {
 230                         /* 8 bpp 332 */
 231                         var->red.length         = 3;
 232                         var->red.offset         = 5;
 233                         var->green.length       = 3;
 234                         var->green.offset       = 2;
 235                         var->blue.length        = 2;
 236                         var->blue.offset        = 0;
 237                 } else {
 238                         var->red.offset         = 0;
 239                         var->red.length         = 8;
 240                         var->green              = var->red;
 241                         var->blue               = var->red;
 242                 }
 243                 break;
 244         case 12:
 245                 /* 12 bpp 444 */
 246                 var->red.length         = 4;
 247                 var->red.offset         = 8;
 248                 var->green.length       = 4;
 249                 var->green.offset       = 4;
 250                 var->blue.length        = 4;
 251                 var->blue.offset        = 0;
 252                 break;
 253
 254         default:
 255         case 16:
 256                 if (display->lcdcon5 & S3C2410_LCDCON5_FRM565) {
 257                         /* 16 bpp, 565 format */
 258                         var->red.offset         = 11;
 259                         var->green.offset       = 5;
 260                         var->blue.offset        = 0;
 261                         var->red.length         = 5;
 262                         var->green.length       = 6;
 263                         var->blue.length        = 5;
 264                 } else {
 265                         /* 16 bpp, 5551 format */
 266                         var->red.offset         = 11;
 267                         var->green.offset       = 6;
 268                         var->blue.offset        = 1;
 269                         var->red.length         = 5;
 270                         var->green.length       = 5;
 271                         var->blue.length        = 5;
 272                 }
 273                 break;
 274         case 32:
 275                 /* 24 bpp 888 and 8 dummy */
 276                 var->red.length         = 8;
 277                 var->red.offset         = 16;
 278                 var->green.length       = 8;
 279                 var->green.offset       = 8;
 280                 var->blue.length        = 8;
 281                 var->blue.offset        = 0;
 282                 break;
 283         }
 284         return 0;
 285 }
 286
 287 /* s3c2410fb_calculate_stn_lcd_regs
 288  *
 289  * calculate register values from var settings
 290  */
 291 static void s3c2410fb_calculate_stn_lcd_regs(const struct fb_info *info,
 292                                              struct s3c2410fb_hw *regs)
 293 {
 294         const struct s3c2410fb_info *fbi = info->par;
 295         const struct fb_var_screeninfo *var = &info->var;
 296         int type = regs->lcdcon1 & ~S3C2410_LCDCON1_TFT;
 297         int hs = var->xres >> 2;
 298         unsigned wdly = (var->left_margin >> 4) - 1;
 299         unsigned wlh = (var->hsync_len >> 4) - 1;
 300
 301         if (type != S3C2410_LCDCON1_STN4)
 302                 hs >>= 1;
 303
 304         regs->lcdcon1 &= ~S3C2410_LCDCON1_MODEMASK;
 305
 306         switch (var->bits_per_pixel) {
 307         case 1:
 308                 regs->lcdcon1 |= S3C2410_LCDCON1_STN1BPP;
 309                 break;
 310         case 2:
 311                 regs->lcdcon1 |= S3C2410_LCDCON1_STN2GREY;
 312                 break;
 313         case 4:
 314                 regs->lcdcon1 |= S3C2410_LCDCON1_STN4GREY;
 315                 break;
 316         case 8:
 317                 regs->lcdcon1 |= S3C2410_LCDCON1_STN8BPP;
 318                 hs *= 3;
 319                 break;
 320         case 12:
 321                 regs->lcdcon1 |= S3C2410_LCDCON1_STN12BPP;
 322                 hs *= 3;
 323                 break;
 324
 325         default:
 326                 /* invalid pixel depth */
 327                 dev_err(fbi->dev, "invalid bpp %d\n",
 328                         var->bits_per_pixel);
 329         }
 330         /* update X/Y info */
 331         dprintk("setting horz: lft=%d, rt=%d, sync=%d\n",
 332                 var->left_margin, var->right_margin, var->hsync_len);
 333
 334         regs->lcdcon2 = S3C2410_LCDCON2_LINEVAL(var->yres - 1);
 335
 336         if (wdly > 3)
 337                 wdly = 3;
 338
 339         if (wlh > 3)
 340                 wlh = 3;
 341
 342         regs->lcdcon3 = S3C2410_LCDCON3_WDLY(wdly) |
 343                         S3C2410_LCDCON3_LINEBLANK(var->right_margin / 8) |
 344                         S3C2410_LCDCON3_HOZVAL(hs - 1);
 345
 346         regs->lcdcon4 = S3C2410_LCDCON4_WLH(wlh);
 347 }
 348
 349 /* s3c2410fb_calculate_tft_lcd_regs
 350  *
 351  * calculate register values from var settings
 352  */
 353 static void s3c2410fb_calculate_tft_lcd_regs(const struct fb_info *info,
 354                                              struct s3c2410fb_hw *regs)
 355 {
 356         const struct s3c2410fb_info *fbi = info->par;
 357         const struct fb_var_screeninfo *var = &info->var;
 358
 359         regs->lcdcon1 &= ~S3C2410_LCDCON1_MODEMASK;
 360
 361         switch (var->bits_per_pixel) {
 362         case 1:
 363                 regs->lcdcon1 |= S3C2410_LCDCON1_TFT1BPP;
 364                 break;
 365         case 2:
 366                 regs->lcdcon1 |= S3C2410_LCDCON1_TFT2BPP;
 367                 break;
 368         case 4:
 369                 regs->lcdcon1 |= S3C2410_LCDCON1_TFT4BPP;
 370                 break;
 371         case 8:
 372                 regs->lcdcon1 |= S3C2410_LCDCON1_TFT8BPP;
 373                 regs->lcdcon5 |= S3C2410_LCDCON5_BSWP |
 374                                  S3C2410_LCDCON5_FRM565;
 375                 regs->lcdcon5 &= ~S3C2410_LCDCON5_HWSWP;
 376                 break;
 377         case 16:
 378                 regs->lcdcon1 |= S3C2410_LCDCON1_TFT16BPP;
 379                 regs->lcdcon5 &= ~S3C2410_LCDCON5_BSWP;
 380                 regs->lcdcon5 |= S3C2410_LCDCON5_HWSWP;
 381                 break;
 382         case 32:
 383                 regs->lcdcon1 |= S3C2410_LCDCON1_TFT24BPP;
 384                 regs->lcdcon5 &= ~(S3C2410_LCDCON5_BSWP |
 385                                    S3C2410_LCDCON5_HWSWP |
 386                                    S3C2410_LCDCON5_BPP24BL);
 387                 break;
 388         default:
 389                 /* invalid pixel depth */
 390                 dev_err(fbi->dev, "invalid bpp %d\n",
 391                         var->bits_per_pixel);
 392         }
 393         /* update X/Y info */
 394         dprintk("setting vert: up=%d, low=%d, sync=%d\n",
 395                 var->upper_margin, var->lower_margin, var->vsync_len);
 396
 397         dprintk("setting horz: lft=%d, rt=%d, sync=%d\n",
 398                 var->left_margin, var->right_margin, var->hsync_len);
 399
 400         regs->lcdcon2 = S3C2410_LCDCON2_LINEVAL(var->yres - 1) |
 401                         S3C2410_LCDCON2_VBPD(var->upper_margin - 1) |
 402                         S3C2410_LCDCON2_VFPD(var->lower_margin - 1) |
 403                         S3C2410_LCDCON2_VSPW(var->vsync_len - 1);
 404
 405         regs->lcdcon3 = S3C2410_LCDCON3_HBPD(var->right_margin - 1) |
 406                         S3C2410_LCDCON3_HFPD(var->left_margin - 1) |
 407                         S3C2410_LCDCON3_HOZVAL(var->xres - 1);
 408
 409         regs->lcdcon4 = S3C2410_LCDCON4_HSPW(var->hsync_len - 1);
 410 }
 411
 412 /* s3c2410fb_activate_var
 413  *
 414  * activate (set) the controller from the given framebuffer
 415  * information
 416  */
 417 static void s3c2410fb_activate_var(struct fb_info *info)
 418 {
 419         struct s3c2410fb_info *fbi = info->par;
 420         void __iomem *regs = fbi->io;
 421         int type = fbi->regs.lcdcon1 & S3C2410_LCDCON1_TFT;
 422         struct fb_var_screeninfo *var = &info->var;
 423         int clkdiv = s3c2410fb_calc_pixclk(fbi, var->pixclock) / 2;
 424
 425         dprintk("%s: var->xres  = %d\n", __FUNCTION__, var->xres);
 426         dprintk("%s: var->yres  = %d\n", __FUNCTION__, var->yres);
 427         dprintk("%s: var->bpp   = %d\n", __FUNCTION__, var->bits_per_pixel);
 428
 429         if (type == S3C2410_LCDCON1_TFT) {
 430                 s3c2410fb_calculate_tft_lcd_regs(info, &fbi->regs);
 431                 --clkdiv;
 432                 if (clkdiv < 0)
 433                         clkdiv = 0;
 434         } else {
 435                 s3c2410fb_calculate_stn_lcd_regs(info, &fbi->regs);
 436                 if (clkdiv < 2)
 437                         clkdiv = 2;
 438         }
 439
 440         fbi->regs.lcdcon1 &= ~S3C2410_LCDCON1_CLKVAL(0x3ff);
 441         fbi->regs.lcdcon1 |=  S3C2410_LCDCON1_CLKVAL(clkdiv);
 442
 443         /* write new registers */
 444
 445         dprintk("new register set:\n");
 446         dprintk("lcdcon[1] = 0x%08lx\n", fbi->regs.lcdcon1);
 447         dprintk("lcdcon[2] = 0x%08lx\n", fbi->regs.lcdcon2);
 448         dprintk("lcdcon[3] = 0x%08lx\n", fbi->regs.lcdcon3);
 449         dprintk("lcdcon[4] = 0x%08lx\n", fbi->regs.lcdcon4);
 450         dprintk("lcdcon[5] = 0x%08lx\n", fbi->regs.lcdcon5);
 451
 452         writel(fbi->regs.lcdcon1 & ~S3C2410_LCDCON1_ENVID,
 453                 regs + S3C2410_LCDCON1);
 454         writel(fbi->regs.lcdcon2, regs + S3C2410_LCDCON2);
 455         writel(fbi->regs.lcdcon3, regs + S3C2410_LCDCON3);
 456         writel(fbi->regs.lcdcon4, regs + S3C2410_LCDCON4);
 457         writel(fbi->regs.lcdcon5, regs + S3C2410_LCDCON5);
 458
 459         /* set lcd address pointers */
 460         s3c2410fb_set_lcdaddr(info);
 461
 462         fbi->regs.lcdcon1 |= S3C2410_LCDCON1_ENVID,
 463         writel(fbi->regs.lcdcon1, regs + S3C2410_LCDCON1);
 464 }
 465
 466 /*
 467  *      s3c2410fb_set_par - Alters the hardware state.
 468  *      @info: frame buffer structure that represents a single frame buffer
 469  *
 470  */
 471 static int s3c2410fb_set_par(struct fb_info *info)
 472 {
 473         struct fb_var_screeninfo *var = &info->var;
 474
 475         switch (var->bits_per_pixel) {
 476         case 32:
 477         case 16:
 478         case 12:
 479                 info->fix.visual = FB_VISUAL_TRUECOLOR;
 480                 break;
 481         case 1:
 482                 info->fix.visual = FB_VISUAL_MONO01;
 483                 break;
 484         default:
 485                 info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
 486                 break;
 487         }
 488
 489         info->fix.line_length = (var->width * var->bits_per_pixel) / 8;
 490
 491         /* activate this new configuration */
 492
 493         s3c2410fb_activate_var(info);
 494         return 0;
 495 }
 496
 497 static void schedule_palette_update(struct s3c2410fb_info *fbi,
 498                                     unsigned int regno, unsigned int val)
 499 {
 500         unsigned long flags;
 501         unsigned long irqen;
 502         void __iomem *regs = fbi->io;
 503
 504         local_irq_save(flags);
 505
 506         fbi->palette_buffer[regno] = val;
 507
 508         if (!fbi->palette_ready) {
 509                 fbi->palette_ready = 1;
 510
 511                 /* enable IRQ */
 512                 irqen = readl(regs + S3C2410_LCDINTMSK);
 513                 irqen &= ~S3C2410_LCDINT_FRSYNC;
 514                 writel(irqen, regs + S3C2410_LCDINTMSK);
 515         }
 516
 517         local_irq_restore(flags);
 518 }
 519
 520 /* from pxafb.c */
 521 static inline unsigned int chan_to_field(unsigned int chan,
 522                                          struct fb_bitfield *bf)
 523 {
 524         chan &= 0xffff;
 525         chan >>= 16 - bf->length;
 526         return chan << bf->offset;
 527 }
 528
 529 static int s3c2410fb_setcolreg(unsigned regno,
 530                                unsigned red, unsigned green, unsigned blue,
 531                                unsigned transp, struct fb_info *info)
 532 {
 533         struct s3c2410fb_info *fbi = info->par;
 534         void __iomem *regs = fbi->io;
 535         unsigned int val;
 536
 537         /* dprintk("setcol: regno=%d, rgb=%d,%d,%d\n",
 538                    regno, red, green, blue); */
 539
 540         switch (info->fix.visual) {
 541         case FB_VISUAL_TRUECOLOR:
 542                 /* true-colour, use pseudo-palette */
 543
 544                 if (regno < 16) {
 545                         u32 *pal = info->pseudo_palette;
 546
 547                         val  = chan_to_field(red,   &info->var.red);
 548                         val |= chan_to_field(green, &info->var.green);
 549                         val |= chan_to_field(blue,  &info->var.blue);
 550
 551                         pal[regno] = val;
 552                 }
 553                 break;
 554
 555         case FB_VISUAL_PSEUDOCOLOR:
 556                 if (regno < 256) {
 557                         /* currently assume RGB 5-6-5 mode */
 558
 559                         val  = (red   >>  0) & 0xf800;
 560                         val |= (green >>  5) & 0x07e0;
 561                         val |= (blue  >> 11) & 0x001f;
 562
 563                         writel(val, regs + S3C2410_TFTPAL(regno));
 564                         schedule_palette_update(fbi, regno, val);
 565                 }
 566
 567                 break;
 568
 569         default:
 570                 return 1;       /* unknown type */
 571         }
 572
 573         return 0;
 574 }
 575
 576 /*
 577  *      s3c2410fb_blank
 578  *      @blank_mode: the blank mode we want.
 579  *      @info: frame buffer structure that represents a single frame buffer
 580  *
 581  *      Blank the screen if blank_mode != 0, else unblank. Return 0 if
 582  *      blanking succeeded, != 0 if un-/blanking failed due to e.g. a
 583  *      video mode which doesn't support it. Implements VESA suspend
 584  *      and powerdown modes on hardware that supports disabling hsync/vsync:
 585  *      blank_mode == 2: suspend vsync
 586  *      blank_mode == 3: suspend hsync
 587  *      blank_mode == 4: powerdown
 588  *
 589  *      Returns negative errno on error, or zero on success.
 590  *
 591  */
 592 static int s3c2410fb_blank(int blank_mode, struct fb_info *info)
 593 {
 594         struct s3c2410fb_info *fbi = info->par;
 595         void __iomem *regs = fbi->io;
 596
 597         dprintk("blank(mode=%d, info=%p)\n", blank_mode, info);
 598
 599         if (blank_mode == FB_BLANK_UNBLANK)
 600                 writel(0x0, regs + S3C2410_TPAL);
 601         else {
 602                 dprintk("setting TPAL to output 0x000000\n");
 603                 writel(S3C2410_TPAL_EN, regs + S3C2410_TPAL);
 604         }
 605
 606         return 0;
 607 }
 608
 609 static int s3c2410fb_debug_show(struct device *dev,
 610                                 struct device_attribute *attr, char *buf)
 611 {
 612         return snprintf(buf, PAGE_SIZE, "%s\n", debug ? "on" : "off");
 613 }
 614
 615 static int s3c2410fb_debug_store(struct device *dev,
 616                                  struct device_attribute *attr,
 617                                  const char *buf, size_t len)
 618 {
 619         if (len < 1)
 620                 return -EINVAL;
 621
 622         if (strnicmp(buf, "on", 2) == 0 ||
 623             strnicmp(buf, "1", 1) == 0) {
 624                 debug = 1;
 625                 printk(KERN_DEBUG "s3c2410fb: Debug On");
 626         } else if (strnicmp(buf, "off", 3) == 0 ||
 627                    strnicmp(buf, "0", 1) == 0) {
 628                 debug = 0;
 629                 printk(KERN_DEBUG "s3c2410fb: Debug Off");
 630         } else {
 631                 return -EINVAL;
 632         }
 633
 634         return len;
 635 }
 636
 637 static DEVICE_ATTR(debug, 0666, s3c2410fb_debug_show, s3c2410fb_debug_store);
 638
 639 static struct fb_ops s3c2410fb_ops = {
 640         .owner          = THIS_MODULE,
 641         .fb_check_var   = s3c2410fb_check_var,
 642         .fb_set_par     = s3c2410fb_set_par,
 643         .fb_blank       = s3c2410fb_blank,
 644         .fb_setcolreg   = s3c2410fb_setcolreg,
 645         .fb_fillrect    = cfb_fillrect,
 646         .fb_copyarea    = cfb_copyarea,
 647         .fb_imageblit   = cfb_imageblit,
 648 };
 649
 650 /*
 651  * s3c2410fb_map_video_memory():
 652  *      Allocates the DRAM memory for the frame buffer.  This buffer is
 653  *      remapped into a non-cached, non-buffered, memory region to
 654  *      allow palette and pixel writes to occur without flushing the
 655  *      cache.  Once this area is remapped, all virtual memory
 656  *      access to the video memory should occur at the new region.
 657  */
 658 static int __init s3c2410fb_map_video_memory(struct fb_info *info)
 659 {
 660         struct s3c2410fb_info *fbi = info->par;
 661         dma_addr_t map_dma;
 662         unsigned map_size = PAGE_ALIGN(info->fix.smem_len);
 663
 664         dprintk("map_video_memory(fbi=%p)\n", fbi);
 665
 666         info->screen_base = dma_alloc_writecombine(fbi->dev, map_size,
 667                                                    &map_dma, GFP_KERNEL);
 668
 669         if (info->screen_base) {
 670                 /* prevent initial garbage on screen */
 671                 dprintk("map_video_memory: clear %p:%08x\n",
 672                         info->screen_base, map_size);
 673                 memset(info->screen_base, 0xf0, map_size);
 674
 675                 info->fix.smem_start = map_dma;
 676
 677                 dprintk("map_video_memory: dma=%08lx cpu=%p size=%08x\n",
 678                         info->fix.smem_start, info->screen_base, map_size);
 679         }
 680
 681         return info->screen_base ? 0 : -ENOMEM;
 682 }
 683
 684 static inline void s3c2410fb_unmap_video_memory(struct fb_info *info)
 685 {
 686         struct s3c2410fb_info *fbi = info->par;
 687
 688         dma_free_writecombine(fbi->dev, PAGE_ALIGN(info->fix.smem_len),
 689                               info->screen_base, info->fix.smem_start);
 690 }
 691
 692 static inline void modify_gpio(void __iomem *reg,
 693                                unsigned long set, unsigned long mask)
 694 {
 695         unsigned long tmp;
 696
 697         tmp = readl(reg) & ~mask;
 698         writel(tmp | set, reg);
 699 }
 700
 701 /*
 702  * s3c2410fb_init_registers - Initialise all LCD-related registers
 703  */
 704 static int s3c2410fb_init_registers(struct fb_info *info)
 705 {
 706         struct s3c2410fb_info *fbi = info->par;
 707         struct s3c2410fb_mach_info *mach_info = fbi->dev->platform_data;
 708         unsigned long flags;
 709         void __iomem *regs = fbi->io;
 710
 711         /* Initialise LCD with values from haret */
 712
 713         local_irq_save(flags);
 714
 715         /* modify the gpio(s) with interrupts set (bjd) */
 716
 717         modify_gpio(S3C2410_GPCUP,  mach_info->gpcup,  mach_info->gpcup_mask);
 718         modify_gpio(S3C2410_GPCCON, mach_info->gpccon, mach_info->gpccon_mask);
 719         modify_gpio(S3C2410_GPDUP,  mach_info->gpdup,  mach_info->gpdup_mask);
 720         modify_gpio(S3C2410_GPDCON, mach_info->gpdcon, mach_info->gpdcon_mask);
 721
 722         local_irq_restore(flags);
 723
 724         dprintk("LPCSEL    = 0x%08lx\n", mach_info->lpcsel);
 725         writel(mach_info->lpcsel, regs + S3C2410_LPCSEL);
 726
 727         dprintk("replacing TPAL %08x\n", readl(regs + S3C2410_TPAL));
 728
 729         /* ensure temporary palette disabled */
 730         writel(0x00, regs + S3C2410_TPAL);
 731
 732         return 0;
 733 }
 734
 735 static void s3c2410fb_write_palette(struct s3c2410fb_info *fbi)
 736 {
 737         unsigned int i;
 738         void __iomem *regs = fbi->io;
 739
 740         fbi->palette_ready = 0;
 741
 742         for (i = 0; i < 256; i++) {
 743                 unsigned long ent = fbi->palette_buffer[i];
 744                 if (ent == PALETTE_BUFF_CLEAR)
 745                         continue;
 746
 747                 writel(ent, regs + S3C2410_TFTPAL(i));
 748
 749                 /* it seems the only way to know exactly
 750                  * if the palette wrote ok, is to check
 751                  * to see if the value verifies ok
 752                  */
 753
 754                 if (readw(regs + S3C2410_TFTPAL(i)) == ent)
 755                         fbi->palette_buffer[i] = PALETTE_BUFF_CLEAR;
 756                 else
 757                         fbi->palette_ready = 1;   /* retry */
 758         }
 759 }
 760
 761 static irqreturn_t s3c2410fb_irq(int irq, void *dev_id)
 762 {
 763         struct s3c2410fb_info *fbi = dev_id;
 764         void __iomem *regs = fbi->io;
 765         unsigned long lcdirq = readl(regs + S3C2410_LCDINTPND);
 766
 767         if (lcdirq & S3C2410_LCDINT_FRSYNC) {
 768                 if (fbi->palette_ready)
 769                         s3c2410fb_write_palette(fbi);
 770
 771                 writel(S3C2410_LCDINT_FRSYNC, regs + S3C2410_LCDINTPND);
 772                 writel(S3C2410_LCDINT_FRSYNC, regs + S3C2410_LCDSRCPND);
 773         }
 774
 775         return IRQ_HANDLED;
 776 }
 777
 778 static char driver_name[] = "s3c2410fb";
 779
 780 static int __init s3c2410fb_probe(struct platform_device *pdev)
 781 {
 782         struct s3c2410fb_info *info;
 783         struct s3c2410fb_display *display;
 784         struct fb_info *fbinfo;
 785         struct s3c2410fb_mach_info *mach_info;
 786         struct resource *res;
 787         int ret;
 788         int irq;
 789         int i;
 790         int size;
 791         u32 lcdcon1;
 792
 793         mach_info = pdev->dev.platform_data;
 794         if (mach_info == NULL) {
 795                 dev_err(&pdev->dev,
 796                         "no platform data for lcd, cannot attach\n");
 797                 return -EINVAL;
 798         }
 799
 800         display = mach_info->displays + mach_info->default_display;
 801
 802         irq = platform_get_irq(pdev, 0);
 803         if (irq < 0) {
 804                 dev_err(&pdev->dev, "no irq for device\n");
 805                 return -ENOENT;
 806         }
 807
 808         fbinfo = framebuffer_alloc(sizeof(struct s3c2410fb_info), &pdev->dev);
 809         if (!fbinfo)
 810                 return -ENOMEM;
 811
 812         platform_set_drvdata(pdev, fbinfo);
 813
 814         info = fbinfo->par;
 815         info->dev = &pdev->dev;
 816
 817         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 818         if (res == NULL) {
 819                 dev_err(&pdev->dev, "failed to get memory registers\n");
 820                 ret = -ENXIO;
 821                 goto dealloc_fb;
 822         }
 823
 824         size = (res->end - res->start) + 1;
 825         info->mem = request_mem_region(res->start, size, pdev->name);
 826         if (info->mem == NULL) {
 827                 dev_err(&pdev->dev, "failed to get memory region\n");
 828                 ret = -ENOENT;
 829                 goto dealloc_fb;
 830         }
 831
 832         info->io = ioremap(res->start, size);
 833         if (info->io == NULL) {
 834                 dev_err(&pdev->dev, "ioremap() of registers failed\n");
 835                 ret = -ENXIO;
 836                 goto release_mem;
 837         }
 838
 839         dprintk("devinit\n");
 840
 841         strcpy(fbinfo->fix.id, driver_name);
 842
 843         /* Stop the video */
 844         lcdcon1 = readl(info->io + S3C2410_LCDCON1);
 845         writel(lcdcon1 & ~S3C2410_LCDCON1_ENVID, info->io + S3C2410_LCDCON1);
 846
 847         fbinfo->fix.type            = FB_TYPE_PACKED_PIXELS;
 848         fbinfo->fix.type_aux        = 0;
 849         fbinfo->fix.xpanstep        = 0;
 850         fbinfo->fix.ypanstep        = 0;
 851         fbinfo->fix.ywrapstep       = 0;
 852         fbinfo->fix.accel           = FB_ACCEL_NONE;
 853
 854         fbinfo->var.nonstd          = 0;
 855         fbinfo->var.activate        = FB_ACTIVATE_NOW;
 856         fbinfo->var.accel_flags     = 0;
 857         fbinfo->var.vmode           = FB_VMODE_NONINTERLACED;
 858
 859         fbinfo->fbops               = &s3c2410fb_ops;
 860         fbinfo->flags               = FBINFO_FLAG_DEFAULT;
 861         fbinfo->pseudo_palette      = &info->pseudo_pal;
 862
 863         for (i = 0; i < 256; i++)
 864                 info->palette_buffer[i] = PALETTE_BUFF_CLEAR;
 865
 866         ret = request_irq(irq, s3c2410fb_irq, IRQF_DISABLED, pdev->name, info);
 867         if (ret) {
 868                 dev_err(&pdev->dev, "cannot get irq %d - err %d\n", irq, ret);
 869                 ret = -EBUSY;
 870                 goto release_regs;
 871         }
 872
 873         info->clk = clk_get(NULL, "lcd");
 874         if (!info->clk || IS_ERR(info->clk)) {
 875                 printk(KERN_ERR "failed to get lcd clock source\n");
 876                 ret = -ENOENT;
 877                 goto release_irq;
 878         }
 879
 880         clk_enable(info->clk);
 881         dprintk("got and enabled clock\n");
 882
 883         msleep(1);
 884
 885         /* find maximum required memory size for display */
 886         for (i = 0; i < mach_info->num_displays; i++) {
 887                 unsigned long smem_len = mach_info->displays[i].xres;
 888
 889                 smem_len *= mach_info->displays[i].yres;
 890                 smem_len *= mach_info->displays[i].bpp;
 891                 smem_len >>= 3;
 892                 if (fbinfo->fix.smem_len < smem_len)
 893                         fbinfo->fix.smem_len = smem_len;
 894         }
 895
 896         /* Initialize video memory */
 897         ret = s3c2410fb_map_video_memory(fbinfo);
 898         if (ret) {
 899                 printk(KERN_ERR "Failed to allocate video RAM: %d\n", ret);
 900                 ret = -ENOMEM;
 901                 goto release_clock;
 902         }
 903
 904         dprintk("got video memory\n");
 905
 906         fbinfo->var.xres = display->xres;
 907         fbinfo->var.yres = display->yres;
 908         fbinfo->var.bits_per_pixel = display->bpp;
 909
 910         s3c2410fb_init_registers(fbinfo);
 911
 912         s3c2410fb_check_var(&fbinfo->var, fbinfo);
 913
 914         ret = register_framebuffer(fbinfo);
 915         if (ret < 0) {
 916                 printk(KERN_ERR "Failed to register framebuffer device: %d\n",
 917                         ret);
 918                 goto free_video_memory;
 919         }
 920
 921         /* create device files */
 922         device_create_file(&pdev->dev, &dev_attr_debug);
 923
 924         printk(KERN_INFO "fb%d: %s frame buffer device\n",
 925                 fbinfo->node, fbinfo->fix.id);
 926
 927         return 0;
 928
 929 free_video_memory:
 930         s3c2410fb_unmap_video_memory(fbinfo);
 931 release_clock:
 932         clk_disable(info->clk);
 933         clk_put(info->clk);
 934 release_irq:
 935         free_irq(irq, info);
 936 release_regs:
 937         iounmap(info->io);
 938 release_mem:
 939         release_resource(info->mem);
 940         kfree(info->mem);
 941 dealloc_fb:
 942         platform_set_drvdata(pdev, NULL);
 943         framebuffer_release(fbinfo);
 944         return ret;
 945 }
 946
 947 /* s3c2410fb_stop_lcd
 948  *
 949  * shutdown the lcd controller
 950  */
 951 static void s3c2410fb_stop_lcd(struct s3c2410fb_info *fbi)
 952 {
 953         unsigned long flags;
 954
 955         local_irq_save(flags);
 956
 957         fbi->regs.lcdcon1 &= ~S3C2410_LCDCON1_ENVID;
 958         writel(fbi->regs.lcdcon1, fbi->io + S3C2410_LCDCON1);
 959
 960         local_irq_restore(flags);
 961 }
 962
 963 /*
 964  *  Cleanup
 965  */
 966 static int s3c2410fb_remove(struct platform_device *pdev)
 967 {
 968         struct fb_info *fbinfo = platform_get_drvdata(pdev);
 969         struct s3c2410fb_info *info = fbinfo->par;
 970         int irq;
 971
 972         unregister_framebuffer(fbinfo);
 973
 974         s3c2410fb_stop_lcd(info);
 975         msleep(1);
 976
 977         s3c2410fb_unmap_video_memory(fbinfo);
 978
 979         if (info->clk) {
 980                 clk_disable(info->clk);
 981                 clk_put(info->clk);
 982                 info->clk = NULL;
 983         }
 984
 985         irq = platform_get_irq(pdev, 0);
 986         free_irq(irq, info);
 987
 988         iounmap(info->io);
 989
 990         release_resource(info->mem);
 991         kfree(info->mem);
 992
 993         platform_set_drvdata(pdev, NULL);
 994         framebuffer_release(fbinfo);
 995
 996         return 0;
 997 }
 998
 999 #ifdef CONFIG_PM
1000
1001 /* suspend and resume support for the lcd controller */
1002 static int s3c2410fb_suspend(struct platform_device *dev, pm_message_t state)
1003 {
1004         struct fb_info     *fbinfo = platform_get_drvdata(dev);
1005         struct s3c2410fb_info *info = fbinfo->par;
1006
1007         s3c2410fb_stop_lcd(info);
1008
1009         /* sleep before disabling the clock, we need to ensure
1010          * the LCD DMA engine is not going to get back on the bus
1011          * before the clock goes off again (bjd) */
1012
1013         msleep(1);
1014         clk_disable(info->clk);
1015
1016         return 0;
1017 }
1018
1019 static int s3c2410fb_resume(struct platform_device *dev)
1020 {
1021         struct fb_info     *fbinfo = platform_get_drvdata(dev);
1022         struct s3c2410fb_info *info = fbinfo->par;
1023
1024         clk_enable(info->clk);
1025         msleep(1);
1026
1027         s3c2410fb_init_registers(info);
1028
1029         return 0;
1030 }
1031
1032 #else
1033 #define s3c2410fb_suspend NULL
1034 #define s3c2410fb_resume  NULL
1035 #endif
1036
1037 static struct platform_driver s3c2410fb_driver = {
1038         .probe          = s3c2410fb_probe,
1039         .remove         = s3c2410fb_remove,
1040         .suspend        = s3c2410fb_suspend,
1041         .resume         = s3c2410fb_resume,
1042         .driver         = {
1043                 .name   = "s3c2410-lcd",
1044                 .owner  = THIS_MODULE,
1045         },
1046 };
1047
1048 int __init s3c2410fb_init(void)
1049 {
1050         return platform_driver_register(&s3c2410fb_driver);
1051 }
1052
1053 static void __exit s3c2410fb_cleanup(void)
1054 {
1055         platform_driver_unregister(&s3c2410fb_driver);
1056 }
1057
1058 module_init(s3c2410fb_init);
1059 module_exit(s3c2410fb_cleanup);
1060
1061 MODULE_AUTHOR("Arnaud Patard <arnaud.patard@rtp-net.org>, "
1062               "Ben Dooks <ben-linux@fluff.org>");
1063 MODULE_DESCRIPTION("Framebuffer driver for the s3c2410");
1064 MODULE_LICENSE("GPL");