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   1 /*
   2  * linux/drivers/video/s3c2410fb.c
   3  *      Copyright (c) Arnaud Patard, Ben Dooks
   4  *
   5  * This file is subject to the terms and conditions of the GNU General Public
   6  * License.  See the file COPYING in the main directory of this archive for
   7  * more details.
   8  *
   9  *          S3C2410 LCD Controller Frame Buffer Driver
  10  *          based on skeletonfb.c, sa1100fb.c and others
  11  *
  12  * ChangeLog
  13  * 2005-04-07: Arnaud Patard <arnaud.patard@rtp-net.org>
  14  *      - u32 state -> pm_message_t state
  15  *      - S3C2410_{VA,SZ}_LCD -> S3C24XX
  16  *
  17  * 2005-03-15: Arnaud Patard <arnaud.patard@rtp-net.org>
  18  *      - Removed the ioctl
  19  *      - use readl/writel instead of __raw_writel/__raw_readl
  20  *
  21  * 2004-12-04: Arnaud Patard <arnaud.patard@rtp-net.org>
  22  *      - Added the possibility to set on or off the
  23  *      debugging messages
  24  *      - Replaced 0 and 1 by on or off when reading the
  25  *      /sys files
  26  *
  27  * 2005-03-23: Ben Dooks <ben-linux@fluff.org>
  28  *      - added non 16bpp modes
  29  *      - updated platform information for range of x/y/bpp
  30  *      - add code to ensure palette is written correctly
  31  *      - add pixel clock divisor control
  32  *
  33  * 2004-11-11: Arnaud Patard <arnaud.patard@rtp-net.org>
  34  *      - Removed the use of currcon as it no more exists
  35  *      - Added LCD power sysfs interface
  36  *
  37  * 2004-11-03: Ben Dooks <ben-linux@fluff.org>
  38  *      - minor cleanups
  39  *      - add suspend/resume support
  40  *      - s3c2410fb_setcolreg() not valid in >8bpp modes
  41  *      - removed last CONFIG_FB_S3C2410_FIXED
  42  *      - ensure lcd controller stopped before cleanup
  43  *      - added sysfs interface for backlight power
  44  *      - added mask for gpio configuration
  45  *      - ensured IRQs disabled during GPIO configuration
  46  *      - disable TPAL before enabling video
  47  *
  48  * 2004-09-20: Arnaud Patard <arnaud.patard@rtp-net.org>
  49  *      - Suppress command line options
  50  *
  51  * 2004-09-15: Arnaud Patard <arnaud.patard@rtp-net.org>
  52  *      - code cleanup
  53  *
  54  * 2004-09-07: Arnaud Patard <arnaud.patard@rtp-net.org>
  55  *      - Renamed from h1940fb.c to s3c2410fb.c
  56  *      - Add support for different devices
  57  *      - Backlight support
  58  *
  59  * 2004-09-05: Herbert Pötzl <herbert@13thfloor.at>
  60  *      - added clock (de-)allocation code
  61  *      - added fixem fbmem option
  62  *
  63  * 2004-07-27: Arnaud Patard <arnaud.patard@rtp-net.org>
  64  *      - code cleanup
  65  *      - added a forgotten return in h1940fb_init
  66  *
  67  * 2004-07-19: Herbert Pötzl <herbert@13thfloor.at>
  68  *      - code cleanup and extended debugging
  69  *
  70  * 2004-07-15: Arnaud Patard <arnaud.patard@rtp-net.org>
  71  *      - First version
  72  */
  73
  74 #include <linux/module.h>
  75 #include <linux/kernel.h>
  76 #include <linux/errno.h>
  77 #include <linux/string.h>
  78 #include <linux/mm.h>
  79 #include <linux/slab.h>
  80 #include <linux/delay.h>
  81 #include <linux/fb.h>
  82 #include <linux/init.h>
  83 #include <linux/dma-mapping.h>
  84 #include <linux/interrupt.h>
  85 #include <linux/platform_device.h>
  86 #include <linux/clk.h>
  87
  88 #include <asm/io.h>
  89 #include <asm/div64.h>
  90
  91 #include <asm/mach/map.h>
  92 #include <asm/arch/regs-lcd.h>
  93 #include <asm/arch/regs-gpio.h>
  94 #include <asm/arch/fb.h>
  95
  96 #ifdef CONFIG_PM
  97 #include <linux/pm.h>
  98 #endif
  99
 100 #include "s3c2410fb.h"
 101
 102 /* Debugging stuff */
 103 #ifdef CONFIG_FB_S3C2410_DEBUG
 104 static int debug        = 1;
 105 #else
 106 static int debug        = 0;
 107 #endif
 108
 109 #define dprintk(msg...) if (debug) { printk(KERN_DEBUG "s3c2410fb: " msg); }
 110
 111 /* useful functions */
 112
 113 static int is_s3c2412(struct s3c2410fb_info *fbi)
 114 {
 115         return (fbi->drv_type == DRV_S3C2412);
 116 }
 117
 118 /* s3c2410fb_set_lcdaddr
 119  *
 120  * initialise lcd controller address pointers
 121  */
 122 static void s3c2410fb_set_lcdaddr(struct fb_info *info)
 123 {
 124         unsigned long saddr1, saddr2, saddr3;
 125         struct s3c2410fb_info *fbi = info->par;
 126         void __iomem *regs = fbi->io;
 127
 128         saddr1  = info->fix.smem_start >> 1;
 129         saddr2  = info->fix.smem_start;
 130         saddr2 += info->fix.line_length * info->var.yres;
 131         saddr2 >>= 1;
 132
 133         saddr3 = S3C2410_OFFSIZE(0) |
 134                  S3C2410_PAGEWIDTH((info->fix.line_length / 2) & 0x3ff);
 135
 136         dprintk("LCDSADDR1 = 0x%08lx\n", saddr1);
 137         dprintk("LCDSADDR2 = 0x%08lx\n", saddr2);
 138         dprintk("LCDSADDR3 = 0x%08lx\n", saddr3);
 139
 140         writel(saddr1, regs + S3C2410_LCDSADDR1);
 141         writel(saddr2, regs + S3C2410_LCDSADDR2);
 142         writel(saddr3, regs + S3C2410_LCDSADDR3);
 143 }
 144
 145 /* s3c2410fb_calc_pixclk()
 146  *
 147  * calculate divisor for clk->pixclk
 148  */
 149 static unsigned int s3c2410fb_calc_pixclk(struct s3c2410fb_info *fbi,
 150                                           unsigned long pixclk)
 151 {
 152         unsigned long clk = clk_get_rate(fbi->clk);
 153         unsigned long long div;
 154
 155         /* pixclk is in picoseconds, our clock is in Hz
 156          *
 157          * Hz -> picoseconds is / 10^-12
 158          */
 159
 160         div = (unsigned long long)clk * pixclk;
 161         div >>= 12;                     /* div / 2^12 */
 162         do_div(div, 625 * 625UL * 625); /* div / 5^12 */
 163
 164         dprintk("pixclk %ld, divisor is %ld\n", pixclk, (long)div);
 165         return div;
 166 }
 167
 168 /*
 169  *      s3c2410fb_check_var():
 170  *      Get the video params out of 'var'. If a value doesn't fit, round it up,
 171  *      if it's too big, return -EINVAL.
 172  *
 173  */
 174 static int s3c2410fb_check_var(struct fb_var_screeninfo *var,
 175                                struct fb_info *info)
 176 {
 177         struct s3c2410fb_info *fbi = info->par;
 178         struct s3c2410fb_mach_info *mach_info = fbi->dev->platform_data;
 179         struct s3c2410fb_display *display = NULL;
 180         struct s3c2410fb_display *default_display = mach_info->displays +
 181                                                     mach_info->default_display;
 182         int type = default_display->type;
 183         unsigned i;
 184
 185         dprintk("check_var(var=%p, info=%p)\n", var, info);
 186
 187         /* validate x/y resolution */
 188         /* choose default mode if possible */
 189         if (var->yres == default_display->yres &&
 190             var->xres == default_display->xres &&
 191             var->bits_per_pixel == default_display->bpp)
 192                 display = default_display;
 193         else
 194                 for (i = 0; i < mach_info->num_displays; i++)
 195                         if (type == mach_info->displays[i].type &&
 196                             var->yres == mach_info->displays[i].yres &&
 197                             var->xres == mach_info->displays[i].xres &&
 198                             var->bits_per_pixel == mach_info->displays[i].bpp) {
 199                                 display = mach_info->displays + i;
 200                                 break;
 201                         }
 202
 203         if (!display) {
 204                 dprintk("wrong resolution or depth %dx%d at %d bpp\n",
 205                         var->xres, var->yres, var->bits_per_pixel);
 206                 return -EINVAL;
 207         }
 208
 209         /* it is always the size as the display */
 210         var->xres_virtual = display->xres;
 211         var->yres_virtual = display->yres;
 212         var->height = display->height;
 213         var->width = display->width;
 214
 215         /* copy lcd settings */
 216         var->pixclock = display->pixclock;
 217         var->left_margin = display->left_margin;
 218         var->right_margin = display->right_margin;
 219         var->upper_margin = display->upper_margin;
 220         var->lower_margin = display->lower_margin;
 221         var->vsync_len = display->vsync_len;
 222         var->hsync_len = display->hsync_len;
 223
 224         fbi->regs.lcdcon5 = display->lcdcon5;
 225         /* set display type */
 226         fbi->regs.lcdcon1 = display->type;
 227
 228         var->transp.offset = 0;
 229         var->transp.length = 0;
 230         /* set r/g/b positions */
 231         switch (var->bits_per_pixel) {
 232         case 1:
 233         case 2:
 234         case 4:
 235                 var->red.offset = 0;
 236                 var->red.length = var->bits_per_pixel;
 237                 var->green      = var->red;
 238                 var->blue       = var->red;
 239                 break;
 240         case 8:
 241                 if (display->type != S3C2410_LCDCON1_TFT) {
 242                         /* 8 bpp 332 */
 243                         var->red.length         = 3;
 244                         var->red.offset         = 5;
 245                         var->green.length       = 3;
 246                         var->green.offset       = 2;
 247                         var->blue.length        = 2;
 248                         var->blue.offset        = 0;
 249                 } else {
 250                         var->red.offset         = 0;
 251                         var->red.length         = 8;
 252                         var->green              = var->red;
 253                         var->blue               = var->red;
 254                 }
 255                 break;
 256         case 12:
 257                 /* 12 bpp 444 */
 258                 var->red.length         = 4;
 259                 var->red.offset         = 8;
 260                 var->green.length       = 4;
 261                 var->green.offset       = 4;
 262                 var->blue.length        = 4;
 263                 var->blue.offset        = 0;
 264                 break;
 265
 266         default:
 267         case 16:
 268                 if (display->lcdcon5 & S3C2410_LCDCON5_FRM565) {
 269                         /* 16 bpp, 565 format */
 270                         var->red.offset         = 11;
 271                         var->green.offset       = 5;
 272                         var->blue.offset        = 0;
 273                         var->red.length         = 5;
 274                         var->green.length       = 6;
 275                         var->blue.length        = 5;
 276                 } else {
 277                         /* 16 bpp, 5551 format */
 278                         var->red.offset         = 11;
 279                         var->green.offset       = 6;
 280                         var->blue.offset        = 1;
 281                         var->red.length         = 5;
 282                         var->green.length       = 5;
 283                         var->blue.length        = 5;
 284                 }
 285                 break;
 286         case 32:
 287                 /* 24 bpp 888 and 8 dummy */
 288                 var->red.length         = 8;
 289                 var->red.offset         = 16;
 290                 var->green.length       = 8;
 291                 var->green.offset       = 8;
 292                 var->blue.length        = 8;
 293                 var->blue.offset        = 0;
 294                 break;
 295         }
 296         return 0;
 297 }
 298
 299 /* s3c2410fb_calculate_stn_lcd_regs
 300  *
 301  * calculate register values from var settings
 302  */
 303 static void s3c2410fb_calculate_stn_lcd_regs(const struct fb_info *info,
 304                                              struct s3c2410fb_hw *regs)
 305 {
 306         const struct s3c2410fb_info *fbi = info->par;
 307         const struct fb_var_screeninfo *var = &info->var;
 308         int type = regs->lcdcon1 & ~S3C2410_LCDCON1_TFT;
 309         int hs = var->xres >> 2;
 310         unsigned wdly = (var->left_margin >> 4) - 1;
 311         unsigned wlh = (var->hsync_len >> 4) - 1;
 312
 313         if (type != S3C2410_LCDCON1_STN4)
 314                 hs >>= 1;
 315
 316         switch (var->bits_per_pixel) {
 317         case 1:
 318                 regs->lcdcon1 |= S3C2410_LCDCON1_STN1BPP;
 319                 break;
 320         case 2:
 321                 regs->lcdcon1 |= S3C2410_LCDCON1_STN2GREY;
 322                 break;
 323         case 4:
 324                 regs->lcdcon1 |= S3C2410_LCDCON1_STN4GREY;
 325                 break;
 326         case 8:
 327                 regs->lcdcon1 |= S3C2410_LCDCON1_STN8BPP;
 328                 hs *= 3;
 329                 break;
 330         case 12:
 331                 regs->lcdcon1 |= S3C2410_LCDCON1_STN12BPP;
 332                 hs *= 3;
 333                 break;
 334
 335         default:
 336                 /* invalid pixel depth */
 337                 dev_err(fbi->dev, "invalid bpp %d\n",
 338                         var->bits_per_pixel);
 339         }
 340         /* update X/Y info */
 341         dprintk("setting horz: lft=%d, rt=%d, sync=%d\n",
 342                 var->left_margin, var->right_margin, var->hsync_len);
 343
 344         regs->lcdcon2 = S3C2410_LCDCON2_LINEVAL(var->yres - 1);
 345
 346         if (wdly > 3)
 347                 wdly = 3;
 348
 349         if (wlh > 3)
 350                 wlh = 3;
 351
 352         regs->lcdcon3 = S3C2410_LCDCON3_WDLY(wdly) |
 353                         S3C2410_LCDCON3_LINEBLANK(var->right_margin / 8) |
 354                         S3C2410_LCDCON3_HOZVAL(hs - 1);
 355
 356         regs->lcdcon4 = S3C2410_LCDCON4_WLH(wlh);
 357 }
 358
 359 /* s3c2410fb_calculate_tft_lcd_regs
 360  *
 361  * calculate register values from var settings
 362  */
 363 static void s3c2410fb_calculate_tft_lcd_regs(const struct fb_info *info,
 364                                              struct s3c2410fb_hw *regs)
 365 {
 366         const struct s3c2410fb_info *fbi = info->par;
 367         const struct fb_var_screeninfo *var = &info->var;
 368
 369         switch (var->bits_per_pixel) {
 370         case 1:
 371                 regs->lcdcon1 |= S3C2410_LCDCON1_TFT1BPP;
 372                 break;
 373         case 2:
 374                 regs->lcdcon1 |= S3C2410_LCDCON1_TFT2BPP;
 375                 break;
 376         case 4:
 377                 regs->lcdcon1 |= S3C2410_LCDCON1_TFT4BPP;
 378                 break;
 379         case 8:
 380                 regs->lcdcon1 |= S3C2410_LCDCON1_TFT8BPP;
 381                 regs->lcdcon5 |= S3C2410_LCDCON5_BSWP |
 382                                  S3C2410_LCDCON5_FRM565;
 383                 regs->lcdcon5 &= ~S3C2410_LCDCON5_HWSWP;
 384                 break;
 385         case 16:
 386                 regs->lcdcon1 |= S3C2410_LCDCON1_TFT16BPP;
 387                 regs->lcdcon5 &= ~S3C2410_LCDCON5_BSWP;
 388                 regs->lcdcon5 |= S3C2410_LCDCON5_HWSWP;
 389                 break;
 390         case 32:
 391                 regs->lcdcon1 |= S3C2410_LCDCON1_TFT24BPP;
 392                 regs->lcdcon5 &= ~(S3C2410_LCDCON5_BSWP |
 393                                    S3C2410_LCDCON5_HWSWP |
 394                                    S3C2410_LCDCON5_BPP24BL);
 395                 break;
 396         default:
 397                 /* invalid pixel depth */
 398                 dev_err(fbi->dev, "invalid bpp %d\n",
 399                         var->bits_per_pixel);
 400         }
 401         /* update X/Y info */
 402         dprintk("setting vert: up=%d, low=%d, sync=%d\n",
 403                 var->upper_margin, var->lower_margin, var->vsync_len);
 404
 405         dprintk("setting horz: lft=%d, rt=%d, sync=%d\n",
 406                 var->left_margin, var->right_margin, var->hsync_len);
 407
 408         regs->lcdcon2 = S3C2410_LCDCON2_LINEVAL(var->yres - 1) |
 409                         S3C2410_LCDCON2_VBPD(var->upper_margin - 1) |
 410                         S3C2410_LCDCON2_VFPD(var->lower_margin - 1) |
 411                         S3C2410_LCDCON2_VSPW(var->vsync_len - 1);
 412
 413         regs->lcdcon3 = S3C2410_LCDCON3_HBPD(var->right_margin - 1) |
 414                         S3C2410_LCDCON3_HFPD(var->left_margin - 1) |
 415                         S3C2410_LCDCON3_HOZVAL(var->xres - 1);
 416
 417         regs->lcdcon4 = S3C2410_LCDCON4_HSPW(var->hsync_len - 1);
 418 }
 419
 420 /* s3c2410fb_activate_var
 421  *
 422  * activate (set) the controller from the given framebuffer
 423  * information
 424  */
 425 static void s3c2410fb_activate_var(struct fb_info *info)
 426 {
 427         struct s3c2410fb_info *fbi = info->par;
 428         void __iomem *regs = fbi->io;
 429         int type = fbi->regs.lcdcon1 & S3C2410_LCDCON1_TFT;
 430         struct fb_var_screeninfo *var = &info->var;
 431         int clkdiv = s3c2410fb_calc_pixclk(fbi, var->pixclock) / 2;
 432
 433         dprintk("%s: var->xres  = %d\n", __func__, var->xres);
 434         dprintk("%s: var->yres  = %d\n", __func__, var->yres);
 435         dprintk("%s: var->bpp   = %d\n", __func__, var->bits_per_pixel);
 436
 437         if (type == S3C2410_LCDCON1_TFT) {
 438                 s3c2410fb_calculate_tft_lcd_regs(info, &fbi->regs);
 439                 --clkdiv;
 440                 if (clkdiv < 0)
 441                         clkdiv = 0;
 442         } else {
 443                 s3c2410fb_calculate_stn_lcd_regs(info, &fbi->regs);
 444                 if (clkdiv < 2)
 445                         clkdiv = 2;
 446         }
 447
 448         fbi->regs.lcdcon1 |=  S3C2410_LCDCON1_CLKVAL(clkdiv);
 449
 450         /* write new registers */
 451
 452         dprintk("new register set:\n");
 453         dprintk("lcdcon[1] = 0x%08lx\n", fbi->regs.lcdcon1);
 454         dprintk("lcdcon[2] = 0x%08lx\n", fbi->regs.lcdcon2);
 455         dprintk("lcdcon[3] = 0x%08lx\n", fbi->regs.lcdcon3);
 456         dprintk("lcdcon[4] = 0x%08lx\n", fbi->regs.lcdcon4);
 457         dprintk("lcdcon[5] = 0x%08lx\n", fbi->regs.lcdcon5);
 458
 459         writel(fbi->regs.lcdcon1 & ~S3C2410_LCDCON1_ENVID,
 460                 regs + S3C2410_LCDCON1);
 461         writel(fbi->regs.lcdcon2, regs + S3C2410_LCDCON2);
 462         writel(fbi->regs.lcdcon3, regs + S3C2410_LCDCON3);
 463         writel(fbi->regs.lcdcon4, regs + S3C2410_LCDCON4);
 464         writel(fbi->regs.lcdcon5, regs + S3C2410_LCDCON5);
 465
 466         /* set lcd address pointers */
 467         s3c2410fb_set_lcdaddr(info);
 468
 469         fbi->regs.lcdcon1 |= S3C2410_LCDCON1_ENVID,
 470         writel(fbi->regs.lcdcon1, regs + S3C2410_LCDCON1);
 471 }
 472
 473 /*
 474  *      s3c2410fb_set_par - Alters the hardware state.
 475  *      @info: frame buffer structure that represents a single frame buffer
 476  *
 477  */
 478 static int s3c2410fb_set_par(struct fb_info *info)
 479 {
 480         struct fb_var_screeninfo *var = &info->var;
 481
 482         switch (var->bits_per_pixel) {
 483         case 32:
 484         case 16:
 485         case 12:
 486                 info->fix.visual = FB_VISUAL_TRUECOLOR;
 487                 break;
 488         case 1:
 489                 info->fix.visual = FB_VISUAL_MONO01;
 490                 break;
 491         default:
 492                 info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
 493                 break;
 494         }
 495
 496         info->fix.line_length = (var->xres_virtual * var->bits_per_pixel) / 8;
 497
 498         /* activate this new configuration */
 499
 500         s3c2410fb_activate_var(info);
 501         return 0;
 502 }
 503
 504 static void schedule_palette_update(struct s3c2410fb_info *fbi,
 505                                     unsigned int regno, unsigned int val)
 506 {
 507         unsigned long flags;
 508         unsigned long irqen;
 509         void __iomem *irq_base = fbi->irq_base;
 510
 511         local_irq_save(flags);
 512
 513         fbi->palette_buffer[regno] = val;
 514
 515         if (!fbi->palette_ready) {
 516                 fbi->palette_ready = 1;
 517
 518                 /* enable IRQ */
 519                 irqen = readl(irq_base + S3C24XX_LCDINTMSK);
 520                 irqen &= ~S3C2410_LCDINT_FRSYNC;
 521                 writel(irqen, irq_base + S3C24XX_LCDINTMSK);
 522         }
 523
 524         local_irq_restore(flags);
 525 }
 526
 527 /* from pxafb.c */
 528 static inline unsigned int chan_to_field(unsigned int chan,
 529                                          struct fb_bitfield *bf)
 530 {
 531         chan &= 0xffff;
 532         chan >>= 16 - bf->length;
 533         return chan << bf->offset;
 534 }
 535
 536 static int s3c2410fb_setcolreg(unsigned regno,
 537                                unsigned red, unsigned green, unsigned blue,
 538                                unsigned transp, struct fb_info *info)
 539 {
 540         struct s3c2410fb_info *fbi = info->par;
 541         void __iomem *regs = fbi->io;
 542         unsigned int val;
 543
 544         /* dprintk("setcol: regno=%d, rgb=%d,%d,%d\n",
 545                    regno, red, green, blue); */
 546
 547         switch (info->fix.visual) {
 548         case FB_VISUAL_TRUECOLOR:
 549                 /* true-colour, use pseudo-palette */
 550
 551                 if (regno < 16) {
 552                         u32 *pal = info->pseudo_palette;
 553
 554                         val  = chan_to_field(red,   &info->var.red);
 555                         val |= chan_to_field(green, &info->var.green);
 556                         val |= chan_to_field(blue,  &info->var.blue);
 557
 558                         pal[regno] = val;
 559                 }
 560                 break;
 561
 562         case FB_VISUAL_PSEUDOCOLOR:
 563                 if (regno < 256) {
 564                         /* currently assume RGB 5-6-5 mode */
 565
 566                         val  = (red   >>  0) & 0xf800;
 567                         val |= (green >>  5) & 0x07e0;
 568                         val |= (blue  >> 11) & 0x001f;
 569
 570                         writel(val, regs + S3C2410_TFTPAL(regno));
 571                         schedule_palette_update(fbi, regno, val);
 572                 }
 573
 574                 break;
 575
 576         default:
 577                 return 1;       /* unknown type */
 578         }
 579
 580         return 0;
 581 }
 582
 583 /* s3c2410fb_lcd_enable
 584  *
 585  * shutdown the lcd controller
 586  */
 587 static void s3c2410fb_lcd_enable(struct s3c2410fb_info *fbi, int enable)
 588 {
 589         unsigned long flags;
 590
 591         local_irq_save(flags);
 592
 593         if (enable)
 594                 fbi->regs.lcdcon1 |= S3C2410_LCDCON1_ENVID;
 595         else
 596                 fbi->regs.lcdcon1 &= ~S3C2410_LCDCON1_ENVID;
 597
 598         writel(fbi->regs.lcdcon1, fbi->io + S3C2410_LCDCON1);
 599
 600         local_irq_restore(flags);
 601 }
 602
 603
 604 /*
 605  *      s3c2410fb_blank
 606  *      @blank_mode: the blank mode we want.
 607  *      @info: frame buffer structure that represents a single frame buffer
 608  *
 609  *      Blank the screen if blank_mode != 0, else unblank. Return 0 if
 610  *      blanking succeeded, != 0 if un-/blanking failed due to e.g. a
 611  *      video mode which doesn't support it. Implements VESA suspend
 612  *      and powerdown modes on hardware that supports disabling hsync/vsync:
 613  *
 614  *      Returns negative errno on error, or zero on success.
 615  *
 616  */
 617 static int s3c2410fb_blank(int blank_mode, struct fb_info *info)
 618 {
 619         struct s3c2410fb_info *fbi = info->par;
 620         void __iomem *tpal_reg = fbi->io;
 621
 622         dprintk("blank(mode=%d, info=%p)\n", blank_mode, info);
 623
 624         tpal_reg += is_s3c2412(fbi) ? S3C2412_TPAL : S3C2410_TPAL;
 625
 626         if (blank_mode == FB_BLANK_POWERDOWN) {
 627                 s3c2410fb_lcd_enable(fbi, 0);
 628         } else {
 629                 s3c2410fb_lcd_enable(fbi, 1);
 630         }
 631
 632         if (blank_mode == FB_BLANK_UNBLANK)
 633                 writel(0x0, tpal_reg);
 634         else {
 635                 dprintk("setting TPAL to output 0x000000\n");
 636                 writel(S3C2410_TPAL_EN, tpal_reg);
 637         }
 638
 639         return 0;
 640 }
 641
 642 static int s3c2410fb_debug_show(struct device *dev,
 643                                 struct device_attribute *attr, char *buf)
 644 {
 645         return snprintf(buf, PAGE_SIZE, "%s\n", debug ? "on" : "off");
 646 }
 647
 648 static int s3c2410fb_debug_store(struct device *dev,
 649                                  struct device_attribute *attr,
 650                                  const char *buf, size_t len)
 651 {
 652         if (len < 1)
 653                 return -EINVAL;
 654
 655         if (strnicmp(buf, "on", 2) == 0 ||
 656             strnicmp(buf, "1", 1) == 0) {
 657                 debug = 1;
 658                 printk(KERN_DEBUG "s3c2410fb: Debug On");
 659         } else if (strnicmp(buf, "off", 3) == 0 ||
 660                    strnicmp(buf, "0", 1) == 0) {
 661                 debug = 0;
 662                 printk(KERN_DEBUG "s3c2410fb: Debug Off");
 663         } else {
 664                 return -EINVAL;
 665         }
 666
 667         return len;
 668 }
 669
 670 static DEVICE_ATTR(debug, 0666, s3c2410fb_debug_show, s3c2410fb_debug_store);
 671
 672 static struct fb_ops s3c2410fb_ops = {
 673         .owner          = THIS_MODULE,
 674         .fb_check_var   = s3c2410fb_check_var,
 675         .fb_set_par     = s3c2410fb_set_par,
 676         .fb_blank       = s3c2410fb_blank,
 677         .fb_setcolreg   = s3c2410fb_setcolreg,
 678         .fb_fillrect    = cfb_fillrect,
 679         .fb_copyarea    = cfb_copyarea,
 680         .fb_imageblit   = cfb_imageblit,
 681 };
 682
 683 /*
 684  * s3c2410fb_map_video_memory():
 685  *      Allocates the DRAM memory for the frame buffer.  This buffer is
 686  *      remapped into a non-cached, non-buffered, memory region to
 687  *      allow palette and pixel writes to occur without flushing the
 688  *      cache.  Once this area is remapped, all virtual memory
 689  *      access to the video memory should occur at the new region.
 690  */
 691 static int __init s3c2410fb_map_video_memory(struct fb_info *info)
 692 {
 693         struct s3c2410fb_info *fbi = info->par;
 694         dma_addr_t map_dma;
 695         unsigned map_size = PAGE_ALIGN(info->fix.smem_len);
 696
 697         dprintk("map_video_memory(fbi=%p) map_size %u\n", fbi, map_size);
 698
 699         info->screen_base = dma_alloc_writecombine(fbi->dev, map_size,
 700                                                    &map_dma, GFP_KERNEL);
 701
 702         if (info->screen_base) {
 703                 /* prevent initial garbage on screen */
 704                 dprintk("map_video_memory: clear %p:%08x\n",
 705                         info->screen_base, map_size);
 706                 memset(info->screen_base, 0x00, map_size);
 707
 708                 info->fix.smem_start = map_dma;
 709
 710                 dprintk("map_video_memory: dma=%08lx cpu=%p size=%08x\n",
 711                         info->fix.smem_start, info->screen_base, map_size);
 712         }
 713
 714         return info->screen_base ? 0 : -ENOMEM;
 715 }
 716
 717 static inline void s3c2410fb_unmap_video_memory(struct fb_info *info)
 718 {
 719         struct s3c2410fb_info *fbi = info->par;
 720
 721         dma_free_writecombine(fbi->dev, PAGE_ALIGN(info->fix.smem_len),
 722                               info->screen_base, info->fix.smem_start);
 723 }
 724
 725 static inline void modify_gpio(void __iomem *reg,
 726                                unsigned long set, unsigned long mask)
 727 {
 728         unsigned long tmp;
 729
 730         tmp = readl(reg) & ~mask;
 731         writel(tmp | set, reg);
 732 }
 733
 734 /*
 735  * s3c2410fb_init_registers - Initialise all LCD-related registers
 736  */
 737 static int s3c2410fb_init_registers(struct fb_info *info)
 738 {
 739         struct s3c2410fb_info *fbi = info->par;
 740         struct s3c2410fb_mach_info *mach_info = fbi->dev->platform_data;
 741         unsigned long flags;
 742         void __iomem *regs = fbi->io;
 743         void __iomem *tpal;
 744         void __iomem *lpcsel;
 745
 746         if (is_s3c2412(fbi)) {
 747                 tpal = regs + S3C2412_TPAL;
 748                 lpcsel = regs + S3C2412_TCONSEL;
 749         } else {
 750                 tpal = regs + S3C2410_TPAL;
 751                 lpcsel = regs + S3C2410_LPCSEL;
 752         }
 753
 754         /* Initialise LCD with values from haret */
 755
 756         local_irq_save(flags);
 757
 758         /* modify the gpio(s) with interrupts set (bjd) */
 759
 760         modify_gpio(S3C2410_GPCUP,  mach_info->gpcup,  mach_info->gpcup_mask);
 761         modify_gpio(S3C2410_GPCCON, mach_info->gpccon, mach_info->gpccon_mask);
 762         modify_gpio(S3C2410_GPDUP,  mach_info->gpdup,  mach_info->gpdup_mask);
 763         modify_gpio(S3C2410_GPDCON, mach_info->gpdcon, mach_info->gpdcon_mask);
 764
 765         local_irq_restore(flags);
 766
 767         dprintk("LPCSEL    = 0x%08lx\n", mach_info->lpcsel);
 768         writel(mach_info->lpcsel, lpcsel);
 769
 770         dprintk("replacing TPAL %08x\n", readl(tpal));
 771
 772         /* ensure temporary palette disabled */
 773         writel(0x00, tpal);
 774
 775         return 0;
 776 }
 777
 778 static void s3c2410fb_write_palette(struct s3c2410fb_info *fbi)
 779 {
 780         unsigned int i;
 781         void __iomem *regs = fbi->io;
 782
 783         fbi->palette_ready = 0;
 784
 785         for (i = 0; i < 256; i++) {
 786                 unsigned long ent = fbi->palette_buffer[i];
 787                 if (ent == PALETTE_BUFF_CLEAR)
 788                         continue;
 789
 790                 writel(ent, regs + S3C2410_TFTPAL(i));
 791
 792                 /* it seems the only way to know exactly
 793                  * if the palette wrote ok, is to check
 794                  * to see if the value verifies ok
 795                  */
 796
 797                 if (readw(regs + S3C2410_TFTPAL(i)) == ent)
 798                         fbi->palette_buffer[i] = PALETTE_BUFF_CLEAR;
 799                 else
 800                         fbi->palette_ready = 1;   /* retry */
 801         }
 802 }
 803
 804 static irqreturn_t s3c2410fb_irq(int irq, void *dev_id)
 805 {
 806         struct s3c2410fb_info *fbi = dev_id;
 807         void __iomem *irq_base = fbi->irq_base;
 808         unsigned long lcdirq = readl(irq_base + S3C24XX_LCDINTPND);
 809
 810         if (lcdirq & S3C2410_LCDINT_FRSYNC) {
 811                 if (fbi->palette_ready)
 812                         s3c2410fb_write_palette(fbi);
 813
 814                 writel(S3C2410_LCDINT_FRSYNC, irq_base + S3C24XX_LCDINTPND);
 815                 writel(S3C2410_LCDINT_FRSYNC, irq_base + S3C24XX_LCDSRCPND);
 816         }
 817
 818         return IRQ_HANDLED;
 819 }
 820
 821 static char driver_name[] = "s3c2410fb";
 822
 823 static int __init s3c24xxfb_probe(struct platform_device *pdev,
 824                                   enum s3c_drv_type drv_type)
 825 {
 826         struct s3c2410fb_info *info;
 827         struct s3c2410fb_display *display;
 828         struct fb_info *fbinfo;
 829         struct s3c2410fb_mach_info *mach_info;
 830         struct resource *res;
 831         int ret;
 832         int irq;
 833         int i;
 834         int size;
 835         u32 lcdcon1;
 836
 837         mach_info = pdev->dev.platform_data;
 838         if (mach_info == NULL) {
 839                 dev_err(&pdev->dev,
 840                         "no platform data for lcd, cannot attach\n");
 841                 return -EINVAL;
 842         }
 843
 844         if (mach_info->default_display >= mach_info->num_displays) {
 845                 dev_err(&pdev->dev, "default is %d but only %d displays\n",
 846                         mach_info->default_display, mach_info->num_displays);
 847                 return -EINVAL;
 848         }
 849
 850         display = mach_info->displays + mach_info->default_display;
 851
 852         irq = platform_get_irq(pdev, 0);
 853         if (irq < 0) {
 854                 dev_err(&pdev->dev, "no irq for device\n");
 855                 return -ENOENT;
 856         }
 857
 858         fbinfo = framebuffer_alloc(sizeof(struct s3c2410fb_info), &pdev->dev);
 859         if (!fbinfo)
 860                 return -ENOMEM;
 861
 862         platform_set_drvdata(pdev, fbinfo);
 863
 864         info = fbinfo->par;
 865         info->dev = &pdev->dev;
 866         info->drv_type = drv_type;
 867
 868         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 869         if (res == NULL) {
 870                 dev_err(&pdev->dev, "failed to get memory registers\n");
 871                 ret = -ENXIO;
 872                 goto dealloc_fb;
 873         }
 874
 875         size = (res->end - res->start) + 1;
 876         info->mem = request_mem_region(res->start, size, pdev->name);
 877         if (info->mem == NULL) {
 878                 dev_err(&pdev->dev, "failed to get memory region\n");
 879                 ret = -ENOENT;
 880                 goto dealloc_fb;
 881         }
 882
 883         info->io = ioremap(res->start, size);
 884         if (info->io == NULL) {
 885                 dev_err(&pdev->dev, "ioremap() of registers failed\n");
 886                 ret = -ENXIO;
 887                 goto release_mem;
 888         }
 889
 890         info->irq_base = info->io + ((drv_type == DRV_S3C2412) ? S3C2412_LCDINTBASE : S3C2410_LCDINTBASE);
 891
 892         dprintk("devinit\n");
 893
 894         strcpy(fbinfo->fix.id, driver_name);
 895
 896         /* Stop the video */
 897         lcdcon1 = readl(info->io + S3C2410_LCDCON1);
 898         writel(lcdcon1 & ~S3C2410_LCDCON1_ENVID, info->io + S3C2410_LCDCON1);
 899
 900         fbinfo->fix.type            = FB_TYPE_PACKED_PIXELS;
 901         fbinfo->fix.type_aux        = 0;
 902         fbinfo->fix.xpanstep        = 0;
 903         fbinfo->fix.ypanstep        = 0;
 904         fbinfo->fix.ywrapstep       = 0;
 905         fbinfo->fix.accel           = FB_ACCEL_NONE;
 906
 907         fbinfo->var.nonstd          = 0;
 908         fbinfo->var.activate        = FB_ACTIVATE_NOW;
 909         fbinfo->var.accel_flags     = 0;
 910         fbinfo->var.vmode           = FB_VMODE_NONINTERLACED;
 911
 912         fbinfo->fbops               = &s3c2410fb_ops;
 913         fbinfo->flags               = FBINFO_FLAG_DEFAULT;
 914         fbinfo->pseudo_palette      = &info->pseudo_pal;
 915
 916         for (i = 0; i < 256; i++)
 917                 info->palette_buffer[i] = PALETTE_BUFF_CLEAR;
 918
 919         ret = request_irq(irq, s3c2410fb_irq, IRQF_DISABLED, pdev->name, info);
 920         if (ret) {
 921                 dev_err(&pdev->dev, "cannot get irq %d - err %d\n", irq, ret);
 922                 ret = -EBUSY;
 923                 goto release_regs;
 924         }
 925
 926         info->clk = clk_get(NULL, "lcd");
 927         if (!info->clk || IS_ERR(info->clk)) {
 928                 printk(KERN_ERR "failed to get lcd clock source\n");
 929                 ret = -ENOENT;
 930                 goto release_irq;
 931         }
 932
 933         clk_enable(info->clk);
 934         dprintk("got and enabled clock\n");
 935
 936         msleep(1);
 937
 938         /* find maximum required memory size for display */
 939         for (i = 0; i < mach_info->num_displays; i++) {
 940                 unsigned long smem_len = mach_info->displays[i].xres;
 941
 942                 smem_len *= mach_info->displays[i].yres;
 943                 smem_len *= mach_info->displays[i].bpp;
 944                 smem_len >>= 3;
 945                 if (fbinfo->fix.smem_len < smem_len)
 946                         fbinfo->fix.smem_len = smem_len;
 947         }
 948
 949         /* Initialize video memory */
 950         ret = s3c2410fb_map_video_memory(fbinfo);
 951         if (ret) {
 952                 printk(KERN_ERR "Failed to allocate video RAM: %d\n", ret);
 953                 ret = -ENOMEM;
 954                 goto release_clock;
 955         }
 956
 957         dprintk("got video memory\n");
 958
 959         fbinfo->var.xres = display->xres;
 960         fbinfo->var.yres = display->yres;
 961         fbinfo->var.bits_per_pixel = display->bpp;
 962
 963         s3c2410fb_init_registers(fbinfo);
 964
 965         s3c2410fb_check_var(&fbinfo->var, fbinfo);
 966
 967         ret = register_framebuffer(fbinfo);
 968         if (ret < 0) {
 969                 printk(KERN_ERR "Failed to register framebuffer device: %d\n",
 970                         ret);
 971                 goto free_video_memory;
 972         }
 973
 974         /* create device files */
 975         device_create_file(&pdev->dev, &dev_attr_debug);
 976
 977         printk(KERN_INFO "fb%d: %s frame buffer device\n",
 978                 fbinfo->node, fbinfo->fix.id);
 979
 980         return 0;
 981
 982 free_video_memory:
 983         s3c2410fb_unmap_video_memory(fbinfo);
 984 release_clock:
 985         clk_disable(info->clk);
 986         clk_put(info->clk);
 987 release_irq:
 988         free_irq(irq, info);
 989 release_regs:
 990         iounmap(info->io);
 991 release_mem:
 992         release_resource(info->mem);
 993         kfree(info->mem);
 994 dealloc_fb:
 995         platform_set_drvdata(pdev, NULL);
 996         framebuffer_release(fbinfo);
 997         return ret;
 998 }
 999
1000 static int __init s3c2410fb_probe(struct platform_device *pdev)
1001 {
1002         return s3c24xxfb_probe(pdev, DRV_S3C2410);
1003 }
1004
1005 static int __init s3c2412fb_probe(struct platform_device *pdev)
1006 {
1007         return s3c24xxfb_probe(pdev, DRV_S3C2412);
1008 }
1009
1010
1011 /*
1012  *  Cleanup
1013  */
1014 static int s3c2410fb_remove(struct platform_device *pdev)
1015 {
1016         struct fb_info *fbinfo = platform_get_drvdata(pdev);
1017         struct s3c2410fb_info *info = fbinfo->par;
1018         int irq;
1019
1020         unregister_framebuffer(fbinfo);
1021
1022         s3c2410fb_lcd_enable(info, 0);
1023         msleep(1);
1024
1025         s3c2410fb_unmap_video_memory(fbinfo);
1026
1027         if (info->clk) {
1028                 clk_disable(info->clk);
1029                 clk_put(info->clk);
1030                 info->clk = NULL;
1031         }
1032
1033         irq = platform_get_irq(pdev, 0);
1034         free_irq(irq, info);
1035
1036         iounmap(info->io);
1037
1038         release_resource(info->mem);
1039         kfree(info->mem);
1040
1041         platform_set_drvdata(pdev, NULL);
1042         framebuffer_release(fbinfo);
1043
1044         return 0;
1045 }
1046
1047 #ifdef CONFIG_PM
1048
1049 /* suspend and resume support for the lcd controller */
1050 static int s3c2410fb_suspend(struct platform_device *dev, pm_message_t state)
1051 {
1052         struct fb_info     *fbinfo = platform_get_drvdata(dev);
1053         struct s3c2410fb_info *info = fbinfo->par;
1054
1055         s3c2410fb_lcd_enable(info, 0);
1056
1057         /* sleep before disabling the clock, we need to ensure
1058          * the LCD DMA engine is not going to get back on the bus
1059          * before the clock goes off again (bjd) */
1060
1061         msleep(1);
1062         clk_disable(info->clk);
1063
1064         return 0;
1065 }
1066
1067 static int s3c2410fb_resume(struct platform_device *dev)
1068 {
1069         struct fb_info     *fbinfo = platform_get_drvdata(dev);
1070         struct s3c2410fb_info *info = fbinfo->par;
1071
1072         clk_enable(info->clk);
1073         msleep(1);
1074
1075         s3c2410fb_init_registers(fbinfo);
1076
1077         return 0;
1078 }
1079
1080 #else
1081 #define s3c2410fb_suspend NULL
1082 #define s3c2410fb_resume  NULL
1083 #endif
1084
1085 static struct platform_driver s3c2410fb_driver = {
1086         .probe          = s3c2410fb_probe,
1087         .remove         = s3c2410fb_remove,
1088         .suspend        = s3c2410fb_suspend,
1089         .resume         = s3c2410fb_resume,
1090         .driver         = {
1091                 .name   = "s3c2410-lcd",
1092                 .owner  = THIS_MODULE,
1093         },
1094 };
1095
1096 static struct platform_driver s3c2412fb_driver = {
1097         .probe          = s3c2412fb_probe,
1098         .remove         = s3c2410fb_remove,
1099         .suspend        = s3c2410fb_suspend,
1100         .resume         = s3c2410fb_resume,
1101         .driver         = {
1102                 .name   = "s3c2412-lcd",
1103                 .owner  = THIS_MODULE,
1104         },
1105 };
1106
1107 int __init s3c2410fb_init(void)
1108 {
1109         int ret = platform_driver_register(&s3c2410fb_driver);
1110
1111         if (ret == 0)
1112                 ret = platform_driver_register(&s3c2412fb_driver);;
1113
1114         return ret;
1115 }
1116
1117 static void __exit s3c2410fb_cleanup(void)
1118 {
1119         platform_driver_unregister(&s3c2410fb_driver);
1120         platform_driver_unregister(&s3c2412fb_driver);
1121 }
1122
1123 module_init(s3c2410fb_init);
1124 module_exit(s3c2410fb_cleanup);
1125
1126 MODULE_AUTHOR("Arnaud Patard <arnaud.patard@rtp-net.org>, "
1127               "Ben Dooks <ben-linux@fluff.org>");
1128 MODULE_DESCRIPTION("Framebuffer driver for the s3c2410");
1129 MODULE_LICENSE("GPL");