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   1 /*
   2  * linux/drivers/video/s3c2410fb.c
   3  *      Copyright (c) Arnaud Patard, Ben Dooks
   4  *
   5  * This file is subject to the terms and conditions of the GNU General Public
   6  * License.  See the file COPYING in the main directory of this archive for
   7  * more details.
   8  *
   9  *          S3C2410 LCD Controller Frame Buffer Driver
  10  *          based on skeletonfb.c, sa1100fb.c and others
  11  *
  12  * ChangeLog
  13  * 2005-04-07: Arnaud Patard <arnaud.patard@rtp-net.org>
  14  *      - u32 state -> pm_message_t state
  15  *      - S3C2410_{VA,SZ}_LCD -> S3C24XX
  16  *
  17  * 2005-03-15: Arnaud Patard <arnaud.patard@rtp-net.org>
  18  *      - Removed the ioctl
  19  *      - use readl/writel instead of __raw_writel/__raw_readl
  20  *
  21  * 2004-12-04: Arnaud Patard <arnaud.patard@rtp-net.org>
  22  *      - Added the possibility to set on or off the
  23  *      debugging mesaages
  24  *      - Replaced 0 and 1 by on or off when reading the
  25  *      /sys files
  26  *
  27  * 2005-03-23: Ben Dooks <ben-linux@fluff.org>
  28  *      - added non 16bpp modes
  29  *      - updated platform information for range of x/y/bpp
  30  *      - add code to ensure palette is written correctly
  31  *      - add pixel clock divisor control
  32  *
  33  * 2004-11-11: Arnaud Patard <arnaud.patard@rtp-net.org>
  34  *      - Removed the use of currcon as it no more exist
  35  *      - Added LCD power sysfs interface
  36  *
  37  * 2004-11-03: Ben Dooks <ben-linux@fluff.org>
  38  *      - minor cleanups
  39  *      - add suspend/resume support
  40  *      - s3c2410fb_setcolreg() not valid in >8bpp modes
  41  *      - removed last CONFIG_FB_S3C2410_FIXED
  42  *      - ensure lcd controller stopped before cleanup
  43  *      - added sysfs interface for backlight power
  44  *      - added mask for gpio configuration
  45  *      - ensured IRQs disabled during GPIO configuration
  46  *      - disable TPAL before enabling video
  47  *
  48  * 2004-09-20: Arnaud Patard <arnaud.patard@rtp-net.org>
  49  *      - Suppress command line options
  50  *
  51  * 2004-09-15: Arnaud Patard <arnaud.patard@rtp-net.org>
  52  *      - code cleanup
  53  *
  54  * 2004-09-07: Arnaud Patard <arnaud.patard@rtp-net.org>
  55  *      - Renamed from h1940fb.c to s3c2410fb.c
  56  *      - Add support for different devices
  57  *      - Backlight support
  58  *
  59  * 2004-09-05: Herbert Pötzl <herbert@13thfloor.at>
  60  *      - added clock (de-)allocation code
  61  *      - added fixem fbmem option
  62  *
  63  * 2004-07-27: Arnaud Patard <arnaud.patard@rtp-net.org>
  64  *      - code cleanup
  65  *      - added a forgotten return in h1940fb_init
  66  *
  67  * 2004-07-19: Herbert Pötzl <herbert@13thfloor.at>
  68  *      - code cleanup and extended debugging
  69  *
  70  * 2004-07-15: Arnaud Patard <arnaud.patard@rtp-net.org>
  71  *      - First version
  72  */
  73
  74 #include <linux/module.h>
  75 #include <linux/kernel.h>
  76 #include <linux/errno.h>
  77 #include <linux/string.h>
  78 #include <linux/mm.h>
  79 #include <linux/slab.h>
  80 #include <linux/delay.h>
  81 #include <linux/fb.h>
  82 #include <linux/init.h>
  83 #include <linux/dma-mapping.h>
  84 #include <linux/interrupt.h>
  85 #include <linux/workqueue.h>
  86 #include <linux/wait.h>
  87 #include <linux/platform_device.h>
  88 #include <linux/clk.h>
  89
  90 #include <asm/io.h>
  91 #include <asm/uaccess.h>
  92 #include <asm/div64.h>
  93
  94 #include <asm/mach/map.h>
  95 #include <asm/arch/regs-lcd.h>
  96 #include <asm/arch/regs-gpio.h>
  97 #include <asm/arch/fb.h>
  98
  99 #ifdef CONFIG_PM
 100 #include <linux/pm.h>
 101 #endif
 102
 103 #include "s3c2410fb.h"
 104
 105 static struct s3c2410fb_mach_info *mach_info;
 106
 107 /* Debugging stuff */
 108 #ifdef CONFIG_FB_S3C2410_DEBUG
 109 static int debug        = 1;
 110 #else
 111 static int debug        = 0;
 112 #endif
 113
 114 #define dprintk(msg...) if (debug) { printk(KERN_DEBUG "s3c2410fb: " msg); }
 115
 116 /* useful functions */
 117
 118 /* s3c2410fb_set_lcdaddr
 119  *
 120  * initialise lcd controller address pointers
 121  */
 122 static void s3c2410fb_set_lcdaddr(struct fb_info *info)
 123 {
 124         unsigned long saddr1, saddr2, saddr3;
 125         int line_length = info->var.xres * info->var.bits_per_pixel;
 126
 127         saddr1  = info->fix.smem_start >> 1;
 128         saddr2  = info->fix.smem_start;
 129         saddr2 += (line_length * info->var.yres) / 8;
 130         saddr2 >>= 1;
 131
 132         saddr3 = S3C2410_OFFSIZE(0) |
 133                  S3C2410_PAGEWIDTH((line_length / 16) & 0x3ff);
 134
 135         dprintk("LCDSADDR1 = 0x%08lx\n", saddr1);
 136         dprintk("LCDSADDR2 = 0x%08lx\n", saddr2);
 137         dprintk("LCDSADDR3 = 0x%08lx\n", saddr3);
 138
 139         writel(saddr1, S3C2410_LCDSADDR1);
 140         writel(saddr2, S3C2410_LCDSADDR2);
 141         writel(saddr3, S3C2410_LCDSADDR3);
 142 }
 143
 144 /* s3c2410fb_calc_pixclk()
 145  *
 146  * calculate divisor for clk->pixclk
 147  */
 148 static unsigned int s3c2410fb_calc_pixclk(struct s3c2410fb_info *fbi,
 149                                           unsigned long pixclk)
 150 {
 151         unsigned long clk = clk_get_rate(fbi->clk);
 152         unsigned long long div;
 153
 154         /* pixclk is in picoseoncds, our clock is in Hz
 155          *
 156          * Hz -> picoseconds is / 10^-12
 157          */
 158
 159         div = (unsigned long long)clk * pixclk;
 160         do_div(div, 1000000UL);
 161         do_div(div, 1000000UL);
 162
 163         dprintk("pixclk %ld, divisor is %ld\n", pixclk, (long)div);
 164         return div;
 165 }
 166
 167 /*
 168  *      s3c2410fb_check_var():
 169  *      Get the video params out of 'var'. If a value doesn't fit, round it up,
 170  *      if it's too big, return -EINVAL.
 171  *
 172  */
 173 static int s3c2410fb_check_var(struct fb_var_screeninfo *var,
 174                                struct fb_info *info)
 175 {
 176         struct s3c2410fb_info *fbi = info->par;
 177         struct s3c2410fb_mach_info *mach_info = fbi->mach_info;
 178         struct s3c2410fb_display *display = NULL;
 179         unsigned i;
 180
 181         dprintk("check_var(var=%p, info=%p)\n", var, info);
 182
 183         /* validate x/y resolution */
 184
 185         for (i = 0; i < mach_info->num_displays; i++)
 186                 if (var->yres == mach_info->displays[i].yres &&
 187                     var->xres == mach_info->displays[i].xres &&
 188                     var->bits_per_pixel == mach_info->displays[i].bpp) {
 189                         display = mach_info->displays + i;
 190                         fbi->current_display = i;
 191                         break;
 192                 }
 193
 194         if (!display) {
 195                 dprintk("wrong resolution or depth %dx%d at %d bpp\n",
 196                         var->xres, var->yres, var->bits_per_pixel);
 197                 return -EINVAL;
 198         }
 199
 200         /* it is always the size as the display */
 201         var->xres_virtual = display->xres;
 202         var->yres_virtual = display->yres;
 203
 204         /* copy lcd settings */
 205         var->left_margin = display->left_margin;
 206         var->right_margin = display->right_margin;
 207
 208         var->transp.offset = 0;
 209         var->transp.length = 0;
 210         /* set r/g/b positions */
 211         switch (var->bits_per_pixel) {
 212         case 1:
 213         case 2:
 214         case 4:
 215                 var->red.offset = 0;
 216                 var->red.length = var->bits_per_pixel;
 217                 var->green      = var->red;
 218                 var->blue       = var->red;
 219                 break;
 220         case 8:
 221                 if (display->type != S3C2410_LCDCON1_TFT) {
 222                         /* 8 bpp 332 */
 223                         var->red.length         = 3;
 224                         var->red.offset         = 5;
 225                         var->green.length       = 3;
 226                         var->green.offset       = 2;
 227                         var->blue.length        = 2;
 228                         var->blue.offset        = 0;
 229                 } else {
 230                         var->red.offset         = 0;
 231                         var->red.length         = 8;
 232                         var->green              = var->red;
 233                         var->blue               = var->red;
 234                 }
 235                 break;
 236         case 12:
 237                 /* 12 bpp 444 */
 238                 var->red.length         = 4;
 239                 var->red.offset         = 8;
 240                 var->green.length       = 4;
 241                 var->green.offset       = 4;
 242                 var->blue.length        = 4;
 243                 var->blue.offset        = 0;
 244                 break;
 245
 246         default:
 247         case 16:
 248                 if (display->lcdcon5 & S3C2410_LCDCON5_FRM565) {
 249                         /* 16 bpp, 565 format */
 250                         var->red.offset         = 11;
 251                         var->green.offset       = 5;
 252                         var->blue.offset        = 0;
 253                         var->red.length         = 5;
 254                         var->green.length       = 6;
 255                         var->blue.length        = 5;
 256                 } else {
 257                         /* 16 bpp, 5551 format */
 258                         var->red.offset         = 11;
 259                         var->green.offset       = 6;
 260                         var->blue.offset        = 1;
 261                         var->red.length         = 5;
 262                         var->green.length       = 5;
 263                         var->blue.length        = 5;
 264                 }
 265                 break;
 266         case 24:
 267                 /* 24 bpp 888 */
 268                 var->red.length         = 8;
 269                 var->red.offset         = 16;
 270                 var->green.length       = 8;
 271                 var->green.offset       = 8;
 272                 var->blue.length        = 8;
 273                 var->blue.offset        = 0;
 274                 break;
 275
 276
 277         }
 278         return 0;
 279 }
 280
 281 /* s3c2410fb_calculate_stn_lcd_regs
 282  *
 283  * calculate register values from var settings
 284  */
 285 static void s3c2410fb_calculate_stn_lcd_regs(const struct fb_info *info,
 286                                              struct s3c2410fb_hw *regs)
 287 {
 288         const struct s3c2410fb_info *fbi = info->par;
 289         const struct fb_var_screeninfo *var = &info->var;
 290         int type = regs->lcdcon1 & ~S3C2410_LCDCON1_TFT;
 291         int hs = var->xres >> 2;
 292         unsigned wdly = (var->left_margin >> 4) - 1;
 293
 294         dprintk("%s: var->xres  = %d\n", __FUNCTION__, var->xres);
 295         dprintk("%s: var->yres  = %d\n", __FUNCTION__, var->yres);
 296         dprintk("%s: var->bpp   = %d\n", __FUNCTION__, var->bits_per_pixel);
 297
 298         if (type != S3C2410_LCDCON1_STN4)
 299                 hs >>= 1;
 300
 301         regs->lcdcon1 &= ~S3C2410_LCDCON1_MODEMASK;
 302
 303         switch (var->bits_per_pixel) {
 304         case 1:
 305                 regs->lcdcon1 |= S3C2410_LCDCON1_STN1BPP;
 306                 break;
 307         case 2:
 308                 regs->lcdcon1 |= S3C2410_LCDCON1_STN2GREY;
 309                 break;
 310         case 4:
 311                 regs->lcdcon1 |= S3C2410_LCDCON1_STN4GREY;
 312                 break;
 313         case 8:
 314                 regs->lcdcon1 |= S3C2410_LCDCON1_STN8BPP;
 315                 hs *= 3;
 316                 break;
 317         case 12:
 318                 regs->lcdcon1 |= S3C2410_LCDCON1_STN12BPP;
 319                 hs *= 3;
 320                 break;
 321
 322         default:
 323                 /* invalid pixel depth */
 324                 dev_err(fbi->dev, "invalid bpp %d\n",
 325                         var->bits_per_pixel);
 326         }
 327         /* update X/Y info */
 328         dprintk("setting horz: lft=%d, rt=%d, sync=%d\n",
 329                 var->left_margin, var->right_margin, var->hsync_len);
 330
 331         regs->lcdcon2 = S3C2410_LCDCON2_LINEVAL(var->yres - 1);
 332
 333         if (wdly > 3)
 334                 wdly = 3;
 335
 336         regs->lcdcon3 = S3C2410_LCDCON3_WDLY(wdly) |
 337                         S3C2410_LCDCON3_LINEBLANK(var->right_margin / 8) |
 338                         S3C2410_LCDCON3_HOZVAL(hs - 1);
 339 }
 340
 341 /* s3c2410fb_calculate_tft_lcd_regs
 342  *
 343  * calculate register values from var settings
 344  */
 345 static void s3c2410fb_calculate_tft_lcd_regs(const struct fb_info *info,
 346                                              struct s3c2410fb_hw *regs)
 347 {
 348         const struct s3c2410fb_info *fbi = info->par;
 349         const struct fb_var_screeninfo *var = &info->var;
 350
 351         dprintk("%s: var->xres  = %d\n", __FUNCTION__, var->xres);
 352         dprintk("%s: var->yres  = %d\n", __FUNCTION__, var->yres);
 353         dprintk("%s: var->bpp   = %d\n", __FUNCTION__, var->bits_per_pixel);
 354
 355         regs->lcdcon1 &= ~S3C2410_LCDCON1_MODEMASK;
 356
 357         switch (var->bits_per_pixel) {
 358         case 1:
 359                 regs->lcdcon1 |= S3C2410_LCDCON1_TFT1BPP;
 360                 break;
 361         case 2:
 362                 regs->lcdcon1 |= S3C2410_LCDCON1_TFT2BPP;
 363                 break;
 364         case 4:
 365                 regs->lcdcon1 |= S3C2410_LCDCON1_TFT4BPP;
 366                 break;
 367         case 8:
 368                 regs->lcdcon1 |= S3C2410_LCDCON1_TFT8BPP;
 369                 break;
 370         case 16:
 371                 regs->lcdcon1 |= S3C2410_LCDCON1_TFT16BPP;
 372                 break;
 373
 374         default:
 375                 /* invalid pixel depth */
 376                 dev_err(fbi->dev, "invalid bpp %d\n",
 377                         var->bits_per_pixel);
 378         }
 379         /* update X/Y info */
 380         dprintk("setting vert: up=%d, low=%d, sync=%d\n",
 381                 var->upper_margin, var->lower_margin, var->vsync_len);
 382
 383         dprintk("setting horz: lft=%d, rt=%d, sync=%d\n",
 384                 var->left_margin, var->right_margin, var->hsync_len);
 385
 386         regs->lcdcon2 &= S3C2410_LCDCON2_VSPW(0x3f);
 387         regs->lcdcon2 |= S3C2410_LCDCON2_LINEVAL(var->yres - 1);
 388         regs->lcdcon2 |= S3C2410_LCDCON2_VBPD(var->upper_margin - 1);
 389         regs->lcdcon2 |= S3C2410_LCDCON2_VFPD(var->lower_margin - 1);
 390
 391         regs->lcdcon3 = S3C2410_LCDCON3_HBPD(var->right_margin - 1) |
 392                         S3C2410_LCDCON3_HFPD(var->left_margin - 1) |
 393                         S3C2410_LCDCON3_HOZVAL(var->xres - 1);
 394 }
 395
 396 /* s3c2410fb_activate_var
 397  *
 398  * activate (set) the controller from the given framebuffer
 399  * information
 400  */
 401 static void s3c2410fb_activate_var(struct fb_info *info)
 402 {
 403         struct s3c2410fb_info *fbi = info->par;
 404         struct fb_var_screeninfo *var = &info->var;
 405         struct s3c2410fb_mach_info *mach_info = fbi->mach_info;
 406         struct s3c2410fb_display *display = mach_info->displays +
 407                                             fbi->current_display;
 408
 409         /* set display type */
 410         fbi->regs.lcdcon1 &= ~S3C2410_LCDCON1_TFT;
 411         fbi->regs.lcdcon1 |= display->type;
 412
 413         /* check to see if we need to update sync/borders */
 414
 415         if (!mach_info->fixed_syncs) {
 416                 fbi->regs.lcdcon2 =
 417                         S3C2410_LCDCON2_VSPW(var->vsync_len - 1);
 418
 419                 fbi->regs.lcdcon4 &= ~S3C2410_LCDCON4_HSPW(0xff);
 420                 fbi->regs.lcdcon4 |=  S3C2410_LCDCON4_HSPW(var->hsync_len - 1);
 421         }
 422
 423         if (var->pixclock > 0) {
 424                 int clkdiv = s3c2410fb_calc_pixclk(fbi, var->pixclock);
 425
 426                 if (display->type == S3C2410_LCDCON1_TFT) {
 427                         clkdiv = (clkdiv / 2) - 1;
 428                         if (clkdiv < 0)
 429                                 clkdiv = 0;
 430                 } else {
 431                         clkdiv = (clkdiv / 2);
 432                         if (clkdiv < 2)
 433                                 clkdiv = 2;
 434                 }
 435
 436                 fbi->regs.lcdcon1 &= ~S3C2410_LCDCON1_CLKVAL(0x3ff);
 437                 fbi->regs.lcdcon1 |=  S3C2410_LCDCON1_CLKVAL(clkdiv);
 438         }
 439
 440         if (display->type == S3C2410_LCDCON1_TFT)
 441                 s3c2410fb_calculate_tft_lcd_regs(info, &fbi->regs);
 442         else
 443                 s3c2410fb_calculate_stn_lcd_regs(info, &fbi->regs);
 444
 445         /* write new registers */
 446
 447         dprintk("new register set:\n");
 448         dprintk("lcdcon[1] = 0x%08lx\n", fbi->regs.lcdcon1);
 449         dprintk("lcdcon[2] = 0x%08lx\n", fbi->regs.lcdcon2);
 450         dprintk("lcdcon[3] = 0x%08lx\n", fbi->regs.lcdcon3);
 451         dprintk("lcdcon[4] = 0x%08lx\n", fbi->regs.lcdcon4);
 452         dprintk("lcdcon[5] = 0x%08lx\n", fbi->regs.lcdcon5);
 453
 454         writel(fbi->regs.lcdcon1 & ~S3C2410_LCDCON1_ENVID, S3C2410_LCDCON1);
 455         writel(fbi->regs.lcdcon2, S3C2410_LCDCON2);
 456         writel(fbi->regs.lcdcon3, S3C2410_LCDCON3);
 457         writel(fbi->regs.lcdcon4, S3C2410_LCDCON4);
 458         writel(fbi->regs.lcdcon5, S3C2410_LCDCON5);
 459
 460         /* set lcd address pointers */
 461         s3c2410fb_set_lcdaddr(info);
 462
 463         writel(fbi->regs.lcdcon1, S3C2410_LCDCON1);
 464 }
 465
 466 /*
 467  *      s3c2410fb_set_par - Alters the hardware state.
 468  *      @info: frame buffer structure that represents a single frame buffer
 469  *
 470  */
 471 static int s3c2410fb_set_par(struct fb_info *info)
 472 {
 473         struct fb_var_screeninfo *var = &info->var;
 474
 475         switch (var->bits_per_pixel) {
 476         case 16:
 477                 info->fix.visual = FB_VISUAL_TRUECOLOR;
 478                 break;
 479         case 1:
 480                 info->fix.visual = FB_VISUAL_MONO01;
 481                 break;
 482         default:
 483                 info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
 484                 break;
 485         }
 486
 487         info->fix.line_length = (var->width * var->bits_per_pixel) / 8;
 488
 489         /* activate this new configuration */
 490
 491         s3c2410fb_activate_var(info);
 492         return 0;
 493 }
 494
 495 static void schedule_palette_update(struct s3c2410fb_info *fbi,
 496                                     unsigned int regno, unsigned int val)
 497 {
 498         unsigned long flags;
 499         unsigned long irqen;
 500         void __iomem *regs = fbi->io;
 501
 502         local_irq_save(flags);
 503
 504         fbi->palette_buffer[regno] = val;
 505
 506         if (!fbi->palette_ready) {
 507                 fbi->palette_ready = 1;
 508
 509                 /* enable IRQ */
 510                 irqen = readl(regs + S3C2410_LCDINTMSK);
 511                 irqen &= ~S3C2410_LCDINT_FRSYNC;
 512                 writel(irqen, regs + S3C2410_LCDINTMSK);
 513         }
 514
 515         local_irq_restore(flags);
 516 }
 517
 518 /* from pxafb.c */
 519 static inline unsigned int chan_to_field(unsigned int chan,
 520                                          struct fb_bitfield *bf)
 521 {
 522         chan &= 0xffff;
 523         chan >>= 16 - bf->length;
 524         return chan << bf->offset;
 525 }
 526
 527 static int s3c2410fb_setcolreg(unsigned regno,
 528                                unsigned red, unsigned green, unsigned blue,
 529                                unsigned transp, struct fb_info *info)
 530 {
 531         struct s3c2410fb_info *fbi = info->par;
 532         unsigned int val;
 533
 534         /* dprintk("setcol: regno=%d, rgb=%d,%d,%d\n",
 535                    regno, red, green, blue); */
 536
 537         switch (info->fix.visual) {
 538         case FB_VISUAL_TRUECOLOR:
 539                 /* true-colour, use pseudo-palette */
 540
 541                 if (regno < 16) {
 542                         u32 *pal = info->pseudo_palette;
 543
 544                         val  = chan_to_field(red,   &info->var.red);
 545                         val |= chan_to_field(green, &info->var.green);
 546                         val |= chan_to_field(blue,  &info->var.blue);
 547
 548                         pal[regno] = val;
 549                 }
 550                 break;
 551
 552         case FB_VISUAL_PSEUDOCOLOR:
 553                 if (regno < 256) {
 554                         /* currently assume RGB 5-6-5 mode */
 555
 556                         val  = ((red   >>  0) & 0xf800);
 557                         val |= ((green >>  5) & 0x07e0);
 558                         val |= ((blue  >> 11) & 0x001f);
 559
 560                         writel(val, S3C2410_TFTPAL(regno));
 561                         schedule_palette_update(fbi, regno, val);
 562                 }
 563
 564                 break;
 565
 566         default:
 567                 return 1;       /* unknown type */
 568         }
 569
 570         return 0;
 571 }
 572
 573 /*
 574  *      s3c2410fb_blank
 575  *      @blank_mode: the blank mode we want.
 576  *      @info: frame buffer structure that represents a single frame buffer
 577  *
 578  *      Blank the screen if blank_mode != 0, else unblank. Return 0 if
 579  *      blanking succeeded, != 0 if un-/blanking failed due to e.g. a
 580  *      video mode which doesn't support it. Implements VESA suspend
 581  *      and powerdown modes on hardware that supports disabling hsync/vsync:
 582  *      blank_mode == 2: suspend vsync
 583  *      blank_mode == 3: suspend hsync
 584  *      blank_mode == 4: powerdown
 585  *
 586  *      Returns negative errno on error, or zero on success.
 587  *
 588  */
 589 static int s3c2410fb_blank(int blank_mode, struct fb_info *info)
 590 {
 591         dprintk("blank(mode=%d, info=%p)\n", blank_mode, info);
 592
 593         if (mach_info == NULL)
 594                 return -EINVAL;
 595
 596         if (blank_mode == FB_BLANK_UNBLANK)
 597                 writel(0x0, S3C2410_TPAL);
 598         else {
 599                 dprintk("setting TPAL to output 0x000000\n");
 600                 writel(S3C2410_TPAL_EN, S3C2410_TPAL);
 601         }
 602
 603         return 0;
 604 }
 605
 606 static int s3c2410fb_debug_show(struct device *dev,
 607                                 struct device_attribute *attr, char *buf)
 608 {
 609         return snprintf(buf, PAGE_SIZE, "%s\n", debug ? "on" : "off");
 610 }
 611 static int s3c2410fb_debug_store(struct device *dev,
 612                                  struct device_attribute *attr,
 613                                  const char *buf, size_t len)
 614 {
 615         if (mach_info == NULL)
 616                 return -EINVAL;
 617
 618         if (len < 1)
 619                 return -EINVAL;
 620
 621         if (strnicmp(buf, "on", 2) == 0 ||
 622             strnicmp(buf, "1", 1) == 0) {
 623                 debug = 1;
 624                 printk(KERN_DEBUG "s3c2410fb: Debug On");
 625         } else if (strnicmp(buf, "off", 3) == 0 ||
 626                    strnicmp(buf, "0", 1) == 0) {
 627                 debug = 0;
 628                 printk(KERN_DEBUG "s3c2410fb: Debug Off");
 629         } else {
 630                 return -EINVAL;
 631         }
 632
 633         return len;
 634 }
 635
 636 static DEVICE_ATTR(debug, 0666, s3c2410fb_debug_show, s3c2410fb_debug_store);
 637
 638 static struct fb_ops s3c2410fb_ops = {
 639         .owner          = THIS_MODULE,
 640         .fb_check_var   = s3c2410fb_check_var,
 641         .fb_set_par     = s3c2410fb_set_par,
 642         .fb_blank       = s3c2410fb_blank,
 643         .fb_setcolreg   = s3c2410fb_setcolreg,
 644         .fb_fillrect    = cfb_fillrect,
 645         .fb_copyarea    = cfb_copyarea,
 646         .fb_imageblit   = cfb_imageblit,
 647 };
 648
 649 /*
 650  * s3c2410fb_map_video_memory():
 651  *      Allocates the DRAM memory for the frame buffer.  This buffer is
 652  *      remapped into a non-cached, non-buffered, memory region to
 653  *      allow palette and pixel writes to occur without flushing the
 654  *      cache.  Once this area is remapped, all virtual memory
 655  *      access to the video memory should occur at the new region.
 656  */
 657 static int __init s3c2410fb_map_video_memory(struct fb_info *info)
 658 {
 659         struct s3c2410fb_info *fbi = info->par;
 660
 661         dprintk("map_video_memory(fbi=%p)\n", fbi);
 662
 663         fbi->map_size = PAGE_ALIGN(info->fix.smem_len + PAGE_SIZE);
 664         fbi->map_cpu  = dma_alloc_writecombine(fbi->dev, fbi->map_size,
 665                                                &fbi->map_dma, GFP_KERNEL);
 666
 667         fbi->map_size = info->fix.smem_len;
 668
 669         if (fbi->map_cpu) {
 670                 /* prevent initial garbage on screen */
 671                 dprintk("map_video_memory: clear %p:%08x\n",
 672                         fbi->map_cpu, fbi->map_size);
 673                 memset(fbi->map_cpu, 0xf0, fbi->map_size);
 674
 675                 fbi->screen_dma         = fbi->map_dma;
 676                 info->screen_base       = fbi->map_cpu;
 677                 info->fix.smem_start    = fbi->screen_dma;
 678
 679                 dprintk("map_video_memory: dma=%08x cpu=%p size=%08x\n",
 680                         fbi->map_dma, fbi->map_cpu, info->fix.smem_len);
 681         }
 682
 683         return fbi->map_cpu ? 0 : -ENOMEM;
 684 }
 685
 686 static inline void s3c2410fb_unmap_video_memory(struct s3c2410fb_info *fbi)
 687 {
 688         dma_free_writecombine(fbi->dev, fbi->map_size, fbi->map_cpu,
 689                               fbi->map_dma);
 690 }
 691
 692 static inline void modify_gpio(void __iomem *reg,
 693                                unsigned long set, unsigned long mask)
 694 {
 695         unsigned long tmp;
 696
 697         tmp = readl(reg) & ~mask;
 698         writel(tmp | set, reg);
 699 }
 700
 701 /*
 702  * s3c2410fb_init_registers - Initialise all LCD-related registers
 703  */
 704 static int s3c2410fb_init_registers(struct fb_info *info)
 705 {
 706         struct s3c2410fb_info *fbi = info->par;
 707         unsigned long flags;
 708         void __iomem *regs = fbi->io;
 709
 710         /* Initialise LCD with values from haret */
 711
 712         local_irq_save(flags);
 713
 714         /* modify the gpio(s) with interrupts set (bjd) */
 715
 716         modify_gpio(S3C2410_GPCUP,  mach_info->gpcup,  mach_info->gpcup_mask);
 717         modify_gpio(S3C2410_GPCCON, mach_info->gpccon, mach_info->gpccon_mask);
 718         modify_gpio(S3C2410_GPDUP,  mach_info->gpdup,  mach_info->gpdup_mask);
 719         modify_gpio(S3C2410_GPDCON, mach_info->gpdcon, mach_info->gpdcon_mask);
 720
 721         local_irq_restore(flags);
 722
 723         writel(fbi->regs.lcdcon1, regs + S3C2410_LCDCON1);
 724         writel(fbi->regs.lcdcon2, regs + S3C2410_LCDCON2);
 725         writel(fbi->regs.lcdcon3, regs + S3C2410_LCDCON3);
 726         writel(fbi->regs.lcdcon4, regs + S3C2410_LCDCON4);
 727         writel(fbi->regs.lcdcon5, regs + S3C2410_LCDCON5);
 728
 729         s3c2410fb_set_lcdaddr(info);
 730
 731         dprintk("LPCSEL    = 0x%08lx\n", mach_info->lpcsel);
 732         writel(mach_info->lpcsel, regs + S3C2410_LPCSEL);
 733
 734         dprintk("replacing TPAL %08x\n", readl(regs + S3C2410_TPAL));
 735
 736         /* ensure temporary palette disabled */
 737         writel(0x00, regs + S3C2410_TPAL);
 738
 739         /* Enable video by setting the ENVID bit to 1 */
 740         fbi->regs.lcdcon1 |= S3C2410_LCDCON1_ENVID;
 741         writel(fbi->regs.lcdcon1, regs + S3C2410_LCDCON1);
 742         return 0;
 743 }
 744
 745 static void s3c2410fb_write_palette(struct s3c2410fb_info *fbi)
 746 {
 747         unsigned int i;
 748         void __iomem *regs = fbi->io;
 749
 750         fbi->palette_ready = 0;
 751
 752         for (i = 0; i < 256; i++) {
 753                 unsigned long ent = fbi->palette_buffer[i];
 754                 if (ent == PALETTE_BUFF_CLEAR)
 755                         continue;
 756
 757                 writel(ent, regs + S3C2410_TFTPAL(i));
 758
 759                 /* it seems the only way to know exactly
 760                  * if the palette wrote ok, is to check
 761                  * to see if the value verifies ok
 762                  */
 763
 764                 if (readw(regs + S3C2410_TFTPAL(i)) == ent)
 765                         fbi->palette_buffer[i] = PALETTE_BUFF_CLEAR;
 766                 else
 767                         fbi->palette_ready = 1;   /* retry */
 768         }
 769 }
 770
 771 static irqreturn_t s3c2410fb_irq(int irq, void *dev_id)
 772 {
 773         struct s3c2410fb_info *fbi = dev_id;
 774         void __iomem *regs = fbi->io;
 775         unsigned long lcdirq = readl(regs + S3C2410_LCDINTPND);
 776
 777         if (lcdirq & S3C2410_LCDINT_FRSYNC) {
 778                 if (fbi->palette_ready)
 779                         s3c2410fb_write_palette(fbi);
 780
 781                 writel(S3C2410_LCDINT_FRSYNC, regs + S3C2410_LCDINTPND);
 782                 writel(S3C2410_LCDINT_FRSYNC, regs + S3C2410_LCDSRCPND);
 783         }
 784
 785         return IRQ_HANDLED;
 786 }
 787
 788 static char driver_name[] = "s3c2410fb";
 789
 790 static int __init s3c2410fb_probe(struct platform_device *pdev)
 791 {
 792         struct s3c2410fb_info *info;
 793         struct s3c2410fb_display *display;
 794         struct fb_info *fbinfo;
 795         struct resource *res;
 796         int ret;
 797         int irq;
 798         int i;
 799         int size;
 800         u32 lcdcon1;
 801
 802         mach_info = pdev->dev.platform_data;
 803         if (mach_info == NULL) {
 804                 dev_err(&pdev->dev,
 805                         "no platform data for lcd, cannot attach\n");
 806                 return -EINVAL;
 807         }
 808
 809         display = mach_info->displays + mach_info->default_display;
 810
 811         irq = platform_get_irq(pdev, 0);
 812         if (irq < 0) {
 813                 dev_err(&pdev->dev, "no irq for device\n");
 814                 return -ENOENT;
 815         }
 816
 817         fbinfo = framebuffer_alloc(sizeof(struct s3c2410fb_info), &pdev->dev);
 818         if (!fbinfo)
 819                 return -ENOMEM;
 820
 821         info = fbinfo->par;
 822         info->dev = &pdev->dev;
 823
 824         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 825         if (res == NULL) {
 826                 dev_err(&pdev->dev, "failed to get memory registers\n");
 827                 ret = -ENXIO;
 828                 goto dealloc_fb;
 829         }
 830
 831         size = (res->end - res->start) + 1;
 832         info->mem = request_mem_region(res->start, size, pdev->name);
 833         if (info->mem == NULL) {
 834                 dev_err(&pdev->dev, "failed to get memory region\n");
 835                 ret = -ENOENT;
 836                 goto dealloc_fb;
 837         }
 838
 839         info->io = ioremap(res->start, size);
 840         if (info->io == NULL) {
 841                 dev_err(&pdev->dev, "ioremap() of registers failed\n");
 842                 ret = -ENXIO;
 843                 goto release_mem;
 844         }
 845
 846         platform_set_drvdata(pdev, fbinfo);
 847
 848         dprintk("devinit\n");
 849
 850         strcpy(fbinfo->fix.id, driver_name);
 851
 852         info->regs.lcdcon1 = display->lcdcon1;
 853         info->regs.lcdcon2 = display->lcdcon2;
 854         info->regs.lcdcon4 = display->lcdcon4;
 855         info->regs.lcdcon5 = display->lcdcon5;
 856
 857         /* Stop the video and unset ENVID if set */
 858         info->regs.lcdcon1 &= ~S3C2410_LCDCON1_ENVID;
 859         lcdcon1 = readl(info->io + S3C2410_LCDCON1);
 860         writel(lcdcon1 & ~S3C2410_LCDCON1_ENVID, info->io + S3C2410_LCDCON1);
 861
 862         info->mach_info             = pdev->dev.platform_data;
 863         info->current_display       = mach_info->default_display;
 864
 865         fbinfo->fix.type            = FB_TYPE_PACKED_PIXELS;
 866         fbinfo->fix.type_aux        = 0;
 867         fbinfo->fix.xpanstep        = 0;
 868         fbinfo->fix.ypanstep        = 0;
 869         fbinfo->fix.ywrapstep       = 0;
 870         fbinfo->fix.accel           = FB_ACCEL_NONE;
 871
 872         fbinfo->var.nonstd          = 0;
 873         fbinfo->var.activate        = FB_ACTIVATE_NOW;
 874         fbinfo->var.height          = display->height;
 875         fbinfo->var.width           = display->width;
 876         fbinfo->var.accel_flags     = 0;
 877         fbinfo->var.vmode           = FB_VMODE_NONINTERLACED;
 878
 879         fbinfo->fbops               = &s3c2410fb_ops;
 880         fbinfo->flags               = FBINFO_FLAG_DEFAULT;
 881         fbinfo->pseudo_palette      = &info->pseudo_pal;
 882
 883         fbinfo->var.xres            = display->xres;
 884         fbinfo->var.xres_virtual    = display->xres;
 885         fbinfo->var.yres            = display->yres;
 886         fbinfo->var.yres_virtual    = display->yres;
 887         fbinfo->var.bits_per_pixel  = display->bpp;
 888         fbinfo->var.left_margin     = display->left_margin;
 889         fbinfo->var.right_margin    = display->right_margin;
 890
 891         fbinfo->var.upper_margin    = display->upper_margin;
 892         fbinfo->var.lower_margin    = display->lower_margin;
 893         fbinfo->var.vsync_len       =
 894                                 S3C2410_LCDCON2_GET_VSPW(display->lcdcon2) + 1;
 895         fbinfo->var.hsync_len       =
 896                                 S3C2410_LCDCON4_GET_HSPW(display->lcdcon4) + 1;
 897
 898         fbinfo->var.red.offset      = 11;
 899         fbinfo->var.green.offset    = 5;
 900         fbinfo->var.blue.offset     = 0;
 901         fbinfo->var.transp.offset   = 0;
 902         fbinfo->var.red.length      = 5;
 903         fbinfo->var.green.length    = 6;
 904         fbinfo->var.blue.length     = 5;
 905         fbinfo->var.transp.length   = 0;
 906
 907         /* find maximum required memory size for display */
 908         for (i = 0; i < mach_info->num_displays; i++) {
 909                 unsigned long smem_len = mach_info->displays[i].xres;
 910
 911                 smem_len *= mach_info->displays[i].yres;
 912                 smem_len *= mach_info->displays[i].bpp;
 913                 smem_len >>= 3;
 914                 if (fbinfo->fix.smem_len < smem_len)
 915                         fbinfo->fix.smem_len = smem_len;
 916         }
 917
 918         for (i = 0; i < 256; i++)
 919                 info->palette_buffer[i] = PALETTE_BUFF_CLEAR;
 920
 921         ret = request_irq(irq, s3c2410fb_irq, IRQF_DISABLED, pdev->name, info);
 922         if (ret) {
 923                 dev_err(&pdev->dev, "cannot get irq %d - err %d\n", irq, ret);
 924                 ret = -EBUSY;
 925                 goto release_regs;
 926         }
 927
 928         info->clk = clk_get(NULL, "lcd");
 929         if (!info->clk || IS_ERR(info->clk)) {
 930                 printk(KERN_ERR "failed to get lcd clock source\n");
 931                 ret = -ENOENT;
 932                 goto release_irq;
 933         }
 934
 935         clk_enable(info->clk);
 936         dprintk("got and enabled clock\n");
 937
 938         msleep(1);
 939
 940         /* Initialize video memory */
 941         ret = s3c2410fb_map_video_memory(fbinfo);
 942         if (ret) {
 943                 printk(KERN_ERR "Failed to allocate video RAM: %d\n", ret);
 944                 ret = -ENOMEM;
 945                 goto release_clock;
 946         }
 947
 948         dprintk("got video memory\n");
 949
 950         s3c2410fb_init_registers(fbinfo);
 951
 952         s3c2410fb_check_var(&fbinfo->var, fbinfo);
 953
 954         ret = register_framebuffer(fbinfo);
 955         if (ret < 0) {
 956                 printk(KERN_ERR "Failed to register framebuffer device: %d\n",
 957                         ret);
 958                 goto free_video_memory;
 959         }
 960
 961         /* create device files */
 962         device_create_file(&pdev->dev, &dev_attr_debug);
 963
 964         printk(KERN_INFO "fb%d: %s frame buffer device\n",
 965                 fbinfo->node, fbinfo->fix.id);
 966
 967         return 0;
 968
 969 free_video_memory:
 970         s3c2410fb_unmap_video_memory(info);
 971 release_clock:
 972         clk_disable(info->clk);
 973         clk_put(info->clk);
 974 release_irq:
 975         free_irq(irq, info);
 976 release_regs:
 977         iounmap(info->io);
 978 release_mem:
 979         release_resource(info->mem);
 980         kfree(info->mem);
 981 dealloc_fb:
 982         framebuffer_release(fbinfo);
 983         return ret;
 984 }
 985
 986 /* s3c2410fb_stop_lcd
 987  *
 988  * shutdown the lcd controller
 989  */
 990 static void s3c2410fb_stop_lcd(struct s3c2410fb_info *fbi)
 991 {
 992         unsigned long flags;
 993
 994         local_irq_save(flags);
 995
 996         fbi->regs.lcdcon1 &= ~S3C2410_LCDCON1_ENVID;
 997         writel(fbi->regs.lcdcon1, fbi->io + S3C2410_LCDCON1);
 998
 999         local_irq_restore(flags);
1000 }
1001
1002 /*
1003  *  Cleanup
1004  */
1005 static int s3c2410fb_remove(struct platform_device *pdev)
1006 {
1007         struct fb_info *fbinfo = platform_get_drvdata(pdev);
1008         struct s3c2410fb_info *info = fbinfo->par;
1009         int irq;
1010
1011         s3c2410fb_stop_lcd(info);
1012         msleep(1);
1013
1014         s3c2410fb_unmap_video_memory(info);
1015
1016         if (info->clk) {
1017                 clk_disable(info->clk);
1018                 clk_put(info->clk);
1019                 info->clk = NULL;
1020         }
1021
1022         irq = platform_get_irq(pdev, 0);
1023         free_irq(irq, info);
1024
1025         release_resource(info->mem);
1026         kfree(info->mem);
1027         iounmap(info->io);
1028         unregister_framebuffer(fbinfo);
1029
1030         return 0;
1031 }
1032
1033 #ifdef CONFIG_PM
1034
1035 /* suspend and resume support for the lcd controller */
1036 static int s3c2410fb_suspend(struct platform_device *dev, pm_message_t state)
1037 {
1038         struct fb_info     *fbinfo = platform_get_drvdata(dev);
1039         struct s3c2410fb_info *info = fbinfo->par;
1040
1041         s3c2410fb_stop_lcd(info);
1042
1043         /* sleep before disabling the clock, we need to ensure
1044          * the LCD DMA engine is not going to get back on the bus
1045          * before the clock goes off again (bjd) */
1046
1047         msleep(1);
1048         clk_disable(info->clk);
1049
1050         return 0;
1051 }
1052
1053 static int s3c2410fb_resume(struct platform_device *dev)
1054 {
1055         struct fb_info     *fbinfo = platform_get_drvdata(dev);
1056         struct s3c2410fb_info *info = fbinfo->par;
1057
1058         clk_enable(info->clk);
1059         msleep(1);
1060
1061         s3c2410fb_init_registers(info);
1062
1063         return 0;
1064 }
1065
1066 #else
1067 #define s3c2410fb_suspend NULL
1068 #define s3c2410fb_resume  NULL
1069 #endif
1070
1071 static struct platform_driver s3c2410fb_driver = {
1072         .probe          = s3c2410fb_probe,
1073         .remove         = s3c2410fb_remove,
1074         .suspend        = s3c2410fb_suspend,
1075         .resume         = s3c2410fb_resume,
1076         .driver         = {
1077                 .name   = "s3c2410-lcd",
1078                 .owner  = THIS_MODULE,
1079         },
1080 };
1081
1082 int __devinit s3c2410fb_init(void)
1083 {
1084         return platform_driver_register(&s3c2410fb_driver);
1085 }
1086
1087 static void __exit s3c2410fb_cleanup(void)
1088 {
1089         platform_driver_unregister(&s3c2410fb_driver);
1090 }
1091
1092 module_init(s3c2410fb_init);
1093 module_exit(s3c2410fb_cleanup);
1094
1095 MODULE_AUTHOR("Arnaud Patard <arnaud.patard@rtp-net.org>, "
1096               "Ben Dooks <ben-linux@fluff.org>");
1097 MODULE_DESCRIPTION("Framebuffer driver for the s3c2410");
1098 MODULE_LICENSE("GPL");