SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/video/s3c2410fb.c

   1 /*
   2  * linux/drivers/video/s3c2410fb.c
   3  *      Copyright (c) Arnaud Patard, Ben Dooks
   4  *
   5  * This file is subject to the terms and conditions of the GNU General Public
   6  * License.  See the file COPYING in the main directory of this archive for
   7  * more details.
   8  *
   9  *          S3C2410 LCD Controller Frame Buffer Driver
  10  *          based on skeletonfb.c, sa1100fb.c and others
  11  *
  12  * ChangeLog
  13  * 2005-04-07: Arnaud Patard <arnaud.patard@rtp-net.org>
  14  *      - u32 state -> pm_message_t state
  15  *      - S3C2410_{VA,SZ}_LCD -> S3C24XX
  16  *
  17  * 2005-03-15: Arnaud Patard <arnaud.patard@rtp-net.org>
  18  *      - Removed the ioctl
  19  *      - use readl/writel instead of __raw_writel/__raw_readl
  20  *
  21  * 2004-12-04: Arnaud Patard <arnaud.patard@rtp-net.org>
  22  *      - Added the possibility to set on or off the
  23  *      debugging messages
  24  *      - Replaced 0 and 1 by on or off when reading the
  25  *      /sys files
  26  *
  27  * 2005-03-23: Ben Dooks <ben-linux@fluff.org>
  28  *      - added non 16bpp modes
  29  *      - updated platform information for range of x/y/bpp
  30  *      - add code to ensure palette is written correctly
  31  *      - add pixel clock divisor control
  32  *
  33  * 2004-11-11: Arnaud Patard <arnaud.patard@rtp-net.org>
  34  *      - Removed the use of currcon as it no more exists
  35  *      - Added LCD power sysfs interface
  36  *
  37  * 2004-11-03: Ben Dooks <ben-linux@fluff.org>
  38  *      - minor cleanups
  39  *      - add suspend/resume support
  40  *      - s3c2410fb_setcolreg() not valid in >8bpp modes
  41  *      - removed last CONFIG_FB_S3C2410_FIXED
  42  *      - ensure lcd controller stopped before cleanup
  43  *      - added sysfs interface for backlight power
  44  *      - added mask for gpio configuration
  45  *      - ensured IRQs disabled during GPIO configuration
  46  *      - disable TPAL before enabling video
  47  *
  48  * 2004-09-20: Arnaud Patard <arnaud.patard@rtp-net.org>
  49  *      - Suppress command line options
  50  *
  51  * 2004-09-15: Arnaud Patard <arnaud.patard@rtp-net.org>
  52  *      - code cleanup
  53  *
  54  * 2004-09-07: Arnaud Patard <arnaud.patard@rtp-net.org>
  55  *      - Renamed from h1940fb.c to s3c2410fb.c
  56  *      - Add support for different devices
  57  *      - Backlight support
  58  *
  59  * 2004-09-05: Herbert Pötzl <herbert@13thfloor.at>
  60  *      - added clock (de-)allocation code
  61  *      - added fixem fbmem option
  62  *
  63  * 2004-07-27: Arnaud Patard <arnaud.patard@rtp-net.org>
  64  *      - code cleanup
  65  *      - added a forgotten return in h1940fb_init
  66  *
  67  * 2004-07-19: Herbert Pötzl <herbert@13thfloor.at>
  68  *      - code cleanup and extended debugging
  69  *
  70  * 2004-07-15: Arnaud Patard <arnaud.patard@rtp-net.org>
  71  *      - First version
  72  */
  73
  74 #include <linux/module.h>
  75 #include <linux/kernel.h>
  76 #include <linux/errno.h>
  77 #include <linux/string.h>
  78 #include <linux/mm.h>
  79 #include <linux/slab.h>
  80 #include <linux/delay.h>
  81 #include <linux/fb.h>
  82 #include <linux/init.h>
  83 #include <linux/dma-mapping.h>
  84 #include <linux/interrupt.h>
  85 #include <linux/platform_device.h>
  86 #include <linux/clk.h>
  87
  88 #include <asm/io.h>
  89 #include <asm/div64.h>
  90
  91 #include <asm/mach/map.h>
  92 #include <asm/arch/regs-lcd.h>
  93 #include <asm/arch/regs-gpio.h>
  94 #include <asm/arch/fb.h>
  95
  96 #ifdef CONFIG_PM
  97 #include <linux/pm.h>
  98 #endif
  99
 100 #include "s3c2410fb.h"
 101
 102 /* Debugging stuff */
 103 #ifdef CONFIG_FB_S3C2410_DEBUG
 104 static int debug        = 1;
 105 #else
 106 static int debug        = 0;
 107 #endif
 108
 109 #define dprintk(msg...) if (debug) { printk(KERN_DEBUG "s3c2410fb: " msg); }
 110
 111 /* useful functions */
 112
 113 /* s3c2410fb_set_lcdaddr
 114  *
 115  * initialise lcd controller address pointers
 116  */
 117 static void s3c2410fb_set_lcdaddr(struct fb_info *info)
 118 {
 119         unsigned long saddr1, saddr2, saddr3;
 120         struct s3c2410fb_info *fbi = info->par;
 121         void __iomem *regs = fbi->io;
 122
 123         saddr1  = info->fix.smem_start >> 1;
 124         saddr2  = info->fix.smem_start;
 125         saddr2 += info->fix.line_length * info->var.yres;
 126         saddr2 >>= 1;
 127
 128         saddr3 = S3C2410_OFFSIZE(0) |
 129                  S3C2410_PAGEWIDTH((info->fix.line_length / 2) & 0x3ff);
 130
 131         dprintk("LCDSADDR1 = 0x%08lx\n", saddr1);
 132         dprintk("LCDSADDR2 = 0x%08lx\n", saddr2);
 133         dprintk("LCDSADDR3 = 0x%08lx\n", saddr3);
 134
 135         writel(saddr1, regs + S3C2410_LCDSADDR1);
 136         writel(saddr2, regs + S3C2410_LCDSADDR2);
 137         writel(saddr3, regs + S3C2410_LCDSADDR3);
 138 }
 139
 140 /* s3c2410fb_calc_pixclk()
 141  *
 142  * calculate divisor for clk->pixclk
 143  */
 144 static unsigned int s3c2410fb_calc_pixclk(struct s3c2410fb_info *fbi,
 145                                           unsigned long pixclk)
 146 {
 147         unsigned long clk = clk_get_rate(fbi->clk);
 148         unsigned long long div;
 149
 150         /* pixclk is in picoseconds, our clock is in Hz
 151          *
 152          * Hz -> picoseconds is / 10^-12
 153          */
 154
 155         div = (unsigned long long)clk * pixclk;
 156         div >>= 12;                     /* div / 2^12 */
 157         do_div(div, 625 * 625UL * 625); /* div / 5^12 */
 158
 159         dprintk("pixclk %ld, divisor is %ld\n", pixclk, (long)div);
 160         return div;
 161 }
 162
 163 /*
 164  *      s3c2410fb_check_var():
 165  *      Get the video params out of 'var'. If a value doesn't fit, round it up,
 166  *      if it's too big, return -EINVAL.
 167  *
 168  */
 169 static int s3c2410fb_check_var(struct fb_var_screeninfo *var,
 170                                struct fb_info *info)
 171 {
 172         struct s3c2410fb_info *fbi = info->par;
 173         struct s3c2410fb_mach_info *mach_info = fbi->dev->platform_data;
 174         struct s3c2410fb_display *display = NULL;
 175         unsigned i;
 176
 177         dprintk("check_var(var=%p, info=%p)\n", var, info);
 178
 179         /* validate x/y resolution */
 180
 181         for (i = 0; i < mach_info->num_displays; i++)
 182                 if (var->yres == mach_info->displays[i].yres &&
 183                     var->xres == mach_info->displays[i].xres &&
 184                     var->bits_per_pixel == mach_info->displays[i].bpp) {
 185                         display = mach_info->displays + i;
 186                         break;
 187                 }
 188
 189         if (!display) {
 190                 dprintk("wrong resolution or depth %dx%d at %d bpp\n",
 191                         var->xres, var->yres, var->bits_per_pixel);
 192                 return -EINVAL;
 193         }
 194
 195         /* it is always the size as the display */
 196         var->xres_virtual = display->xres;
 197         var->yres_virtual = display->yres;
 198         var->height = display->height;
 199         var->width = display->width;
 200
 201         /* copy lcd settings */
 202         var->pixclock = display->pixclock;
 203         var->left_margin = display->left_margin;
 204         var->right_margin = display->right_margin;
 205         var->upper_margin = display->upper_margin;
 206         var->lower_margin = display->lower_margin;
 207         var->vsync_len = display->vsync_len;
 208         var->hsync_len = display->hsync_len;
 209
 210         fbi->regs.lcdcon5 = display->lcdcon5;
 211         /* set display type */
 212         fbi->regs.lcdcon1 = display->type;
 213
 214         var->transp.offset = 0;
 215         var->transp.length = 0;
 216         /* set r/g/b positions */
 217         switch (var->bits_per_pixel) {
 218         case 1:
 219         case 2:
 220         case 4:
 221                 var->red.offset = 0;
 222                 var->red.length = var->bits_per_pixel;
 223                 var->green      = var->red;
 224                 var->blue       = var->red;
 225                 break;
 226         case 8:
 227                 if (display->type != S3C2410_LCDCON1_TFT) {
 228                         /* 8 bpp 332 */
 229                         var->red.length         = 3;
 230                         var->red.offset         = 5;
 231                         var->green.length       = 3;
 232                         var->green.offset       = 2;
 233                         var->blue.length        = 2;
 234                         var->blue.offset        = 0;
 235                 } else {
 236                         var->red.offset         = 0;
 237                         var->red.length         = 8;
 238                         var->green              = var->red;
 239                         var->blue               = var->red;
 240                 }
 241                 break;
 242         case 12:
 243                 /* 12 bpp 444 */
 244                 var->red.length         = 4;
 245                 var->red.offset         = 8;
 246                 var->green.length       = 4;
 247                 var->green.offset       = 4;
 248                 var->blue.length        = 4;
 249                 var->blue.offset        = 0;
 250                 break;
 251
 252         default:
 253         case 16:
 254                 if (display->lcdcon5 & S3C2410_LCDCON5_FRM565) {
 255                         /* 16 bpp, 565 format */
 256                         var->red.offset         = 11;
 257                         var->green.offset       = 5;
 258                         var->blue.offset        = 0;
 259                         var->red.length         = 5;
 260                         var->green.length       = 6;
 261                         var->blue.length        = 5;
 262                 } else {
 263                         /* 16 bpp, 5551 format */
 264                         var->red.offset         = 11;
 265                         var->green.offset       = 6;
 266                         var->blue.offset        = 1;
 267                         var->red.length         = 5;
 268                         var->green.length       = 5;
 269                         var->blue.length        = 5;
 270                 }
 271                 break;
 272         case 32:
 273                 /* 24 bpp 888 and 8 dummy */
 274                 var->red.length         = 8;
 275                 var->red.offset         = 16;
 276                 var->green.length       = 8;
 277                 var->green.offset       = 8;
 278                 var->blue.length        = 8;
 279                 var->blue.offset        = 0;
 280                 break;
 281         }
 282         return 0;
 283 }
 284
 285 /* s3c2410fb_calculate_stn_lcd_regs
 286  *
 287  * calculate register values from var settings
 288  */
 289 static void s3c2410fb_calculate_stn_lcd_regs(const struct fb_info *info,
 290                                              struct s3c2410fb_hw *regs)
 291 {
 292         const struct s3c2410fb_info *fbi = info->par;
 293         const struct fb_var_screeninfo *var = &info->var;
 294         int type = regs->lcdcon1 & ~S3C2410_LCDCON1_TFT;
 295         int hs = var->xres >> 2;
 296         unsigned wdly = (var->left_margin >> 4) - 1;
 297         unsigned wlh = (var->hsync_len >> 4) - 1;
 298
 299         if (type != S3C2410_LCDCON1_STN4)
 300                 hs >>= 1;
 301
 302         switch (var->bits_per_pixel) {
 303         case 1:
 304                 regs->lcdcon1 |= S3C2410_LCDCON1_STN1BPP;
 305                 break;
 306         case 2:
 307                 regs->lcdcon1 |= S3C2410_LCDCON1_STN2GREY;
 308                 break;
 309         case 4:
 310                 regs->lcdcon1 |= S3C2410_LCDCON1_STN4GREY;
 311                 break;
 312         case 8:
 313                 regs->lcdcon1 |= S3C2410_LCDCON1_STN8BPP;
 314                 hs *= 3;
 315                 break;
 316         case 12:
 317                 regs->lcdcon1 |= S3C2410_LCDCON1_STN12BPP;
 318                 hs *= 3;
 319                 break;
 320
 321         default:
 322                 /* invalid pixel depth */
 323                 dev_err(fbi->dev, "invalid bpp %d\n",
 324                         var->bits_per_pixel);
 325         }
 326         /* update X/Y info */
 327         dprintk("setting horz: lft=%d, rt=%d, sync=%d\n",
 328                 var->left_margin, var->right_margin, var->hsync_len);
 329
 330         regs->lcdcon2 = S3C2410_LCDCON2_LINEVAL(var->yres - 1);
 331
 332         if (wdly > 3)
 333                 wdly = 3;
 334
 335         if (wlh > 3)
 336                 wlh = 3;
 337
 338         regs->lcdcon3 = S3C2410_LCDCON3_WDLY(wdly) |
 339                         S3C2410_LCDCON3_LINEBLANK(var->right_margin / 8) |
 340                         S3C2410_LCDCON3_HOZVAL(hs - 1);
 341
 342         regs->lcdcon4 = S3C2410_LCDCON4_WLH(wlh);
 343 }
 344
 345 /* s3c2410fb_calculate_tft_lcd_regs
 346  *
 347  * calculate register values from var settings
 348  */
 349 static void s3c2410fb_calculate_tft_lcd_regs(const struct fb_info *info,
 350                                              struct s3c2410fb_hw *regs)
 351 {
 352         const struct s3c2410fb_info *fbi = info->par;
 353         const struct fb_var_screeninfo *var = &info->var;
 354
 355         switch (var->bits_per_pixel) {
 356         case 1:
 357                 regs->lcdcon1 |= S3C2410_LCDCON1_TFT1BPP;
 358                 break;
 359         case 2:
 360                 regs->lcdcon1 |= S3C2410_LCDCON1_TFT2BPP;
 361                 break;
 362         case 4:
 363                 regs->lcdcon1 |= S3C2410_LCDCON1_TFT4BPP;
 364                 break;
 365         case 8:
 366                 regs->lcdcon1 |= S3C2410_LCDCON1_TFT8BPP;
 367                 regs->lcdcon5 |= S3C2410_LCDCON5_BSWP |
 368                                  S3C2410_LCDCON5_FRM565;
 369                 regs->lcdcon5 &= ~S3C2410_LCDCON5_HWSWP;
 370                 break;
 371         case 16:
 372                 regs->lcdcon1 |= S3C2410_LCDCON1_TFT16BPP;
 373                 regs->lcdcon5 &= ~S3C2410_LCDCON5_BSWP;
 374                 regs->lcdcon5 |= S3C2410_LCDCON5_HWSWP;
 375                 break;
 376         case 32:
 377                 regs->lcdcon1 |= S3C2410_LCDCON1_TFT24BPP;
 378                 regs->lcdcon5 &= ~(S3C2410_LCDCON5_BSWP |
 379                                    S3C2410_LCDCON5_HWSWP |
 380                                    S3C2410_LCDCON5_BPP24BL);
 381                 break;
 382         default:
 383                 /* invalid pixel depth */
 384                 dev_err(fbi->dev, "invalid bpp %d\n",
 385                         var->bits_per_pixel);
 386         }
 387         /* update X/Y info */
 388         dprintk("setting vert: up=%d, low=%d, sync=%d\n",
 389                 var->upper_margin, var->lower_margin, var->vsync_len);
 390
 391         dprintk("setting horz: lft=%d, rt=%d, sync=%d\n",
 392                 var->left_margin, var->right_margin, var->hsync_len);
 393
 394         regs->lcdcon2 = S3C2410_LCDCON2_LINEVAL(var->yres - 1) |
 395                         S3C2410_LCDCON2_VBPD(var->upper_margin - 1) |
 396                         S3C2410_LCDCON2_VFPD(var->lower_margin - 1) |
 397                         S3C2410_LCDCON2_VSPW(var->vsync_len - 1);
 398
 399         regs->lcdcon3 = S3C2410_LCDCON3_HBPD(var->right_margin - 1) |
 400                         S3C2410_LCDCON3_HFPD(var->left_margin - 1) |
 401                         S3C2410_LCDCON3_HOZVAL(var->xres - 1);
 402
 403         regs->lcdcon4 = S3C2410_LCDCON4_HSPW(var->hsync_len - 1);
 404 }
 405
 406 /* s3c2410fb_activate_var
 407  *
 408  * activate (set) the controller from the given framebuffer
 409  * information
 410  */
 411 static void s3c2410fb_activate_var(struct fb_info *info)
 412 {
 413         struct s3c2410fb_info *fbi = info->par;
 414         void __iomem *regs = fbi->io;
 415         int type = fbi->regs.lcdcon1 & S3C2410_LCDCON1_TFT;
 416         struct fb_var_screeninfo *var = &info->var;
 417         int clkdiv = s3c2410fb_calc_pixclk(fbi, var->pixclock) / 2;
 418
 419         dprintk("%s: var->xres  = %d\n", __FUNCTION__, var->xres);
 420         dprintk("%s: var->yres  = %d\n", __FUNCTION__, var->yres);
 421         dprintk("%s: var->bpp   = %d\n", __FUNCTION__, var->bits_per_pixel);
 422
 423         if (type == S3C2410_LCDCON1_TFT) {
 424                 s3c2410fb_calculate_tft_lcd_regs(info, &fbi->regs);
 425                 --clkdiv;
 426                 if (clkdiv < 0)
 427                         clkdiv = 0;
 428         } else {
 429                 s3c2410fb_calculate_stn_lcd_regs(info, &fbi->regs);
 430                 if (clkdiv < 2)
 431                         clkdiv = 2;
 432         }
 433
 434         fbi->regs.lcdcon1 |=  S3C2410_LCDCON1_CLKVAL(clkdiv);
 435
 436         /* write new registers */
 437
 438         dprintk("new register set:\n");
 439         dprintk("lcdcon[1] = 0x%08lx\n", fbi->regs.lcdcon1);
 440         dprintk("lcdcon[2] = 0x%08lx\n", fbi->regs.lcdcon2);
 441         dprintk("lcdcon[3] = 0x%08lx\n", fbi->regs.lcdcon3);
 442         dprintk("lcdcon[4] = 0x%08lx\n", fbi->regs.lcdcon4);
 443         dprintk("lcdcon[5] = 0x%08lx\n", fbi->regs.lcdcon5);
 444
 445         writel(fbi->regs.lcdcon1 & ~S3C2410_LCDCON1_ENVID,
 446                 regs + S3C2410_LCDCON1);
 447         writel(fbi->regs.lcdcon2, regs + S3C2410_LCDCON2);
 448         writel(fbi->regs.lcdcon3, regs + S3C2410_LCDCON3);
 449         writel(fbi->regs.lcdcon4, regs + S3C2410_LCDCON4);
 450         writel(fbi->regs.lcdcon5, regs + S3C2410_LCDCON5);
 451
 452         /* set lcd address pointers */
 453         s3c2410fb_set_lcdaddr(info);
 454
 455         fbi->regs.lcdcon1 |= S3C2410_LCDCON1_ENVID,
 456         writel(fbi->regs.lcdcon1, regs + S3C2410_LCDCON1);
 457 }
 458
 459 /*
 460  *      s3c2410fb_set_par - Alters the hardware state.
 461  *      @info: frame buffer structure that represents a single frame buffer
 462  *
 463  */
 464 static int s3c2410fb_set_par(struct fb_info *info)
 465 {
 466         struct fb_var_screeninfo *var = &info->var;
 467
 468         switch (var->bits_per_pixel) {
 469         case 32:
 470         case 16:
 471         case 12:
 472                 info->fix.visual = FB_VISUAL_TRUECOLOR;
 473                 break;
 474         case 1:
 475                 info->fix.visual = FB_VISUAL_MONO01;
 476                 break;
 477         default:
 478                 info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
 479                 break;
 480         }
 481
 482         info->fix.line_length = (var->width * var->bits_per_pixel) / 8;
 483
 484         /* activate this new configuration */
 485
 486         s3c2410fb_activate_var(info);
 487         return 0;
 488 }
 489
 490 static void schedule_palette_update(struct s3c2410fb_info *fbi,
 491                                     unsigned int regno, unsigned int val)
 492 {
 493         unsigned long flags;
 494         unsigned long irqen;
 495         void __iomem *regs = fbi->io;
 496
 497         local_irq_save(flags);
 498
 499         fbi->palette_buffer[regno] = val;
 500
 501         if (!fbi->palette_ready) {
 502                 fbi->palette_ready = 1;
 503
 504                 /* enable IRQ */
 505                 irqen = readl(regs + S3C2410_LCDINTMSK);
 506                 irqen &= ~S3C2410_LCDINT_FRSYNC;
 507                 writel(irqen, regs + S3C2410_LCDINTMSK);
 508         }
 509
 510         local_irq_restore(flags);
 511 }
 512
 513 /* from pxafb.c */
 514 static inline unsigned int chan_to_field(unsigned int chan,
 515                                          struct fb_bitfield *bf)
 516 {
 517         chan &= 0xffff;
 518         chan >>= 16 - bf->length;
 519         return chan << bf->offset;
 520 }
 521
 522 static int s3c2410fb_setcolreg(unsigned regno,
 523                                unsigned red, unsigned green, unsigned blue,
 524                                unsigned transp, struct fb_info *info)
 525 {
 526         struct s3c2410fb_info *fbi = info->par;
 527         void __iomem *regs = fbi->io;
 528         unsigned int val;
 529
 530         /* dprintk("setcol: regno=%d, rgb=%d,%d,%d\n",
 531                    regno, red, green, blue); */
 532
 533         switch (info->fix.visual) {
 534         case FB_VISUAL_TRUECOLOR:
 535                 /* true-colour, use pseudo-palette */
 536
 537                 if (regno < 16) {
 538                         u32 *pal = info->pseudo_palette;
 539
 540                         val  = chan_to_field(red,   &info->var.red);
 541                         val |= chan_to_field(green, &info->var.green);
 542                         val |= chan_to_field(blue,  &info->var.blue);
 543
 544                         pal[regno] = val;
 545                 }
 546                 break;
 547
 548         case FB_VISUAL_PSEUDOCOLOR:
 549                 if (regno < 256) {
 550                         /* currently assume RGB 5-6-5 mode */
 551
 552                         val  = (red   >>  0) & 0xf800;
 553                         val |= (green >>  5) & 0x07e0;
 554                         val |= (blue  >> 11) & 0x001f;
 555
 556                         writel(val, regs + S3C2410_TFTPAL(regno));
 557                         schedule_palette_update(fbi, regno, val);
 558                 }
 559
 560                 break;
 561
 562         default:
 563                 return 1;       /* unknown type */
 564         }
 565
 566         return 0;
 567 }
 568
 569 /*
 570  *      s3c2410fb_blank
 571  *      @blank_mode: the blank mode we want.
 572  *      @info: frame buffer structure that represents a single frame buffer
 573  *
 574  *      Blank the screen if blank_mode != 0, else unblank. Return 0 if
 575  *      blanking succeeded, != 0 if un-/blanking failed due to e.g. a
 576  *      video mode which doesn't support it. Implements VESA suspend
 577  *      and powerdown modes on hardware that supports disabling hsync/vsync:
 578  *      blank_mode == 2: suspend vsync
 579  *      blank_mode == 3: suspend hsync
 580  *      blank_mode == 4: powerdown
 581  *
 582  *      Returns negative errno on error, or zero on success.
 583  *
 584  */
 585 static int s3c2410fb_blank(int blank_mode, struct fb_info *info)
 586 {
 587         struct s3c2410fb_info *fbi = info->par;
 588         void __iomem *regs = fbi->io;
 589
 590         dprintk("blank(mode=%d, info=%p)\n", blank_mode, info);
 591
 592         if (blank_mode == FB_BLANK_UNBLANK)
 593                 writel(0x0, regs + S3C2410_TPAL);
 594         else {
 595                 dprintk("setting TPAL to output 0x000000\n");
 596                 writel(S3C2410_TPAL_EN, regs + S3C2410_TPAL);
 597         }
 598
 599         return 0;
 600 }
 601
 602 static int s3c2410fb_debug_show(struct device *dev,
 603                                 struct device_attribute *attr, char *buf)
 604 {
 605         return snprintf(buf, PAGE_SIZE, "%s\n", debug ? "on" : "off");
 606 }
 607
 608 static int s3c2410fb_debug_store(struct device *dev,
 609                                  struct device_attribute *attr,
 610                                  const char *buf, size_t len)
 611 {
 612         if (len < 1)
 613                 return -EINVAL;
 614
 615         if (strnicmp(buf, "on", 2) == 0 ||
 616             strnicmp(buf, "1", 1) == 0) {
 617                 debug = 1;
 618                 printk(KERN_DEBUG "s3c2410fb: Debug On");
 619         } else if (strnicmp(buf, "off", 3) == 0 ||
 620                    strnicmp(buf, "0", 1) == 0) {
 621                 debug = 0;
 622                 printk(KERN_DEBUG "s3c2410fb: Debug Off");
 623         } else {
 624                 return -EINVAL;
 625         }
 626
 627         return len;
 628 }
 629
 630 static DEVICE_ATTR(debug, 0666, s3c2410fb_debug_show, s3c2410fb_debug_store);
 631
 632 static struct fb_ops s3c2410fb_ops = {
 633         .owner          = THIS_MODULE,
 634         .fb_check_var   = s3c2410fb_check_var,
 635         .fb_set_par     = s3c2410fb_set_par,
 636         .fb_blank       = s3c2410fb_blank,
 637         .fb_setcolreg   = s3c2410fb_setcolreg,
 638         .fb_fillrect    = cfb_fillrect,
 639         .fb_copyarea    = cfb_copyarea,
 640         .fb_imageblit   = cfb_imageblit,
 641 };
 642
 643 /*
 644  * s3c2410fb_map_video_memory():
 645  *      Allocates the DRAM memory for the frame buffer.  This buffer is
 646  *      remapped into a non-cached, non-buffered, memory region to
 647  *      allow palette and pixel writes to occur without flushing the
 648  *      cache.  Once this area is remapped, all virtual memory
 649  *      access to the video memory should occur at the new region.
 650  */
 651 static int __init s3c2410fb_map_video_memory(struct fb_info *info)
 652 {
 653         struct s3c2410fb_info *fbi = info->par;
 654         dma_addr_t map_dma;
 655         unsigned map_size = PAGE_ALIGN(info->fix.smem_len);
 656
 657         dprintk("map_video_memory(fbi=%p)\n", fbi);
 658
 659         info->screen_base = dma_alloc_writecombine(fbi->dev, map_size,
 660                                                    &map_dma, GFP_KERNEL);
 661
 662         if (info->screen_base) {
 663                 /* prevent initial garbage on screen */
 664                 dprintk("map_video_memory: clear %p:%08x\n",
 665                         info->screen_base, map_size);
 666                 memset(info->screen_base, 0xf0, map_size);
 667
 668                 info->fix.smem_start = map_dma;
 669
 670                 dprintk("map_video_memory: dma=%08lx cpu=%p size=%08x\n",
 671                         info->fix.smem_start, info->screen_base, map_size);
 672         }
 673
 674         return info->screen_base ? 0 : -ENOMEM;
 675 }
 676
 677 static inline void s3c2410fb_unmap_video_memory(struct fb_info *info)
 678 {
 679         struct s3c2410fb_info *fbi = info->par;
 680
 681         dma_free_writecombine(fbi->dev, PAGE_ALIGN(info->fix.smem_len),
 682                               info->screen_base, info->fix.smem_start);
 683 }
 684
 685 static inline void modify_gpio(void __iomem *reg,
 686                                unsigned long set, unsigned long mask)
 687 {
 688         unsigned long tmp;
 689
 690         tmp = readl(reg) & ~mask;
 691         writel(tmp | set, reg);
 692 }
 693
 694 /*
 695  * s3c2410fb_init_registers - Initialise all LCD-related registers
 696  */
 697 static int s3c2410fb_init_registers(struct fb_info *info)
 698 {
 699         struct s3c2410fb_info *fbi = info->par;
 700         struct s3c2410fb_mach_info *mach_info = fbi->dev->platform_data;
 701         unsigned long flags;
 702         void __iomem *regs = fbi->io;
 703
 704         /* Initialise LCD with values from haret */
 705
 706         local_irq_save(flags);
 707
 708         /* modify the gpio(s) with interrupts set (bjd) */
 709
 710         modify_gpio(S3C2410_GPCUP,  mach_info->gpcup,  mach_info->gpcup_mask);
 711         modify_gpio(S3C2410_GPCCON, mach_info->gpccon, mach_info->gpccon_mask);
 712         modify_gpio(S3C2410_GPDUP,  mach_info->gpdup,  mach_info->gpdup_mask);
 713         modify_gpio(S3C2410_GPDCON, mach_info->gpdcon, mach_info->gpdcon_mask);
 714
 715         local_irq_restore(flags);
 716
 717         dprintk("LPCSEL    = 0x%08lx\n", mach_info->lpcsel);
 718         writel(mach_info->lpcsel, regs + S3C2410_LPCSEL);
 719
 720         dprintk("replacing TPAL %08x\n", readl(regs + S3C2410_TPAL));
 721
 722         /* ensure temporary palette disabled */
 723         writel(0x00, regs + S3C2410_TPAL);
 724
 725         return 0;
 726 }
 727
 728 static void s3c2410fb_write_palette(struct s3c2410fb_info *fbi)
 729 {
 730         unsigned int i;
 731         void __iomem *regs = fbi->io;
 732
 733         fbi->palette_ready = 0;
 734
 735         for (i = 0; i < 256; i++) {
 736                 unsigned long ent = fbi->palette_buffer[i];
 737                 if (ent == PALETTE_BUFF_CLEAR)
 738                         continue;
 739
 740                 writel(ent, regs + S3C2410_TFTPAL(i));
 741
 742                 /* it seems the only way to know exactly
 743                  * if the palette wrote ok, is to check
 744                  * to see if the value verifies ok
 745                  */
 746
 747                 if (readw(regs + S3C2410_TFTPAL(i)) == ent)
 748                         fbi->palette_buffer[i] = PALETTE_BUFF_CLEAR;
 749                 else
 750                         fbi->palette_ready = 1;   /* retry */
 751         }
 752 }
 753
 754 static irqreturn_t s3c2410fb_irq(int irq, void *dev_id)
 755 {
 756         struct s3c2410fb_info *fbi = dev_id;
 757         void __iomem *regs = fbi->io;
 758         unsigned long lcdirq = readl(regs + S3C2410_LCDINTPND);
 759
 760         if (lcdirq & S3C2410_LCDINT_FRSYNC) {
 761                 if (fbi->palette_ready)
 762                         s3c2410fb_write_palette(fbi);
 763
 764                 writel(S3C2410_LCDINT_FRSYNC, regs + S3C2410_LCDINTPND);
 765                 writel(S3C2410_LCDINT_FRSYNC, regs + S3C2410_LCDSRCPND);
 766         }
 767
 768         return IRQ_HANDLED;
 769 }
 770
 771 static char driver_name[] = "s3c2410fb";
 772
 773 static int __init s3c2410fb_probe(struct platform_device *pdev)
 774 {
 775         struct s3c2410fb_info *info;
 776         struct s3c2410fb_display *display;
 777         struct fb_info *fbinfo;
 778         struct s3c2410fb_mach_info *mach_info;
 779         struct resource *res;
 780         int ret;
 781         int irq;
 782         int i;
 783         int size;
 784         u32 lcdcon1;
 785
 786         mach_info = pdev->dev.platform_data;
 787         if (mach_info == NULL) {
 788                 dev_err(&pdev->dev,
 789                         "no platform data for lcd, cannot attach\n");
 790                 return -EINVAL;
 791         }
 792
 793         display = mach_info->displays + mach_info->default_display;
 794
 795         irq = platform_get_irq(pdev, 0);
 796         if (irq < 0) {
 797                 dev_err(&pdev->dev, "no irq for device\n");
 798                 return -ENOENT;
 799         }
 800
 801         fbinfo = framebuffer_alloc(sizeof(struct s3c2410fb_info), &pdev->dev);
 802         if (!fbinfo)
 803                 return -ENOMEM;
 804
 805         platform_set_drvdata(pdev, fbinfo);
 806
 807         info = fbinfo->par;
 808         info->dev = &pdev->dev;
 809
 810         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 811         if (res == NULL) {
 812                 dev_err(&pdev->dev, "failed to get memory registers\n");
 813                 ret = -ENXIO;
 814                 goto dealloc_fb;
 815         }
 816
 817         size = (res->end - res->start) + 1;
 818         info->mem = request_mem_region(res->start, size, pdev->name);
 819         if (info->mem == NULL) {
 820                 dev_err(&pdev->dev, "failed to get memory region\n");
 821                 ret = -ENOENT;
 822                 goto dealloc_fb;
 823         }
 824
 825         info->io = ioremap(res->start, size);
 826         if (info->io == NULL) {
 827                 dev_err(&pdev->dev, "ioremap() of registers failed\n");
 828                 ret = -ENXIO;
 829                 goto release_mem;
 830         }
 831
 832         dprintk("devinit\n");
 833
 834         strcpy(fbinfo->fix.id, driver_name);
 835
 836         /* Stop the video */
 837         lcdcon1 = readl(info->io + S3C2410_LCDCON1);
 838         writel(lcdcon1 & ~S3C2410_LCDCON1_ENVID, info->io + S3C2410_LCDCON1);
 839
 840         fbinfo->fix.type            = FB_TYPE_PACKED_PIXELS;
 841         fbinfo->fix.type_aux        = 0;
 842         fbinfo->fix.xpanstep        = 0;
 843         fbinfo->fix.ypanstep        = 0;
 844         fbinfo->fix.ywrapstep       = 0;
 845         fbinfo->fix.accel           = FB_ACCEL_NONE;
 846
 847         fbinfo->var.nonstd          = 0;
 848         fbinfo->var.activate        = FB_ACTIVATE_NOW;
 849         fbinfo->var.accel_flags     = 0;
 850         fbinfo->var.vmode           = FB_VMODE_NONINTERLACED;
 851
 852         fbinfo->fbops               = &s3c2410fb_ops;
 853         fbinfo->flags               = FBINFO_FLAG_DEFAULT;
 854         fbinfo->pseudo_palette      = &info->pseudo_pal;
 855
 856         for (i = 0; i < 256; i++)
 857                 info->palette_buffer[i] = PALETTE_BUFF_CLEAR;
 858
 859         ret = request_irq(irq, s3c2410fb_irq, IRQF_DISABLED, pdev->name, info);
 860         if (ret) {
 861                 dev_err(&pdev->dev, "cannot get irq %d - err %d\n", irq, ret);
 862                 ret = -EBUSY;
 863                 goto release_regs;
 864         }
 865
 866         info->clk = clk_get(NULL, "lcd");
 867         if (!info->clk || IS_ERR(info->clk)) {
 868                 printk(KERN_ERR "failed to get lcd clock source\n");
 869                 ret = -ENOENT;
 870                 goto release_irq;
 871         }
 872
 873         clk_enable(info->clk);
 874         dprintk("got and enabled clock\n");
 875
 876         msleep(1);
 877
 878         /* find maximum required memory size for display */
 879         for (i = 0; i < mach_info->num_displays; i++) {
 880                 unsigned long smem_len = mach_info->displays[i].xres;
 881
 882                 smem_len *= mach_info->displays[i].yres;
 883                 smem_len *= mach_info->displays[i].bpp;
 884                 smem_len >>= 3;
 885                 if (fbinfo->fix.smem_len < smem_len)
 886                         fbinfo->fix.smem_len = smem_len;
 887         }
 888
 889         /* Initialize video memory */
 890         ret = s3c2410fb_map_video_memory(fbinfo);
 891         if (ret) {
 892                 printk(KERN_ERR "Failed to allocate video RAM: %d\n", ret);
 893                 ret = -ENOMEM;
 894                 goto release_clock;
 895         }
 896
 897         dprintk("got video memory\n");
 898
 899         fbinfo->var.xres = display->xres;
 900         fbinfo->var.yres = display->yres;
 901         fbinfo->var.bits_per_pixel = display->bpp;
 902
 903         s3c2410fb_init_registers(fbinfo);
 904
 905         s3c2410fb_check_var(&fbinfo->var, fbinfo);
 906
 907         ret = register_framebuffer(fbinfo);
 908         if (ret < 0) {
 909                 printk(KERN_ERR "Failed to register framebuffer device: %d\n",
 910                         ret);
 911                 goto free_video_memory;
 912         }
 913
 914         /* create device files */
 915         device_create_file(&pdev->dev, &dev_attr_debug);
 916
 917         printk(KERN_INFO "fb%d: %s frame buffer device\n",
 918                 fbinfo->node, fbinfo->fix.id);
 919
 920         return 0;
 921
 922 free_video_memory:
 923         s3c2410fb_unmap_video_memory(fbinfo);
 924 release_clock:
 925         clk_disable(info->clk);
 926         clk_put(info->clk);
 927 release_irq:
 928         free_irq(irq, info);
 929 release_regs:
 930         iounmap(info->io);
 931 release_mem:
 932         release_resource(info->mem);
 933         kfree(info->mem);
 934 dealloc_fb:
 935         platform_set_drvdata(pdev, NULL);
 936         framebuffer_release(fbinfo);
 937         return ret;
 938 }
 939
 940 /* s3c2410fb_stop_lcd
 941  *
 942  * shutdown the lcd controller
 943  */
 944 static void s3c2410fb_stop_lcd(struct s3c2410fb_info *fbi)
 945 {
 946         unsigned long flags;
 947
 948         local_irq_save(flags);
 949
 950         fbi->regs.lcdcon1 &= ~S3C2410_LCDCON1_ENVID;
 951         writel(fbi->regs.lcdcon1, fbi->io + S3C2410_LCDCON1);
 952
 953         local_irq_restore(flags);
 954 }
 955
 956 /*
 957  *  Cleanup
 958  */
 959 static int s3c2410fb_remove(struct platform_device *pdev)
 960 {
 961         struct fb_info *fbinfo = platform_get_drvdata(pdev);
 962         struct s3c2410fb_info *info = fbinfo->par;
 963         int irq;
 964
 965         unregister_framebuffer(fbinfo);
 966
 967         s3c2410fb_stop_lcd(info);
 968         msleep(1);
 969
 970         s3c2410fb_unmap_video_memory(fbinfo);
 971
 972         if (info->clk) {
 973                 clk_disable(info->clk);
 974                 clk_put(info->clk);
 975                 info->clk = NULL;
 976         }
 977
 978         irq = platform_get_irq(pdev, 0);
 979         free_irq(irq, info);
 980
 981         iounmap(info->io);
 982
 983         release_resource(info->mem);
 984         kfree(info->mem);
 985
 986         platform_set_drvdata(pdev, NULL);
 987         framebuffer_release(fbinfo);
 988
 989         return 0;
 990 }
 991
 992 #ifdef CONFIG_PM
 993
 994 /* suspend and resume support for the lcd controller */
 995 static int s3c2410fb_suspend(struct platform_device *dev, pm_message_t state)
 996 {
 997         struct fb_info     *fbinfo = platform_get_drvdata(dev);
 998         struct s3c2410fb_info *info = fbinfo->par;
 999
1000         s3c2410fb_stop_lcd(info);
1001
1002         /* sleep before disabling the clock, we need to ensure
1003          * the LCD DMA engine is not going to get back on the bus
1004          * before the clock goes off again (bjd) */
1005
1006         msleep(1);
1007         clk_disable(info->clk);
1008
1009         return 0;
1010 }
1011
1012 static int s3c2410fb_resume(struct platform_device *dev)
1013 {
1014         struct fb_info     *fbinfo = platform_get_drvdata(dev);
1015         struct s3c2410fb_info *info = fbinfo->par;
1016
1017         clk_enable(info->clk);
1018         msleep(1);
1019
1020         s3c2410fb_init_registers(info);
1021
1022         return 0;
1023 }
1024
1025 #else
1026 #define s3c2410fb_suspend NULL
1027 #define s3c2410fb_resume  NULL
1028 #endif
1029
1030 static struct platform_driver s3c2410fb_driver = {
1031         .probe          = s3c2410fb_probe,
1032         .remove         = s3c2410fb_remove,
1033         .suspend        = s3c2410fb_suspend,
1034         .resume         = s3c2410fb_resume,
1035         .driver         = {
1036                 .name   = "s3c2410-lcd",
1037                 .owner  = THIS_MODULE,
1038         },
1039 };
1040
1041 int __init s3c2410fb_init(void)
1042 {
1043         return platform_driver_register(&s3c2410fb_driver);
1044 }
1045
1046 static void __exit s3c2410fb_cleanup(void)
1047 {
1048         platform_driver_unregister(&s3c2410fb_driver);
1049 }
1050
1051 module_init(s3c2410fb_init);
1052 module_exit(s3c2410fb_cleanup);
1053
1054 MODULE_AUTHOR("Arnaud Patard <arnaud.patard@rtp-net.org>, "
1055               "Ben Dooks <ben-linux@fluff.org>");
1056 MODULE_DESCRIPTION("Framebuffer driver for the s3c2410");
1057 MODULE_LICENSE("GPL");