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   1 /*
   2  * linux/drivers/video/s3c2410fb.c
   3  *      Copyright (c) Arnaud Patard, Ben Dooks
   4  *
   5  * This file is subject to the terms and conditions of the GNU General Public
   6  * License.  See the file COPYING in the main directory of this archive for
   7  * more details.
   8  *
   9  *          S3C2410 LCD Controller Frame Buffer Driver
  10  *          based on skeletonfb.c, sa1100fb.c and others
  11  *
  12  * ChangeLog
  13  * 2005-04-07: Arnaud Patard <arnaud.patard@rtp-net.org>
  14  *      - u32 state -> pm_message_t state
  15  *      - S3C2410_{VA,SZ}_LCD -> S3C24XX
  16  *
  17  * 2005-03-15: Arnaud Patard <arnaud.patard@rtp-net.org>
  18  *      - Removed the ioctl
  19  *      - use readl/writel instead of __raw_writel/__raw_readl
  20  *
  21  * 2004-12-04: Arnaud Patard <arnaud.patard@rtp-net.org>
  22  *      - Added the possibility to set on or off the
  23  *      debugging mesaages
  24  *      - Replaced 0 and 1 by on or off when reading the
  25  *      /sys files
  26  *
  27  * 2005-03-23: Ben Dooks <ben-linux@fluff.org>
  28  *      - added non 16bpp modes
  29  *      - updated platform information for range of x/y/bpp
  30  *      - add code to ensure palette is written correctly
  31  *      - add pixel clock divisor control
  32  *
  33  * 2004-11-11: Arnaud Patard <arnaud.patard@rtp-net.org>
  34  *      - Removed the use of currcon as it no more exist
  35  *      - Added LCD power sysfs interface
  36  *
  37  * 2004-11-03: Ben Dooks <ben-linux@fluff.org>
  38  *      - minor cleanups
  39  *      - add suspend/resume support
  40  *      - s3c2410fb_setcolreg() not valid in >8bpp modes
  41  *      - removed last CONFIG_FB_S3C2410_FIXED
  42  *      - ensure lcd controller stopped before cleanup
  43  *      - added sysfs interface for backlight power
  44  *      - added mask for gpio configuration
  45  *      - ensured IRQs disabled during GPIO configuration
  46  *      - disable TPAL before enabling video
  47  *
  48  * 2004-09-20: Arnaud Patard <arnaud.patard@rtp-net.org>
  49  *      - Suppress command line options
  50  *
  51  * 2004-09-15: Arnaud Patard <arnaud.patard@rtp-net.org>
  52  *      - code cleanup
  53  *
  54  * 2004-09-07: Arnaud Patard <arnaud.patard@rtp-net.org>
  55  *      - Renamed from h1940fb.c to s3c2410fb.c
  56  *      - Add support for different devices
  57  *      - Backlight support
  58  *
  59  * 2004-09-05: Herbert Pötzl <herbert@13thfloor.at>
  60  *      - added clock (de-)allocation code
  61  *      - added fixem fbmem option
  62  *
  63  * 2004-07-27: Arnaud Patard <arnaud.patard@rtp-net.org>
  64  *      - code cleanup
  65  *      - added a forgotten return in h1940fb_init
  66  *
  67  * 2004-07-19: Herbert Pötzl <herbert@13thfloor.at>
  68  *      - code cleanup and extended debugging
  69  *
  70  * 2004-07-15: Arnaud Patard <arnaud.patard@rtp-net.org>
  71  *      - First version
  72  */
  73
  74 #include <linux/module.h>
  75 #include <linux/kernel.h>
  76 #include <linux/errno.h>
  77 #include <linux/string.h>
  78 #include <linux/mm.h>
  79 #include <linux/slab.h>
  80 #include <linux/delay.h>
  81 #include <linux/fb.h>
  82 #include <linux/init.h>
  83 #include <linux/dma-mapping.h>
  84 #include <linux/interrupt.h>
  85 #include <linux/workqueue.h>
  86 #include <linux/wait.h>
  87 #include <linux/platform_device.h>
  88 #include <linux/clk.h>
  89
  90 #include <asm/io.h>
  91 #include <asm/uaccess.h>
  92 #include <asm/div64.h>
  93
  94 #include <asm/mach/map.h>
  95 #include <asm/arch/regs-lcd.h>
  96 #include <asm/arch/regs-gpio.h>
  97 #include <asm/arch/fb.h>
  98
  99 #ifdef CONFIG_PM
 100 #include <linux/pm.h>
 101 #endif
 102
 103 #include "s3c2410fb.h"
 104
 105 static struct s3c2410fb_mach_info *mach_info;
 106
 107 /* Debugging stuff */
 108 #ifdef CONFIG_FB_S3C2410_DEBUG
 109 static int debug        = 1;
 110 #else
 111 static int debug        = 0;
 112 #endif
 113
 114 #define dprintk(msg...) if (debug) { printk(KERN_DEBUG "s3c2410fb: " msg); }
 115
 116 /* useful functions */
 117
 118 /* s3c2410fb_set_lcdaddr
 119  *
 120  * initialise lcd controller address pointers
 121  */
 122 static void s3c2410fb_set_lcdaddr(struct fb_info *info)
 123 {
 124         unsigned long saddr1, saddr2, saddr3;
 125         int line_length = info->var.xres * info->var.bits_per_pixel;
 126
 127         saddr1  = info->fix.smem_start >> 1;
 128         saddr2  = info->fix.smem_start;
 129         saddr2 += (line_length * info->var.yres) / 8;
 130         saddr2 >>= 1;
 131
 132         saddr3 = S3C2410_OFFSIZE(0) |
 133                  S3C2410_PAGEWIDTH((line_length / 16) & 0x3ff);
 134
 135         dprintk("LCDSADDR1 = 0x%08lx\n", saddr1);
 136         dprintk("LCDSADDR2 = 0x%08lx\n", saddr2);
 137         dprintk("LCDSADDR3 = 0x%08lx\n", saddr3);
 138
 139         writel(saddr1, S3C2410_LCDSADDR1);
 140         writel(saddr2, S3C2410_LCDSADDR2);
 141         writel(saddr3, S3C2410_LCDSADDR3);
 142 }
 143
 144 /* s3c2410fb_calc_pixclk()
 145  *
 146  * calculate divisor for clk->pixclk
 147  */
 148 static unsigned int s3c2410fb_calc_pixclk(struct s3c2410fb_info *fbi,
 149                                           unsigned long pixclk)
 150 {
 151         unsigned long clk = clk_get_rate(fbi->clk);
 152         unsigned long long div;
 153
 154         /* pixclk is in picoseoncds, our clock is in Hz
 155          *
 156          * Hz -> picoseconds is / 10^-12
 157          */
 158
 159         div = (unsigned long long)clk * pixclk;
 160         do_div(div, 1000000UL);
 161         do_div(div, 1000000UL);
 162
 163         dprintk("pixclk %ld, divisor is %ld\n", pixclk, (long)div);
 164         return div;
 165 }
 166
 167 /*
 168  *      s3c2410fb_check_var():
 169  *      Get the video params out of 'var'. If a value doesn't fit, round it up,
 170  *      if it's too big, return -EINVAL.
 171  *
 172  */
 173 static int s3c2410fb_check_var(struct fb_var_screeninfo *var,
 174                                struct fb_info *info)
 175 {
 176         struct s3c2410fb_info *fbi = info->par;
 177         struct s3c2410fb_mach_info *mach_info = fbi->mach_info;
 178         struct s3c2410fb_display *display = NULL;
 179         unsigned i;
 180
 181         dprintk("check_var(var=%p, info=%p)\n", var, info);
 182
 183         /* validate x/y resolution */
 184
 185         for (i = 0; i < mach_info->num_displays; i++)
 186                 if (var->yres == mach_info->displays[i].yres &&
 187                     var->xres == mach_info->displays[i].xres &&
 188                     var->bits_per_pixel == mach_info->displays[i].bpp) {
 189                         display = mach_info->displays + i;
 190                         fbi->current_display = i;
 191                         break;
 192                 }
 193
 194         if (!display) {
 195                 dprintk("wrong resolution or depth %dx%d at %d bpp\n",
 196                         var->xres, var->yres, var->bits_per_pixel);
 197                 return -EINVAL;
 198         }
 199
 200         var->transp.offset = 0;
 201         var->transp.length = 0;
 202         /* set r/g/b positions */
 203         switch (var->bits_per_pixel) {
 204         case 1:
 205         case 2:
 206         case 4:
 207                 var->red.offset = 0;
 208                 var->red.length = var->bits_per_pixel;
 209                 var->green      = var->red;
 210                 var->blue       = var->red;
 211                 break;
 212         case 8:
 213                 if (display->type != S3C2410_LCDCON1_TFT) {
 214                         /* 8 bpp 332 */
 215                         var->red.length         = 3;
 216                         var->red.offset         = 5;
 217                         var->green.length       = 3;
 218                         var->green.offset       = 2;
 219                         var->blue.length        = 2;
 220                         var->blue.offset        = 0;
 221                 } else {
 222                         var->red.offset         = 0;
 223                         var->red.length         = 8;
 224                         var->green              = var->red;
 225                         var->blue               = var->red;
 226                 }
 227                 break;
 228         case 12:
 229                 /* 12 bpp 444 */
 230                 var->red.length         = 4;
 231                 var->red.offset         = 8;
 232                 var->green.length       = 4;
 233                 var->green.offset       = 4;
 234                 var->blue.length        = 4;
 235                 var->blue.offset        = 0;
 236                 break;
 237
 238         default:
 239         case 16:
 240                 if (display->regs.lcdcon5 & S3C2410_LCDCON5_FRM565) {
 241                         /* 16 bpp, 565 format */
 242                         var->red.offset         = 11;
 243                         var->green.offset       = 5;
 244                         var->blue.offset        = 0;
 245                         var->red.length         = 5;
 246                         var->green.length       = 6;
 247                         var->blue.length        = 5;
 248                 } else {
 249                         /* 16 bpp, 5551 format */
 250                         var->red.offset         = 11;
 251                         var->green.offset       = 6;
 252                         var->blue.offset        = 1;
 253                         var->red.length         = 5;
 254                         var->green.length       = 5;
 255                         var->blue.length        = 5;
 256                 }
 257                 break;
 258         case 24:
 259                 /* 24 bpp 888 */
 260                 var->red.length         = 8;
 261                 var->red.offset         = 16;
 262                 var->green.length       = 8;
 263                 var->green.offset       = 8;
 264                 var->blue.length        = 8;
 265                 var->blue.offset        = 0;
 266                 break;
 267
 268
 269         }
 270         return 0;
 271 }
 272
 273 /* s3c2410fb_activate_var
 274  *
 275  * activate (set) the controller from the given framebuffer
 276  * information
 277  */
 278 static void s3c2410fb_activate_var(struct fb_info *info,
 279                                    struct fb_var_screeninfo *var)
 280 {
 281         struct s3c2410fb_info *fbi = info->par;
 282         struct s3c2410fb_mach_info *mach_info = fbi->mach_info;
 283         struct s3c2410fb_display *display = mach_info->displays +
 284                                             fbi->current_display;
 285         int hs;
 286
 287         fbi->regs.lcdcon1 &= ~S3C2410_LCDCON1_MODEMASK;
 288         fbi->regs.lcdcon1 &= ~S3C2410_LCDCON1_TFT;
 289
 290         dprintk("%s: var->xres  = %d\n", __FUNCTION__, var->xres);
 291         dprintk("%s: var->yres  = %d\n", __FUNCTION__, var->yres);
 292         dprintk("%s: var->bpp   = %d\n", __FUNCTION__, var->bits_per_pixel);
 293
 294         fbi->regs.lcdcon1 |= display->type;
 295
 296         if (display->type == S3C2410_LCDCON1_TFT)
 297                 switch (var->bits_per_pixel) {
 298                 case 1:
 299                         fbi->regs.lcdcon1 |= S3C2410_LCDCON1_TFT1BPP;
 300                         break;
 301                 case 2:
 302                         fbi->regs.lcdcon1 |= S3C2410_LCDCON1_TFT2BPP;
 303                         break;
 304                 case 4:
 305                         fbi->regs.lcdcon1 |= S3C2410_LCDCON1_TFT4BPP;
 306                         break;
 307                 case 8:
 308                         fbi->regs.lcdcon1 |= S3C2410_LCDCON1_TFT8BPP;
 309                         break;
 310                 case 16:
 311                         fbi->regs.lcdcon1 |= S3C2410_LCDCON1_TFT16BPP;
 312                         break;
 313
 314                 default:
 315                         /* invalid pixel depth */
 316                         dev_err(fbi->dev, "invalid bpp %d\n",
 317                                 var->bits_per_pixel);
 318                 }
 319         else
 320                 switch (var->bits_per_pixel) {
 321                 case 1:
 322                         fbi->regs.lcdcon1 |= S3C2410_LCDCON1_STN1BPP;
 323                         break;
 324                 case 2:
 325                         fbi->regs.lcdcon1 |= S3C2410_LCDCON1_STN2GREY;
 326                         break;
 327                 case 4:
 328                         fbi->regs.lcdcon1 |= S3C2410_LCDCON1_STN4GREY;
 329                         break;
 330                 case 8:
 331                         fbi->regs.lcdcon1 |= S3C2410_LCDCON1_STN8BPP;
 332                         break;
 333                 case 12:
 334                         fbi->regs.lcdcon1 |= S3C2410_LCDCON1_STN12BPP;
 335                         break;
 336
 337                 default:
 338                         /* invalid pixel depth */
 339                         dev_err(fbi->dev, "invalid bpp %d\n",
 340                                 var->bits_per_pixel);
 341                 }
 342
 343         /* check to see if we need to update sync/borders */
 344
 345         if (!mach_info->fixed_syncs) {
 346                 dprintk("setting vert: up=%d, low=%d, sync=%d\n",
 347                         var->upper_margin, var->lower_margin, var->vsync_len);
 348
 349                 dprintk("setting horz: lft=%d, rt=%d, sync=%d\n",
 350                         var->left_margin, var->right_margin, var->hsync_len);
 351
 352                 fbi->regs.lcdcon2 =
 353                         S3C2410_LCDCON2_VBPD(var->upper_margin - 1) |
 354                         S3C2410_LCDCON2_VFPD(var->lower_margin - 1) |
 355                         S3C2410_LCDCON2_VSPW(var->vsync_len - 1);
 356
 357                 fbi->regs.lcdcon3 =
 358                         S3C2410_LCDCON3_HBPD(var->right_margin - 1) |
 359                         S3C2410_LCDCON3_HFPD(var->left_margin - 1);
 360
 361                 fbi->regs.lcdcon4 &= ~S3C2410_LCDCON4_HSPW(0xff);
 362                 fbi->regs.lcdcon4 |=  S3C2410_LCDCON4_HSPW(var->hsync_len - 1);
 363         }
 364
 365         /* update X/Y info */
 366
 367         fbi->regs.lcdcon2 &= ~S3C2410_LCDCON2_LINEVAL(0x3ff);
 368         fbi->regs.lcdcon2 |=  S3C2410_LCDCON2_LINEVAL(var->yres - 1);
 369
 370         switch (display->type) {
 371         case S3C2410_LCDCON1_DSCAN4:
 372         case S3C2410_LCDCON1_STN8:
 373                 hs = var->xres / 8;
 374                 break;
 375         case S3C2410_LCDCON1_STN4:
 376                 hs = var->xres / 4;
 377                 break;
 378         default:
 379         case S3C2410_LCDCON1_TFT:
 380                 hs = var->xres;
 381                 break;
 382         }
 383
 384         /* Special cases : STN color displays */
 385         if (((fbi->regs.lcdcon1 & S3C2410_LCDCON1_MODEMASK) == S3C2410_LCDCON1_STN8BPP) ||
 386             ((fbi->regs.lcdcon1 & S3C2410_LCDCON1_MODEMASK) == S3C2410_LCDCON1_STN12BPP))
 387                 hs = hs * 3;
 388
 389         fbi->regs.lcdcon3 &= ~S3C2410_LCDCON3_HOZVAL(0x7ff);
 390         fbi->regs.lcdcon3 |=  S3C2410_LCDCON3_HOZVAL(hs - 1);
 391
 392         if (var->pixclock > 0) {
 393                 int clkdiv = s3c2410fb_calc_pixclk(fbi, var->pixclock);
 394
 395                 if (display->type == S3C2410_LCDCON1_TFT) {
 396                         clkdiv = (clkdiv / 2) - 1;
 397                         if (clkdiv < 0)
 398                                 clkdiv = 0;
 399                 } else {
 400                         clkdiv = (clkdiv / 2);
 401                         if (clkdiv < 2)
 402                                 clkdiv = 2;
 403                 }
 404
 405                 fbi->regs.lcdcon1 &= ~S3C2410_LCDCON1_CLKVAL(0x3ff);
 406                 fbi->regs.lcdcon1 |=  S3C2410_LCDCON1_CLKVAL(clkdiv);
 407         }
 408
 409         /* write new registers */
 410
 411         dprintk("new register set:\n");
 412         dprintk("lcdcon[1] = 0x%08lx\n", fbi->regs.lcdcon1);
 413         dprintk("lcdcon[2] = 0x%08lx\n", fbi->regs.lcdcon2);
 414         dprintk("lcdcon[3] = 0x%08lx\n", fbi->regs.lcdcon3);
 415         dprintk("lcdcon[4] = 0x%08lx\n", fbi->regs.lcdcon4);
 416         dprintk("lcdcon[5] = 0x%08lx\n", fbi->regs.lcdcon5);
 417
 418         writel(fbi->regs.lcdcon1 & ~S3C2410_LCDCON1_ENVID, S3C2410_LCDCON1);
 419         writel(fbi->regs.lcdcon2, S3C2410_LCDCON2);
 420         writel(fbi->regs.lcdcon3, S3C2410_LCDCON3);
 421         writel(fbi->regs.lcdcon4, S3C2410_LCDCON4);
 422         writel(fbi->regs.lcdcon5, S3C2410_LCDCON5);
 423
 424         /* set lcd address pointers */
 425         s3c2410fb_set_lcdaddr(info);
 426
 427         writel(fbi->regs.lcdcon1, S3C2410_LCDCON1);
 428 }
 429
 430 /*
 431  *      s3c2410fb_set_par - Alters the hardware state.
 432  *      @info: frame buffer structure that represents a single frame buffer
 433  *
 434  */
 435 static int s3c2410fb_set_par(struct fb_info *info)
 436 {
 437         struct fb_var_screeninfo *var = &info->var;
 438
 439         switch (var->bits_per_pixel) {
 440         case 16:
 441                 info->fix.visual = FB_VISUAL_TRUECOLOR;
 442                 break;
 443         case 1:
 444                 info->fix.visual = FB_VISUAL_MONO01;
 445                 break;
 446         default:
 447                 info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
 448                 break;
 449         }
 450
 451         info->fix.line_length = (var->width * var->bits_per_pixel) / 8;
 452
 453         /* activate this new configuration */
 454
 455         s3c2410fb_activate_var(info, var);
 456         return 0;
 457 }
 458
 459 static void schedule_palette_update(struct s3c2410fb_info *fbi,
 460                                     unsigned int regno, unsigned int val)
 461 {
 462         unsigned long flags;
 463         unsigned long irqen;
 464         void __iomem *regs = fbi->io;
 465
 466         local_irq_save(flags);
 467
 468         fbi->palette_buffer[regno] = val;
 469
 470         if (!fbi->palette_ready) {
 471                 fbi->palette_ready = 1;
 472
 473                 /* enable IRQ */
 474                 irqen = readl(regs + S3C2410_LCDINTMSK);
 475                 irqen &= ~S3C2410_LCDINT_FRSYNC;
 476                 writel(irqen, regs + S3C2410_LCDINTMSK);
 477         }
 478
 479         local_irq_restore(flags);
 480 }
 481
 482 /* from pxafb.c */
 483 static inline unsigned int chan_to_field(unsigned int chan,
 484                                          struct fb_bitfield *bf)
 485 {
 486         chan &= 0xffff;
 487         chan >>= 16 - bf->length;
 488         return chan << bf->offset;
 489 }
 490
 491 static int s3c2410fb_setcolreg(unsigned regno,
 492                                unsigned red, unsigned green, unsigned blue,
 493                                unsigned transp, struct fb_info *info)
 494 {
 495         struct s3c2410fb_info *fbi = info->par;
 496         unsigned int val;
 497
 498         /* dprintk("setcol: regno=%d, rgb=%d,%d,%d\n",
 499                    regno, red, green, blue); */
 500
 501         switch (info->fix.visual) {
 502         case FB_VISUAL_TRUECOLOR:
 503                 /* true-colour, use pseudo-palette */
 504
 505                 if (regno < 16) {
 506                         u32 *pal = info->pseudo_palette;
 507
 508                         val  = chan_to_field(red,   &info->var.red);
 509                         val |= chan_to_field(green, &info->var.green);
 510                         val |= chan_to_field(blue,  &info->var.blue);
 511
 512                         pal[regno] = val;
 513                 }
 514                 break;
 515
 516         case FB_VISUAL_PSEUDOCOLOR:
 517                 if (regno < 256) {
 518                         /* currently assume RGB 5-6-5 mode */
 519
 520                         val  = ((red   >>  0) & 0xf800);
 521                         val |= ((green >>  5) & 0x07e0);
 522                         val |= ((blue  >> 11) & 0x001f);
 523
 524                         writel(val, S3C2410_TFTPAL(regno));
 525                         schedule_palette_update(fbi, regno, val);
 526                 }
 527
 528                 break;
 529
 530         default:
 531                 return 1;       /* unknown type */
 532         }
 533
 534         return 0;
 535 }
 536
 537 /*
 538  *      s3c2410fb_blank
 539  *      @blank_mode: the blank mode we want.
 540  *      @info: frame buffer structure that represents a single frame buffer
 541  *
 542  *      Blank the screen if blank_mode != 0, else unblank. Return 0 if
 543  *      blanking succeeded, != 0 if un-/blanking failed due to e.g. a
 544  *      video mode which doesn't support it. Implements VESA suspend
 545  *      and powerdown modes on hardware that supports disabling hsync/vsync:
 546  *      blank_mode == 2: suspend vsync
 547  *      blank_mode == 3: suspend hsync
 548  *      blank_mode == 4: powerdown
 549  *
 550  *      Returns negative errno on error, or zero on success.
 551  *
 552  */
 553 static int s3c2410fb_blank(int blank_mode, struct fb_info *info)
 554 {
 555         dprintk("blank(mode=%d, info=%p)\n", blank_mode, info);
 556
 557         if (mach_info == NULL)
 558                 return -EINVAL;
 559
 560         if (blank_mode == FB_BLANK_UNBLANK)
 561                 writel(0x0, S3C2410_TPAL);
 562         else {
 563                 dprintk("setting TPAL to output 0x000000\n");
 564                 writel(S3C2410_TPAL_EN, S3C2410_TPAL);
 565         }
 566
 567         return 0;
 568 }
 569
 570 static int s3c2410fb_debug_show(struct device *dev,
 571                                 struct device_attribute *attr, char *buf)
 572 {
 573         return snprintf(buf, PAGE_SIZE, "%s\n", debug ? "on" : "off");
 574 }
 575 static int s3c2410fb_debug_store(struct device *dev,
 576                                  struct device_attribute *attr,
 577                                  const char *buf, size_t len)
 578 {
 579         if (mach_info == NULL)
 580                 return -EINVAL;
 581
 582         if (len < 1)
 583                 return -EINVAL;
 584
 585         if (strnicmp(buf, "on", 2) == 0 ||
 586             strnicmp(buf, "1", 1) == 0) {
 587                 debug = 1;
 588                 printk(KERN_DEBUG "s3c2410fb: Debug On");
 589         } else if (strnicmp(buf, "off", 3) == 0 ||
 590                    strnicmp(buf, "0", 1) == 0) {
 591                 debug = 0;
 592                 printk(KERN_DEBUG "s3c2410fb: Debug Off");
 593         } else {
 594                 return -EINVAL;
 595         }
 596
 597         return len;
 598 }
 599
 600 static DEVICE_ATTR(debug, 0666, s3c2410fb_debug_show, s3c2410fb_debug_store);
 601
 602 static struct fb_ops s3c2410fb_ops = {
 603         .owner          = THIS_MODULE,
 604         .fb_check_var   = s3c2410fb_check_var,
 605         .fb_set_par     = s3c2410fb_set_par,
 606         .fb_blank       = s3c2410fb_blank,
 607         .fb_setcolreg   = s3c2410fb_setcolreg,
 608         .fb_fillrect    = cfb_fillrect,
 609         .fb_copyarea    = cfb_copyarea,
 610         .fb_imageblit   = cfb_imageblit,
 611 };
 612
 613 /*
 614  * s3c2410fb_map_video_memory():
 615  *      Allocates the DRAM memory for the frame buffer.  This buffer is
 616  *      remapped into a non-cached, non-buffered, memory region to
 617  *      allow palette and pixel writes to occur without flushing the
 618  *      cache.  Once this area is remapped, all virtual memory
 619  *      access to the video memory should occur at the new region.
 620  */
 621 static int __init s3c2410fb_map_video_memory(struct fb_info *info)
 622 {
 623         struct s3c2410fb_info *fbi = info->par;
 624
 625         dprintk("map_video_memory(fbi=%p)\n", fbi);
 626
 627         fbi->map_size = PAGE_ALIGN(info->fix.smem_len + PAGE_SIZE);
 628         fbi->map_cpu  = dma_alloc_writecombine(fbi->dev, fbi->map_size,
 629                                                &fbi->map_dma, GFP_KERNEL);
 630
 631         fbi->map_size = info->fix.smem_len;
 632
 633         if (fbi->map_cpu) {
 634                 /* prevent initial garbage on screen */
 635                 dprintk("map_video_memory: clear %p:%08x\n",
 636                         fbi->map_cpu, fbi->map_size);
 637                 memset(fbi->map_cpu, 0xf0, fbi->map_size);
 638
 639                 fbi->screen_dma         = fbi->map_dma;
 640                 info->screen_base       = fbi->map_cpu;
 641                 info->fix.smem_start    = fbi->screen_dma;
 642
 643                 dprintk("map_video_memory: dma=%08x cpu=%p size=%08x\n",
 644                         fbi->map_dma, fbi->map_cpu, info->fix.smem_len);
 645         }
 646
 647         return fbi->map_cpu ? 0 : -ENOMEM;
 648 }
 649
 650 static inline void s3c2410fb_unmap_video_memory(struct s3c2410fb_info *fbi)
 651 {
 652         dma_free_writecombine(fbi->dev, fbi->map_size, fbi->map_cpu,
 653                               fbi->map_dma);
 654 }
 655
 656 static inline void modify_gpio(void __iomem *reg,
 657                                unsigned long set, unsigned long mask)
 658 {
 659         unsigned long tmp;
 660
 661         tmp = readl(reg) & ~mask;
 662         writel(tmp | set, reg);
 663 }
 664
 665 /*
 666  * s3c2410fb_init_registers - Initialise all LCD-related registers
 667  */
 668 static int s3c2410fb_init_registers(struct fb_info *info)
 669 {
 670         struct s3c2410fb_info *fbi = info->par;
 671         unsigned long flags;
 672         void __iomem *regs = fbi->io;
 673
 674         /* Initialise LCD with values from haret */
 675
 676         local_irq_save(flags);
 677
 678         /* modify the gpio(s) with interrupts set (bjd) */
 679
 680         modify_gpio(S3C2410_GPCUP,  mach_info->gpcup,  mach_info->gpcup_mask);
 681         modify_gpio(S3C2410_GPCCON, mach_info->gpccon, mach_info->gpccon_mask);
 682         modify_gpio(S3C2410_GPDUP,  mach_info->gpdup,  mach_info->gpdup_mask);
 683         modify_gpio(S3C2410_GPDCON, mach_info->gpdcon, mach_info->gpdcon_mask);
 684
 685         local_irq_restore(flags);
 686
 687         writel(fbi->regs.lcdcon1, regs + S3C2410_LCDCON1);
 688         writel(fbi->regs.lcdcon2, regs + S3C2410_LCDCON2);
 689         writel(fbi->regs.lcdcon3, regs + S3C2410_LCDCON3);
 690         writel(fbi->regs.lcdcon4, regs + S3C2410_LCDCON4);
 691         writel(fbi->regs.lcdcon5, regs + S3C2410_LCDCON5);
 692
 693         s3c2410fb_set_lcdaddr(info);
 694
 695         dprintk("LPCSEL    = 0x%08lx\n", mach_info->lpcsel);
 696         writel(mach_info->lpcsel, regs + S3C2410_LPCSEL);
 697
 698         dprintk("replacing TPAL %08x\n", readl(regs + S3C2410_TPAL));
 699
 700         /* ensure temporary palette disabled */
 701         writel(0x00, regs + S3C2410_TPAL);
 702
 703         /* Enable video by setting the ENVID bit to 1 */
 704         fbi->regs.lcdcon1 |= S3C2410_LCDCON1_ENVID;
 705         writel(fbi->regs.lcdcon1, regs + S3C2410_LCDCON1);
 706         return 0;
 707 }
 708
 709 static void s3c2410fb_write_palette(struct s3c2410fb_info *fbi)
 710 {
 711         unsigned int i;
 712         void __iomem *regs = fbi->io;
 713
 714         fbi->palette_ready = 0;
 715
 716         for (i = 0; i < 256; i++) {
 717                 unsigned long ent = fbi->palette_buffer[i];
 718                 if (ent == PALETTE_BUFF_CLEAR)
 719                         continue;
 720
 721                 writel(ent, regs + S3C2410_TFTPAL(i));
 722
 723                 /* it seems the only way to know exactly
 724                  * if the palette wrote ok, is to check
 725                  * to see if the value verifies ok
 726                  */
 727
 728                 if (readw(regs + S3C2410_TFTPAL(i)) == ent)
 729                         fbi->palette_buffer[i] = PALETTE_BUFF_CLEAR;
 730                 else
 731                         fbi->palette_ready = 1;   /* retry */
 732         }
 733 }
 734
 735 static irqreturn_t s3c2410fb_irq(int irq, void *dev_id)
 736 {
 737         struct s3c2410fb_info *fbi = dev_id;
 738         void __iomem *regs = fbi->io;
 739         unsigned long lcdirq = readl(regs + S3C2410_LCDINTPND);
 740
 741         if (lcdirq & S3C2410_LCDINT_FRSYNC) {
 742                 if (fbi->palette_ready)
 743                         s3c2410fb_write_palette(fbi);
 744
 745                 writel(S3C2410_LCDINT_FRSYNC, regs + S3C2410_LCDINTPND);
 746                 writel(S3C2410_LCDINT_FRSYNC, regs + S3C2410_LCDSRCPND);
 747         }
 748
 749         return IRQ_HANDLED;
 750 }
 751
 752 static char driver_name[] = "s3c2410fb";
 753
 754 static int __init s3c2410fb_probe(struct platform_device *pdev)
 755 {
 756         struct s3c2410fb_info *info;
 757         struct s3c2410fb_display *display;
 758         struct fb_info *fbinfo;
 759         struct s3c2410fb_hw *mregs;
 760         struct resource *res;
 761         int ret;
 762         int irq;
 763         int i;
 764         int size;
 765         u32 lcdcon1;
 766
 767         mach_info = pdev->dev.platform_data;
 768         if (mach_info == NULL) {
 769                 dev_err(&pdev->dev,
 770                         "no platform data for lcd, cannot attach\n");
 771                 return -EINVAL;
 772         }
 773
 774         display = mach_info->displays + mach_info->default_display;
 775         mregs = &display->regs;
 776
 777         irq = platform_get_irq(pdev, 0);
 778         if (irq < 0) {
 779                 dev_err(&pdev->dev, "no irq for device\n");
 780                 return -ENOENT;
 781         }
 782
 783         fbinfo = framebuffer_alloc(sizeof(struct s3c2410fb_info), &pdev->dev);
 784         if (!fbinfo)
 785                 return -ENOMEM;
 786
 787         info = fbinfo->par;
 788         info->dev = &pdev->dev;
 789
 790         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 791         if (res == NULL) {
 792                 dev_err(&pdev->dev, "failed to get memory registers\n");
 793                 ret = -ENXIO;
 794                 goto dealloc_fb;
 795         }
 796
 797         size = (res->end - res->start) + 1;
 798         info->mem = request_mem_region(res->start, size, pdev->name);
 799         if (info->mem == NULL) {
 800                 dev_err(&pdev->dev, "failed to get memory region\n");
 801                 ret = -ENOENT;
 802                 goto dealloc_fb;
 803         }
 804
 805         info->io = ioremap(res->start, size);
 806         if (info->io == NULL) {
 807                 dev_err(&pdev->dev, "ioremap() of registers failed\n");
 808                 ret = -ENXIO;
 809                 goto release_mem;
 810         }
 811
 812         platform_set_drvdata(pdev, fbinfo);
 813
 814         dprintk("devinit\n");
 815
 816         strcpy(fbinfo->fix.id, driver_name);
 817
 818         memcpy(&info->regs, &display->regs, sizeof(info->regs));
 819
 820         /* Stop the video and unset ENVID if set */
 821         info->regs.lcdcon1 &= ~S3C2410_LCDCON1_ENVID;
 822         lcdcon1 = readl(info->io + S3C2410_LCDCON1);
 823         writel(lcdcon1 & ~S3C2410_LCDCON1_ENVID, info->io + S3C2410_LCDCON1);
 824
 825         info->mach_info             = pdev->dev.platform_data;
 826         info->current_display       = mach_info->default_display;
 827
 828         fbinfo->fix.type            = FB_TYPE_PACKED_PIXELS;
 829         fbinfo->fix.type_aux        = 0;
 830         fbinfo->fix.xpanstep        = 0;
 831         fbinfo->fix.ypanstep        = 0;
 832         fbinfo->fix.ywrapstep       = 0;
 833         fbinfo->fix.accel           = FB_ACCEL_NONE;
 834
 835         fbinfo->var.nonstd          = 0;
 836         fbinfo->var.activate        = FB_ACTIVATE_NOW;
 837         fbinfo->var.height          = display->height;
 838         fbinfo->var.width           = display->width;
 839         fbinfo->var.accel_flags     = 0;
 840         fbinfo->var.vmode           = FB_VMODE_NONINTERLACED;
 841
 842         fbinfo->fbops               = &s3c2410fb_ops;
 843         fbinfo->flags               = FBINFO_FLAG_DEFAULT;
 844         fbinfo->pseudo_palette      = &info->pseudo_pal;
 845
 846         fbinfo->var.xres            = display->xres;
 847         fbinfo->var.xres_virtual    = display->xres;
 848         fbinfo->var.yres            = display->yres;
 849         fbinfo->var.yres_virtual    = display->yres;
 850         fbinfo->var.bits_per_pixel  = display->bpp;
 851
 852         fbinfo->var.upper_margin    =
 853                                 S3C2410_LCDCON2_GET_VBPD(mregs->lcdcon2) + 1;
 854         fbinfo->var.lower_margin    =
 855                                 S3C2410_LCDCON2_GET_VFPD(mregs->lcdcon2) + 1;
 856         fbinfo->var.vsync_len       =
 857                                 S3C2410_LCDCON2_GET_VSPW(mregs->lcdcon2) + 1;
 858
 859         fbinfo->var.left_margin     =
 860                                 S3C2410_LCDCON3_GET_HFPD(mregs->lcdcon3) + 1;
 861         fbinfo->var.right_margin    =
 862                                 S3C2410_LCDCON3_GET_HBPD(mregs->lcdcon3) + 1;
 863         fbinfo->var.hsync_len       =
 864                                 S3C2410_LCDCON4_GET_HSPW(mregs->lcdcon4) + 1;
 865
 866         fbinfo->var.red.offset      = 11;
 867         fbinfo->var.green.offset    = 5;
 868         fbinfo->var.blue.offset     = 0;
 869         fbinfo->var.transp.offset   = 0;
 870         fbinfo->var.red.length      = 5;
 871         fbinfo->var.green.length    = 6;
 872         fbinfo->var.blue.length     = 5;
 873         fbinfo->var.transp.length   = 0;
 874
 875         /* find maximum required memory size for display */
 876         for (i = 0; i < mach_info->num_displays; i++) {
 877                 unsigned long smem_len = mach_info->displays[i].xres;
 878
 879                 smem_len *= mach_info->displays[i].yres;
 880                 smem_len *= mach_info->displays[i].bpp;
 881                 smem_len >>= 3;
 882                 if (fbinfo->fix.smem_len < smem_len)
 883                         fbinfo->fix.smem_len = smem_len;
 884         }
 885
 886         for (i = 0; i < 256; i++)
 887                 info->palette_buffer[i] = PALETTE_BUFF_CLEAR;
 888
 889         ret = request_irq(irq, s3c2410fb_irq, IRQF_DISABLED, pdev->name, info);
 890         if (ret) {
 891                 dev_err(&pdev->dev, "cannot get irq %d - err %d\n", irq, ret);
 892                 ret = -EBUSY;
 893                 goto release_regs;
 894         }
 895
 896         info->clk = clk_get(NULL, "lcd");
 897         if (!info->clk || IS_ERR(info->clk)) {
 898                 printk(KERN_ERR "failed to get lcd clock source\n");
 899                 ret = -ENOENT;
 900                 goto release_irq;
 901         }
 902
 903         clk_enable(info->clk);
 904         dprintk("got and enabled clock\n");
 905
 906         msleep(1);
 907
 908         /* Initialize video memory */
 909         ret = s3c2410fb_map_video_memory(fbinfo);
 910         if (ret) {
 911                 printk(KERN_ERR "Failed to allocate video RAM: %d\n", ret);
 912                 ret = -ENOMEM;
 913                 goto release_clock;
 914         }
 915
 916         dprintk("got video memory\n");
 917
 918         s3c2410fb_init_registers(fbinfo);
 919
 920         s3c2410fb_check_var(&fbinfo->var, fbinfo);
 921
 922         ret = register_framebuffer(fbinfo);
 923         if (ret < 0) {
 924                 printk(KERN_ERR "Failed to register framebuffer device: %d\n",
 925                         ret);
 926                 goto free_video_memory;
 927         }
 928
 929         /* create device files */
 930         device_create_file(&pdev->dev, &dev_attr_debug);
 931
 932         printk(KERN_INFO "fb%d: %s frame buffer device\n",
 933                 fbinfo->node, fbinfo->fix.id);
 934
 935         return 0;
 936
 937 free_video_memory:
 938         s3c2410fb_unmap_video_memory(info);
 939 release_clock:
 940         clk_disable(info->clk);
 941         clk_put(info->clk);
 942 release_irq:
 943         free_irq(irq, info);
 944 release_regs:
 945         iounmap(info->io);
 946 release_mem:
 947         release_resource(info->mem);
 948         kfree(info->mem);
 949 dealloc_fb:
 950         framebuffer_release(fbinfo);
 951         return ret;
 952 }
 953
 954 /* s3c2410fb_stop_lcd
 955  *
 956  * shutdown the lcd controller
 957  */
 958 static void s3c2410fb_stop_lcd(struct s3c2410fb_info *fbi)
 959 {
 960         unsigned long flags;
 961
 962         local_irq_save(flags);
 963
 964         fbi->regs.lcdcon1 &= ~S3C2410_LCDCON1_ENVID;
 965         writel(fbi->regs.lcdcon1, fbi->io + S3C2410_LCDCON1);
 966
 967         local_irq_restore(flags);
 968 }
 969
 970 /*
 971  *  Cleanup
 972  */
 973 static int s3c2410fb_remove(struct platform_device *pdev)
 974 {
 975         struct fb_info *fbinfo = platform_get_drvdata(pdev);
 976         struct s3c2410fb_info *info = fbinfo->par;
 977         int irq;
 978
 979         s3c2410fb_stop_lcd(info);
 980         msleep(1);
 981
 982         s3c2410fb_unmap_video_memory(info);
 983
 984         if (info->clk) {
 985                 clk_disable(info->clk);
 986                 clk_put(info->clk);
 987                 info->clk = NULL;
 988         }
 989
 990         irq = platform_get_irq(pdev, 0);
 991         free_irq(irq, info);
 992
 993         release_resource(info->mem);
 994         kfree(info->mem);
 995         iounmap(info->io);
 996         unregister_framebuffer(fbinfo);
 997
 998         return 0;
 999 }
1000
1001 #ifdef CONFIG_PM
1002
1003 /* suspend and resume support for the lcd controller */
1004 static int s3c2410fb_suspend(struct platform_device *dev, pm_message_t state)
1005 {
1006         struct fb_info     *fbinfo = platform_get_drvdata(dev);
1007         struct s3c2410fb_info *info = fbinfo->par;
1008
1009         s3c2410fb_stop_lcd(info);
1010
1011         /* sleep before disabling the clock, we need to ensure
1012          * the LCD DMA engine is not going to get back on the bus
1013          * before the clock goes off again (bjd) */
1014
1015         msleep(1);
1016         clk_disable(info->clk);
1017
1018         return 0;
1019 }
1020
1021 static int s3c2410fb_resume(struct platform_device *dev)
1022 {
1023         struct fb_info     *fbinfo = platform_get_drvdata(dev);
1024         struct s3c2410fb_info *info = fbinfo->par;
1025
1026         clk_enable(info->clk);
1027         msleep(1);
1028
1029         s3c2410fb_init_registers(info);
1030
1031         return 0;
1032 }
1033
1034 #else
1035 #define s3c2410fb_suspend NULL
1036 #define s3c2410fb_resume  NULL
1037 #endif
1038
1039 static struct platform_driver s3c2410fb_driver = {
1040         .probe          = s3c2410fb_probe,
1041         .remove         = s3c2410fb_remove,
1042         .suspend        = s3c2410fb_suspend,
1043         .resume         = s3c2410fb_resume,
1044         .driver         = {
1045                 .name   = "s3c2410-lcd",
1046                 .owner  = THIS_MODULE,
1047         },
1048 };
1049
1050 int __devinit s3c2410fb_init(void)
1051 {
1052         return platform_driver_register(&s3c2410fb_driver);
1053 }
1054
1055 static void __exit s3c2410fb_cleanup(void)
1056 {
1057         platform_driver_unregister(&s3c2410fb_driver);
1058 }
1059
1060 module_init(s3c2410fb_init);
1061 module_exit(s3c2410fb_cleanup);
1062
1063 MODULE_AUTHOR("Arnaud Patard <arnaud.patard@rtp-net.org>, "
1064               "Ben Dooks <ben-linux@fluff.org>");
1065 MODULE_DESCRIPTION("Framebuffer driver for the s3c2410");
1066 MODULE_LICENSE("GPL");