2 * linux/drivers/video/s3c2410fb.c
3 * Copyright (c) Arnaud Patard, Ben Dooks
5 * This file is subject to the terms and conditions of the GNU General Public
6 * License. See the file COPYING in the main directory of this archive for
9 * S3C2410 LCD Controller Frame Buffer Driver
10 * based on skeletonfb.c, sa1100fb.c and others
13 * 2005-04-07: Arnaud Patard <arnaud.patard@rtp-net.org>
14 * - u32 state -> pm_message_t state
15 * - S3C2410_{VA,SZ}_LCD -> S3C24XX
17 * 2005-03-15: Arnaud Patard <arnaud.patard@rtp-net.org>
19 * - use readl/writel instead of __raw_writel/__raw_readl
21 * 2004-12-04: Arnaud Patard <arnaud.patard@rtp-net.org>
22 * - Added the possibility to set on or off the
24 * - Replaced 0 and 1 by on or off when reading the
27 * 2005-03-23: Ben Dooks <ben-linux@fluff.org>
28 * - added non 16bpp modes
29 * - updated platform information for range of x/y/bpp
30 * - add code to ensure palette is written correctly
31 * - add pixel clock divisor control
33 * 2004-11-11: Arnaud Patard <arnaud.patard@rtp-net.org>
34 * - Removed the use of currcon as it no more exist
35 * - Added LCD power sysfs interface
37 * 2004-11-03: Ben Dooks <ben-linux@fluff.org>
39 * - add suspend/resume support
40 * - s3c2410fb_setcolreg() not valid in >8bpp modes
41 * - removed last CONFIG_FB_S3C2410_FIXED
42 * - ensure lcd controller stopped before cleanup
43 * - added sysfs interface for backlight power
44 * - added mask for gpio configuration
45 * - ensured IRQs disabled during GPIO configuration
46 * - disable TPAL before enabling video
48 * 2004-09-20: Arnaud Patard <arnaud.patard@rtp-net.org>
49 * - Suppress command line options
51 * 2004-09-15: Arnaud Patard <arnaud.patard@rtp-net.org>
54 * 2004-09-07: Arnaud Patard <arnaud.patard@rtp-net.org>
55 * - Renamed from h1940fb.c to s3c2410fb.c
56 * - Add support for different devices
59 * 2004-09-05: Herbert Pötzl <herbert@13thfloor.at>
60 * - added clock (de-)allocation code
61 * - added fixem fbmem option
63 * 2004-07-27: Arnaud Patard <arnaud.patard@rtp-net.org>
65 * - added a forgotten return in h1940fb_init
67 * 2004-07-19: Herbert Pötzl <herbert@13thfloor.at>
68 * - code cleanup and extended debugging
70 * 2004-07-15: Arnaud Patard <arnaud.patard@rtp-net.org>
74 #include <linux/module.h>
75 #include <linux/kernel.h>
76 #include <linux/errno.h>
77 #include <linux/string.h>
79 #include <linux/slab.h>
80 #include <linux/delay.h>
82 #include <linux/init.h>
83 #include <linux/dma-mapping.h>
84 #include <linux/interrupt.h>
85 #include <linux/workqueue.h>
86 #include <linux/wait.h>
87 #include <linux/platform_device.h>
88 #include <linux/clk.h>
91 #include <asm/uaccess.h>
92 #include <asm/div64.h>
94 #include <asm/mach/map.h>
95 #include <asm/arch/regs-lcd.h>
96 #include <asm/arch/regs-gpio.h>
97 #include <asm/arch/fb.h>
100 #include <linux/pm.h>
103 #include "s3c2410fb.h"
105 static struct s3c2410fb_mach_info *mach_info;
107 /* Debugging stuff */
108 #ifdef CONFIG_FB_S3C2410_DEBUG
109 static int debug = 1;
111 static int debug = 0;
114 #define dprintk(msg...) if (debug) { printk(KERN_DEBUG "s3c2410fb: " msg); }
116 /* useful functions */
118 /* s3c2410fb_set_lcdaddr
120 * initialise lcd controller address pointers
122 static void s3c2410fb_set_lcdaddr(struct fb_info *info)
124 unsigned long saddr1, saddr2, saddr3;
125 int line_length = info->var.xres * info->var.bits_per_pixel;
127 saddr1 = info->fix.smem_start >> 1;
128 saddr2 = info->fix.smem_start;
129 saddr2 += (line_length * info->var.yres) / 8;
132 saddr3 = S3C2410_OFFSIZE(0) |
133 S3C2410_PAGEWIDTH((line_length / 16) & 0x3ff);
135 dprintk("LCDSADDR1 = 0x%08lx\n", saddr1);
136 dprintk("LCDSADDR2 = 0x%08lx\n", saddr2);
137 dprintk("LCDSADDR3 = 0x%08lx\n", saddr3);
139 writel(saddr1, S3C2410_LCDSADDR1);
140 writel(saddr2, S3C2410_LCDSADDR2);
141 writel(saddr3, S3C2410_LCDSADDR3);
144 /* s3c2410fb_calc_pixclk()
146 * calculate divisor for clk->pixclk
148 static unsigned int s3c2410fb_calc_pixclk(struct s3c2410fb_info *fbi,
149 unsigned long pixclk)
151 unsigned long clk = clk_get_rate(fbi->clk);
152 unsigned long long div;
154 /* pixclk is in picoseoncds, our clock is in Hz
156 * Hz -> picoseconds is / 10^-12
159 div = (unsigned long long)clk * pixclk;
160 do_div(div, 1000000UL);
161 do_div(div, 1000000UL);
163 dprintk("pixclk %ld, divisor is %ld\n", pixclk, (long)div);
168 * s3c2410fb_check_var():
169 * Get the video params out of 'var'. If a value doesn't fit, round it up,
170 * if it's too big, return -EINVAL.
173 static int s3c2410fb_check_var(struct fb_var_screeninfo *var,
174 struct fb_info *info)
176 struct s3c2410fb_info *fbi = info->par;
177 struct s3c2410fb_mach_info *mach_info = fbi->mach_info;
178 struct s3c2410fb_display *display = NULL;
181 dprintk("check_var(var=%p, info=%p)\n", var, info);
183 /* validate x/y resolution */
185 for (i = 0; i < mach_info->num_displays; i++)
186 if (var->yres == mach_info->displays[i].yres &&
187 var->xres == mach_info->displays[i].xres &&
188 var->bits_per_pixel == mach_info->displays[i].bpp) {
189 display = mach_info->displays + i;
190 fbi->current_display = i;
195 dprintk("wrong resolution or depth %dx%d at %d bpp\n",
196 var->xres, var->yres, var->bits_per_pixel);
200 /* it is always the size as the display */
201 var->xres_virtual = display->xres;
202 var->yres_virtual = display->yres;
204 /* copy lcd settings */
205 var->left_margin = display->left_margin;
206 var->right_margin = display->right_margin;
208 var->transp.offset = 0;
209 var->transp.length = 0;
210 /* set r/g/b positions */
211 switch (var->bits_per_pixel) {
216 var->red.length = var->bits_per_pixel;
217 var->green = var->red;
218 var->blue = var->red;
221 if (display->type != S3C2410_LCDCON1_TFT) {
225 var->green.length = 3;
226 var->green.offset = 2;
227 var->blue.length = 2;
228 var->blue.offset = 0;
232 var->green = var->red;
233 var->blue = var->red;
240 var->green.length = 4;
241 var->green.offset = 4;
242 var->blue.length = 4;
243 var->blue.offset = 0;
248 if (display->lcdcon5 & S3C2410_LCDCON5_FRM565) {
249 /* 16 bpp, 565 format */
250 var->red.offset = 11;
251 var->green.offset = 5;
252 var->blue.offset = 0;
254 var->green.length = 6;
255 var->blue.length = 5;
257 /* 16 bpp, 5551 format */
258 var->red.offset = 11;
259 var->green.offset = 6;
260 var->blue.offset = 1;
262 var->green.length = 5;
263 var->blue.length = 5;
269 var->red.offset = 16;
270 var->green.length = 8;
271 var->green.offset = 8;
272 var->blue.length = 8;
273 var->blue.offset = 0;
281 /* s3c2410fb_calculate_stn_lcd_regs
283 * calculate register values from var settings
285 static void s3c2410fb_calculate_stn_lcd_regs(const struct fb_info *info,
286 struct s3c2410fb_hw *regs)
288 const struct s3c2410fb_info *fbi = info->par;
289 const struct fb_var_screeninfo *var = &info->var;
290 int type = regs->lcdcon1 & ~S3C2410_LCDCON1_TFT;
291 int hs = var->xres >> 2;
292 unsigned wdly = (var->left_margin >> 4) - 1;
294 dprintk("%s: var->xres = %d\n", __FUNCTION__, var->xres);
295 dprintk("%s: var->yres = %d\n", __FUNCTION__, var->yres);
296 dprintk("%s: var->bpp = %d\n", __FUNCTION__, var->bits_per_pixel);
298 if (type != S3C2410_LCDCON1_STN4)
301 regs->lcdcon1 &= ~S3C2410_LCDCON1_MODEMASK;
303 switch (var->bits_per_pixel) {
305 regs->lcdcon1 |= S3C2410_LCDCON1_STN1BPP;
308 regs->lcdcon1 |= S3C2410_LCDCON1_STN2GREY;
311 regs->lcdcon1 |= S3C2410_LCDCON1_STN4GREY;
314 regs->lcdcon1 |= S3C2410_LCDCON1_STN8BPP;
318 regs->lcdcon1 |= S3C2410_LCDCON1_STN12BPP;
323 /* invalid pixel depth */
324 dev_err(fbi->dev, "invalid bpp %d\n",
325 var->bits_per_pixel);
327 /* update X/Y info */
328 dprintk("setting horz: lft=%d, rt=%d, sync=%d\n",
329 var->left_margin, var->right_margin, var->hsync_len);
331 regs->lcdcon2 = S3C2410_LCDCON2_LINEVAL(var->yres - 1);
336 regs->lcdcon3 = S3C2410_LCDCON3_WDLY(wdly) |
337 S3C2410_LCDCON3_LINEBLANK(var->right_margin / 8) |
338 S3C2410_LCDCON3_HOZVAL(hs - 1);
341 /* s3c2410fb_calculate_tft_lcd_regs
343 * calculate register values from var settings
345 static void s3c2410fb_calculate_tft_lcd_regs(const struct fb_info *info,
346 struct s3c2410fb_hw *regs)
348 const struct s3c2410fb_info *fbi = info->par;
349 const struct fb_var_screeninfo *var = &info->var;
351 dprintk("%s: var->xres = %d\n", __FUNCTION__, var->xres);
352 dprintk("%s: var->yres = %d\n", __FUNCTION__, var->yres);
353 dprintk("%s: var->bpp = %d\n", __FUNCTION__, var->bits_per_pixel);
355 regs->lcdcon1 &= ~S3C2410_LCDCON1_MODEMASK;
357 switch (var->bits_per_pixel) {
359 regs->lcdcon1 |= S3C2410_LCDCON1_TFT1BPP;
362 regs->lcdcon1 |= S3C2410_LCDCON1_TFT2BPP;
365 regs->lcdcon1 |= S3C2410_LCDCON1_TFT4BPP;
368 regs->lcdcon1 |= S3C2410_LCDCON1_TFT8BPP;
371 regs->lcdcon1 |= S3C2410_LCDCON1_TFT16BPP;
375 /* invalid pixel depth */
376 dev_err(fbi->dev, "invalid bpp %d\n",
377 var->bits_per_pixel);
379 /* update X/Y info */
380 dprintk("setting vert: up=%d, low=%d, sync=%d\n",
381 var->upper_margin, var->lower_margin, var->vsync_len);
383 dprintk("setting horz: lft=%d, rt=%d, sync=%d\n",
384 var->left_margin, var->right_margin, var->hsync_len);
386 regs->lcdcon2 &= S3C2410_LCDCON2_VSPW(0x3f);
387 regs->lcdcon2 |= S3C2410_LCDCON2_LINEVAL(var->yres - 1);
388 regs->lcdcon2 |= S3C2410_LCDCON2_VBPD(var->upper_margin - 1);
389 regs->lcdcon2 |= S3C2410_LCDCON2_VFPD(var->lower_margin - 1);
391 regs->lcdcon3 = S3C2410_LCDCON3_HBPD(var->right_margin - 1) |
392 S3C2410_LCDCON3_HFPD(var->left_margin - 1) |
393 S3C2410_LCDCON3_HOZVAL(var->xres - 1);
396 /* s3c2410fb_activate_var
398 * activate (set) the controller from the given framebuffer
401 static void s3c2410fb_activate_var(struct fb_info *info)
403 struct s3c2410fb_info *fbi = info->par;
404 struct fb_var_screeninfo *var = &info->var;
405 struct s3c2410fb_mach_info *mach_info = fbi->mach_info;
406 struct s3c2410fb_display *display = mach_info->displays +
407 fbi->current_display;
409 /* set display type */
410 fbi->regs.lcdcon1 &= ~S3C2410_LCDCON1_TFT;
411 fbi->regs.lcdcon1 |= display->type;
413 /* check to see if we need to update sync/borders */
415 if (!mach_info->fixed_syncs) {
417 S3C2410_LCDCON2_VSPW(var->vsync_len - 1);
419 fbi->regs.lcdcon4 &= ~S3C2410_LCDCON4_HSPW(0xff);
420 fbi->regs.lcdcon4 |= S3C2410_LCDCON4_HSPW(var->hsync_len - 1);
423 if (var->pixclock > 0) {
424 int clkdiv = s3c2410fb_calc_pixclk(fbi, var->pixclock);
426 if (display->type == S3C2410_LCDCON1_TFT) {
427 clkdiv = (clkdiv / 2) - 1;
431 clkdiv = (clkdiv / 2);
436 fbi->regs.lcdcon1 &= ~S3C2410_LCDCON1_CLKVAL(0x3ff);
437 fbi->regs.lcdcon1 |= S3C2410_LCDCON1_CLKVAL(clkdiv);
440 if (display->type == S3C2410_LCDCON1_TFT)
441 s3c2410fb_calculate_tft_lcd_regs(info, &fbi->regs);
443 s3c2410fb_calculate_stn_lcd_regs(info, &fbi->regs);
445 /* write new registers */
447 dprintk("new register set:\n");
448 dprintk("lcdcon[1] = 0x%08lx\n", fbi->regs.lcdcon1);
449 dprintk("lcdcon[2] = 0x%08lx\n", fbi->regs.lcdcon2);
450 dprintk("lcdcon[3] = 0x%08lx\n", fbi->regs.lcdcon3);
451 dprintk("lcdcon[4] = 0x%08lx\n", fbi->regs.lcdcon4);
452 dprintk("lcdcon[5] = 0x%08lx\n", fbi->regs.lcdcon5);
454 writel(fbi->regs.lcdcon1 & ~S3C2410_LCDCON1_ENVID, S3C2410_LCDCON1);
455 writel(fbi->regs.lcdcon2, S3C2410_LCDCON2);
456 writel(fbi->regs.lcdcon3, S3C2410_LCDCON3);
457 writel(fbi->regs.lcdcon4, S3C2410_LCDCON4);
458 writel(fbi->regs.lcdcon5, S3C2410_LCDCON5);
460 /* set lcd address pointers */
461 s3c2410fb_set_lcdaddr(info);
463 writel(fbi->regs.lcdcon1, S3C2410_LCDCON1);
467 * s3c2410fb_set_par - Alters the hardware state.
468 * @info: frame buffer structure that represents a single frame buffer
471 static int s3c2410fb_set_par(struct fb_info *info)
473 struct fb_var_screeninfo *var = &info->var;
475 switch (var->bits_per_pixel) {
477 info->fix.visual = FB_VISUAL_TRUECOLOR;
480 info->fix.visual = FB_VISUAL_MONO01;
483 info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
487 info->fix.line_length = (var->width * var->bits_per_pixel) / 8;
489 /* activate this new configuration */
491 s3c2410fb_activate_var(info);
495 static void schedule_palette_update(struct s3c2410fb_info *fbi,
496 unsigned int regno, unsigned int val)
500 void __iomem *regs = fbi->io;
502 local_irq_save(flags);
504 fbi->palette_buffer[regno] = val;
506 if (!fbi->palette_ready) {
507 fbi->palette_ready = 1;
510 irqen = readl(regs + S3C2410_LCDINTMSK);
511 irqen &= ~S3C2410_LCDINT_FRSYNC;
512 writel(irqen, regs + S3C2410_LCDINTMSK);
515 local_irq_restore(flags);
519 static inline unsigned int chan_to_field(unsigned int chan,
520 struct fb_bitfield *bf)
523 chan >>= 16 - bf->length;
524 return chan << bf->offset;
527 static int s3c2410fb_setcolreg(unsigned regno,
528 unsigned red, unsigned green, unsigned blue,
529 unsigned transp, struct fb_info *info)
531 struct s3c2410fb_info *fbi = info->par;
534 /* dprintk("setcol: regno=%d, rgb=%d,%d,%d\n",
535 regno, red, green, blue); */
537 switch (info->fix.visual) {
538 case FB_VISUAL_TRUECOLOR:
539 /* true-colour, use pseudo-palette */
542 u32 *pal = info->pseudo_palette;
544 val = chan_to_field(red, &info->var.red);
545 val |= chan_to_field(green, &info->var.green);
546 val |= chan_to_field(blue, &info->var.blue);
552 case FB_VISUAL_PSEUDOCOLOR:
554 /* currently assume RGB 5-6-5 mode */
556 val = ((red >> 0) & 0xf800);
557 val |= ((green >> 5) & 0x07e0);
558 val |= ((blue >> 11) & 0x001f);
560 writel(val, S3C2410_TFTPAL(regno));
561 schedule_palette_update(fbi, regno, val);
567 return 1; /* unknown type */
575 * @blank_mode: the blank mode we want.
576 * @info: frame buffer structure that represents a single frame buffer
578 * Blank the screen if blank_mode != 0, else unblank. Return 0 if
579 * blanking succeeded, != 0 if un-/blanking failed due to e.g. a
580 * video mode which doesn't support it. Implements VESA suspend
581 * and powerdown modes on hardware that supports disabling hsync/vsync:
582 * blank_mode == 2: suspend vsync
583 * blank_mode == 3: suspend hsync
584 * blank_mode == 4: powerdown
586 * Returns negative errno on error, or zero on success.
589 static int s3c2410fb_blank(int blank_mode, struct fb_info *info)
591 dprintk("blank(mode=%d, info=%p)\n", blank_mode, info);
593 if (mach_info == NULL)
596 if (blank_mode == FB_BLANK_UNBLANK)
597 writel(0x0, S3C2410_TPAL);
599 dprintk("setting TPAL to output 0x000000\n");
600 writel(S3C2410_TPAL_EN, S3C2410_TPAL);
606 static int s3c2410fb_debug_show(struct device *dev,
607 struct device_attribute *attr, char *buf)
609 return snprintf(buf, PAGE_SIZE, "%s\n", debug ? "on" : "off");
611 static int s3c2410fb_debug_store(struct device *dev,
612 struct device_attribute *attr,
613 const char *buf, size_t len)
615 if (mach_info == NULL)
621 if (strnicmp(buf, "on", 2) == 0 ||
622 strnicmp(buf, "1", 1) == 0) {
624 printk(KERN_DEBUG "s3c2410fb: Debug On");
625 } else if (strnicmp(buf, "off", 3) == 0 ||
626 strnicmp(buf, "0", 1) == 0) {
628 printk(KERN_DEBUG "s3c2410fb: Debug Off");
636 static DEVICE_ATTR(debug, 0666, s3c2410fb_debug_show, s3c2410fb_debug_store);
638 static struct fb_ops s3c2410fb_ops = {
639 .owner = THIS_MODULE,
640 .fb_check_var = s3c2410fb_check_var,
641 .fb_set_par = s3c2410fb_set_par,
642 .fb_blank = s3c2410fb_blank,
643 .fb_setcolreg = s3c2410fb_setcolreg,
644 .fb_fillrect = cfb_fillrect,
645 .fb_copyarea = cfb_copyarea,
646 .fb_imageblit = cfb_imageblit,
650 * s3c2410fb_map_video_memory():
651 * Allocates the DRAM memory for the frame buffer. This buffer is
652 * remapped into a non-cached, non-buffered, memory region to
653 * allow palette and pixel writes to occur without flushing the
654 * cache. Once this area is remapped, all virtual memory
655 * access to the video memory should occur at the new region.
657 static int __init s3c2410fb_map_video_memory(struct fb_info *info)
659 struct s3c2410fb_info *fbi = info->par;
661 dprintk("map_video_memory(fbi=%p)\n", fbi);
663 fbi->map_size = PAGE_ALIGN(info->fix.smem_len + PAGE_SIZE);
664 fbi->map_cpu = dma_alloc_writecombine(fbi->dev, fbi->map_size,
665 &fbi->map_dma, GFP_KERNEL);
667 fbi->map_size = info->fix.smem_len;
670 /* prevent initial garbage on screen */
671 dprintk("map_video_memory: clear %p:%08x\n",
672 fbi->map_cpu, fbi->map_size);
673 memset(fbi->map_cpu, 0xf0, fbi->map_size);
675 fbi->screen_dma = fbi->map_dma;
676 info->screen_base = fbi->map_cpu;
677 info->fix.smem_start = fbi->screen_dma;
679 dprintk("map_video_memory: dma=%08x cpu=%p size=%08x\n",
680 fbi->map_dma, fbi->map_cpu, info->fix.smem_len);
683 return fbi->map_cpu ? 0 : -ENOMEM;
686 static inline void s3c2410fb_unmap_video_memory(struct s3c2410fb_info *fbi)
688 dma_free_writecombine(fbi->dev, fbi->map_size, fbi->map_cpu,
692 static inline void modify_gpio(void __iomem *reg,
693 unsigned long set, unsigned long mask)
697 tmp = readl(reg) & ~mask;
698 writel(tmp | set, reg);
702 * s3c2410fb_init_registers - Initialise all LCD-related registers
704 static int s3c2410fb_init_registers(struct fb_info *info)
706 struct s3c2410fb_info *fbi = info->par;
708 void __iomem *regs = fbi->io;
710 /* Initialise LCD with values from haret */
712 local_irq_save(flags);
714 /* modify the gpio(s) with interrupts set (bjd) */
716 modify_gpio(S3C2410_GPCUP, mach_info->gpcup, mach_info->gpcup_mask);
717 modify_gpio(S3C2410_GPCCON, mach_info->gpccon, mach_info->gpccon_mask);
718 modify_gpio(S3C2410_GPDUP, mach_info->gpdup, mach_info->gpdup_mask);
719 modify_gpio(S3C2410_GPDCON, mach_info->gpdcon, mach_info->gpdcon_mask);
721 local_irq_restore(flags);
723 writel(fbi->regs.lcdcon1, regs + S3C2410_LCDCON1);
724 writel(fbi->regs.lcdcon2, regs + S3C2410_LCDCON2);
725 writel(fbi->regs.lcdcon3, regs + S3C2410_LCDCON3);
726 writel(fbi->regs.lcdcon4, regs + S3C2410_LCDCON4);
727 writel(fbi->regs.lcdcon5, regs + S3C2410_LCDCON5);
729 s3c2410fb_set_lcdaddr(info);
731 dprintk("LPCSEL = 0x%08lx\n", mach_info->lpcsel);
732 writel(mach_info->lpcsel, regs + S3C2410_LPCSEL);
734 dprintk("replacing TPAL %08x\n", readl(regs + S3C2410_TPAL));
736 /* ensure temporary palette disabled */
737 writel(0x00, regs + S3C2410_TPAL);
739 /* Enable video by setting the ENVID bit to 1 */
740 fbi->regs.lcdcon1 |= S3C2410_LCDCON1_ENVID;
741 writel(fbi->regs.lcdcon1, regs + S3C2410_LCDCON1);
745 static void s3c2410fb_write_palette(struct s3c2410fb_info *fbi)
748 void __iomem *regs = fbi->io;
750 fbi->palette_ready = 0;
752 for (i = 0; i < 256; i++) {
753 unsigned long ent = fbi->palette_buffer[i];
754 if (ent == PALETTE_BUFF_CLEAR)
757 writel(ent, regs + S3C2410_TFTPAL(i));
759 /* it seems the only way to know exactly
760 * if the palette wrote ok, is to check
761 * to see if the value verifies ok
764 if (readw(regs + S3C2410_TFTPAL(i)) == ent)
765 fbi->palette_buffer[i] = PALETTE_BUFF_CLEAR;
767 fbi->palette_ready = 1; /* retry */
771 static irqreturn_t s3c2410fb_irq(int irq, void *dev_id)
773 struct s3c2410fb_info *fbi = dev_id;
774 void __iomem *regs = fbi->io;
775 unsigned long lcdirq = readl(regs + S3C2410_LCDINTPND);
777 if (lcdirq & S3C2410_LCDINT_FRSYNC) {
778 if (fbi->palette_ready)
779 s3c2410fb_write_palette(fbi);
781 writel(S3C2410_LCDINT_FRSYNC, regs + S3C2410_LCDINTPND);
782 writel(S3C2410_LCDINT_FRSYNC, regs + S3C2410_LCDSRCPND);
788 static char driver_name[] = "s3c2410fb";
790 static int __init s3c2410fb_probe(struct platform_device *pdev)
792 struct s3c2410fb_info *info;
793 struct s3c2410fb_display *display;
794 struct fb_info *fbinfo;
795 struct resource *res;
802 mach_info = pdev->dev.platform_data;
803 if (mach_info == NULL) {
805 "no platform data for lcd, cannot attach\n");
809 display = mach_info->displays + mach_info->default_display;
811 irq = platform_get_irq(pdev, 0);
813 dev_err(&pdev->dev, "no irq for device\n");
817 fbinfo = framebuffer_alloc(sizeof(struct s3c2410fb_info), &pdev->dev);
822 info->dev = &pdev->dev;
824 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
826 dev_err(&pdev->dev, "failed to get memory registers\n");
831 size = (res->end - res->start) + 1;
832 info->mem = request_mem_region(res->start, size, pdev->name);
833 if (info->mem == NULL) {
834 dev_err(&pdev->dev, "failed to get memory region\n");
839 info->io = ioremap(res->start, size);
840 if (info->io == NULL) {
841 dev_err(&pdev->dev, "ioremap() of registers failed\n");
846 platform_set_drvdata(pdev, fbinfo);
848 dprintk("devinit\n");
850 strcpy(fbinfo->fix.id, driver_name);
852 info->regs.lcdcon1 = display->lcdcon1;
853 info->regs.lcdcon2 = display->lcdcon2;
854 info->regs.lcdcon4 = display->lcdcon4;
855 info->regs.lcdcon5 = display->lcdcon5;
857 /* Stop the video and unset ENVID if set */
858 info->regs.lcdcon1 &= ~S3C2410_LCDCON1_ENVID;
859 lcdcon1 = readl(info->io + S3C2410_LCDCON1);
860 writel(lcdcon1 & ~S3C2410_LCDCON1_ENVID, info->io + S3C2410_LCDCON1);
862 info->mach_info = pdev->dev.platform_data;
863 info->current_display = mach_info->default_display;
865 fbinfo->fix.type = FB_TYPE_PACKED_PIXELS;
866 fbinfo->fix.type_aux = 0;
867 fbinfo->fix.xpanstep = 0;
868 fbinfo->fix.ypanstep = 0;
869 fbinfo->fix.ywrapstep = 0;
870 fbinfo->fix.accel = FB_ACCEL_NONE;
872 fbinfo->var.nonstd = 0;
873 fbinfo->var.activate = FB_ACTIVATE_NOW;
874 fbinfo->var.height = display->height;
875 fbinfo->var.width = display->width;
876 fbinfo->var.accel_flags = 0;
877 fbinfo->var.vmode = FB_VMODE_NONINTERLACED;
879 fbinfo->fbops = &s3c2410fb_ops;
880 fbinfo->flags = FBINFO_FLAG_DEFAULT;
881 fbinfo->pseudo_palette = &info->pseudo_pal;
883 fbinfo->var.xres = display->xres;
884 fbinfo->var.xres_virtual = display->xres;
885 fbinfo->var.yres = display->yres;
886 fbinfo->var.yres_virtual = display->yres;
887 fbinfo->var.bits_per_pixel = display->bpp;
888 fbinfo->var.left_margin = display->left_margin;
889 fbinfo->var.right_margin = display->right_margin;
891 fbinfo->var.upper_margin = display->upper_margin;
892 fbinfo->var.lower_margin = display->lower_margin;
893 fbinfo->var.vsync_len =
894 S3C2410_LCDCON2_GET_VSPW(display->lcdcon2) + 1;
895 fbinfo->var.hsync_len =
896 S3C2410_LCDCON4_GET_HSPW(display->lcdcon4) + 1;
898 fbinfo->var.red.offset = 11;
899 fbinfo->var.green.offset = 5;
900 fbinfo->var.blue.offset = 0;
901 fbinfo->var.transp.offset = 0;
902 fbinfo->var.red.length = 5;
903 fbinfo->var.green.length = 6;
904 fbinfo->var.blue.length = 5;
905 fbinfo->var.transp.length = 0;
907 /* find maximum required memory size for display */
908 for (i = 0; i < mach_info->num_displays; i++) {
909 unsigned long smem_len = mach_info->displays[i].xres;
911 smem_len *= mach_info->displays[i].yres;
912 smem_len *= mach_info->displays[i].bpp;
914 if (fbinfo->fix.smem_len < smem_len)
915 fbinfo->fix.smem_len = smem_len;
918 for (i = 0; i < 256; i++)
919 info->palette_buffer[i] = PALETTE_BUFF_CLEAR;
921 ret = request_irq(irq, s3c2410fb_irq, IRQF_DISABLED, pdev->name, info);
923 dev_err(&pdev->dev, "cannot get irq %d - err %d\n", irq, ret);
928 info->clk = clk_get(NULL, "lcd");
929 if (!info->clk || IS_ERR(info->clk)) {
930 printk(KERN_ERR "failed to get lcd clock source\n");
935 clk_enable(info->clk);
936 dprintk("got and enabled clock\n");
940 /* Initialize video memory */
941 ret = s3c2410fb_map_video_memory(fbinfo);
943 printk(KERN_ERR "Failed to allocate video RAM: %d\n", ret);
948 dprintk("got video memory\n");
950 s3c2410fb_init_registers(fbinfo);
952 s3c2410fb_check_var(&fbinfo->var, fbinfo);
954 ret = register_framebuffer(fbinfo);
956 printk(KERN_ERR "Failed to register framebuffer device: %d\n",
958 goto free_video_memory;
961 /* create device files */
962 device_create_file(&pdev->dev, &dev_attr_debug);
964 printk(KERN_INFO "fb%d: %s frame buffer device\n",
965 fbinfo->node, fbinfo->fix.id);
970 s3c2410fb_unmap_video_memory(info);
972 clk_disable(info->clk);
979 release_resource(info->mem);
982 framebuffer_release(fbinfo);
986 /* s3c2410fb_stop_lcd
988 * shutdown the lcd controller
990 static void s3c2410fb_stop_lcd(struct s3c2410fb_info *fbi)
994 local_irq_save(flags);
996 fbi->regs.lcdcon1 &= ~S3C2410_LCDCON1_ENVID;
997 writel(fbi->regs.lcdcon1, fbi->io + S3C2410_LCDCON1);
999 local_irq_restore(flags);
1005 static int s3c2410fb_remove(struct platform_device *pdev)
1007 struct fb_info *fbinfo = platform_get_drvdata(pdev);
1008 struct s3c2410fb_info *info = fbinfo->par;
1011 s3c2410fb_stop_lcd(info);
1014 s3c2410fb_unmap_video_memory(info);
1017 clk_disable(info->clk);
1022 irq = platform_get_irq(pdev, 0);
1023 free_irq(irq, info);
1025 release_resource(info->mem);
1028 unregister_framebuffer(fbinfo);
1035 /* suspend and resume support for the lcd controller */
1036 static int s3c2410fb_suspend(struct platform_device *dev, pm_message_t state)
1038 struct fb_info *fbinfo = platform_get_drvdata(dev);
1039 struct s3c2410fb_info *info = fbinfo->par;
1041 s3c2410fb_stop_lcd(info);
1043 /* sleep before disabling the clock, we need to ensure
1044 * the LCD DMA engine is not going to get back on the bus
1045 * before the clock goes off again (bjd) */
1048 clk_disable(info->clk);
1053 static int s3c2410fb_resume(struct platform_device *dev)
1055 struct fb_info *fbinfo = platform_get_drvdata(dev);
1056 struct s3c2410fb_info *info = fbinfo->par;
1058 clk_enable(info->clk);
1061 s3c2410fb_init_registers(info);
1067 #define s3c2410fb_suspend NULL
1068 #define s3c2410fb_resume NULL
1071 static struct platform_driver s3c2410fb_driver = {
1072 .probe = s3c2410fb_probe,
1073 .remove = s3c2410fb_remove,
1074 .suspend = s3c2410fb_suspend,
1075 .resume = s3c2410fb_resume,
1077 .name = "s3c2410-lcd",
1078 .owner = THIS_MODULE,
1082 int __devinit s3c2410fb_init(void)
1084 return platform_driver_register(&s3c2410fb_driver);
1087 static void __exit s3c2410fb_cleanup(void)
1089 platform_driver_unregister(&s3c2410fb_driver);
1092 module_init(s3c2410fb_init);
1093 module_exit(s3c2410fb_cleanup);
1095 MODULE_AUTHOR("Arnaud Patard <arnaud.patard@rtp-net.org>, "
1096 "Ben Dooks <ben-linux@fluff.org>");
1097 MODULE_DESCRIPTION("Framebuffer driver for the s3c2410");
1098 MODULE_LICENSE("GPL");