2 * linux/drivers/video/pxafb.c
4 * Copyright (C) 1999 Eric A. Thomas.
5 * Copyright (C) 2004 Jean-Frederic Clere.
6 * Copyright (C) 2004 Ian Campbell.
7 * Copyright (C) 2004 Jeff Lackey.
8 * Based on sa1100fb.c Copyright (C) 1999 Eric A. Thomas
10 * Based on acornfb.c Copyright (C) Russell King.
12 * This file is subject to the terms and conditions of the GNU General Public
13 * License. See the file COPYING in the main directory of this archive for
16 * Intel PXA250/210 LCD Controller Frame Buffer Driver
18 * Please direct your questions and comments on this driver to the following
21 * linux-arm-kernel@lists.arm.linux.org.uk
25 #include <linux/module.h>
26 #include <linux/moduleparam.h>
27 #include <linux/kernel.h>
28 #include <linux/sched.h>
29 #include <linux/errno.h>
30 #include <linux/string.h>
31 #include <linux/interrupt.h>
32 #include <linux/slab.h>
34 #include <linux/delay.h>
35 #include <linux/init.h>
36 #include <linux/ioport.h>
37 #include <linux/cpufreq.h>
38 #include <linux/platform_device.h>
39 #include <linux/dma-mapping.h>
40 #include <linux/clk.h>
41 #include <linux/err.h>
42 #include <linux/completion.h>
44 #include <asm/hardware.h>
47 #include <asm/div64.h>
48 #include <asm/arch/pxa-regs.h>
49 #include <asm/arch/pxa2xx-gpio.h>
50 #include <asm/arch/bitfield.h>
51 #include <asm/arch/pxafb.h>
54 * Complain if VAR is out of range.
60 /* Bits which should not be set in machine configuration structures */
61 #define LCCR0_INVALID_CONFIG_MASK (LCCR0_OUM | LCCR0_BM | LCCR0_QDM |\
62 LCCR0_DIS | LCCR0_EFM | LCCR0_IUM |\
63 LCCR0_SFM | LCCR0_LDM | LCCR0_ENB)
65 #define LCCR3_INVALID_CONFIG_MASK (LCCR3_HSP | LCCR3_VSP |\
66 LCCR3_PCD | LCCR3_BPP)
68 static void (*pxafb_backlight_power)(int);
69 static void (*pxafb_lcd_power)(int, struct fb_var_screeninfo *);
71 static int pxafb_activate_var(struct fb_var_screeninfo *var,
73 static void set_ctrlr_state(struct pxafb_info *fbi, u_int state);
75 static inline unsigned long
76 lcd_readl(struct pxafb_info *fbi, unsigned int off)
78 return __raw_readl(fbi->mmio_base + off);
82 lcd_writel(struct pxafb_info *fbi, unsigned int off, unsigned long val)
84 __raw_writel(val, fbi->mmio_base + off);
87 static inline void pxafb_schedule_work(struct pxafb_info *fbi, u_int state)
91 local_irq_save(flags);
93 * We need to handle two requests being made at the same time.
94 * There are two important cases:
95 * 1. When we are changing VT (C_REENABLE) while unblanking
96 * (C_ENABLE) We must perform the unblanking, which will
97 * do our REENABLE for us.
98 * 2. When we are blanking, but immediately unblank before
99 * we have blanked. We do the "REENABLE" thing here as
100 * well, just to be sure.
102 if (fbi->task_state == C_ENABLE && state == C_REENABLE)
104 if (fbi->task_state == C_DISABLE && state == C_ENABLE)
107 if (state != (u_int)-1) {
108 fbi->task_state = state;
109 schedule_work(&fbi->task);
111 local_irq_restore(flags);
114 static inline u_int chan_to_field(u_int chan, struct fb_bitfield *bf)
117 chan >>= 16 - bf->length;
118 return chan << bf->offset;
122 pxafb_setpalettereg(u_int regno, u_int red, u_int green, u_int blue,
123 u_int trans, struct fb_info *info)
125 struct pxafb_info *fbi = (struct pxafb_info *)info;
128 if (regno >= fbi->palette_size)
131 if (fbi->fb.var.grayscale) {
132 fbi->palette_cpu[regno] = ((blue >> 8) & 0x00ff);
136 switch (fbi->lccr4 & LCCR4_PAL_FOR_MASK) {
137 case LCCR4_PAL_FOR_0:
138 val = ((red >> 0) & 0xf800);
139 val |= ((green >> 5) & 0x07e0);
140 val |= ((blue >> 11) & 0x001f);
141 fbi->palette_cpu[regno] = val;
143 case LCCR4_PAL_FOR_1:
144 val = ((red << 8) & 0x00f80000);
145 val |= ((green >> 0) & 0x0000fc00);
146 val |= ((blue >> 8) & 0x000000f8);
147 ((u32 *)(fbi->palette_cpu))[regno] = val;
149 case LCCR4_PAL_FOR_2:
150 val = ((red << 8) & 0x00fc0000);
151 val |= ((green >> 0) & 0x0000fc00);
152 val |= ((blue >> 8) & 0x000000fc);
153 ((u32 *)(fbi->palette_cpu))[regno] = val;
161 pxafb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
162 u_int trans, struct fb_info *info)
164 struct pxafb_info *fbi = (struct pxafb_info *)info;
169 * If inverse mode was selected, invert all the colours
170 * rather than the register number. The register number
171 * is what you poke into the framebuffer to produce the
172 * colour you requested.
174 if (fbi->cmap_inverse) {
176 green = 0xffff - green;
177 blue = 0xffff - blue;
181 * If greyscale is true, then we convert the RGB value
182 * to greyscale no matter what visual we are using.
184 if (fbi->fb.var.grayscale)
185 red = green = blue = (19595 * red + 38470 * green +
188 switch (fbi->fb.fix.visual) {
189 case FB_VISUAL_TRUECOLOR:
191 * 16-bit True Colour. We encode the RGB value
192 * according to the RGB bitfield information.
195 u32 *pal = fbi->fb.pseudo_palette;
197 val = chan_to_field(red, &fbi->fb.var.red);
198 val |= chan_to_field(green, &fbi->fb.var.green);
199 val |= chan_to_field(blue, &fbi->fb.var.blue);
206 case FB_VISUAL_STATIC_PSEUDOCOLOR:
207 case FB_VISUAL_PSEUDOCOLOR:
208 ret = pxafb_setpalettereg(regno, red, green, blue, trans, info);
216 * pxafb_bpp_to_lccr3():
217 * Convert a bits per pixel value to the correct bit pattern for LCCR3
219 static int pxafb_bpp_to_lccr3(struct fb_var_screeninfo *var)
222 switch (var->bits_per_pixel) {
223 case 1: ret = LCCR3_1BPP; break;
224 case 2: ret = LCCR3_2BPP; break;
225 case 4: ret = LCCR3_4BPP; break;
226 case 8: ret = LCCR3_8BPP; break;
227 case 16: ret = LCCR3_16BPP; break;
232 #ifdef CONFIG_CPU_FREQ
234 * pxafb_display_dma_period()
235 * Calculate the minimum period (in picoseconds) between two DMA
236 * requests for the LCD controller. If we hit this, it means we're
237 * doing nothing but LCD DMA.
239 static unsigned int pxafb_display_dma_period(struct fb_var_screeninfo *var)
242 * Period = pixclock * bits_per_byte * bytes_per_transfer
243 * / memory_bits_per_pixel;
245 return var->pixclock * 8 * 16 / var->bits_per_pixel;
250 * Select the smallest mode that allows the desired resolution to be
251 * displayed. If desired parameters can be rounded up.
253 static struct pxafb_mode_info *pxafb_getmode(struct pxafb_mach_info *mach,
254 struct fb_var_screeninfo *var)
256 struct pxafb_mode_info *mode = NULL;
257 struct pxafb_mode_info *modelist = mach->modes;
258 unsigned int best_x = 0xffffffff, best_y = 0xffffffff;
261 for (i = 0; i < mach->num_modes; i++) {
262 if (modelist[i].xres >= var->xres &&
263 modelist[i].yres >= var->yres &&
264 modelist[i].xres < best_x &&
265 modelist[i].yres < best_y &&
266 modelist[i].bpp >= var->bits_per_pixel) {
267 best_x = modelist[i].xres;
268 best_y = modelist[i].yres;
276 static void pxafb_setmode(struct fb_var_screeninfo *var,
277 struct pxafb_mode_info *mode)
279 var->xres = mode->xres;
280 var->yres = mode->yres;
281 var->bits_per_pixel = mode->bpp;
282 var->pixclock = mode->pixclock;
283 var->hsync_len = mode->hsync_len;
284 var->left_margin = mode->left_margin;
285 var->right_margin = mode->right_margin;
286 var->vsync_len = mode->vsync_len;
287 var->upper_margin = mode->upper_margin;
288 var->lower_margin = mode->lower_margin;
289 var->sync = mode->sync;
290 var->grayscale = mode->cmap_greyscale;
291 var->xres_virtual = var->xres;
292 var->yres_virtual = var->yres;
297 * Get the video params out of 'var'. If a value doesn't fit, round it up,
298 * if it's too big, return -EINVAL.
300 * Round up in the following order: bits_per_pixel, xres,
301 * yres, xres_virtual, yres_virtual, xoffset, yoffset, grayscale,
302 * bitfields, horizontal timing, vertical timing.
304 static int pxafb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
306 struct pxafb_info *fbi = (struct pxafb_info *)info;
307 struct pxafb_mach_info *inf = fbi->dev->platform_data;
309 if (var->xres < MIN_XRES)
310 var->xres = MIN_XRES;
311 if (var->yres < MIN_YRES)
312 var->yres = MIN_YRES;
314 if (inf->fixed_modes) {
315 struct pxafb_mode_info *mode;
317 mode = pxafb_getmode(inf, var);
320 pxafb_setmode(var, mode);
322 if (var->xres > inf->modes->xres)
324 if (var->yres > inf->modes->yres)
326 if (var->bits_per_pixel > inf->modes->bpp)
331 max(var->xres_virtual, var->xres);
333 max(var->yres_virtual, var->yres);
336 * Setup the RGB parameters for this display.
338 * The pixel packing format is described on page 7-11 of the
339 * PXA2XX Developer's Manual.
341 if (var->bits_per_pixel == 16) {
342 var->red.offset = 11; var->red.length = 5;
343 var->green.offset = 5; var->green.length = 6;
344 var->blue.offset = 0; var->blue.length = 5;
345 var->transp.offset = var->transp.length = 0;
347 var->red.offset = var->green.offset = 0;
348 var->blue.offset = var->transp.offset = 0;
350 var->green.length = 8;
351 var->blue.length = 8;
352 var->transp.length = 0;
355 #ifdef CONFIG_CPU_FREQ
356 pr_debug("pxafb: dma period = %d ps, clock = %d kHz\n",
357 pxafb_display_dma_period(var),
358 get_clk_frequency_khz(0));
364 static inline void pxafb_set_truecolor(u_int is_true_color)
366 /* do your machine-specific setup if needed */
371 * Set the user defined part of the display for the specified console
373 static int pxafb_set_par(struct fb_info *info)
375 struct pxafb_info *fbi = (struct pxafb_info *)info;
376 struct fb_var_screeninfo *var = &info->var;
378 if (var->bits_per_pixel == 16)
379 fbi->fb.fix.visual = FB_VISUAL_TRUECOLOR;
380 else if (!fbi->cmap_static)
381 fbi->fb.fix.visual = FB_VISUAL_PSEUDOCOLOR;
384 * Some people have weird ideas about wanting static
385 * pseudocolor maps. I suspect their user space
386 * applications are broken.
388 fbi->fb.fix.visual = FB_VISUAL_STATIC_PSEUDOCOLOR;
391 fbi->fb.fix.line_length = var->xres_virtual *
392 var->bits_per_pixel / 8;
393 if (var->bits_per_pixel == 16)
394 fbi->palette_size = 0;
396 fbi->palette_size = var->bits_per_pixel == 1 ?
397 4 : 1 << var->bits_per_pixel;
399 fbi->palette_cpu = (u16 *)&fbi->dma_buff->palette[0];
402 * Set (any) board control register to handle new color depth
404 pxafb_set_truecolor(fbi->fb.fix.visual == FB_VISUAL_TRUECOLOR);
406 if (fbi->fb.var.bits_per_pixel == 16)
407 fb_dealloc_cmap(&fbi->fb.cmap);
409 fb_alloc_cmap(&fbi->fb.cmap, 1<<fbi->fb.var.bits_per_pixel, 0);
411 pxafb_activate_var(var, fbi);
418 * Blank the display by setting all palette values to zero. Note, the
419 * 16 bpp mode does not really use the palette, so this will not
420 * blank the display in all modes.
422 static int pxafb_blank(int blank, struct fb_info *info)
424 struct pxafb_info *fbi = (struct pxafb_info *)info;
428 case FB_BLANK_POWERDOWN:
429 case FB_BLANK_VSYNC_SUSPEND:
430 case FB_BLANK_HSYNC_SUSPEND:
431 case FB_BLANK_NORMAL:
432 if (fbi->fb.fix.visual == FB_VISUAL_PSEUDOCOLOR ||
433 fbi->fb.fix.visual == FB_VISUAL_STATIC_PSEUDOCOLOR)
434 for (i = 0; i < fbi->palette_size; i++)
435 pxafb_setpalettereg(i, 0, 0, 0, 0, info);
437 pxafb_schedule_work(fbi, C_DISABLE);
438 /* TODO if (pxafb_blank_helper) pxafb_blank_helper(blank); */
441 case FB_BLANK_UNBLANK:
442 /* TODO if (pxafb_blank_helper) pxafb_blank_helper(blank); */
443 if (fbi->fb.fix.visual == FB_VISUAL_PSEUDOCOLOR ||
444 fbi->fb.fix.visual == FB_VISUAL_STATIC_PSEUDOCOLOR)
445 fb_set_cmap(&fbi->fb.cmap, info);
446 pxafb_schedule_work(fbi, C_ENABLE);
451 static int pxafb_mmap(struct fb_info *info,
452 struct vm_area_struct *vma)
454 struct pxafb_info *fbi = (struct pxafb_info *)info;
455 unsigned long off = vma->vm_pgoff << PAGE_SHIFT;
457 if (off < info->fix.smem_len) {
459 return dma_mmap_writecombine(fbi->dev, vma, fbi->map_cpu,
460 fbi->map_dma, fbi->map_size);
465 static struct fb_ops pxafb_ops = {
466 .owner = THIS_MODULE,
467 .fb_check_var = pxafb_check_var,
468 .fb_set_par = pxafb_set_par,
469 .fb_setcolreg = pxafb_setcolreg,
470 .fb_fillrect = cfb_fillrect,
471 .fb_copyarea = cfb_copyarea,
472 .fb_imageblit = cfb_imageblit,
473 .fb_blank = pxafb_blank,
474 .fb_mmap = pxafb_mmap,
478 * Calculate the PCD value from the clock rate (in picoseconds).
479 * We take account of the PPCR clock setting.
480 * From PXA Developer's Manual:
491 * LCLK = LCD/Memory Clock
494 * PixelClock here is in Hz while the pixclock argument given is the
495 * period in picoseconds. Hence PixelClock = 1 / ( pixclock * 10^-12 )
497 * The function get_lclk_frequency_10khz returns LCLK in units of
498 * 10khz. Calling the result of this function lclk gives us the
501 * PCD = (lclk * 10^4 ) * ( pixclock * 10^-12 )
502 * -------------------------------------- - 1
505 * Factoring the 10^4 and 10^-12 out gives 10^-8 == 1 / 100000000 as used below.
507 static inline unsigned int get_pcd(struct pxafb_info *fbi,
508 unsigned int pixclock)
510 unsigned long long pcd;
512 /* FIXME: Need to take into account Double Pixel Clock mode
513 * (DPC) bit? or perhaps set it based on the various clock
515 pcd = (unsigned long long)(clk_get_rate(fbi->clk) / 10000);
517 do_div(pcd, 100000000 * 2);
518 /* no need for this, since we should subtract 1 anyway. they cancel */
519 /* pcd += 1; */ /* make up for integer math truncations */
520 return (unsigned int)pcd;
524 * Some touchscreens need hsync information from the video driver to
525 * function correctly. We export it here. Note that 'hsync_time' and
526 * the value returned from pxafb_get_hsync_time() is the *reciprocal*
527 * of the hsync period in seconds.
529 static inline void set_hsync_time(struct pxafb_info *fbi, unsigned int pcd)
533 if ((pcd == 0) || (fbi->fb.var.hsync_len == 0)) {
538 htime = clk_get_rate(fbi->clk) / (pcd * fbi->fb.var.hsync_len);
540 fbi->hsync_time = htime;
543 unsigned long pxafb_get_hsync_time(struct device *dev)
545 struct pxafb_info *fbi = dev_get_drvdata(dev);
547 /* If display is blanked/suspended, hsync isn't active */
548 if (!fbi || (fbi->state != C_ENABLE))
551 return fbi->hsync_time;
553 EXPORT_SYMBOL(pxafb_get_hsync_time);
555 static int setup_frame_dma(struct pxafb_info *fbi, int dma, int pal,
556 unsigned int offset, size_t size)
558 struct pxafb_dma_descriptor *dma_desc, *pal_desc;
559 unsigned int dma_desc_off, pal_desc_off;
561 if (dma < 0 || dma >= DMA_MAX)
564 dma_desc = &fbi->dma_buff->dma_desc[dma];
565 dma_desc_off = offsetof(struct pxafb_dma_buff, dma_desc[dma]);
567 dma_desc->fsadr = fbi->screen_dma + offset;
569 dma_desc->ldcmd = size;
571 if (pal < 0 || pal >= PAL_MAX) {
572 dma_desc->fdadr = fbi->dma_buff_phys + dma_desc_off;
573 fbi->fdadr[dma] = fbi->dma_buff_phys + dma_desc_off;
575 pal_desc = &fbi->dma_buff->pal_desc[dma];
576 pal_desc_off = offsetof(struct pxafb_dma_buff, dma_desc[pal]);
578 pal_desc->fsadr = fbi->dma_buff_phys + pal * PALETTE_SIZE;
581 if ((fbi->lccr4 & LCCR4_PAL_FOR_MASK) == LCCR4_PAL_FOR_0)
582 pal_desc->ldcmd = fbi->palette_size * sizeof(u16);
584 pal_desc->ldcmd = fbi->palette_size * sizeof(u32);
586 pal_desc->ldcmd |= LDCMD_PAL;
588 /* flip back and forth between palette and frame buffer */
589 pal_desc->fdadr = fbi->dma_buff_phys + dma_desc_off;
590 dma_desc->fdadr = fbi->dma_buff_phys + pal_desc_off;
591 fbi->fdadr[dma] = fbi->dma_buff_phys + dma_desc_off;
598 * pxafb_activate_var():
599 * Configures LCD Controller based on entries in var parameter.
600 * Settings are only written to the controller if changes were made.
602 static int pxafb_activate_var(struct fb_var_screeninfo *var,
603 struct pxafb_info *fbi)
605 struct pxafb_lcd_reg new_regs;
607 u_int lines_per_panel, pcd = get_pcd(fbi, var->pixclock);
611 if (var->xres < 16 || var->xres > 1024)
612 printk(KERN_ERR "%s: invalid xres %d\n",
613 fbi->fb.fix.id, var->xres);
614 switch (var->bits_per_pixel) {
622 printk(KERN_ERR "%s: invalid bit depth %d\n",
623 fbi->fb.fix.id, var->bits_per_pixel);
626 if (var->hsync_len < 1 || var->hsync_len > 64)
627 printk(KERN_ERR "%s: invalid hsync_len %d\n",
628 fbi->fb.fix.id, var->hsync_len);
629 if (var->left_margin < 1 || var->left_margin > 255)
630 printk(KERN_ERR "%s: invalid left_margin %d\n",
631 fbi->fb.fix.id, var->left_margin);
632 if (var->right_margin < 1 || var->right_margin > 255)
633 printk(KERN_ERR "%s: invalid right_margin %d\n",
634 fbi->fb.fix.id, var->right_margin);
635 if (var->yres < 1 || var->yres > 1024)
636 printk(KERN_ERR "%s: invalid yres %d\n",
637 fbi->fb.fix.id, var->yres);
638 if (var->vsync_len < 1 || var->vsync_len > 64)
639 printk(KERN_ERR "%s: invalid vsync_len %d\n",
640 fbi->fb.fix.id, var->vsync_len);
641 if (var->upper_margin < 0 || var->upper_margin > 255)
642 printk(KERN_ERR "%s: invalid upper_margin %d\n",
643 fbi->fb.fix.id, var->upper_margin);
644 if (var->lower_margin < 0 || var->lower_margin > 255)
645 printk(KERN_ERR "%s: invalid lower_margin %d\n",
646 fbi->fb.fix.id, var->lower_margin);
649 new_regs.lccr0 = fbi->lccr0 |
650 (LCCR0_LDM | LCCR0_SFM | LCCR0_IUM | LCCR0_EFM |
651 LCCR0_QDM | LCCR0_BM | LCCR0_OUM);
654 LCCR1_DisWdth(var->xres) +
655 LCCR1_HorSnchWdth(var->hsync_len) +
656 LCCR1_BegLnDel(var->left_margin) +
657 LCCR1_EndLnDel(var->right_margin);
660 * If we have a dual scan LCD, we need to halve
661 * the YRES parameter.
663 lines_per_panel = var->yres;
664 if ((fbi->lccr0 & LCCR0_SDS) == LCCR0_Dual)
665 lines_per_panel /= 2;
668 LCCR2_DisHght(lines_per_panel) +
669 LCCR2_VrtSnchWdth(var->vsync_len) +
670 LCCR2_BegFrmDel(var->upper_margin) +
671 LCCR2_EndFrmDel(var->lower_margin);
673 new_regs.lccr3 = fbi->lccr3 |
674 pxafb_bpp_to_lccr3(var) |
675 (var->sync & FB_SYNC_HOR_HIGH_ACT ?
676 LCCR3_HorSnchH : LCCR3_HorSnchL) |
677 (var->sync & FB_SYNC_VERT_HIGH_ACT ?
678 LCCR3_VrtSnchH : LCCR3_VrtSnchL);
681 new_regs.lccr3 |= LCCR3_PixClkDiv(pcd);
683 /* Update shadow copy atomically */
684 local_irq_save(flags);
686 nbytes = lines_per_panel * fbi->fb.fix.line_length;
688 if ((fbi->lccr0 & LCCR0_SDS) == LCCR0_Dual)
689 setup_frame_dma(fbi, DMA_LOWER, PAL_NONE, nbytes, nbytes);
691 if (var->bits_per_pixel >= 16)
692 setup_frame_dma(fbi, DMA_BASE, PAL_NONE, 0, nbytes);
694 setup_frame_dma(fbi, DMA_BASE, PAL_BASE, 0, nbytes);
696 fbi->reg_lccr0 = new_regs.lccr0;
697 fbi->reg_lccr1 = new_regs.lccr1;
698 fbi->reg_lccr2 = new_regs.lccr2;
699 fbi->reg_lccr3 = new_regs.lccr3;
700 fbi->reg_lccr4 = lcd_readl(fbi, LCCR4) & ~LCCR4_PAL_FOR_MASK;
701 fbi->reg_lccr4 |= (fbi->lccr4 & LCCR4_PAL_FOR_MASK);
702 set_hsync_time(fbi, pcd);
703 local_irq_restore(flags);
706 * Only update the registers if the controller is enabled
707 * and something has changed.
709 if ((lcd_readl(fbi, LCCR0) != fbi->reg_lccr0) ||
710 (lcd_readl(fbi, LCCR1) != fbi->reg_lccr1) ||
711 (lcd_readl(fbi, LCCR2) != fbi->reg_lccr2) ||
712 (lcd_readl(fbi, LCCR3) != fbi->reg_lccr3) ||
713 (lcd_readl(fbi, FDADR0) != fbi->fdadr[0]) ||
714 (lcd_readl(fbi, FDADR1) != fbi->fdadr[1]))
715 pxafb_schedule_work(fbi, C_REENABLE);
721 * NOTE! The following functions are purely helpers for set_ctrlr_state.
722 * Do not call them directly; set_ctrlr_state does the correct serialisation
723 * to ensure that things happen in the right way 100% of time time.
726 static inline void __pxafb_backlight_power(struct pxafb_info *fbi, int on)
728 pr_debug("pxafb: backlight o%s\n", on ? "n" : "ff");
730 if (pxafb_backlight_power)
731 pxafb_backlight_power(on);
734 static inline void __pxafb_lcd_power(struct pxafb_info *fbi, int on)
736 pr_debug("pxafb: LCD power o%s\n", on ? "n" : "ff");
739 pxafb_lcd_power(on, &fbi->fb.var);
742 static void pxafb_setup_gpio(struct pxafb_info *fbi)
745 unsigned int lccr0 = fbi->lccr0;
748 * setup is based on type of panel supported
751 /* 4 bit interface */
752 if ((lccr0 & LCCR0_CMS) == LCCR0_Mono &&
753 (lccr0 & LCCR0_SDS) == LCCR0_Sngl &&
754 (lccr0 & LCCR0_DPD) == LCCR0_4PixMono)
757 /* 8 bit interface */
758 else if (((lccr0 & LCCR0_CMS) == LCCR0_Mono &&
759 ((lccr0 & LCCR0_SDS) == LCCR0_Dual ||
760 (lccr0 & LCCR0_DPD) == LCCR0_8PixMono)) ||
761 ((lccr0 & LCCR0_CMS) == LCCR0_Color &&
762 (lccr0 & LCCR0_PAS) == LCCR0_Pas &&
763 (lccr0 & LCCR0_SDS) == LCCR0_Sngl))
766 /* 16 bit interface */
767 else if ((lccr0 & LCCR0_CMS) == LCCR0_Color &&
768 ((lccr0 & LCCR0_SDS) == LCCR0_Dual ||
769 (lccr0 & LCCR0_PAS) == LCCR0_Act))
773 printk(KERN_ERR "pxafb_setup_gpio: unable to determine "
778 for (gpio = 58; ldd_bits; gpio++, ldd_bits--)
779 pxa_gpio_mode(gpio | GPIO_ALT_FN_2_OUT);
780 pxa_gpio_mode(GPIO74_LCD_FCLK_MD);
781 pxa_gpio_mode(GPIO75_LCD_LCLK_MD);
782 pxa_gpio_mode(GPIO76_LCD_PCLK_MD);
783 pxa_gpio_mode(GPIO77_LCD_ACBIAS_MD);
786 static void pxafb_enable_controller(struct pxafb_info *fbi)
788 pr_debug("pxafb: Enabling LCD controller\n");
789 pr_debug("fdadr0 0x%08x\n", (unsigned int) fbi->fdadr[0]);
790 pr_debug("fdadr1 0x%08x\n", (unsigned int) fbi->fdadr[1]);
791 pr_debug("reg_lccr0 0x%08x\n", (unsigned int) fbi->reg_lccr0);
792 pr_debug("reg_lccr1 0x%08x\n", (unsigned int) fbi->reg_lccr1);
793 pr_debug("reg_lccr2 0x%08x\n", (unsigned int) fbi->reg_lccr2);
794 pr_debug("reg_lccr3 0x%08x\n", (unsigned int) fbi->reg_lccr3);
796 /* enable LCD controller clock */
797 clk_enable(fbi->clk);
799 /* Sequence from 11.7.10 */
800 lcd_writel(fbi, LCCR3, fbi->reg_lccr3);
801 lcd_writel(fbi, LCCR2, fbi->reg_lccr2);
802 lcd_writel(fbi, LCCR1, fbi->reg_lccr1);
803 lcd_writel(fbi, LCCR0, fbi->reg_lccr0 & ~LCCR0_ENB);
805 lcd_writel(fbi, FDADR0, fbi->fdadr[0]);
806 lcd_writel(fbi, FDADR1, fbi->fdadr[1]);
807 lcd_writel(fbi, LCCR0, fbi->reg_lccr0 | LCCR0_ENB);
810 static void pxafb_disable_controller(struct pxafb_info *fbi)
814 /* Clear LCD Status Register */
815 lcd_writel(fbi, LCSR, 0xffffffff);
817 lccr0 = lcd_readl(fbi, LCCR0) & ~LCCR0_LDM;
818 lcd_writel(fbi, LCCR0, lccr0);
819 lcd_writel(fbi, LCCR0, lccr0 | LCCR0_DIS);
821 wait_for_completion_timeout(&fbi->disable_done, 200 * HZ / 1000);
823 /* disable LCD controller clock */
824 clk_disable(fbi->clk);
828 * pxafb_handle_irq: Handle 'LCD DONE' interrupts.
830 static irqreturn_t pxafb_handle_irq(int irq, void *dev_id)
832 struct pxafb_info *fbi = dev_id;
833 unsigned int lccr0, lcsr = lcd_readl(fbi, LCSR);
835 if (lcsr & LCSR_LDD) {
836 lccr0 = lcd_readl(fbi, LCCR0);
837 lcd_writel(fbi, LCCR0, lccr0 | LCCR0_LDM);
838 complete(&fbi->disable_done);
841 lcd_writel(fbi, LCSR, lcsr);
846 * This function must be called from task context only, since it will
847 * sleep when disabling the LCD controller, or if we get two contending
848 * processes trying to alter state.
850 static void set_ctrlr_state(struct pxafb_info *fbi, u_int state)
854 down(&fbi->ctrlr_sem);
856 old_state = fbi->state;
859 * Hack around fbcon initialisation.
861 if (old_state == C_STARTUP && state == C_REENABLE)
865 case C_DISABLE_CLKCHANGE:
867 * Disable controller for clock change. If the
868 * controller is already disabled, then do nothing.
870 if (old_state != C_DISABLE && old_state != C_DISABLE_PM) {
872 /* TODO __pxafb_lcd_power(fbi, 0); */
873 pxafb_disable_controller(fbi);
882 if (old_state != C_DISABLE) {
884 __pxafb_backlight_power(fbi, 0);
885 __pxafb_lcd_power(fbi, 0);
886 if (old_state != C_DISABLE_CLKCHANGE)
887 pxafb_disable_controller(fbi);
891 case C_ENABLE_CLKCHANGE:
893 * Enable the controller after clock change. Only
894 * do this if we were disabled for the clock change.
896 if (old_state == C_DISABLE_CLKCHANGE) {
897 fbi->state = C_ENABLE;
898 pxafb_enable_controller(fbi);
899 /* TODO __pxafb_lcd_power(fbi, 1); */
905 * Re-enable the controller only if it was already
906 * enabled. This is so we reprogram the control
909 if (old_state == C_ENABLE) {
910 __pxafb_lcd_power(fbi, 0);
911 pxafb_disable_controller(fbi);
912 pxafb_setup_gpio(fbi);
913 pxafb_enable_controller(fbi);
914 __pxafb_lcd_power(fbi, 1);
920 * Re-enable the controller after PM. This is not
921 * perfect - think about the case where we were doing
922 * a clock change, and we suspended half-way through.
924 if (old_state != C_DISABLE_PM)
930 * Power up the LCD screen, enable controller, and
931 * turn on the backlight.
933 if (old_state != C_ENABLE) {
934 fbi->state = C_ENABLE;
935 pxafb_setup_gpio(fbi);
936 pxafb_enable_controller(fbi);
937 __pxafb_lcd_power(fbi, 1);
938 __pxafb_backlight_power(fbi, 1);
946 * Our LCD controller task (which is called when we blank or unblank)
949 static void pxafb_task(struct work_struct *work)
951 struct pxafb_info *fbi =
952 container_of(work, struct pxafb_info, task);
953 u_int state = xchg(&fbi->task_state, -1);
955 set_ctrlr_state(fbi, state);
958 #ifdef CONFIG_CPU_FREQ
960 * CPU clock speed change handler. We need to adjust the LCD timing
961 * parameters when the CPU clock is adjusted by the power management
964 * TODO: Determine why f->new != 10*get_lclk_frequency_10khz()
967 pxafb_freq_transition(struct notifier_block *nb, unsigned long val, void *data)
969 struct pxafb_info *fbi = TO_INF(nb, freq_transition);
970 /* TODO struct cpufreq_freqs *f = data; */
974 case CPUFREQ_PRECHANGE:
975 set_ctrlr_state(fbi, C_DISABLE_CLKCHANGE);
978 case CPUFREQ_POSTCHANGE:
979 pcd = get_pcd(fbi, fbi->fb.var.pixclock);
980 set_hsync_time(fbi, pcd);
981 fbi->reg_lccr3 = (fbi->reg_lccr3 & ~0xff) |
982 LCCR3_PixClkDiv(pcd);
983 set_ctrlr_state(fbi, C_ENABLE_CLKCHANGE);
990 pxafb_freq_policy(struct notifier_block *nb, unsigned long val, void *data)
992 struct pxafb_info *fbi = TO_INF(nb, freq_policy);
993 struct fb_var_screeninfo *var = &fbi->fb.var;
994 struct cpufreq_policy *policy = data;
998 case CPUFREQ_INCOMPATIBLE:
999 pr_debug("min dma period: %d ps, "
1000 "new clock %d kHz\n", pxafb_display_dma_period(var),
1002 /* TODO: fill in min/max values */
1011 * Power management hooks. Note that we won't be called from IRQ context,
1012 * unlike the blank functions above, so we may sleep.
1014 static int pxafb_suspend(struct platform_device *dev, pm_message_t state)
1016 struct pxafb_info *fbi = platform_get_drvdata(dev);
1018 set_ctrlr_state(fbi, C_DISABLE_PM);
1022 static int pxafb_resume(struct platform_device *dev)
1024 struct pxafb_info *fbi = platform_get_drvdata(dev);
1026 set_ctrlr_state(fbi, C_ENABLE_PM);
1030 #define pxafb_suspend NULL
1031 #define pxafb_resume NULL
1035 * pxafb_map_video_memory():
1036 * Allocates the DRAM memory for the frame buffer. This buffer is
1037 * remapped into a non-cached, non-buffered, memory region to
1038 * allow palette and pixel writes to occur without flushing the
1039 * cache. Once this area is remapped, all virtual memory
1040 * access to the video memory should occur at the new region.
1042 static int __init pxafb_map_video_memory(struct pxafb_info *fbi)
1045 * We reserve one page for the palette, plus the size
1046 * of the framebuffer.
1048 fbi->map_size = PAGE_ALIGN(fbi->fb.fix.smem_len + PAGE_SIZE);
1049 fbi->map_cpu = dma_alloc_writecombine(fbi->dev, fbi->map_size,
1050 &fbi->map_dma, GFP_KERNEL);
1053 /* prevent initial garbage on screen */
1054 memset(fbi->map_cpu, 0, fbi->map_size);
1055 fbi->fb.screen_base = fbi->map_cpu + PAGE_SIZE;
1056 fbi->screen_dma = fbi->map_dma + PAGE_SIZE;
1058 * FIXME: this is actually the wrong thing to place in
1059 * smem_start. But fbdev suffers from the problem that
1060 * it needs an API which doesn't exist (in this case,
1061 * dma_writecombine_mmap)
1063 fbi->fb.fix.smem_start = fbi->screen_dma;
1064 fbi->palette_size = fbi->fb.var.bits_per_pixel == 8 ? 256 : 16;
1066 fbi->dma_buff = (void *)fbi->map_cpu;
1067 fbi->dma_buff_phys = fbi->map_dma;
1068 fbi->palette_cpu = (u16 *)&fbi->dma_buff->palette[0];
1071 return fbi->map_cpu ? 0 : -ENOMEM;
1074 static void pxafb_decode_mode_info(struct pxafb_info *fbi,
1075 struct pxafb_mode_info *modes,
1076 unsigned int num_modes)
1078 unsigned int i, smemlen;
1080 pxafb_setmode(&fbi->fb.var, &modes[0]);
1082 for (i = 0; i < num_modes; i++) {
1083 smemlen = modes[i].xres * modes[i].yres * modes[i].bpp / 8;
1084 if (smemlen > fbi->fb.fix.smem_len)
1085 fbi->fb.fix.smem_len = smemlen;
1089 static int pxafb_decode_mach_info(struct pxafb_info *fbi,
1090 struct pxafb_mach_info *inf)
1092 unsigned int lcd_conn = inf->lcd_conn;
1094 fbi->cmap_inverse = inf->cmap_inverse;
1095 fbi->cmap_static = inf->cmap_static;
1097 switch (lcd_conn & 0xf) {
1098 case LCD_TYPE_MONO_STN:
1099 fbi->lccr0 = LCCR0_CMS;
1101 case LCD_TYPE_MONO_DSTN:
1102 fbi->lccr0 = LCCR0_CMS | LCCR0_SDS;
1104 case LCD_TYPE_COLOR_STN:
1107 case LCD_TYPE_COLOR_DSTN:
1108 fbi->lccr0 = LCCR0_SDS;
1110 case LCD_TYPE_COLOR_TFT:
1111 fbi->lccr0 = LCCR0_PAS;
1113 case LCD_TYPE_SMART_PANEL:
1114 fbi->lccr0 = LCCR0_LCDT | LCCR0_PAS;
1117 /* fall back to backward compatibility way */
1118 fbi->lccr0 = inf->lccr0;
1119 fbi->lccr3 = inf->lccr3;
1120 fbi->lccr4 = inf->lccr4;
1124 if (lcd_conn == LCD_MONO_STN_8BPP)
1125 fbi->lccr0 |= LCCR0_DPD;
1127 fbi->lccr3 = LCCR3_Acb((inf->lcd_conn >> 10) & 0xff);
1128 fbi->lccr3 |= (lcd_conn & LCD_BIAS_ACTIVE_LOW) ? LCCR3_OEP : 0;
1129 fbi->lccr3 |= (lcd_conn & LCD_PCLK_EDGE_FALL) ? LCCR3_PCP : 0;
1131 pxafb_decode_mode_info(fbi, inf->modes, inf->num_modes);
1135 static struct pxafb_info * __init pxafb_init_fbinfo(struct device *dev)
1137 struct pxafb_info *fbi;
1139 struct pxafb_mach_info *inf = dev->platform_data;
1140 struct pxafb_mode_info *mode = inf->modes;
1142 /* Alloc the pxafb_info and pseudo_palette in one step */
1143 fbi = kmalloc(sizeof(struct pxafb_info) + sizeof(u32) * 16, GFP_KERNEL);
1147 memset(fbi, 0, sizeof(struct pxafb_info));
1150 fbi->clk = clk_get(dev, "LCDCLK");
1151 if (IS_ERR(fbi->clk)) {
1156 strcpy(fbi->fb.fix.id, PXA_NAME);
1158 fbi->fb.fix.type = FB_TYPE_PACKED_PIXELS;
1159 fbi->fb.fix.type_aux = 0;
1160 fbi->fb.fix.xpanstep = 0;
1161 fbi->fb.fix.ypanstep = 0;
1162 fbi->fb.fix.ywrapstep = 0;
1163 fbi->fb.fix.accel = FB_ACCEL_NONE;
1165 fbi->fb.var.nonstd = 0;
1166 fbi->fb.var.activate = FB_ACTIVATE_NOW;
1167 fbi->fb.var.height = -1;
1168 fbi->fb.var.width = -1;
1169 fbi->fb.var.accel_flags = 0;
1170 fbi->fb.var.vmode = FB_VMODE_NONINTERLACED;
1172 fbi->fb.fbops = &pxafb_ops;
1173 fbi->fb.flags = FBINFO_DEFAULT;
1177 addr = addr + sizeof(struct pxafb_info);
1178 fbi->fb.pseudo_palette = addr;
1180 fbi->state = C_STARTUP;
1181 fbi->task_state = (u_char)-1;
1183 pxafb_decode_mach_info(fbi, inf);
1185 init_waitqueue_head(&fbi->ctrlr_wait);
1186 INIT_WORK(&fbi->task, pxafb_task);
1187 init_MUTEX(&fbi->ctrlr_sem);
1188 init_completion(&fbi->disable_done);
1193 #ifdef CONFIG_FB_PXA_PARAMETERS
1194 static int __init parse_opt_mode(struct device *dev, const char *this_opt)
1196 struct pxafb_mach_info *inf = dev->platform_data;
1198 const char *name = this_opt+5;
1199 unsigned int namelen = strlen(name);
1200 int res_specified = 0, bpp_specified = 0;
1201 unsigned int xres = 0, yres = 0, bpp = 0;
1202 int yres_specified = 0;
1204 for (i = namelen-1; i >= 0; i--) {
1208 if (!bpp_specified && !yres_specified) {
1209 bpp = simple_strtoul(&name[i+1], NULL, 0);
1215 if (!yres_specified) {
1216 yres = simple_strtoul(&name[i+1], NULL, 0);
1227 if (i < 0 && yres_specified) {
1228 xres = simple_strtoul(name, NULL, 0);
1232 if (res_specified) {
1233 dev_info(dev, "overriding resolution: %dx%d\n", xres, yres);
1234 inf->modes[0].xres = xres; inf->modes[0].yres = yres;
1243 inf->modes[0].bpp = bpp;
1244 dev_info(dev, "overriding bit depth: %d\n", bpp);
1247 dev_err(dev, "Depth %d is not valid\n", bpp);
1253 static int __init parse_opt(struct device *dev, char *this_opt)
1255 struct pxafb_mach_info *inf = dev->platform_data;
1256 struct pxafb_mode_info *mode = &inf->modes[0];
1261 if (!strncmp(this_opt, "mode:", 5)) {
1262 return parse_opt_mode(dev, this_opt);
1263 } else if (!strncmp(this_opt, "pixclock:", 9)) {
1264 mode->pixclock = simple_strtoul(this_opt+9, NULL, 0);
1265 sprintf(s, "pixclock: %ld\n", mode->pixclock);
1266 } else if (!strncmp(this_opt, "left:", 5)) {
1267 mode->left_margin = simple_strtoul(this_opt+5, NULL, 0);
1268 sprintf(s, "left: %u\n", mode->left_margin);
1269 } else if (!strncmp(this_opt, "right:", 6)) {
1270 mode->right_margin = simple_strtoul(this_opt+6, NULL, 0);
1271 sprintf(s, "right: %u\n", mode->right_margin);
1272 } else if (!strncmp(this_opt, "upper:", 6)) {
1273 mode->upper_margin = simple_strtoul(this_opt+6, NULL, 0);
1274 sprintf(s, "upper: %u\n", mode->upper_margin);
1275 } else if (!strncmp(this_opt, "lower:", 6)) {
1276 mode->lower_margin = simple_strtoul(this_opt+6, NULL, 0);
1277 sprintf(s, "lower: %u\n", mode->lower_margin);
1278 } else if (!strncmp(this_opt, "hsynclen:", 9)) {
1279 mode->hsync_len = simple_strtoul(this_opt+9, NULL, 0);
1280 sprintf(s, "hsynclen: %u\n", mode->hsync_len);
1281 } else if (!strncmp(this_opt, "vsynclen:", 9)) {
1282 mode->vsync_len = simple_strtoul(this_opt+9, NULL, 0);
1283 sprintf(s, "vsynclen: %u\n", mode->vsync_len);
1284 } else if (!strncmp(this_opt, "hsync:", 6)) {
1285 if (simple_strtoul(this_opt+6, NULL, 0) == 0) {
1286 sprintf(s, "hsync: Active Low\n");
1287 mode->sync &= ~FB_SYNC_HOR_HIGH_ACT;
1289 sprintf(s, "hsync: Active High\n");
1290 mode->sync |= FB_SYNC_HOR_HIGH_ACT;
1292 } else if (!strncmp(this_opt, "vsync:", 6)) {
1293 if (simple_strtoul(this_opt+6, NULL, 0) == 0) {
1294 sprintf(s, "vsync: Active Low\n");
1295 mode->sync &= ~FB_SYNC_VERT_HIGH_ACT;
1297 sprintf(s, "vsync: Active High\n");
1298 mode->sync |= FB_SYNC_VERT_HIGH_ACT;
1300 } else if (!strncmp(this_opt, "dpc:", 4)) {
1301 if (simple_strtoul(this_opt+4, NULL, 0) == 0) {
1302 sprintf(s, "double pixel clock: false\n");
1303 inf->lccr3 &= ~LCCR3_DPC;
1305 sprintf(s, "double pixel clock: true\n");
1306 inf->lccr3 |= LCCR3_DPC;
1308 } else if (!strncmp(this_opt, "outputen:", 9)) {
1309 if (simple_strtoul(this_opt+9, NULL, 0) == 0) {
1310 sprintf(s, "output enable: active low\n");
1311 inf->lccr3 = (inf->lccr3 & ~LCCR3_OEP) | LCCR3_OutEnL;
1313 sprintf(s, "output enable: active high\n");
1314 inf->lccr3 = (inf->lccr3 & ~LCCR3_OEP) | LCCR3_OutEnH;
1316 } else if (!strncmp(this_opt, "pixclockpol:", 12)) {
1317 if (simple_strtoul(this_opt+12, NULL, 0) == 0) {
1318 sprintf(s, "pixel clock polarity: falling edge\n");
1319 inf->lccr3 = (inf->lccr3 & ~LCCR3_PCP) | LCCR3_PixFlEdg;
1321 sprintf(s, "pixel clock polarity: rising edge\n");
1322 inf->lccr3 = (inf->lccr3 & ~LCCR3_PCP) | LCCR3_PixRsEdg;
1324 } else if (!strncmp(this_opt, "color", 5)) {
1325 inf->lccr0 = (inf->lccr0 & ~LCCR0_CMS) | LCCR0_Color;
1326 } else if (!strncmp(this_opt, "mono", 4)) {
1327 inf->lccr0 = (inf->lccr0 & ~LCCR0_CMS) | LCCR0_Mono;
1328 } else if (!strncmp(this_opt, "active", 6)) {
1329 inf->lccr0 = (inf->lccr0 & ~LCCR0_PAS) | LCCR0_Act;
1330 } else if (!strncmp(this_opt, "passive", 7)) {
1331 inf->lccr0 = (inf->lccr0 & ~LCCR0_PAS) | LCCR0_Pas;
1332 } else if (!strncmp(this_opt, "single", 6)) {
1333 inf->lccr0 = (inf->lccr0 & ~LCCR0_SDS) | LCCR0_Sngl;
1334 } else if (!strncmp(this_opt, "dual", 4)) {
1335 inf->lccr0 = (inf->lccr0 & ~LCCR0_SDS) | LCCR0_Dual;
1336 } else if (!strncmp(this_opt, "4pix", 4)) {
1337 inf->lccr0 = (inf->lccr0 & ~LCCR0_DPD) | LCCR0_4PixMono;
1338 } else if (!strncmp(this_opt, "8pix", 4)) {
1339 inf->lccr0 = (inf->lccr0 & ~LCCR0_DPD) | LCCR0_8PixMono;
1341 dev_err(dev, "unknown option: %s\n", this_opt);
1346 dev_info(dev, "override %s", s);
1351 static int __init pxafb_parse_options(struct device *dev, char *options)
1356 if (!options || !*options)
1359 dev_dbg(dev, "options are \"%s\"\n", options ? options : "null");
1361 /* could be made table driven or similar?... */
1362 while ((this_opt = strsep(&options, ",")) != NULL) {
1363 ret = parse_opt(dev, this_opt);
1370 static char g_options[256] __devinitdata = "";
1372 #ifndef CONFIG_MODULES
1373 static int __devinit pxafb_setup_options(void)
1375 char *options = NULL;
1377 if (fb_get_options("pxafb", &options))
1381 strlcpy(g_options, options, sizeof(g_options));
1386 #define pxafb_setup_options() (0)
1388 module_param_string(options, g_options, sizeof(g_options), 0);
1389 MODULE_PARM_DESC(options, "LCD parameters (see Documentation/fb/pxafb.txt)");
1393 #define pxafb_parse_options(...) (0)
1394 #define pxafb_setup_options() (0)
1397 static int __init pxafb_probe(struct platform_device *dev)
1399 struct pxafb_info *fbi;
1400 struct pxafb_mach_info *inf;
1404 dev_dbg(&dev->dev, "pxafb_probe\n");
1406 inf = dev->dev.platform_data;
1412 ret = pxafb_parse_options(&dev->dev, g_options);
1417 /* Check for various illegal bit-combinations. Currently only
1418 * a warning is given. */
1420 if (inf->lccr0 & LCCR0_INVALID_CONFIG_MASK)
1421 dev_warn(&dev->dev, "machine LCCR0 setting contains "
1422 "illegal bits: %08x\n",
1423 inf->lccr0 & LCCR0_INVALID_CONFIG_MASK);
1424 if (inf->lccr3 & LCCR3_INVALID_CONFIG_MASK)
1425 dev_warn(&dev->dev, "machine LCCR3 setting contains "
1426 "illegal bits: %08x\n",
1427 inf->lccr3 & LCCR3_INVALID_CONFIG_MASK);
1428 if (inf->lccr0 & LCCR0_DPD &&
1429 ((inf->lccr0 & LCCR0_PAS) != LCCR0_Pas ||
1430 (inf->lccr0 & LCCR0_SDS) != LCCR0_Sngl ||
1431 (inf->lccr0 & LCCR0_CMS) != LCCR0_Mono))
1432 dev_warn(&dev->dev, "Double Pixel Data (DPD) mode is "
1433 "only valid in passive mono"
1434 " single panel mode\n");
1435 if ((inf->lccr0 & LCCR0_PAS) == LCCR0_Act &&
1436 (inf->lccr0 & LCCR0_SDS) == LCCR0_Dual)
1437 dev_warn(&dev->dev, "Dual panel only valid in passive mode\n");
1438 if ((inf->lccr0 & LCCR0_PAS) == LCCR0_Pas &&
1439 (inf->modes->upper_margin || inf->modes->lower_margin))
1440 dev_warn(&dev->dev, "Upper and lower margins must be 0 in "
1444 dev_dbg(&dev->dev, "got a %dx%dx%d LCD\n",
1448 if (inf->modes->xres == 0 ||
1449 inf->modes->yres == 0 ||
1450 inf->modes->bpp == 0) {
1451 dev_err(&dev->dev, "Invalid resolution or bit depth\n");
1455 pxafb_backlight_power = inf->pxafb_backlight_power;
1456 pxafb_lcd_power = inf->pxafb_lcd_power;
1457 fbi = pxafb_init_fbinfo(&dev->dev);
1459 /* only reason for pxafb_init_fbinfo to fail is kmalloc */
1460 dev_err(&dev->dev, "Failed to initialize framebuffer device\n");
1465 r = platform_get_resource(dev, IORESOURCE_MEM, 0);
1467 dev_err(&dev->dev, "no I/O memory resource defined\n");
1472 r = request_mem_region(r->start, r->end - r->start + 1, dev->name);
1474 dev_err(&dev->dev, "failed to request I/O memory\n");
1479 fbi->mmio_base = ioremap(r->start, r->end - r->start + 1);
1480 if (fbi->mmio_base == NULL) {
1481 dev_err(&dev->dev, "failed to map I/O memory\n");
1483 goto failed_free_res;
1486 /* Initialize video memory */
1487 ret = pxafb_map_video_memory(fbi);
1489 dev_err(&dev->dev, "Failed to allocate video RAM: %d\n", ret);
1491 goto failed_free_io;
1494 irq = platform_get_irq(dev, 0);
1496 dev_err(&dev->dev, "no IRQ defined\n");
1498 goto failed_free_mem;
1501 ret = request_irq(irq, pxafb_handle_irq, IRQF_DISABLED, "LCD", fbi);
1503 dev_err(&dev->dev, "request_irq failed: %d\n", ret);
1505 goto failed_free_mem;
1509 * This makes sure that our colour bitfield
1510 * descriptors are correctly initialised.
1512 pxafb_check_var(&fbi->fb.var, &fbi->fb);
1513 pxafb_set_par(&fbi->fb);
1515 platform_set_drvdata(dev, fbi);
1517 ret = register_framebuffer(&fbi->fb);
1520 "Failed to register framebuffer device: %d\n", ret);
1521 goto failed_free_irq;
1524 #ifdef CONFIG_CPU_FREQ
1525 fbi->freq_transition.notifier_call = pxafb_freq_transition;
1526 fbi->freq_policy.notifier_call = pxafb_freq_policy;
1527 cpufreq_register_notifier(&fbi->freq_transition,
1528 CPUFREQ_TRANSITION_NOTIFIER);
1529 cpufreq_register_notifier(&fbi->freq_policy,
1530 CPUFREQ_POLICY_NOTIFIER);
1534 * Ok, now enable the LCD controller
1536 set_ctrlr_state(fbi, C_ENABLE);
1543 release_mem_region(r->start, r->end - r->start + 1);
1545 iounmap(fbi->mmio_base);
1547 dma_free_writecombine(&dev->dev, fbi->map_size,
1548 fbi->map_cpu, fbi->map_dma);
1550 platform_set_drvdata(dev, NULL);
1555 static struct platform_driver pxafb_driver = {
1556 .probe = pxafb_probe,
1557 .suspend = pxafb_suspend,
1558 .resume = pxafb_resume,
1560 .name = "pxa2xx-fb",
1564 static int __devinit pxafb_init(void)
1566 if (pxafb_setup_options())
1569 return platform_driver_register(&pxafb_driver);
1572 module_init(pxafb_init);
1574 MODULE_DESCRIPTION("loadable framebuffer driver for PXA");
1575 MODULE_LICENSE("GPL");