2 * linux/drivers/video/pxafb.c
4 * Copyright (C) 1999 Eric A. Thomas.
5 * Copyright (C) 2004 Jean-Frederic Clere.
6 * Copyright (C) 2004 Ian Campbell.
7 * Copyright (C) 2004 Jeff Lackey.
8 * Based on sa1100fb.c Copyright (C) 1999 Eric A. Thomas
10 * Based on acornfb.c Copyright (C) Russell King.
12 * This file is subject to the terms and conditions of the GNU General Public
13 * License. See the file COPYING in the main directory of this archive for
16 * Intel PXA250/210 LCD Controller Frame Buffer Driver
18 * Please direct your questions and comments on this driver to the following
21 * linux-arm-kernel@lists.arm.linux.org.uk
25 #include <linux/module.h>
26 #include <linux/moduleparam.h>
27 #include <linux/kernel.h>
28 #include <linux/sched.h>
29 #include <linux/errno.h>
30 #include <linux/string.h>
31 #include <linux/interrupt.h>
32 #include <linux/slab.h>
35 #include <linux/delay.h>
36 #include <linux/init.h>
37 #include <linux/ioport.h>
38 #include <linux/cpufreq.h>
39 #include <linux/platform_device.h>
40 #include <linux/dma-mapping.h>
41 #include <linux/clk.h>
42 #include <linux/err.h>
43 #include <linux/completion.h>
44 #include <linux/mutex.h>
45 #include <linux/kthread.h>
46 #include <linux/freezer.h>
48 #include <mach/hardware.h>
51 #include <asm/div64.h>
52 #include <mach/pxa-regs.h>
53 #include <mach/bitfield.h>
54 #include <mach/pxafb.h>
57 * Complain if VAR is out of range.
63 /* Bits which should not be set in machine configuration structures */
64 #define LCCR0_INVALID_CONFIG_MASK (LCCR0_OUM | LCCR0_BM | LCCR0_QDM |\
65 LCCR0_DIS | LCCR0_EFM | LCCR0_IUM |\
66 LCCR0_SFM | LCCR0_LDM | LCCR0_ENB)
68 #define LCCR3_INVALID_CONFIG_MASK (LCCR3_HSP | LCCR3_VSP |\
69 LCCR3_PCD | LCCR3_BPP)
71 static int pxafb_activate_var(struct fb_var_screeninfo *var,
73 static void set_ctrlr_state(struct pxafb_info *fbi, u_int state);
75 static unsigned long video_mem_size = 0;
77 static inline unsigned long
78 lcd_readl(struct pxafb_info *fbi, unsigned int off)
80 return __raw_readl(fbi->mmio_base + off);
84 lcd_writel(struct pxafb_info *fbi, unsigned int off, unsigned long val)
86 __raw_writel(val, fbi->mmio_base + off);
89 static inline void pxafb_schedule_work(struct pxafb_info *fbi, u_int state)
93 local_irq_save(flags);
95 * We need to handle two requests being made at the same time.
96 * There are two important cases:
97 * 1. When we are changing VT (C_REENABLE) while unblanking
98 * (C_ENABLE) We must perform the unblanking, which will
99 * do our REENABLE for us.
100 * 2. When we are blanking, but immediately unblank before
101 * we have blanked. We do the "REENABLE" thing here as
102 * well, just to be sure.
104 if (fbi->task_state == C_ENABLE && state == C_REENABLE)
106 if (fbi->task_state == C_DISABLE && state == C_ENABLE)
109 if (state != (u_int)-1) {
110 fbi->task_state = state;
111 schedule_work(&fbi->task);
113 local_irq_restore(flags);
116 static inline u_int chan_to_field(u_int chan, struct fb_bitfield *bf)
119 chan >>= 16 - bf->length;
120 return chan << bf->offset;
124 pxafb_setpalettereg(u_int regno, u_int red, u_int green, u_int blue,
125 u_int trans, struct fb_info *info)
127 struct pxafb_info *fbi = (struct pxafb_info *)info;
130 if (regno >= fbi->palette_size)
133 if (fbi->fb.var.grayscale) {
134 fbi->palette_cpu[regno] = ((blue >> 8) & 0x00ff);
138 switch (fbi->lccr4 & LCCR4_PAL_FOR_MASK) {
139 case LCCR4_PAL_FOR_0:
140 val = ((red >> 0) & 0xf800);
141 val |= ((green >> 5) & 0x07e0);
142 val |= ((blue >> 11) & 0x001f);
143 fbi->palette_cpu[regno] = val;
145 case LCCR4_PAL_FOR_1:
146 val = ((red << 8) & 0x00f80000);
147 val |= ((green >> 0) & 0x0000fc00);
148 val |= ((blue >> 8) & 0x000000f8);
149 ((u32 *)(fbi->palette_cpu))[regno] = val;
151 case LCCR4_PAL_FOR_2:
152 val = ((red << 8) & 0x00fc0000);
153 val |= ((green >> 0) & 0x0000fc00);
154 val |= ((blue >> 8) & 0x000000fc);
155 ((u32 *)(fbi->palette_cpu))[regno] = val;
163 pxafb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
164 u_int trans, struct fb_info *info)
166 struct pxafb_info *fbi = (struct pxafb_info *)info;
171 * If inverse mode was selected, invert all the colours
172 * rather than the register number. The register number
173 * is what you poke into the framebuffer to produce the
174 * colour you requested.
176 if (fbi->cmap_inverse) {
178 green = 0xffff - green;
179 blue = 0xffff - blue;
183 * If greyscale is true, then we convert the RGB value
184 * to greyscale no matter what visual we are using.
186 if (fbi->fb.var.grayscale)
187 red = green = blue = (19595 * red + 38470 * green +
190 switch (fbi->fb.fix.visual) {
191 case FB_VISUAL_TRUECOLOR:
193 * 16-bit True Colour. We encode the RGB value
194 * according to the RGB bitfield information.
197 u32 *pal = fbi->fb.pseudo_palette;
199 val = chan_to_field(red, &fbi->fb.var.red);
200 val |= chan_to_field(green, &fbi->fb.var.green);
201 val |= chan_to_field(blue, &fbi->fb.var.blue);
208 case FB_VISUAL_STATIC_PSEUDOCOLOR:
209 case FB_VISUAL_PSEUDOCOLOR:
210 ret = pxafb_setpalettereg(regno, red, green, blue, trans, info);
218 * pxafb_bpp_to_lccr3():
219 * Convert a bits per pixel value to the correct bit pattern for LCCR3
221 static int pxafb_bpp_to_lccr3(struct fb_var_screeninfo *var)
224 switch (var->bits_per_pixel) {
225 case 1: ret = LCCR3_1BPP; break;
226 case 2: ret = LCCR3_2BPP; break;
227 case 4: ret = LCCR3_4BPP; break;
228 case 8: ret = LCCR3_8BPP; break;
229 case 16: ret = LCCR3_16BPP; break;
231 switch (var->red.length + var->green.length +
232 var->blue.length + var->transp.length) {
233 case 18: ret = LCCR3_18BPP_P | LCCR3_PDFOR_3; break;
234 case 19: ret = LCCR3_19BPP_P; break;
238 switch (var->red.length + var->green.length +
239 var->blue.length + var->transp.length) {
240 case 18: ret = LCCR3_18BPP | LCCR3_PDFOR_3; break;
241 case 19: ret = LCCR3_19BPP; break;
242 case 24: ret = LCCR3_24BPP | LCCR3_PDFOR_3; break;
243 case 25: ret = LCCR3_25BPP; break;
250 #ifdef CONFIG_CPU_FREQ
252 * pxafb_display_dma_period()
253 * Calculate the minimum period (in picoseconds) between two DMA
254 * requests for the LCD controller. If we hit this, it means we're
255 * doing nothing but LCD DMA.
257 static unsigned int pxafb_display_dma_period(struct fb_var_screeninfo *var)
260 * Period = pixclock * bits_per_byte * bytes_per_transfer
261 * / memory_bits_per_pixel;
263 return var->pixclock * 8 * 16 / var->bits_per_pixel;
268 * Select the smallest mode that allows the desired resolution to be
269 * displayed. If desired parameters can be rounded up.
271 static struct pxafb_mode_info *pxafb_getmode(struct pxafb_mach_info *mach,
272 struct fb_var_screeninfo *var)
274 struct pxafb_mode_info *mode = NULL;
275 struct pxafb_mode_info *modelist = mach->modes;
276 unsigned int best_x = 0xffffffff, best_y = 0xffffffff;
279 for (i = 0; i < mach->num_modes; i++) {
280 if (modelist[i].xres >= var->xres &&
281 modelist[i].yres >= var->yres &&
282 modelist[i].xres < best_x &&
283 modelist[i].yres < best_y &&
284 modelist[i].bpp >= var->bits_per_pixel) {
285 best_x = modelist[i].xres;
286 best_y = modelist[i].yres;
294 static void pxafb_setmode(struct fb_var_screeninfo *var,
295 struct pxafb_mode_info *mode)
297 var->xres = mode->xres;
298 var->yres = mode->yres;
299 var->bits_per_pixel = mode->bpp;
300 var->pixclock = mode->pixclock;
301 var->hsync_len = mode->hsync_len;
302 var->left_margin = mode->left_margin;
303 var->right_margin = mode->right_margin;
304 var->vsync_len = mode->vsync_len;
305 var->upper_margin = mode->upper_margin;
306 var->lower_margin = mode->lower_margin;
307 var->sync = mode->sync;
308 var->grayscale = mode->cmap_greyscale;
309 var->xres_virtual = var->xres;
310 var->yres_virtual = var->yres;
315 * Get the video params out of 'var'. If a value doesn't fit, round it up,
316 * if it's too big, return -EINVAL.
318 * Round up in the following order: bits_per_pixel, xres,
319 * yres, xres_virtual, yres_virtual, xoffset, yoffset, grayscale,
320 * bitfields, horizontal timing, vertical timing.
322 static int pxafb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
324 struct pxafb_info *fbi = (struct pxafb_info *)info;
325 struct pxafb_mach_info *inf = fbi->dev->platform_data;
327 if (var->xres < MIN_XRES)
328 var->xres = MIN_XRES;
329 if (var->yres < MIN_YRES)
330 var->yres = MIN_YRES;
332 if (inf->fixed_modes) {
333 struct pxafb_mode_info *mode;
335 mode = pxafb_getmode(inf, var);
338 pxafb_setmode(var, mode);
340 if (var->xres > inf->modes->xres)
342 if (var->yres > inf->modes->yres)
344 if (var->bits_per_pixel > inf->modes->bpp)
349 max(var->xres_virtual, var->xres);
351 max(var->yres_virtual, var->yres);
354 * Setup the RGB parameters for this display.
356 * The pixel packing format is described on page 7-11 of the
357 * PXA2XX Developer's Manual.
359 if (var->bits_per_pixel == 16) {
360 var->red.offset = 11; var->red.length = 5;
361 var->green.offset = 5; var->green.length = 6;
362 var->blue.offset = 0; var->blue.length = 5;
363 var->transp.offset = var->transp.length = 0;
364 } else if (var->bits_per_pixel > 16) {
365 struct pxafb_mode_info *mode;
367 mode = pxafb_getmode(inf, var);
371 switch (mode->depth) {
372 case 18: /* RGB666 */
373 var->transp.offset = var->transp.length = 0;
374 var->red.offset = 12; var->red.length = 6;
375 var->green.offset = 6; var->green.length = 6;
376 var->blue.offset = 0; var->blue.length = 6;
378 case 19: /* RGBT666 */
379 var->transp.offset = 18; var->transp.length = 1;
380 var->red.offset = 12; var->red.length = 6;
381 var->green.offset = 6; var->green.length = 6;
382 var->blue.offset = 0; var->blue.length = 6;
384 case 24: /* RGB888 */
385 var->transp.offset = var->transp.length = 0;
386 var->red.offset = 16; var->red.length = 8;
387 var->green.offset = 8; var->green.length = 8;
388 var->blue.offset = 0; var->blue.length = 8;
390 case 25: /* RGBT888 */
391 var->transp.offset = 24; var->transp.length = 1;
392 var->red.offset = 16; var->red.length = 8;
393 var->green.offset = 8; var->green.length = 8;
394 var->blue.offset = 0; var->blue.length = 8;
400 var->red.offset = var->green.offset = 0;
401 var->blue.offset = var->transp.offset = 0;
403 var->green.length = 8;
404 var->blue.length = 8;
405 var->transp.length = 0;
408 #ifdef CONFIG_CPU_FREQ
409 pr_debug("pxafb: dma period = %d ps\n",
410 pxafb_display_dma_period(var));
416 static inline void pxafb_set_truecolor(u_int is_true_color)
418 /* do your machine-specific setup if needed */
423 * Set the user defined part of the display for the specified console
425 static int pxafb_set_par(struct fb_info *info)
427 struct pxafb_info *fbi = (struct pxafb_info *)info;
428 struct fb_var_screeninfo *var = &info->var;
430 if (var->bits_per_pixel >= 16)
431 fbi->fb.fix.visual = FB_VISUAL_TRUECOLOR;
432 else if (!fbi->cmap_static)
433 fbi->fb.fix.visual = FB_VISUAL_PSEUDOCOLOR;
436 * Some people have weird ideas about wanting static
437 * pseudocolor maps. I suspect their user space
438 * applications are broken.
440 fbi->fb.fix.visual = FB_VISUAL_STATIC_PSEUDOCOLOR;
443 fbi->fb.fix.line_length = var->xres_virtual *
444 var->bits_per_pixel / 8;
445 if (var->bits_per_pixel >= 16)
446 fbi->palette_size = 0;
448 fbi->palette_size = var->bits_per_pixel == 1 ?
449 4 : 1 << var->bits_per_pixel;
451 fbi->palette_cpu = (u16 *)&fbi->dma_buff->palette[0];
454 * Set (any) board control register to handle new color depth
456 pxafb_set_truecolor(fbi->fb.fix.visual == FB_VISUAL_TRUECOLOR);
458 if (fbi->fb.var.bits_per_pixel >= 16)
459 fb_dealloc_cmap(&fbi->fb.cmap);
461 fb_alloc_cmap(&fbi->fb.cmap, 1<<fbi->fb.var.bits_per_pixel, 0);
463 pxafb_activate_var(var, fbi);
470 * Blank the display by setting all palette values to zero. Note, the
471 * 16 bpp mode does not really use the palette, so this will not
472 * blank the display in all modes.
474 static int pxafb_blank(int blank, struct fb_info *info)
476 struct pxafb_info *fbi = (struct pxafb_info *)info;
480 case FB_BLANK_POWERDOWN:
481 case FB_BLANK_VSYNC_SUSPEND:
482 case FB_BLANK_HSYNC_SUSPEND:
483 case FB_BLANK_NORMAL:
484 if (fbi->fb.fix.visual == FB_VISUAL_PSEUDOCOLOR ||
485 fbi->fb.fix.visual == FB_VISUAL_STATIC_PSEUDOCOLOR)
486 for (i = 0; i < fbi->palette_size; i++)
487 pxafb_setpalettereg(i, 0, 0, 0, 0, info);
489 pxafb_schedule_work(fbi, C_DISABLE);
490 /* TODO if (pxafb_blank_helper) pxafb_blank_helper(blank); */
493 case FB_BLANK_UNBLANK:
494 /* TODO if (pxafb_blank_helper) pxafb_blank_helper(blank); */
495 if (fbi->fb.fix.visual == FB_VISUAL_PSEUDOCOLOR ||
496 fbi->fb.fix.visual == FB_VISUAL_STATIC_PSEUDOCOLOR)
497 fb_set_cmap(&fbi->fb.cmap, info);
498 pxafb_schedule_work(fbi, C_ENABLE);
503 static struct fb_ops pxafb_ops = {
504 .owner = THIS_MODULE,
505 .fb_check_var = pxafb_check_var,
506 .fb_set_par = pxafb_set_par,
507 .fb_setcolreg = pxafb_setcolreg,
508 .fb_fillrect = cfb_fillrect,
509 .fb_copyarea = cfb_copyarea,
510 .fb_imageblit = cfb_imageblit,
511 .fb_blank = pxafb_blank,
515 * Calculate the PCD value from the clock rate (in picoseconds).
516 * We take account of the PPCR clock setting.
517 * From PXA Developer's Manual:
528 * LCLK = LCD/Memory Clock
531 * PixelClock here is in Hz while the pixclock argument given is the
532 * period in picoseconds. Hence PixelClock = 1 / ( pixclock * 10^-12 )
534 * The function get_lclk_frequency_10khz returns LCLK in units of
535 * 10khz. Calling the result of this function lclk gives us the
538 * PCD = (lclk * 10^4 ) * ( pixclock * 10^-12 )
539 * -------------------------------------- - 1
542 * Factoring the 10^4 and 10^-12 out gives 10^-8 == 1 / 100000000 as used below.
544 static inline unsigned int get_pcd(struct pxafb_info *fbi,
545 unsigned int pixclock)
547 unsigned long long pcd;
549 /* FIXME: Need to take into account Double Pixel Clock mode
550 * (DPC) bit? or perhaps set it based on the various clock
552 pcd = (unsigned long long)(clk_get_rate(fbi->clk) / 10000);
554 do_div(pcd, 100000000 * 2);
555 /* no need for this, since we should subtract 1 anyway. they cancel */
556 /* pcd += 1; */ /* make up for integer math truncations */
557 return (unsigned int)pcd;
561 * Some touchscreens need hsync information from the video driver to
562 * function correctly. We export it here. Note that 'hsync_time' and
563 * the value returned from pxafb_get_hsync_time() is the *reciprocal*
564 * of the hsync period in seconds.
566 static inline void set_hsync_time(struct pxafb_info *fbi, unsigned int pcd)
570 if ((pcd == 0) || (fbi->fb.var.hsync_len == 0)) {
575 htime = clk_get_rate(fbi->clk) / (pcd * fbi->fb.var.hsync_len);
577 fbi->hsync_time = htime;
580 unsigned long pxafb_get_hsync_time(struct device *dev)
582 struct pxafb_info *fbi = dev_get_drvdata(dev);
584 /* If display is blanked/suspended, hsync isn't active */
585 if (!fbi || (fbi->state != C_ENABLE))
588 return fbi->hsync_time;
590 EXPORT_SYMBOL(pxafb_get_hsync_time);
592 static int setup_frame_dma(struct pxafb_info *fbi, int dma, int pal,
593 unsigned int offset, size_t size)
595 struct pxafb_dma_descriptor *dma_desc, *pal_desc;
596 unsigned int dma_desc_off, pal_desc_off;
598 if (dma < 0 || dma >= DMA_MAX)
601 dma_desc = &fbi->dma_buff->dma_desc[dma];
602 dma_desc_off = offsetof(struct pxafb_dma_buff, dma_desc[dma]);
604 dma_desc->fsadr = fbi->video_mem_phys + offset;
606 dma_desc->ldcmd = size;
608 if (pal < 0 || pal >= PAL_MAX) {
609 dma_desc->fdadr = fbi->dma_buff_phys + dma_desc_off;
610 fbi->fdadr[dma] = fbi->dma_buff_phys + dma_desc_off;
612 pal_desc = &fbi->dma_buff->pal_desc[pal];
613 pal_desc_off = offsetof(struct pxafb_dma_buff, pal_desc[pal]);
615 pal_desc->fsadr = fbi->dma_buff_phys + pal * PALETTE_SIZE;
618 if ((fbi->lccr4 & LCCR4_PAL_FOR_MASK) == LCCR4_PAL_FOR_0)
619 pal_desc->ldcmd = fbi->palette_size * sizeof(u16);
621 pal_desc->ldcmd = fbi->palette_size * sizeof(u32);
623 pal_desc->ldcmd |= LDCMD_PAL;
625 /* flip back and forth between palette and frame buffer */
626 pal_desc->fdadr = fbi->dma_buff_phys + dma_desc_off;
627 dma_desc->fdadr = fbi->dma_buff_phys + pal_desc_off;
628 fbi->fdadr[dma] = fbi->dma_buff_phys + dma_desc_off;
634 #ifdef CONFIG_FB_PXA_SMARTPANEL
635 static int setup_smart_dma(struct pxafb_info *fbi)
637 struct pxafb_dma_descriptor *dma_desc;
638 unsigned long dma_desc_off, cmd_buff_off;
640 dma_desc = &fbi->dma_buff->dma_desc[DMA_CMD];
641 dma_desc_off = offsetof(struct pxafb_dma_buff, dma_desc[DMA_CMD]);
642 cmd_buff_off = offsetof(struct pxafb_dma_buff, cmd_buff);
644 dma_desc->fdadr = fbi->dma_buff_phys + dma_desc_off;
645 dma_desc->fsadr = fbi->dma_buff_phys + cmd_buff_off;
647 dma_desc->ldcmd = fbi->n_smart_cmds * sizeof(uint16_t);
649 fbi->fdadr[DMA_CMD] = dma_desc->fdadr;
653 int pxafb_smart_flush(struct fb_info *info)
655 struct pxafb_info *fbi = container_of(info, struct pxafb_info, fb);
659 /* disable controller until all registers are set up */
660 lcd_writel(fbi, LCCR0, fbi->reg_lccr0 & ~LCCR0_ENB);
662 /* 1. make it an even number of commands to align on 32-bit boundary
663 * 2. add the interrupt command to the end of the chain so we can
664 * keep track of the end of the transfer
667 while (fbi->n_smart_cmds & 1)
668 fbi->smart_cmds[fbi->n_smart_cmds++] = SMART_CMD_NOOP;
670 fbi->smart_cmds[fbi->n_smart_cmds++] = SMART_CMD_INTERRUPT;
671 fbi->smart_cmds[fbi->n_smart_cmds++] = SMART_CMD_WAIT_FOR_VSYNC;
672 setup_smart_dma(fbi);
674 /* continue to execute next command */
675 prsr = lcd_readl(fbi, PRSR) | PRSR_ST_OK | PRSR_CON_NT;
676 lcd_writel(fbi, PRSR, prsr);
678 /* stop the processor in case it executed "wait for sync" cmd */
679 lcd_writel(fbi, CMDCR, 0x0001);
681 /* don't send interrupts for fifo underruns on channel 6 */
682 lcd_writel(fbi, LCCR5, LCCR5_IUM(6));
684 lcd_writel(fbi, LCCR1, fbi->reg_lccr1);
685 lcd_writel(fbi, LCCR2, fbi->reg_lccr2);
686 lcd_writel(fbi, LCCR3, fbi->reg_lccr3);
687 lcd_writel(fbi, FDADR0, fbi->fdadr[0]);
688 lcd_writel(fbi, FDADR6, fbi->fdadr[6]);
691 lcd_writel(fbi, LCCR0, fbi->reg_lccr0 | LCCR0_ENB);
693 if (wait_for_completion_timeout(&fbi->command_done, HZ/2) == 0) {
694 pr_warning("%s: timeout waiting for command done\n",
700 prsr = lcd_readl(fbi, PRSR) & ~(PRSR_ST_OK | PRSR_CON_NT);
701 lcd_writel(fbi, PRSR, prsr);
702 lcd_writel(fbi, LCCR0, fbi->reg_lccr0 & ~LCCR0_ENB);
703 lcd_writel(fbi, FDADR6, 0);
704 fbi->n_smart_cmds = 0;
708 int pxafb_smart_queue(struct fb_info *info, uint16_t *cmds, int n_cmds)
711 struct pxafb_info *fbi = container_of(info, struct pxafb_info, fb);
713 for (i = 0; i < n_cmds; i++, cmds++) {
714 /* if it is a software delay, flush and delay */
715 if ((*cmds & 0xff00) == SMART_CMD_DELAY) {
716 pxafb_smart_flush(info);
717 mdelay(*cmds & 0xff);
721 /* leave 2 commands for INTERRUPT and WAIT_FOR_SYNC */
722 if (fbi->n_smart_cmds == CMD_BUFF_SIZE - 8)
723 pxafb_smart_flush(info);
725 fbi->smart_cmds[fbi->n_smart_cmds++] = *cmds;
731 static unsigned int __smart_timing(unsigned time_ns, unsigned long lcd_clk)
733 unsigned int t = (time_ns * (lcd_clk / 1000000) / 1000);
734 return (t == 0) ? 1 : t;
737 static void setup_smart_timing(struct pxafb_info *fbi,
738 struct fb_var_screeninfo *var)
740 struct pxafb_mach_info *inf = fbi->dev->platform_data;
741 struct pxafb_mode_info *mode = &inf->modes[0];
742 unsigned long lclk = clk_get_rate(fbi->clk);
743 unsigned t1, t2, t3, t4;
745 t1 = max(mode->a0csrd_set_hld, mode->a0cswr_set_hld);
746 t2 = max(mode->rd_pulse_width, mode->wr_pulse_width);
747 t3 = mode->op_hold_time;
748 t4 = mode->cmd_inh_time;
751 LCCR1_DisWdth(var->xres) |
752 LCCR1_BegLnDel(__smart_timing(t1, lclk)) |
753 LCCR1_EndLnDel(__smart_timing(t2, lclk)) |
754 LCCR1_HorSnchWdth(__smart_timing(t3, lclk));
756 fbi->reg_lccr2 = LCCR2_DisHght(var->yres);
757 fbi->reg_lccr3 = fbi->lccr3 | LCCR3_PixClkDiv(__smart_timing(t4, lclk));
758 fbi->reg_lccr3 |= (var->sync & FB_SYNC_HOR_HIGH_ACT) ? LCCR3_HSP : 0;
759 fbi->reg_lccr3 |= (var->sync & FB_SYNC_VERT_HIGH_ACT) ? LCCR3_VSP : 0;
761 /* FIXME: make this configurable */
765 static int pxafb_smart_thread(void *arg)
767 struct pxafb_info *fbi = arg;
768 struct pxafb_mach_info *inf = fbi->dev->platform_data;
770 if (!fbi || !inf->smart_update) {
771 pr_err("%s: not properly initialized, thread terminated\n",
776 pr_debug("%s(): task starting\n", __func__);
779 while (!kthread_should_stop()) {
784 mutex_lock(&fbi->ctrlr_lock);
786 if (fbi->state == C_ENABLE) {
787 inf->smart_update(&fbi->fb);
788 complete(&fbi->refresh_done);
791 mutex_unlock(&fbi->ctrlr_lock);
793 set_current_state(TASK_INTERRUPTIBLE);
794 schedule_timeout(30 * HZ / 1000);
797 pr_debug("%s(): task ending\n", __func__);
801 static int pxafb_smart_init(struct pxafb_info *fbi)
803 if (!(fbi->lccr0 & LCCR0_LCDT))
806 fbi->smart_cmds = (uint16_t *) fbi->dma_buff->cmd_buff;
807 fbi->n_smart_cmds = 0;
809 init_completion(&fbi->command_done);
810 init_completion(&fbi->refresh_done);
812 fbi->smart_thread = kthread_run(pxafb_smart_thread, fbi,
814 if (IS_ERR(fbi->smart_thread)) {
815 pr_err("%s: unable to create kernel thread\n", __func__);
816 return PTR_ERR(fbi->smart_thread);
822 int pxafb_smart_queue(struct fb_info *info, uint16_t *cmds, int n_cmds)
827 int pxafb_smart_flush(struct fb_info *info)
832 static inline int pxafb_smart_init(struct pxafb_info *fbi) { return 0; }
833 #endif /* CONFIG_FB_PXA_SMARTPANEL */
835 static void setup_parallel_timing(struct pxafb_info *fbi,
836 struct fb_var_screeninfo *var)
838 unsigned int lines_per_panel, pcd = get_pcd(fbi, var->pixclock);
841 LCCR1_DisWdth(var->xres) +
842 LCCR1_HorSnchWdth(var->hsync_len) +
843 LCCR1_BegLnDel(var->left_margin) +
844 LCCR1_EndLnDel(var->right_margin);
847 * If we have a dual scan LCD, we need to halve
848 * the YRES parameter.
850 lines_per_panel = var->yres;
851 if ((fbi->lccr0 & LCCR0_SDS) == LCCR0_Dual)
852 lines_per_panel /= 2;
855 LCCR2_DisHght(lines_per_panel) +
856 LCCR2_VrtSnchWdth(var->vsync_len) +
857 LCCR2_BegFrmDel(var->upper_margin) +
858 LCCR2_EndFrmDel(var->lower_margin);
860 fbi->reg_lccr3 = fbi->lccr3 |
861 (var->sync & FB_SYNC_HOR_HIGH_ACT ?
862 LCCR3_HorSnchH : LCCR3_HorSnchL) |
863 (var->sync & FB_SYNC_VERT_HIGH_ACT ?
864 LCCR3_VrtSnchH : LCCR3_VrtSnchL);
867 fbi->reg_lccr3 |= LCCR3_PixClkDiv(pcd);
868 set_hsync_time(fbi, pcd);
873 * pxafb_activate_var():
874 * Configures LCD Controller based on entries in var parameter.
875 * Settings are only written to the controller if changes were made.
877 static int pxafb_activate_var(struct fb_var_screeninfo *var,
878 struct pxafb_info *fbi)
884 if (!(fbi->lccr0 & LCCR0_LCDT)) {
885 if (var->xres < 16 || var->xres > 1024)
886 printk(KERN_ERR "%s: invalid xres %d\n",
887 fbi->fb.fix.id, var->xres);
888 switch (var->bits_per_pixel) {
898 printk(KERN_ERR "%s: invalid bit depth %d\n",
899 fbi->fb.fix.id, var->bits_per_pixel);
903 if (var->hsync_len < 1 || var->hsync_len > 64)
904 printk(KERN_ERR "%s: invalid hsync_len %d\n",
905 fbi->fb.fix.id, var->hsync_len);
906 if (var->left_margin < 1 || var->left_margin > 255)
907 printk(KERN_ERR "%s: invalid left_margin %d\n",
908 fbi->fb.fix.id, var->left_margin);
909 if (var->right_margin < 1 || var->right_margin > 255)
910 printk(KERN_ERR "%s: invalid right_margin %d\n",
911 fbi->fb.fix.id, var->right_margin);
912 if (var->yres < 1 || var->yres > 1024)
913 printk(KERN_ERR "%s: invalid yres %d\n",
914 fbi->fb.fix.id, var->yres);
915 if (var->vsync_len < 1 || var->vsync_len > 64)
916 printk(KERN_ERR "%s: invalid vsync_len %d\n",
917 fbi->fb.fix.id, var->vsync_len);
918 if (var->upper_margin < 0 || var->upper_margin > 255)
919 printk(KERN_ERR "%s: invalid upper_margin %d\n",
920 fbi->fb.fix.id, var->upper_margin);
921 if (var->lower_margin < 0 || var->lower_margin > 255)
922 printk(KERN_ERR "%s: invalid lower_margin %d\n",
923 fbi->fb.fix.id, var->lower_margin);
926 /* Update shadow copy atomically */
927 local_irq_save(flags);
929 #ifdef CONFIG_FB_PXA_SMARTPANEL
930 if (fbi->lccr0 & LCCR0_LCDT)
931 setup_smart_timing(fbi, var);
934 setup_parallel_timing(fbi, var);
936 fbi->reg_lccr0 = fbi->lccr0 |
937 (LCCR0_LDM | LCCR0_SFM | LCCR0_IUM | LCCR0_EFM |
938 LCCR0_QDM | LCCR0_BM | LCCR0_OUM);
940 fbi->reg_lccr3 |= pxafb_bpp_to_lccr3(var);
942 nbytes = var->yres * fbi->fb.fix.line_length;
944 if ((fbi->lccr0 & LCCR0_SDS) == LCCR0_Dual) {
946 setup_frame_dma(fbi, DMA_LOWER, PAL_NONE, nbytes, nbytes);
949 if ((var->bits_per_pixel >= 16) || (fbi->lccr0 & LCCR0_LCDT))
950 setup_frame_dma(fbi, DMA_BASE, PAL_NONE, 0, nbytes);
952 setup_frame_dma(fbi, DMA_BASE, PAL_BASE, 0, nbytes);
954 fbi->reg_lccr4 = lcd_readl(fbi, LCCR4) & ~LCCR4_PAL_FOR_MASK;
955 fbi->reg_lccr4 |= (fbi->lccr4 & LCCR4_PAL_FOR_MASK);
956 local_irq_restore(flags);
959 * Only update the registers if the controller is enabled
960 * and something has changed.
962 if ((lcd_readl(fbi, LCCR0) != fbi->reg_lccr0) ||
963 (lcd_readl(fbi, LCCR1) != fbi->reg_lccr1) ||
964 (lcd_readl(fbi, LCCR2) != fbi->reg_lccr2) ||
965 (lcd_readl(fbi, LCCR3) != fbi->reg_lccr3) ||
966 (lcd_readl(fbi, FDADR0) != fbi->fdadr[0]) ||
967 (lcd_readl(fbi, FDADR1) != fbi->fdadr[1]))
968 pxafb_schedule_work(fbi, C_REENABLE);
974 * NOTE! The following functions are purely helpers for set_ctrlr_state.
975 * Do not call them directly; set_ctrlr_state does the correct serialisation
976 * to ensure that things happen in the right way 100% of time time.
979 static inline void __pxafb_backlight_power(struct pxafb_info *fbi, int on)
981 pr_debug("pxafb: backlight o%s\n", on ? "n" : "ff");
983 if (fbi->backlight_power)
984 fbi->backlight_power(on);
987 static inline void __pxafb_lcd_power(struct pxafb_info *fbi, int on)
989 pr_debug("pxafb: LCD power o%s\n", on ? "n" : "ff");
992 fbi->lcd_power(on, &fbi->fb.var);
995 static void pxafb_enable_controller(struct pxafb_info *fbi)
997 pr_debug("pxafb: Enabling LCD controller\n");
998 pr_debug("fdadr0 0x%08x\n", (unsigned int) fbi->fdadr[0]);
999 pr_debug("fdadr1 0x%08x\n", (unsigned int) fbi->fdadr[1]);
1000 pr_debug("reg_lccr0 0x%08x\n", (unsigned int) fbi->reg_lccr0);
1001 pr_debug("reg_lccr1 0x%08x\n", (unsigned int) fbi->reg_lccr1);
1002 pr_debug("reg_lccr2 0x%08x\n", (unsigned int) fbi->reg_lccr2);
1003 pr_debug("reg_lccr3 0x%08x\n", (unsigned int) fbi->reg_lccr3);
1005 /* enable LCD controller clock */
1006 clk_enable(fbi->clk);
1008 if (fbi->lccr0 & LCCR0_LCDT)
1011 /* Sequence from 11.7.10 */
1012 lcd_writel(fbi, LCCR3, fbi->reg_lccr3);
1013 lcd_writel(fbi, LCCR2, fbi->reg_lccr2);
1014 lcd_writel(fbi, LCCR1, fbi->reg_lccr1);
1015 lcd_writel(fbi, LCCR0, fbi->reg_lccr0 & ~LCCR0_ENB);
1017 lcd_writel(fbi, FDADR0, fbi->fdadr[0]);
1018 lcd_writel(fbi, FDADR1, fbi->fdadr[1]);
1019 lcd_writel(fbi, LCCR0, fbi->reg_lccr0 | LCCR0_ENB);
1022 static void pxafb_disable_controller(struct pxafb_info *fbi)
1026 #ifdef CONFIG_FB_PXA_SMARTPANEL
1027 if (fbi->lccr0 & LCCR0_LCDT) {
1028 wait_for_completion_timeout(&fbi->refresh_done,
1034 /* Clear LCD Status Register */
1035 lcd_writel(fbi, LCSR, 0xffffffff);
1037 lccr0 = lcd_readl(fbi, LCCR0) & ~LCCR0_LDM;
1038 lcd_writel(fbi, LCCR0, lccr0);
1039 lcd_writel(fbi, LCCR0, lccr0 | LCCR0_DIS);
1041 wait_for_completion_timeout(&fbi->disable_done, 200 * HZ / 1000);
1043 /* disable LCD controller clock */
1044 clk_disable(fbi->clk);
1048 * pxafb_handle_irq: Handle 'LCD DONE' interrupts.
1050 static irqreturn_t pxafb_handle_irq(int irq, void *dev_id)
1052 struct pxafb_info *fbi = dev_id;
1053 unsigned int lccr0, lcsr = lcd_readl(fbi, LCSR);
1055 if (lcsr & LCSR_LDD) {
1056 lccr0 = lcd_readl(fbi, LCCR0);
1057 lcd_writel(fbi, LCCR0, lccr0 | LCCR0_LDM);
1058 complete(&fbi->disable_done);
1061 #ifdef CONFIG_FB_PXA_SMARTPANEL
1062 if (lcsr & LCSR_CMD_INT)
1063 complete(&fbi->command_done);
1066 lcd_writel(fbi, LCSR, lcsr);
1071 * This function must be called from task context only, since it will
1072 * sleep when disabling the LCD controller, or if we get two contending
1073 * processes trying to alter state.
1075 static void set_ctrlr_state(struct pxafb_info *fbi, u_int state)
1079 mutex_lock(&fbi->ctrlr_lock);
1081 old_state = fbi->state;
1084 * Hack around fbcon initialisation.
1086 if (old_state == C_STARTUP && state == C_REENABLE)
1090 case C_DISABLE_CLKCHANGE:
1092 * Disable controller for clock change. If the
1093 * controller is already disabled, then do nothing.
1095 if (old_state != C_DISABLE && old_state != C_DISABLE_PM) {
1097 /* TODO __pxafb_lcd_power(fbi, 0); */
1098 pxafb_disable_controller(fbi);
1105 * Disable controller
1107 if (old_state != C_DISABLE) {
1109 __pxafb_backlight_power(fbi, 0);
1110 __pxafb_lcd_power(fbi, 0);
1111 if (old_state != C_DISABLE_CLKCHANGE)
1112 pxafb_disable_controller(fbi);
1116 case C_ENABLE_CLKCHANGE:
1118 * Enable the controller after clock change. Only
1119 * do this if we were disabled for the clock change.
1121 if (old_state == C_DISABLE_CLKCHANGE) {
1122 fbi->state = C_ENABLE;
1123 pxafb_enable_controller(fbi);
1124 /* TODO __pxafb_lcd_power(fbi, 1); */
1130 * Re-enable the controller only if it was already
1131 * enabled. This is so we reprogram the control
1134 if (old_state == C_ENABLE) {
1135 __pxafb_lcd_power(fbi, 0);
1136 pxafb_disable_controller(fbi);
1137 pxafb_enable_controller(fbi);
1138 __pxafb_lcd_power(fbi, 1);
1144 * Re-enable the controller after PM. This is not
1145 * perfect - think about the case where we were doing
1146 * a clock change, and we suspended half-way through.
1148 if (old_state != C_DISABLE_PM)
1154 * Power up the LCD screen, enable controller, and
1155 * turn on the backlight.
1157 if (old_state != C_ENABLE) {
1158 fbi->state = C_ENABLE;
1159 pxafb_enable_controller(fbi);
1160 __pxafb_lcd_power(fbi, 1);
1161 __pxafb_backlight_power(fbi, 1);
1165 mutex_unlock(&fbi->ctrlr_lock);
1169 * Our LCD controller task (which is called when we blank or unblank)
1172 static void pxafb_task(struct work_struct *work)
1174 struct pxafb_info *fbi =
1175 container_of(work, struct pxafb_info, task);
1176 u_int state = xchg(&fbi->task_state, -1);
1178 set_ctrlr_state(fbi, state);
1181 #ifdef CONFIG_CPU_FREQ
1183 * CPU clock speed change handler. We need to adjust the LCD timing
1184 * parameters when the CPU clock is adjusted by the power management
1187 * TODO: Determine why f->new != 10*get_lclk_frequency_10khz()
1190 pxafb_freq_transition(struct notifier_block *nb, unsigned long val, void *data)
1192 struct pxafb_info *fbi = TO_INF(nb, freq_transition);
1193 /* TODO struct cpufreq_freqs *f = data; */
1197 case CPUFREQ_PRECHANGE:
1198 set_ctrlr_state(fbi, C_DISABLE_CLKCHANGE);
1201 case CPUFREQ_POSTCHANGE:
1202 pcd = get_pcd(fbi, fbi->fb.var.pixclock);
1203 set_hsync_time(fbi, pcd);
1204 fbi->reg_lccr3 = (fbi->reg_lccr3 & ~0xff) |
1205 LCCR3_PixClkDiv(pcd);
1206 set_ctrlr_state(fbi, C_ENABLE_CLKCHANGE);
1213 pxafb_freq_policy(struct notifier_block *nb, unsigned long val, void *data)
1215 struct pxafb_info *fbi = TO_INF(nb, freq_policy);
1216 struct fb_var_screeninfo *var = &fbi->fb.var;
1217 struct cpufreq_policy *policy = data;
1220 case CPUFREQ_ADJUST:
1221 case CPUFREQ_INCOMPATIBLE:
1222 pr_debug("min dma period: %d ps, "
1223 "new clock %d kHz\n", pxafb_display_dma_period(var),
1225 /* TODO: fill in min/max values */
1234 * Power management hooks. Note that we won't be called from IRQ context,
1235 * unlike the blank functions above, so we may sleep.
1237 static int pxafb_suspend(struct platform_device *dev, pm_message_t state)
1239 struct pxafb_info *fbi = platform_get_drvdata(dev);
1241 set_ctrlr_state(fbi, C_DISABLE_PM);
1245 static int pxafb_resume(struct platform_device *dev)
1247 struct pxafb_info *fbi = platform_get_drvdata(dev);
1249 set_ctrlr_state(fbi, C_ENABLE_PM);
1253 #define pxafb_suspend NULL
1254 #define pxafb_resume NULL
1257 static int __devinit pxafb_init_video_memory(struct pxafb_info *fbi)
1259 int size = PAGE_ALIGN(fbi->video_mem_size);
1261 fbi->video_mem = alloc_pages_exact(size, GFP_KERNEL | __GFP_ZERO);
1262 if (fbi->video_mem == NULL)
1265 fbi->video_mem_phys = virt_to_phys(fbi->video_mem);
1266 fbi->video_mem_size = size;
1268 fbi->fb.fix.smem_start = fbi->video_mem_phys;
1269 fbi->fb.fix.smem_len = fbi->video_mem_size;
1270 fbi->fb.screen_base = fbi->video_mem;
1272 return fbi->video_mem ? 0 : -ENOMEM;
1275 static void pxafb_decode_mach_info(struct pxafb_info *fbi,
1276 struct pxafb_mach_info *inf)
1278 unsigned int lcd_conn = inf->lcd_conn;
1279 struct pxafb_mode_info *m;
1282 fbi->cmap_inverse = inf->cmap_inverse;
1283 fbi->cmap_static = inf->cmap_static;
1285 switch (lcd_conn & LCD_TYPE_MASK) {
1286 case LCD_TYPE_MONO_STN:
1287 fbi->lccr0 = LCCR0_CMS;
1289 case LCD_TYPE_MONO_DSTN:
1290 fbi->lccr0 = LCCR0_CMS | LCCR0_SDS;
1292 case LCD_TYPE_COLOR_STN:
1295 case LCD_TYPE_COLOR_DSTN:
1296 fbi->lccr0 = LCCR0_SDS;
1298 case LCD_TYPE_COLOR_TFT:
1299 fbi->lccr0 = LCCR0_PAS;
1301 case LCD_TYPE_SMART_PANEL:
1302 fbi->lccr0 = LCCR0_LCDT | LCCR0_PAS;
1305 /* fall back to backward compatibility way */
1306 fbi->lccr0 = inf->lccr0;
1307 fbi->lccr3 = inf->lccr3;
1308 fbi->lccr4 = inf->lccr4;
1312 if (lcd_conn == LCD_MONO_STN_8BPP)
1313 fbi->lccr0 |= LCCR0_DPD;
1315 fbi->lccr0 |= (lcd_conn & LCD_ALTERNATE_MAPPING) ? LCCR0_LDDALT : 0;
1317 fbi->lccr3 = LCCR3_Acb((inf->lcd_conn >> 10) & 0xff);
1318 fbi->lccr3 |= (lcd_conn & LCD_BIAS_ACTIVE_LOW) ? LCCR3_OEP : 0;
1319 fbi->lccr3 |= (lcd_conn & LCD_PCLK_EDGE_FALL) ? LCCR3_PCP : 0;
1322 pxafb_setmode(&fbi->fb.var, &inf->modes[0]);
1324 /* decide video memory size as follows:
1325 * 1. default to mode of maximum resolution
1326 * 2. allow platform to override
1327 * 3. allow module parameter to override
1329 for (i = 0, m = &inf->modes[0]; i < inf->num_modes; i++, m++)
1330 fbi->video_mem_size = max_t(size_t, fbi->video_mem_size,
1331 m->xres * m->yres * m->bpp / 8);
1333 if (inf->video_mem_size > fbi->video_mem_size)
1334 fbi->video_mem_size = inf->video_mem_size;
1336 if (video_mem_size > fbi->video_mem_size)
1337 fbi->video_mem_size = video_mem_size;
1340 static struct pxafb_info * __devinit pxafb_init_fbinfo(struct device *dev)
1342 struct pxafb_info *fbi;
1344 struct pxafb_mach_info *inf = dev->platform_data;
1346 /* Alloc the pxafb_info and pseudo_palette in one step */
1347 fbi = kmalloc(sizeof(struct pxafb_info) + sizeof(u32) * 16, GFP_KERNEL);
1351 memset(fbi, 0, sizeof(struct pxafb_info));
1354 fbi->clk = clk_get(dev, "LCDCLK");
1355 if (IS_ERR(fbi->clk)) {
1360 strcpy(fbi->fb.fix.id, PXA_NAME);
1362 fbi->fb.fix.type = FB_TYPE_PACKED_PIXELS;
1363 fbi->fb.fix.type_aux = 0;
1364 fbi->fb.fix.xpanstep = 0;
1365 fbi->fb.fix.ypanstep = 0;
1366 fbi->fb.fix.ywrapstep = 0;
1367 fbi->fb.fix.accel = FB_ACCEL_NONE;
1369 fbi->fb.var.nonstd = 0;
1370 fbi->fb.var.activate = FB_ACTIVATE_NOW;
1371 fbi->fb.var.height = -1;
1372 fbi->fb.var.width = -1;
1373 fbi->fb.var.accel_flags = 0;
1374 fbi->fb.var.vmode = FB_VMODE_NONINTERLACED;
1376 fbi->fb.fbops = &pxafb_ops;
1377 fbi->fb.flags = FBINFO_DEFAULT;
1381 addr = addr + sizeof(struct pxafb_info);
1382 fbi->fb.pseudo_palette = addr;
1384 fbi->state = C_STARTUP;
1385 fbi->task_state = (u_char)-1;
1387 pxafb_decode_mach_info(fbi, inf);
1389 init_waitqueue_head(&fbi->ctrlr_wait);
1390 INIT_WORK(&fbi->task, pxafb_task);
1391 mutex_init(&fbi->ctrlr_lock);
1392 init_completion(&fbi->disable_done);
1397 #ifdef CONFIG_FB_PXA_PARAMETERS
1398 static int __devinit parse_opt_mode(struct device *dev, const char *this_opt)
1400 struct pxafb_mach_info *inf = dev->platform_data;
1402 const char *name = this_opt+5;
1403 unsigned int namelen = strlen(name);
1404 int res_specified = 0, bpp_specified = 0;
1405 unsigned int xres = 0, yres = 0, bpp = 0;
1406 int yres_specified = 0;
1408 for (i = namelen-1; i >= 0; i--) {
1412 if (!bpp_specified && !yres_specified) {
1413 bpp = simple_strtoul(&name[i+1], NULL, 0);
1419 if (!yres_specified) {
1420 yres = simple_strtoul(&name[i+1], NULL, 0);
1431 if (i < 0 && yres_specified) {
1432 xres = simple_strtoul(name, NULL, 0);
1436 if (res_specified) {
1437 dev_info(dev, "overriding resolution: %dx%d\n", xres, yres);
1438 inf->modes[0].xres = xres; inf->modes[0].yres = yres;
1447 inf->modes[0].bpp = bpp;
1448 dev_info(dev, "overriding bit depth: %d\n", bpp);
1451 dev_err(dev, "Depth %d is not valid\n", bpp);
1457 static int __devinit parse_opt(struct device *dev, char *this_opt)
1459 struct pxafb_mach_info *inf = dev->platform_data;
1460 struct pxafb_mode_info *mode = &inf->modes[0];
1465 if (!strncmp(this_opt, "vmem:", 5)) {
1466 video_mem_size = memparse(this_opt + 5, NULL);
1467 } else if (!strncmp(this_opt, "mode:", 5)) {
1468 return parse_opt_mode(dev, this_opt);
1469 } else if (!strncmp(this_opt, "pixclock:", 9)) {
1470 mode->pixclock = simple_strtoul(this_opt+9, NULL, 0);
1471 sprintf(s, "pixclock: %ld\n", mode->pixclock);
1472 } else if (!strncmp(this_opt, "left:", 5)) {
1473 mode->left_margin = simple_strtoul(this_opt+5, NULL, 0);
1474 sprintf(s, "left: %u\n", mode->left_margin);
1475 } else if (!strncmp(this_opt, "right:", 6)) {
1476 mode->right_margin = simple_strtoul(this_opt+6, NULL, 0);
1477 sprintf(s, "right: %u\n", mode->right_margin);
1478 } else if (!strncmp(this_opt, "upper:", 6)) {
1479 mode->upper_margin = simple_strtoul(this_opt+6, NULL, 0);
1480 sprintf(s, "upper: %u\n", mode->upper_margin);
1481 } else if (!strncmp(this_opt, "lower:", 6)) {
1482 mode->lower_margin = simple_strtoul(this_opt+6, NULL, 0);
1483 sprintf(s, "lower: %u\n", mode->lower_margin);
1484 } else if (!strncmp(this_opt, "hsynclen:", 9)) {
1485 mode->hsync_len = simple_strtoul(this_opt+9, NULL, 0);
1486 sprintf(s, "hsynclen: %u\n", mode->hsync_len);
1487 } else if (!strncmp(this_opt, "vsynclen:", 9)) {
1488 mode->vsync_len = simple_strtoul(this_opt+9, NULL, 0);
1489 sprintf(s, "vsynclen: %u\n", mode->vsync_len);
1490 } else if (!strncmp(this_opt, "hsync:", 6)) {
1491 if (simple_strtoul(this_opt+6, NULL, 0) == 0) {
1492 sprintf(s, "hsync: Active Low\n");
1493 mode->sync &= ~FB_SYNC_HOR_HIGH_ACT;
1495 sprintf(s, "hsync: Active High\n");
1496 mode->sync |= FB_SYNC_HOR_HIGH_ACT;
1498 } else if (!strncmp(this_opt, "vsync:", 6)) {
1499 if (simple_strtoul(this_opt+6, NULL, 0) == 0) {
1500 sprintf(s, "vsync: Active Low\n");
1501 mode->sync &= ~FB_SYNC_VERT_HIGH_ACT;
1503 sprintf(s, "vsync: Active High\n");
1504 mode->sync |= FB_SYNC_VERT_HIGH_ACT;
1506 } else if (!strncmp(this_opt, "dpc:", 4)) {
1507 if (simple_strtoul(this_opt+4, NULL, 0) == 0) {
1508 sprintf(s, "double pixel clock: false\n");
1509 inf->lccr3 &= ~LCCR3_DPC;
1511 sprintf(s, "double pixel clock: true\n");
1512 inf->lccr3 |= LCCR3_DPC;
1514 } else if (!strncmp(this_opt, "outputen:", 9)) {
1515 if (simple_strtoul(this_opt+9, NULL, 0) == 0) {
1516 sprintf(s, "output enable: active low\n");
1517 inf->lccr3 = (inf->lccr3 & ~LCCR3_OEP) | LCCR3_OutEnL;
1519 sprintf(s, "output enable: active high\n");
1520 inf->lccr3 = (inf->lccr3 & ~LCCR3_OEP) | LCCR3_OutEnH;
1522 } else if (!strncmp(this_opt, "pixclockpol:", 12)) {
1523 if (simple_strtoul(this_opt+12, NULL, 0) == 0) {
1524 sprintf(s, "pixel clock polarity: falling edge\n");
1525 inf->lccr3 = (inf->lccr3 & ~LCCR3_PCP) | LCCR3_PixFlEdg;
1527 sprintf(s, "pixel clock polarity: rising edge\n");
1528 inf->lccr3 = (inf->lccr3 & ~LCCR3_PCP) | LCCR3_PixRsEdg;
1530 } else if (!strncmp(this_opt, "color", 5)) {
1531 inf->lccr0 = (inf->lccr0 & ~LCCR0_CMS) | LCCR0_Color;
1532 } else if (!strncmp(this_opt, "mono", 4)) {
1533 inf->lccr0 = (inf->lccr0 & ~LCCR0_CMS) | LCCR0_Mono;
1534 } else if (!strncmp(this_opt, "active", 6)) {
1535 inf->lccr0 = (inf->lccr0 & ~LCCR0_PAS) | LCCR0_Act;
1536 } else if (!strncmp(this_opt, "passive", 7)) {
1537 inf->lccr0 = (inf->lccr0 & ~LCCR0_PAS) | LCCR0_Pas;
1538 } else if (!strncmp(this_opt, "single", 6)) {
1539 inf->lccr0 = (inf->lccr0 & ~LCCR0_SDS) | LCCR0_Sngl;
1540 } else if (!strncmp(this_opt, "dual", 4)) {
1541 inf->lccr0 = (inf->lccr0 & ~LCCR0_SDS) | LCCR0_Dual;
1542 } else if (!strncmp(this_opt, "4pix", 4)) {
1543 inf->lccr0 = (inf->lccr0 & ~LCCR0_DPD) | LCCR0_4PixMono;
1544 } else if (!strncmp(this_opt, "8pix", 4)) {
1545 inf->lccr0 = (inf->lccr0 & ~LCCR0_DPD) | LCCR0_8PixMono;
1547 dev_err(dev, "unknown option: %s\n", this_opt);
1552 dev_info(dev, "override %s", s);
1557 static int __devinit pxafb_parse_options(struct device *dev, char *options)
1562 if (!options || !*options)
1565 dev_dbg(dev, "options are \"%s\"\n", options ? options : "null");
1567 /* could be made table driven or similar?... */
1568 while ((this_opt = strsep(&options, ",")) != NULL) {
1569 ret = parse_opt(dev, this_opt);
1576 static char g_options[256] __devinitdata = "";
1579 static int __init pxafb_setup_options(void)
1581 char *options = NULL;
1583 if (fb_get_options("pxafb", &options))
1587 strlcpy(g_options, options, sizeof(g_options));
1592 #define pxafb_setup_options() (0)
1594 module_param_string(options, g_options, sizeof(g_options), 0);
1595 MODULE_PARM_DESC(options, "LCD parameters (see Documentation/fb/pxafb.txt)");
1599 #define pxafb_parse_options(...) (0)
1600 #define pxafb_setup_options() (0)
1604 /* Check for various illegal bit-combinations. Currently only
1605 * a warning is given. */
1606 static void __devinit pxafb_check_options(struct device *dev,
1607 struct pxafb_mach_info *inf)
1612 if (inf->lccr0 & LCCR0_INVALID_CONFIG_MASK)
1613 dev_warn(dev, "machine LCCR0 setting contains "
1614 "illegal bits: %08x\n",
1615 inf->lccr0 & LCCR0_INVALID_CONFIG_MASK);
1616 if (inf->lccr3 & LCCR3_INVALID_CONFIG_MASK)
1617 dev_warn(dev, "machine LCCR3 setting contains "
1618 "illegal bits: %08x\n",
1619 inf->lccr3 & LCCR3_INVALID_CONFIG_MASK);
1620 if (inf->lccr0 & LCCR0_DPD &&
1621 ((inf->lccr0 & LCCR0_PAS) != LCCR0_Pas ||
1622 (inf->lccr0 & LCCR0_SDS) != LCCR0_Sngl ||
1623 (inf->lccr0 & LCCR0_CMS) != LCCR0_Mono))
1624 dev_warn(dev, "Double Pixel Data (DPD) mode is "
1625 "only valid in passive mono"
1626 " single panel mode\n");
1627 if ((inf->lccr0 & LCCR0_PAS) == LCCR0_Act &&
1628 (inf->lccr0 & LCCR0_SDS) == LCCR0_Dual)
1629 dev_warn(dev, "Dual panel only valid in passive mode\n");
1630 if ((inf->lccr0 & LCCR0_PAS) == LCCR0_Pas &&
1631 (inf->modes->upper_margin || inf->modes->lower_margin))
1632 dev_warn(dev, "Upper and lower margins must be 0 in "
1636 #define pxafb_check_options(...) do {} while (0)
1639 static int __devinit pxafb_probe(struct platform_device *dev)
1641 struct pxafb_info *fbi;
1642 struct pxafb_mach_info *inf;
1646 dev_dbg(&dev->dev, "pxafb_probe\n");
1648 inf = dev->dev.platform_data;
1654 ret = pxafb_parse_options(&dev->dev, g_options);
1658 pxafb_check_options(&dev->dev, inf);
1660 dev_dbg(&dev->dev, "got a %dx%dx%d LCD\n",
1664 if (inf->modes->xres == 0 ||
1665 inf->modes->yres == 0 ||
1666 inf->modes->bpp == 0) {
1667 dev_err(&dev->dev, "Invalid resolution or bit depth\n");
1672 fbi = pxafb_init_fbinfo(&dev->dev);
1674 /* only reason for pxafb_init_fbinfo to fail is kmalloc */
1675 dev_err(&dev->dev, "Failed to initialize framebuffer device\n");
1680 fbi->backlight_power = inf->pxafb_backlight_power;
1681 fbi->lcd_power = inf->pxafb_lcd_power;
1683 r = platform_get_resource(dev, IORESOURCE_MEM, 0);
1685 dev_err(&dev->dev, "no I/O memory resource defined\n");
1690 r = request_mem_region(r->start, r->end - r->start + 1, dev->name);
1692 dev_err(&dev->dev, "failed to request I/O memory\n");
1697 fbi->mmio_base = ioremap(r->start, r->end - r->start + 1);
1698 if (fbi->mmio_base == NULL) {
1699 dev_err(&dev->dev, "failed to map I/O memory\n");
1701 goto failed_free_res;
1704 fbi->dma_buff_size = PAGE_ALIGN(sizeof(struct pxafb_dma_buff));
1705 fbi->dma_buff = dma_alloc_coherent(fbi->dev, fbi->dma_buff_size,
1706 &fbi->dma_buff_phys, GFP_KERNEL);
1707 if (fbi->dma_buff == NULL) {
1708 dev_err(&dev->dev, "failed to allocate memory for DMA\n");
1710 goto failed_free_io;
1713 ret = pxafb_init_video_memory(fbi);
1715 dev_err(&dev->dev, "Failed to allocate video RAM: %d\n", ret);
1717 goto failed_free_dma;
1720 irq = platform_get_irq(dev, 0);
1722 dev_err(&dev->dev, "no IRQ defined\n");
1724 goto failed_free_mem;
1727 ret = request_irq(irq, pxafb_handle_irq, IRQF_DISABLED, "LCD", fbi);
1729 dev_err(&dev->dev, "request_irq failed: %d\n", ret);
1731 goto failed_free_mem;
1734 ret = pxafb_smart_init(fbi);
1736 dev_err(&dev->dev, "failed to initialize smartpanel\n");
1737 goto failed_free_irq;
1741 * This makes sure that our colour bitfield
1742 * descriptors are correctly initialised.
1744 ret = pxafb_check_var(&fbi->fb.var, &fbi->fb);
1746 dev_err(&dev->dev, "failed to get suitable mode\n");
1747 goto failed_free_irq;
1750 ret = pxafb_set_par(&fbi->fb);
1752 dev_err(&dev->dev, "Failed to set parameters\n");
1753 goto failed_free_irq;
1756 platform_set_drvdata(dev, fbi);
1758 ret = register_framebuffer(&fbi->fb);
1761 "Failed to register framebuffer device: %d\n", ret);
1762 goto failed_free_cmap;
1765 #ifdef CONFIG_CPU_FREQ
1766 fbi->freq_transition.notifier_call = pxafb_freq_transition;
1767 fbi->freq_policy.notifier_call = pxafb_freq_policy;
1768 cpufreq_register_notifier(&fbi->freq_transition,
1769 CPUFREQ_TRANSITION_NOTIFIER);
1770 cpufreq_register_notifier(&fbi->freq_policy,
1771 CPUFREQ_POLICY_NOTIFIER);
1775 * Ok, now enable the LCD controller
1777 set_ctrlr_state(fbi, C_ENABLE);
1782 if (fbi->fb.cmap.len)
1783 fb_dealloc_cmap(&fbi->fb.cmap);
1787 free_pages_exact(fbi->video_mem, fbi->video_mem_size);
1789 dma_free_coherent(&dev->dev, fbi->dma_buff_size,
1790 fbi->dma_buff, fbi->dma_buff_phys);
1792 iounmap(fbi->mmio_base);
1794 release_mem_region(r->start, r->end - r->start + 1);
1797 platform_set_drvdata(dev, NULL);
1803 static int __devexit pxafb_remove(struct platform_device *dev)
1805 struct pxafb_info *fbi = platform_get_drvdata(dev);
1808 struct fb_info *info;
1815 unregister_framebuffer(info);
1817 pxafb_disable_controller(fbi);
1819 if (fbi->fb.cmap.len)
1820 fb_dealloc_cmap(&fbi->fb.cmap);
1822 irq = platform_get_irq(dev, 0);
1825 free_pages_exact(fbi->video_mem, fbi->video_mem_size);
1827 dma_free_writecombine(&dev->dev, fbi->dma_buff_size,
1828 fbi->dma_buff, fbi->dma_buff_phys);
1830 iounmap(fbi->mmio_base);
1832 r = platform_get_resource(dev, IORESOURCE_MEM, 0);
1833 release_mem_region(r->start, r->end - r->start + 1);
1841 static struct platform_driver pxafb_driver = {
1842 .probe = pxafb_probe,
1843 .remove = pxafb_remove,
1844 .suspend = pxafb_suspend,
1845 .resume = pxafb_resume,
1847 .owner = THIS_MODULE,
1848 .name = "pxa2xx-fb",
1852 static int __init pxafb_init(void)
1854 if (pxafb_setup_options())
1857 return platform_driver_register(&pxafb_driver);
1860 static void __exit pxafb_exit(void)
1862 platform_driver_unregister(&pxafb_driver);
1865 module_init(pxafb_init);
1866 module_exit(pxafb_exit);
1868 MODULE_DESCRIPTION("loadable framebuffer driver for PXA");
1869 MODULE_LICENSE("GPL");